1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * CAAM hardware register-level view 4 * 5 * Copyright 2008-2011 Freescale Semiconductor, Inc. 6 */ 7 8 #ifndef REGS_H 9 #define REGS_H 10 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 #include <linux/io.h> 14 15 /* 16 * Architecture-specific register access methods 17 * 18 * CAAM's bus-addressable registers are 64 bits internally. 19 * They have been wired to be safely accessible on 32-bit 20 * architectures, however. Registers were organized such 21 * that (a) they can be contained in 32 bits, (b) if not, then they 22 * can be treated as two 32-bit entities, or finally (c) if they 23 * must be treated as a single 64-bit value, then this can safely 24 * be done with two 32-bit cycles. 25 * 26 * For 32-bit operations on 64-bit values, CAAM follows the same 27 * 64-bit register access conventions as it's predecessors, in that 28 * writes are "triggered" by a write to the register at the numerically 29 * higher address, thus, a full 64-bit write cycle requires a write 30 * to the lower address, followed by a write to the higher address, 31 * which will latch/execute the write cycle. 32 * 33 * For example, let's assume a SW reset of CAAM through the master 34 * configuration register. 35 * - SWRST is in bit 31 of MCFG. 36 * - MCFG begins at base+0x0000. 37 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) 38 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) 39 * 40 * (and on Power, the convention is 0-31, 32-63, I know...) 41 * 42 * Assuming a 64-bit write to this MCFG to perform a software reset 43 * would then require a write of 0 to base+0x0000, followed by a 44 * write of 0x80000000 to base+0x0004, which would "execute" the 45 * reset. 46 * 47 * Of course, since MCFG 63-32 is all zero, we could cheat and simply 48 * write 0x8000000 to base+0x0004, and the reset would work fine. 49 * However, since CAAM does contain some write-and-read-intended 50 * 64-bit registers, this code defines 64-bit access methods for 51 * the sake of internal consistency and simplicity, and so that a 52 * clean transition to 64-bit is possible when it becomes necessary. 53 * 54 * There are limitations to this that the developer must recognize. 55 * 32-bit architectures cannot enforce an atomic-64 operation, 56 * Therefore: 57 * 58 * - On writes, since the HW is assumed to latch the cycle on the 59 * write of the higher-numeric-address word, then ordered 60 * writes work OK. 61 * 62 * - For reads, where a register contains a relevant value of more 63 * that 32 bits, the hardware employs logic to latch the other 64 * "half" of the data until read, ensuring an accurate value. 65 * This is of particular relevance when dealing with CAAM's 66 * performance counters. 67 * 68 */ 69 70 extern bool caam_little_end; 71 extern bool caam_imx; 72 73 #define caam_to_cpu(len) \ 74 static inline u##len caam##len ## _to_cpu(u##len val) \ 75 { \ 76 if (caam_little_end) \ 77 return le##len ## _to_cpu(val); \ 78 else \ 79 return be##len ## _to_cpu(val); \ 80 } 81 82 #define cpu_to_caam(len) \ 83 static inline u##len cpu_to_caam##len(u##len val) \ 84 { \ 85 if (caam_little_end) \ 86 return cpu_to_le##len(val); \ 87 else \ 88 return cpu_to_be##len(val); \ 89 } 90 91 caam_to_cpu(16) 92 caam_to_cpu(32) 93 caam_to_cpu(64) 94 cpu_to_caam(16) 95 cpu_to_caam(32) 96 cpu_to_caam(64) 97 98 static inline void wr_reg32(void __iomem *reg, u32 data) 99 { 100 if (caam_little_end) 101 iowrite32(data, reg); 102 else 103 iowrite32be(data, reg); 104 } 105 106 static inline u32 rd_reg32(void __iomem *reg) 107 { 108 if (caam_little_end) 109 return ioread32(reg); 110 111 return ioread32be(reg); 112 } 113 114 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) 115 { 116 if (caam_little_end) 117 iowrite32((ioread32(reg) & ~clear) | set, reg); 118 else 119 iowrite32be((ioread32be(reg) & ~clear) | set, reg); 120 } 121 122 /* 123 * The only users of these wr/rd_reg64 functions is the Job Ring (JR). 124 * The DMA address registers in the JR are handled differently depending on 125 * platform: 126 * 127 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): 128 * 129 * base + 0x0000 : most-significant 32 bits 130 * base + 0x0004 : least-significant 32 bits 131 * 132 * The 32-bit version of this core therefore has to write to base + 0x0004 133 * to set the 32-bit wide DMA address. 134 * 135 * 2. All other LE CAAM platforms (LS1021A etc.) 136 * base + 0x0000 : least-significant 32 bits 137 * base + 0x0004 : most-significant 32 bits 138 */ 139 #ifdef CONFIG_64BIT 140 static inline void wr_reg64(void __iomem *reg, u64 data) 141 { 142 if (caam_little_end) 143 iowrite64(data, reg); 144 else 145 iowrite64be(data, reg); 146 } 147 148 static inline u64 rd_reg64(void __iomem *reg) 149 { 150 if (caam_little_end) 151 return ioread64(reg); 152 else 153 return ioread64be(reg); 154 } 155 156 #else /* CONFIG_64BIT */ 157 static inline void wr_reg64(void __iomem *reg, u64 data) 158 { 159 if (!caam_imx && caam_little_end) { 160 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); 161 wr_reg32((u32 __iomem *)(reg), data); 162 } else { 163 wr_reg32((u32 __iomem *)(reg), data >> 32); 164 wr_reg32((u32 __iomem *)(reg) + 1, data); 165 } 166 } 167 168 static inline u64 rd_reg64(void __iomem *reg) 169 { 170 if (!caam_imx && caam_little_end) 171 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | 172 (u64)rd_reg32((u32 __iomem *)(reg))); 173 174 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | 175 (u64)rd_reg32((u32 __iomem *)(reg) + 1)); 176 } 177 #endif /* CONFIG_64BIT */ 178 179 static inline u64 cpu_to_caam_dma64(dma_addr_t value) 180 { 181 if (caam_imx) 182 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | 183 (u64)cpu_to_caam32(upper_32_bits(value))); 184 185 return cpu_to_caam64(value); 186 } 187 188 static inline u64 caam_dma64_to_cpu(u64 value) 189 { 190 if (caam_imx) 191 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | 192 (u64)caam32_to_cpu(upper_32_bits(value))); 193 194 return caam64_to_cpu(value); 195 } 196 197 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 198 #define cpu_to_caam_dma(value) cpu_to_caam_dma64(value) 199 #define caam_dma_to_cpu(value) caam_dma64_to_cpu(value) 200 #else 201 #define cpu_to_caam_dma(value) cpu_to_caam32(value) 202 #define caam_dma_to_cpu(value) caam32_to_cpu(value) 203 #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ 204 205 /* 206 * jr_outentry 207 * Represents each entry in a JobR output ring 208 */ 209 struct jr_outentry { 210 dma_addr_t desc;/* Pointer to completed descriptor */ 211 u32 jrstatus; /* Status for completed descriptor */ 212 } __packed; 213 214 /* 215 * caam_perfmon - Performance Monitor/Secure Memory Status/ 216 * CAAM Global Status/Component Version IDs 217 * 218 * Spans f00-fff wherever instantiated 219 */ 220 221 /* Number of DECOs */ 222 #define CHA_NUM_MS_DECONUM_SHIFT 24 223 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) 224 225 /* 226 * CHA version IDs / instantiation bitfields 227 * Defined for use with the cha_id fields in perfmon, but the same shift/mask 228 * selectors can be used to pull out the number of instantiated blocks within 229 * cha_num fields in perfmon because the locations are the same. 230 */ 231 #define CHA_ID_LS_AES_SHIFT 0 232 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) 233 #define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT) 234 #define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT) 235 236 #define CHA_ID_LS_DES_SHIFT 4 237 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) 238 239 #define CHA_ID_LS_ARC4_SHIFT 8 240 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) 241 242 #define CHA_ID_LS_MD_SHIFT 12 243 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) 244 #define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT) 245 #define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT) 246 #define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT) 247 248 #define CHA_ID_LS_RNG_SHIFT 16 249 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) 250 251 #define CHA_ID_LS_SNW8_SHIFT 20 252 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) 253 254 #define CHA_ID_LS_KAS_SHIFT 24 255 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) 256 257 #define CHA_ID_LS_PK_SHIFT 28 258 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) 259 260 #define CHA_ID_MS_CRC_SHIFT 0 261 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) 262 263 #define CHA_ID_MS_SNW9_SHIFT 4 264 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) 265 266 #define CHA_ID_MS_DECO_SHIFT 24 267 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) 268 269 #define CHA_ID_MS_JR_SHIFT 28 270 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) 271 272 struct sec_vid { 273 u16 ip_id; 274 u8 maj_rev; 275 u8 min_rev; 276 }; 277 278 struct caam_perfmon { 279 /* Performance Monitor Registers f00-f9f */ 280 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ 281 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ 282 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ 283 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ 284 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ 285 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ 286 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ 287 u64 rsvd[13]; 288 289 /* CAAM Hardware Instantiation Parameters fa0-fbf */ 290 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ 291 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ 292 #define CTPR_MS_QI_SHIFT 25 293 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) 294 #define CTPR_MS_DPAA2 BIT(13) 295 #define CTPR_MS_VIRT_EN_INCL 0x00000001 296 #define CTPR_MS_VIRT_EN_POR 0x00000002 297 #define CTPR_MS_PG_SZ_MASK 0x10 298 #define CTPR_MS_PG_SZ_SHIFT 4 299 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ 300 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ 301 u64 rsvd1[2]; 302 303 /* CAAM Global Status fc0-fdf */ 304 u64 faultaddr; /* FAR - Fault Address */ 305 u32 faultliodn; /* FALR - Fault Address LIODN */ 306 u32 faultdetail; /* FADR - Fault Addr Detail */ 307 u32 rsvd2; 308 #define CSTA_PLEND BIT(10) 309 #define CSTA_ALT_PLEND BIT(18) 310 u32 status; /* CSTA - CAAM Status */ 311 u64 rsvd3; 312 313 /* Component Instantiation Parameters fe0-fff */ 314 u32 rtic_id; /* RVID - RTIC Version ID */ 315 #define CCBVID_ERA_MASK 0xff000000 316 #define CCBVID_ERA_SHIFT 24 317 u32 ccb_id; /* CCBVID - CCB Version ID */ 318 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ 319 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ 320 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ 321 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ 322 #define SECVID_MS_IPID_MASK 0xffff0000 323 #define SECVID_MS_IPID_SHIFT 16 324 #define SECVID_MS_MAJ_REV_MASK 0x0000ff00 325 #define SECVID_MS_MAJ_REV_SHIFT 8 326 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ 327 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ 328 }; 329 330 /* LIODN programming for DMA configuration */ 331 #define MSTRID_LOCK_LIODN 0x80000000 332 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ 333 334 #define MSTRID_LIODN_MASK 0x0fff 335 struct masterid { 336 u32 liodn_ms; /* lock and make-trusted control bits */ 337 u32 liodn_ls; /* LIODN for non-sequence and seq access */ 338 }; 339 340 /* Partition ID for DMA configuration */ 341 struct partid { 342 u32 rsvd1; 343 u32 pidr; /* partition ID, DECO */ 344 }; 345 346 /* RNGB test mode (replicated twice in some configurations) */ 347 /* Padded out to 0x100 */ 348 struct rngtst { 349 u32 mode; /* RTSTMODEx - Test mode */ 350 u32 rsvd1[3]; 351 u32 reset; /* RTSTRESETx - Test reset control */ 352 u32 rsvd2[3]; 353 u32 status; /* RTSTSSTATUSx - Test status */ 354 u32 rsvd3; 355 u32 errstat; /* RTSTERRSTATx - Test error status */ 356 u32 rsvd4; 357 u32 errctl; /* RTSTERRCTLx - Test error control */ 358 u32 rsvd5; 359 u32 entropy; /* RTSTENTROPYx - Test entropy */ 360 u32 rsvd6[15]; 361 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ 362 u32 rsvd7; 363 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ 364 u32 rsvd8; 365 u32 verifdata; /* RTSTVERIFDx - Test verification data */ 366 u32 rsvd9; 367 u32 xkey; /* RTSTXKEYx - Test XKEY */ 368 u32 rsvd10; 369 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ 370 u32 rsvd11; 371 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ 372 u32 rsvd12; 373 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ 374 u32 rsvd13[2]; 375 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ 376 u32 rsvd14[15]; 377 }; 378 379 /* RNG4 TRNG test registers */ 380 struct rng4tst { 381 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 382 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 383 both entropy shifter and 384 statistical checker */ 385 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 386 entropy shifter and 387 statistical checker */ 388 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 389 entropy shifter, raw data 390 in statistical checker */ 391 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 392 u32 rtmctl; /* misc. control register */ 393 u32 rtscmisc; /* statistical check misc. register */ 394 u32 rtpkrrng; /* poker range register */ 395 union { 396 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 397 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 398 }; 399 #define RTSDCTL_ENT_DLY_SHIFT 16 400 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 401 #define RTSDCTL_ENT_DLY_MIN 3200 402 #define RTSDCTL_ENT_DLY_MAX 12800 403 u32 rtsdctl; /* seed control register */ 404 union { 405 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 406 u32 rttotsam; /* PRGM=0: total samples register */ 407 }; 408 u32 rtfrqmin; /* frequency count min. limit register */ 409 #define RTFRQMAX_DISABLE (1 << 20) 410 union { 411 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 412 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 413 }; 414 u32 rsvd1[40]; 415 #define RDSTA_SKVT 0x80000000 416 #define RDSTA_SKVN 0x40000000 417 #define RDSTA_IF0 0x00000001 418 #define RDSTA_IF1 0x00000002 419 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) 420 u32 rdsta; 421 u32 rsvd2[15]; 422 }; 423 424 /* 425 * caam_ctrl - basic core configuration 426 * starts base + 0x0000 padded out to 0x1000 427 */ 428 429 #define KEK_KEY_SIZE 8 430 #define TKEK_KEY_SIZE 8 431 #define TDSK_KEY_SIZE 8 432 433 #define DECO_RESET 1 /* Use with DECO reset/availability regs */ 434 #define DECO_RESET_0 (DECO_RESET << 0) 435 #define DECO_RESET_1 (DECO_RESET << 1) 436 #define DECO_RESET_2 (DECO_RESET << 2) 437 #define DECO_RESET_3 (DECO_RESET << 3) 438 #define DECO_RESET_4 (DECO_RESET << 4) 439 440 struct caam_ctrl { 441 /* Basic Configuration Section 000-01f */ 442 /* Read/Writable */ 443 u32 rsvd1; 444 u32 mcr; /* MCFG Master Config Register */ 445 u32 rsvd2; 446 u32 scfgr; /* SCFGR, Security Config Register */ 447 448 /* Bus Access Configuration Section 010-11f */ 449 /* Read/Writable */ 450 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ 451 u32 rsvd3[11]; 452 u32 jrstart; /* JRSTART - Job Ring Start Register */ 453 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ 454 u32 rsvd4[5]; 455 u32 deco_rsr; /* DECORSR - Deco Request Source */ 456 u32 rsvd11; 457 u32 deco_rq; /* DECORR - DECO Request */ 458 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ 459 u32 rsvd5[22]; 460 461 /* DECO Availability/Reset Section 120-3ff */ 462 u32 deco_avail; /* DAR - DECO availability */ 463 u32 deco_reset; /* DRR - DECO reset */ 464 u32 rsvd6[182]; 465 466 /* Key Encryption/Decryption Configuration 400-5ff */ 467 /* Read/Writable only while in Non-secure mode */ 468 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ 469 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ 470 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ 471 u32 rsvd7[32]; 472 u64 sknonce; /* SKNR - Secure Key Nonce */ 473 u32 rsvd8[70]; 474 475 /* RNG Test/Verification/Debug Access 600-7ff */ 476 /* (Useful in Test/Debug modes only...) */ 477 union { 478 struct rngtst rtst[2]; 479 struct rng4tst r4tst[2]; 480 }; 481 482 u32 rsvd9[448]; 483 484 /* Performance Monitor f00-fff */ 485 struct caam_perfmon perfmon; 486 }; 487 488 /* 489 * Controller master config register defs 490 */ 491 #define MCFGR_SWRESET 0x80000000 /* software reset */ 492 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ 493 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ 494 #define MCFGR_DMA_RESET 0x10000000 495 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ 496 #define SCFGR_RDBENABLE 0x00000400 497 #define SCFGR_VIRT_EN 0x00008000 498 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ 499 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ 500 #define DECORSR_VALID 0x80000000 501 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ 502 503 /* AXI read cache control */ 504 #define MCFGR_ARCACHE_SHIFT 12 505 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 506 #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) 507 #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) 508 #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) 509 510 /* AXI write cache control */ 511 #define MCFGR_AWCACHE_SHIFT 8 512 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 513 #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) 514 #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) 515 #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) 516 517 /* AXI pipeline depth */ 518 #define MCFGR_AXIPIPE_SHIFT 4 519 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) 520 521 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ 522 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ 523 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ 524 525 /* JRSTART register offsets */ 526 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ 527 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ 528 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ 529 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ 530 531 /* 532 * caam_job_ring - direct job ring setup 533 * 1-4 possible per instantiation, base + 1000/2000/3000/4000 534 * Padded out to 0x1000 535 */ 536 struct caam_job_ring { 537 /* Input ring */ 538 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ 539 u32 rsvd1; 540 u32 inpring_size; /* IRSx - Input ring size */ 541 u32 rsvd2; 542 u32 inpring_avail; /* IRSAx - Input ring room remaining */ 543 u32 rsvd3; 544 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ 545 546 /* Output Ring */ 547 u64 outring_base; /* ORBAx - Output status ring base addr */ 548 u32 rsvd4; 549 u32 outring_size; /* ORSx - Output ring size */ 550 u32 rsvd5; 551 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ 552 u32 rsvd6; 553 u32 outring_used; /* ORSFx - Output ring slots full */ 554 555 /* Status/Configuration */ 556 u32 rsvd7; 557 u32 jroutstatus; /* JRSTAx - JobR output status */ 558 u32 rsvd8; 559 u32 jrintstatus; /* JRINTx - JobR interrupt status */ 560 u32 rconfig_hi; /* JRxCFG - Ring configuration */ 561 u32 rconfig_lo; 562 563 /* Indices. CAAM maintains as "heads" of each queue */ 564 u32 rsvd9; 565 u32 inp_rdidx; /* IRRIx - Input ring read index */ 566 u32 rsvd10; 567 u32 out_wtidx; /* ORWIx - Output ring write index */ 568 569 /* Command/control */ 570 u32 rsvd11; 571 u32 jrcommand; /* JRCRx - JobR command */ 572 573 u32 rsvd12[932]; 574 575 /* Performance Monitor f00-fff */ 576 struct caam_perfmon perfmon; 577 }; 578 579 #define JR_RINGSIZE_MASK 0x03ff 580 /* 581 * jrstatus - Job Ring Output Status 582 * All values in lo word 583 * Also note, same values written out as status through QI 584 * in the command/status field of a frame descriptor 585 */ 586 #define JRSTA_SSRC_SHIFT 28 587 #define JRSTA_SSRC_MASK 0xf0000000 588 589 #define JRSTA_SSRC_NONE 0x00000000 590 #define JRSTA_SSRC_CCB_ERROR 0x20000000 591 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 592 #define JRSTA_SSRC_DECO 0x40000000 593 #define JRSTA_SSRC_JRERROR 0x60000000 594 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 595 596 #define JRSTA_DECOERR_JUMP 0x08000000 597 #define JRSTA_DECOERR_INDEX_SHIFT 8 598 #define JRSTA_DECOERR_INDEX_MASK 0xff00 599 #define JRSTA_DECOERR_ERROR_MASK 0x00ff 600 601 #define JRSTA_DECOERR_NONE 0x00 602 #define JRSTA_DECOERR_LINKLEN 0x01 603 #define JRSTA_DECOERR_LINKPTR 0x02 604 #define JRSTA_DECOERR_JRCTRL 0x03 605 #define JRSTA_DECOERR_DESCCMD 0x04 606 #define JRSTA_DECOERR_ORDER 0x05 607 #define JRSTA_DECOERR_KEYCMD 0x06 608 #define JRSTA_DECOERR_LOADCMD 0x07 609 #define JRSTA_DECOERR_STORECMD 0x08 610 #define JRSTA_DECOERR_OPCMD 0x09 611 #define JRSTA_DECOERR_FIFOLDCMD 0x0a 612 #define JRSTA_DECOERR_FIFOSTCMD 0x0b 613 #define JRSTA_DECOERR_MOVECMD 0x0c 614 #define JRSTA_DECOERR_JUMPCMD 0x0d 615 #define JRSTA_DECOERR_MATHCMD 0x0e 616 #define JRSTA_DECOERR_SHASHCMD 0x0f 617 #define JRSTA_DECOERR_SEQCMD 0x10 618 #define JRSTA_DECOERR_DECOINTERNAL 0x11 619 #define JRSTA_DECOERR_SHDESCHDR 0x12 620 #define JRSTA_DECOERR_HDRLEN 0x13 621 #define JRSTA_DECOERR_BURSTER 0x14 622 #define JRSTA_DECOERR_DESCSIGNATURE 0x15 623 #define JRSTA_DECOERR_DMA 0x16 624 #define JRSTA_DECOERR_BURSTFIFO 0x17 625 #define JRSTA_DECOERR_JRRESET 0x1a 626 #define JRSTA_DECOERR_JOBFAIL 0x1b 627 #define JRSTA_DECOERR_DNRERR 0x80 628 #define JRSTA_DECOERR_UNDEFPCL 0x81 629 #define JRSTA_DECOERR_PDBERR 0x82 630 #define JRSTA_DECOERR_ANRPLY_LATE 0x83 631 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 632 #define JRSTA_DECOERR_SEQOVF 0x85 633 #define JRSTA_DECOERR_INVSIGN 0x86 634 #define JRSTA_DECOERR_DSASIGN 0x87 635 636 #define JRSTA_CCBERR_JUMP 0x08000000 637 #define JRSTA_CCBERR_INDEX_MASK 0xff00 638 #define JRSTA_CCBERR_INDEX_SHIFT 8 639 #define JRSTA_CCBERR_CHAID_MASK 0x00f0 640 #define JRSTA_CCBERR_CHAID_SHIFT 4 641 #define JRSTA_CCBERR_ERRID_MASK 0x000f 642 643 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) 644 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) 645 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) 646 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) 647 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) 648 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) 649 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) 650 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) 651 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) 652 653 #define JRSTA_CCBERR_ERRID_NONE 0x00 654 #define JRSTA_CCBERR_ERRID_MODE 0x01 655 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 656 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 657 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 658 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 659 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 660 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 661 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 662 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 663 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a 664 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b 665 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c 666 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f 667 668 #define JRINT_ERR_INDEX_MASK 0x3fff0000 669 #define JRINT_ERR_INDEX_SHIFT 16 670 #define JRINT_ERR_TYPE_MASK 0xf00 671 #define JRINT_ERR_TYPE_SHIFT 8 672 #define JRINT_ERR_HALT_MASK 0xc 673 #define JRINT_ERR_HALT_SHIFT 2 674 #define JRINT_ERR_HALT_INPROGRESS 0x4 675 #define JRINT_ERR_HALT_COMPLETE 0x8 676 #define JRINT_JR_ERROR 0x02 677 #define JRINT_JR_INT 0x01 678 679 #define JRINT_ERR_TYPE_WRITE 1 680 #define JRINT_ERR_TYPE_BAD_INPADDR 3 681 #define JRINT_ERR_TYPE_BAD_OUTADDR 4 682 #define JRINT_ERR_TYPE_INV_INPWRT 5 683 #define JRINT_ERR_TYPE_INV_OUTWRT 6 684 #define JRINT_ERR_TYPE_RESET 7 685 #define JRINT_ERR_TYPE_REMOVE_OFL 8 686 #define JRINT_ERR_TYPE_ADD_OFL 9 687 688 #define JRCFG_SOE 0x04 689 #define JRCFG_ICEN 0x02 690 #define JRCFG_IMSK 0x01 691 #define JRCFG_ICDCT_SHIFT 8 692 #define JRCFG_ICTT_SHIFT 16 693 694 #define JRCR_RESET 0x01 695 696 /* 697 * caam_assurance - Assurance Controller View 698 * base + 0x6000 padded out to 0x1000 699 */ 700 701 struct rtic_element { 702 u64 address; 703 u32 rsvd; 704 u32 length; 705 }; 706 707 struct rtic_block { 708 struct rtic_element element[2]; 709 }; 710 711 struct rtic_memhash { 712 u32 memhash_be[32]; 713 u32 memhash_le[32]; 714 }; 715 716 struct caam_assurance { 717 /* Status/Command/Watchdog */ 718 u32 rsvd1; 719 u32 status; /* RSTA - Status */ 720 u32 rsvd2; 721 u32 cmd; /* RCMD - Command */ 722 u32 rsvd3; 723 u32 ctrl; /* RCTL - Control */ 724 u32 rsvd4; 725 u32 throttle; /* RTHR - Throttle */ 726 u32 rsvd5[2]; 727 u64 watchdog; /* RWDOG - Watchdog Timer */ 728 u32 rsvd6; 729 u32 rend; /* REND - Endian corrections */ 730 u32 rsvd7[50]; 731 732 /* Block access/configuration @ 100/110/120/130 */ 733 struct rtic_block memblk[4]; /* Memory Blocks A-D */ 734 u32 rsvd8[32]; 735 736 /* Block hashes @ 200/300/400/500 */ 737 struct rtic_memhash hash[4]; /* Block hash values A-D */ 738 u32 rsvd_3[640]; 739 }; 740 741 /* 742 * caam_queue_if - QI configuration and control 743 * starts base + 0x7000, padded out to 0x1000 long 744 */ 745 746 struct caam_queue_if { 747 u32 qi_control_hi; /* QICTL - QI Control */ 748 u32 qi_control_lo; 749 u32 rsvd1; 750 u32 qi_status; /* QISTA - QI Status */ 751 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ 752 u32 qi_deq_cfg_lo; 753 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ 754 u32 qi_enq_cfg_lo; 755 u32 rsvd2[1016]; 756 }; 757 758 /* QI control bits - low word */ 759 #define QICTL_DQEN 0x01 /* Enable frame pop */ 760 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ 761 #define QICTL_SOE 0x04 /* Stop on error */ 762 763 /* QI control bits - high word */ 764 #define QICTL_MBSI 0x01 765 #define QICTL_MHWSI 0x02 766 #define QICTL_MWSI 0x04 767 #define QICTL_MDWSI 0x08 768 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ 769 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ 770 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ 771 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ 772 #define QICTL_MBSO 0x0100 773 #define QICTL_MHWSO 0x0200 774 #define QICTL_MWSO 0x0400 775 #define QICTL_MDWSO 0x0800 776 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ 777 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ 778 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ 779 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ 780 #define QICTL_DMBS 0x010000 781 #define QICTL_EPO 0x020000 782 783 /* QI status bits */ 784 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ 785 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ 786 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ 787 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ 788 #define QISTA_BTSERR 0x10 /* Buffer Undersize */ 789 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ 790 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ 791 792 /* deco_sg_table - DECO view of scatter/gather table */ 793 struct deco_sg_table { 794 u64 addr; /* Segment Address */ 795 u32 elen; /* E, F bits + 30-bit length */ 796 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ 797 }; 798 799 /* 800 * caam_deco - descriptor controller - CHA cluster block 801 * 802 * Only accessible when direct DECO access is turned on 803 * (done in DECORR, via MID programmed in DECOxMID 804 * 805 * 5 typical, base + 0x8000/9000/a000/b000 806 * Padded out to 0x1000 long 807 */ 808 struct caam_deco { 809 u32 rsvd1; 810 u32 cls1_mode; /* CxC1MR - Class 1 Mode */ 811 u32 rsvd2; 812 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ 813 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ 814 u32 cls1_datasize_lo; 815 u32 rsvd3; 816 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ 817 u32 rsvd4[5]; 818 u32 cha_ctrl; /* CCTLR - CHA control */ 819 u32 rsvd5; 820 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ 821 u32 rsvd6; 822 u32 clr_written; /* CxCWR - Clear-Written */ 823 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ 824 u32 ccb_status_lo; 825 u32 rsvd7[3]; 826 u32 aad_size; /* CxAADSZR - Current AAD Size */ 827 u32 rsvd8; 828 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ 829 u32 rsvd9[7]; 830 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ 831 u32 rsvd10; 832 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ 833 u32 rsvd11; 834 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ 835 u32 rsvd12; 836 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ 837 u32 rsvd13[24]; 838 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ 839 u32 rsvd14[48]; 840 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ 841 u32 rsvd15[121]; 842 u32 cls2_mode; /* CxC2MR - Class 2 Mode */ 843 u32 rsvd16; 844 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ 845 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ 846 u32 cls2_datasize_lo; 847 u32 rsvd17; 848 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ 849 u32 rsvd18[56]; 850 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ 851 u32 rsvd19[46]; 852 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ 853 u32 rsvd20[84]; 854 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ 855 u32 inp_infofifo_lo; 856 u32 rsvd21[2]; 857 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ 858 u32 rsvd22[2]; 859 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ 860 u32 rsvd23[2]; 861 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 862 u32 jr_ctl_lo; 863 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 864 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF 865 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 866 u32 op_status_lo; 867 u32 rsvd24[2]; 868 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ 869 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ 870 u32 rsvd26[6]; 871 u64 math[4]; /* DxMTH - Math register */ 872 u32 rsvd27[8]; 873 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ 874 u32 rsvd28[16]; 875 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ 876 u32 rsvd29[48]; 877 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 878 u32 rscvd30[193]; 879 #define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 880 #define DESC_DBG_DECO_STAT_VALID 0x80000000 881 #define DESC_DBG_DECO_STAT_MASK 0x00F00000 882 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 883 u32 rsvd31[126]; 884 }; 885 886 #define DECO_JQCR_WHL 0x20000000 887 #define DECO_JQCR_FOUR 0x10000000 888 889 #define JR_BLOCK_NUMBER 1 890 #define ASSURE_BLOCK_NUMBER 6 891 #define QI_BLOCK_NUMBER 7 892 #define DECO_BLOCK_NUMBER 8 893 #define PG_SIZE_4K 0x1000 894 #define PG_SIZE_64K 0x10000 895 #endif /* REGS_H */ 896