1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * CAAM/SEC 4.x driver backend 4 * Private/internal definitions between modules 5 * 6 * Copyright 2008-2011 Freescale Semiconductor, Inc. 7 * Copyright 2019 NXP 8 */ 9 10 #ifndef INTERN_H 11 #define INTERN_H 12 13 #include "ctrl.h" 14 #include <crypto/engine.h> 15 16 /* Currently comes from Kconfig param as a ^2 (driver-required) */ 17 #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE) 18 19 /* Kconfig params for interrupt coalescing if selected (else zero) */ 20 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_INTC 21 #define JOBR_INTC JRCFG_ICEN 22 #define JOBR_INTC_TIME_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD 23 #define JOBR_INTC_COUNT_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD 24 #else 25 #define JOBR_INTC 0 26 #define JOBR_INTC_TIME_THLD 0 27 #define JOBR_INTC_COUNT_THLD 0 28 #endif 29 30 /* 31 * Storage for tracking each in-process entry moving across a ring 32 * Each entry on an output ring needs one of these 33 */ 34 struct caam_jrentry_info { 35 void (*callbk)(struct device *dev, u32 *desc, u32 status, void *arg); 36 void *cbkarg; /* Argument per ring entry */ 37 u32 *desc_addr_virt; /* Stored virt addr for postprocessing */ 38 dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */ 39 u32 desc_size; /* Stored size for postprocessing, header derived */ 40 }; 41 42 /* Private sub-storage for a single JobR */ 43 struct caam_drv_private_jr { 44 struct list_head list_node; /* Job Ring device list */ 45 struct device *dev; 46 int ridx; 47 struct caam_job_ring __iomem *rregs; /* JobR's register space */ 48 struct tasklet_struct irqtask; 49 int irq; /* One per queue */ 50 bool hwrng; 51 52 /* Number of scatterlist crypt transforms active on the JobR */ 53 atomic_t tfm_count ____cacheline_aligned; 54 55 /* Job ring info */ 56 struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */ 57 spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */ 58 u32 inpring_avail; /* Number of free entries in input ring */ 59 int head; /* entinfo (s/w ring) head index */ 60 void *inpring; /* Base of input ring, alloc 61 * DMA-safe */ 62 int out_ring_read_index; /* Output index "tail" */ 63 int tail; /* entinfo (s/w ring) tail index */ 64 void *outring; /* Base of output ring, DMA-safe */ 65 struct crypto_engine *engine; 66 }; 67 68 /* 69 * Driver-private storage for a single CAAM block instance 70 */ 71 struct caam_drv_private { 72 /* Physical-presence section */ 73 struct caam_ctrl __iomem *ctrl; /* controller region */ 74 struct caam_deco __iomem *deco; /* DECO/CCB views */ 75 struct caam_assurance __iomem *assure; 76 struct caam_queue_if __iomem *qi; /* QI control region */ 77 struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ 78 79 struct iommu_domain *domain; 80 81 /* 82 * Detected geometry block. Filled in from device tree if powerpc, 83 * or from register-based version detection code 84 */ 85 u8 total_jobrs; /* Total Job Rings in device */ 86 u8 qi_present; /* Nonzero if QI present in device */ 87 u8 mc_en; /* Nonzero if MC f/w is active */ 88 int secvio_irq; /* Security violation interrupt number */ 89 int virt_en; /* Virtualization enabled in CAAM */ 90 int era; /* CAAM Era (internal HW revision) */ 91 92 #define RNG4_MAX_HANDLES 2 93 /* RNG4 block */ 94 u32 rng4_sh_init; /* This bitmap shows which of the State 95 Handles of the RNG4 block are initialized 96 by this driver */ 97 98 struct clk_bulk_data *clks; 99 int num_clks; 100 /* 101 * debugfs entries for developer view into driver/device 102 * variables at runtime. 103 */ 104 #ifdef CONFIG_DEBUG_FS 105 struct dentry *ctl; /* controller dir */ 106 struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap; 107 #endif 108 }; 109 110 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API 111 112 int caam_algapi_init(struct device *dev); 113 void caam_algapi_exit(void); 114 115 #else 116 117 static inline int caam_algapi_init(struct device *dev) 118 { 119 return 0; 120 } 121 122 static inline void caam_algapi_exit(void) 123 { 124 } 125 126 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API */ 127 128 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API 129 130 int caam_algapi_hash_init(struct device *dev); 131 void caam_algapi_hash_exit(void); 132 133 #else 134 135 static inline int caam_algapi_hash_init(struct device *dev) 136 { 137 return 0; 138 } 139 140 static inline void caam_algapi_hash_exit(void) 141 { 142 } 143 144 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API */ 145 146 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API 147 148 int caam_pkc_init(struct device *dev); 149 void caam_pkc_exit(void); 150 151 #else 152 153 static inline int caam_pkc_init(struct device *dev) 154 { 155 return 0; 156 } 157 158 static inline void caam_pkc_exit(void) 159 { 160 } 161 162 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API */ 163 164 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API 165 166 int caam_rng_init(struct device *dev); 167 void caam_rng_exit(struct device *dev); 168 169 #else 170 171 static inline int caam_rng_init(struct device *dev) 172 { 173 return 0; 174 } 175 176 static inline void caam_rng_exit(struct device *dev) {} 177 178 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */ 179 180 #ifdef CONFIG_CAAM_QI 181 182 int caam_qi_algapi_init(struct device *dev); 183 void caam_qi_algapi_exit(void); 184 185 #else 186 187 static inline int caam_qi_algapi_init(struct device *dev) 188 { 189 return 0; 190 } 191 192 static inline void caam_qi_algapi_exit(void) 193 { 194 } 195 196 #endif /* CONFIG_CAAM_QI */ 197 198 static inline u64 caam_get_dma_mask(struct device *dev) 199 { 200 struct device_node *nprop = dev->of_node; 201 202 if (caam_ptr_sz != sizeof(u64)) 203 return DMA_BIT_MASK(32); 204 205 if (caam_dpaa2) 206 return DMA_BIT_MASK(49); 207 208 if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring") || 209 of_device_is_compatible(nprop, "fsl,sec-v5.0")) 210 return DMA_BIT_MASK(40); 211 212 return DMA_BIT_MASK(36); 213 } 214 215 216 #endif /* INTERN_H */ 217