xref: /openbmc/linux/drivers/crypto/caam/ctrl.c (revision e2f1cf25)
1 /* * CAAM control-plane driver backend
2  * Controller-level driver, kernel property detection, initialization
3  *
4  * Copyright 2008-2012 Freescale Semiconductor, Inc.
5  */
6 
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
10 
11 #include "compat.h"
12 #include "regs.h"
13 #include "intern.h"
14 #include "jr.h"
15 #include "desc_constr.h"
16 #include "error.h"
17 
18 /*
19  * Descriptor to instantiate RNG State Handle 0 in normal mode and
20  * load the JDKEK, TDKEK and TDSK registers
21  */
22 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
23 {
24 	u32 *jump_cmd, op_flags;
25 
26 	init_job_desc(desc, 0);
27 
28 	op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
29 			(handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
30 
31 	/* INIT RNG in non-test mode */
32 	append_operation(desc, op_flags);
33 
34 	if (!handle && do_sk) {
35 		/*
36 		 * For SH0, Secure Keys must be generated as well
37 		 */
38 
39 		/* wait for done */
40 		jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
41 		set_jump_tgt_here(desc, jump_cmd);
42 
43 		/*
44 		 * load 1 to clear written reg:
45 		 * resets the done interrrupt and returns the RNG to idle.
46 		 */
47 		append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
48 
49 		/* Initialize State Handle  */
50 		append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
51 				 OP_ALG_AAI_RNG4_SK);
52 	}
53 
54 	append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
55 }
56 
57 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
58 static void build_deinstantiation_desc(u32 *desc, int handle)
59 {
60 	init_job_desc(desc, 0);
61 
62 	/* Uninstantiate State Handle 0 */
63 	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
64 			 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
65 
66 	append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
67 }
68 
69 /*
70  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
71  *			  the software (no JR/QI used).
72  * @ctrldev - pointer to device
73  * @status - descriptor status, after being run
74  *
75  * Return: - 0 if no error occurred
76  *	   - -ENODEV if the DECO couldn't be acquired
77  *	   - -EAGAIN if an error occurred while executing the descriptor
78  */
79 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
80 					u32 *status)
81 {
82 	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
83 	struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
84 	struct caam_deco __iomem *deco = ctrlpriv->deco;
85 	unsigned int timeout = 100000;
86 	u32 deco_dbg_reg, flags;
87 	int i;
88 
89 
90 	if (ctrlpriv->virt_en == 1) {
91 		setbits32(&ctrl->deco_rsr, DECORSR_JR0);
92 
93 		while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
94 		       --timeout)
95 			cpu_relax();
96 
97 		timeout = 100000;
98 	}
99 
100 	setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
101 
102 	while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
103 								 --timeout)
104 		cpu_relax();
105 
106 	if (!timeout) {
107 		dev_err(ctrldev, "failed to acquire DECO 0\n");
108 		clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
109 		return -ENODEV;
110 	}
111 
112 	for (i = 0; i < desc_len(desc); i++)
113 		wr_reg32(&deco->descbuf[i], *(desc + i));
114 
115 	flags = DECO_JQCR_WHL;
116 	/*
117 	 * If the descriptor length is longer than 4 words, then the
118 	 * FOUR bit in JRCTRL register must be set.
119 	 */
120 	if (desc_len(desc) >= 4)
121 		flags |= DECO_JQCR_FOUR;
122 
123 	/* Instruct the DECO to execute it */
124 	wr_reg32(&deco->jr_ctl_hi, flags);
125 
126 	timeout = 10000000;
127 	do {
128 		deco_dbg_reg = rd_reg32(&deco->desc_dbg);
129 		/*
130 		 * If an error occured in the descriptor, then
131 		 * the DECO status field will be set to 0x0D
132 		 */
133 		if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
134 		    DESC_DBG_DECO_STAT_HOST_ERR)
135 			break;
136 		cpu_relax();
137 	} while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
138 
139 	*status = rd_reg32(&deco->op_status_hi) &
140 		  DECO_OP_STATUS_HI_ERR_MASK;
141 
142 	if (ctrlpriv->virt_en == 1)
143 		clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
144 
145 	/* Mark the DECO as free */
146 	clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
147 
148 	if (!timeout)
149 		return -EAGAIN;
150 
151 	return 0;
152 }
153 
154 /*
155  * instantiate_rng - builds and executes a descriptor on DECO0,
156  *		     which initializes the RNG block.
157  * @ctrldev - pointer to device
158  * @state_handle_mask - bitmask containing the instantiation status
159  *			for the RNG4 state handles which exist in
160  *			the RNG4 block: 1 if it's been instantiated
161  *			by an external entry, 0 otherwise.
162  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
163  *	      Caution: this can be done only once; if the keys need to be
164  *	      regenerated, a POR is required
165  *
166  * Return: - 0 if no error occurred
167  *	   - -ENOMEM if there isn't enough memory to allocate the descriptor
168  *	   - -ENODEV if DECO0 couldn't be acquired
169  *	   - -EAGAIN if an error occurred when executing the descriptor
170  *	      f.i. there was a RNG hardware error due to not "good enough"
171  *	      entropy being aquired.
172  */
173 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
174 			   int gen_sk)
175 {
176 	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
177 	struct caam_ctrl __iomem *ctrl;
178 	u32 *desc, status, rdsta_val;
179 	int ret = 0, sh_idx;
180 
181 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
182 	desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
183 	if (!desc)
184 		return -ENOMEM;
185 
186 	for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
187 		/*
188 		 * If the corresponding bit is set, this state handle
189 		 * was initialized by somebody else, so it's left alone.
190 		 */
191 		if ((1 << sh_idx) & state_handle_mask)
192 			continue;
193 
194 		/* Create the descriptor for instantiating RNG State Handle */
195 		build_instantiation_desc(desc, sh_idx, gen_sk);
196 
197 		/* Try to run it through DECO0 */
198 		ret = run_descriptor_deco0(ctrldev, desc, &status);
199 
200 		/*
201 		 * If ret is not 0, or descriptor status is not 0, then
202 		 * something went wrong. No need to try the next state
203 		 * handle (if available), bail out here.
204 		 * Also, if for some reason, the State Handle didn't get
205 		 * instantiated although the descriptor has finished
206 		 * without any error (HW optimizations for later
207 		 * CAAM eras), then try again.
208 		 */
209 		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
210 		if (status || !(rdsta_val & (1 << sh_idx)))
211 			ret = -EAGAIN;
212 		if (ret)
213 			break;
214 		dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
215 		/* Clear the contents before recreating the descriptor */
216 		memset(desc, 0x00, CAAM_CMD_SZ * 7);
217 	}
218 
219 	kfree(desc);
220 
221 	return ret;
222 }
223 
224 /*
225  * deinstantiate_rng - builds and executes a descriptor on DECO0,
226  *		       which deinitializes the RNG block.
227  * @ctrldev - pointer to device
228  * @state_handle_mask - bitmask containing the instantiation status
229  *			for the RNG4 state handles which exist in
230  *			the RNG4 block: 1 if it's been instantiated
231  *
232  * Return: - 0 if no error occurred
233  *	   - -ENOMEM if there isn't enough memory to allocate the descriptor
234  *	   - -ENODEV if DECO0 couldn't be acquired
235  *	   - -EAGAIN if an error occurred when executing the descriptor
236  */
237 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
238 {
239 	u32 *desc, status;
240 	int sh_idx, ret = 0;
241 
242 	desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
243 	if (!desc)
244 		return -ENOMEM;
245 
246 	for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
247 		/*
248 		 * If the corresponding bit is set, then it means the state
249 		 * handle was initialized by us, and thus it needs to be
250 		 * deintialized as well
251 		 */
252 		if ((1 << sh_idx) & state_handle_mask) {
253 			/*
254 			 * Create the descriptor for deinstantating this state
255 			 * handle
256 			 */
257 			build_deinstantiation_desc(desc, sh_idx);
258 
259 			/* Try to run it through DECO0 */
260 			ret = run_descriptor_deco0(ctrldev, desc, &status);
261 
262 			if (ret || status) {
263 				dev_err(ctrldev,
264 					"Failed to deinstantiate RNG4 SH%d\n",
265 					sh_idx);
266 				break;
267 			}
268 			dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
269 		}
270 	}
271 
272 	kfree(desc);
273 
274 	return ret;
275 }
276 
277 static int caam_remove(struct platform_device *pdev)
278 {
279 	struct device *ctrldev;
280 	struct caam_drv_private *ctrlpriv;
281 	struct caam_ctrl __iomem *ctrl;
282 	int ring, ret = 0;
283 
284 	ctrldev = &pdev->dev;
285 	ctrlpriv = dev_get_drvdata(ctrldev);
286 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
287 
288 	/* Remove platform devices for JobRs */
289 	for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
290 		if (ctrlpriv->jrpdev[ring])
291 			of_device_unregister(ctrlpriv->jrpdev[ring]);
292 	}
293 
294 	/* De-initialize RNG state handles initialized by this driver. */
295 	if (ctrlpriv->rng4_sh_init)
296 		deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
297 
298 	/* Shut down debug views */
299 #ifdef CONFIG_DEBUG_FS
300 	debugfs_remove_recursive(ctrlpriv->dfs_root);
301 #endif
302 
303 	/* Unmap controller region */
304 	iounmap(ctrl);
305 
306 	return ret;
307 }
308 
309 /*
310  * kick_trng - sets the various parameters for enabling the initialization
311  *	       of the RNG4 block in CAAM
312  * @pdev - pointer to the platform device
313  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
314  */
315 static void kick_trng(struct platform_device *pdev, int ent_delay)
316 {
317 	struct device *ctrldev = &pdev->dev;
318 	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
319 	struct caam_ctrl __iomem *ctrl;
320 	struct rng4tst __iomem *r4tst;
321 	u32 val;
322 
323 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
324 	r4tst = &ctrl->r4tst[0];
325 
326 	/* put RNG4 into program mode */
327 	setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
328 
329 	/*
330 	 * Performance-wise, it does not make sense to
331 	 * set the delay to a value that is lower
332 	 * than the last one that worked (i.e. the state handles
333 	 * were instantiated properly. Thus, instead of wasting
334 	 * time trying to set the values controlling the sample
335 	 * frequency, the function simply returns.
336 	 */
337 	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
338 	      >> RTSDCTL_ENT_DLY_SHIFT;
339 	if (ent_delay <= val) {
340 		/* put RNG4 into run mode */
341 		clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
342 		return;
343 	}
344 
345 	val = rd_reg32(&r4tst->rtsdctl);
346 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
347 	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
348 	wr_reg32(&r4tst->rtsdctl, val);
349 	/* min. freq. count, equal to 1/4 of the entropy sample length */
350 	wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
351 	/* disable maximum frequency count */
352 	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
353 	/* read the control register */
354 	val = rd_reg32(&r4tst->rtmctl);
355 	/*
356 	 * select raw sampling in both entropy shifter
357 	 * and statistical checker
358 	 */
359 	setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
360 	/* put RNG4 into run mode */
361 	clrbits32(&val, RTMCTL_PRGM);
362 	/* write back the control register */
363 	wr_reg32(&r4tst->rtmctl, val);
364 }
365 
366 /**
367  * caam_get_era() - Return the ERA of the SEC on SoC, based
368  * on "sec-era" propery in the DTS. This property is updated by u-boot.
369  **/
370 int caam_get_era(void)
371 {
372 	struct device_node *caam_node;
373 	for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") {
374 		const uint32_t *prop = (uint32_t *)of_get_property(caam_node,
375 				"fsl,sec-era",
376 				NULL);
377 		return prop ? *prop : -ENOTSUPP;
378 	}
379 
380 	return -ENOTSUPP;
381 }
382 EXPORT_SYMBOL(caam_get_era);
383 
384 /* Probe routine for CAAM top (controller) level */
385 static int caam_probe(struct platform_device *pdev)
386 {
387 	int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
388 	u64 caam_id;
389 	struct device *dev;
390 	struct device_node *nprop, *np;
391 	struct caam_ctrl __iomem *ctrl;
392 	struct caam_drv_private *ctrlpriv;
393 #ifdef CONFIG_DEBUG_FS
394 	struct caam_perfmon *perfmon;
395 #endif
396 	u32 scfgr, comp_params;
397 	u32 cha_vid_ls;
398 	int pg_size;
399 	int BLOCK_OFFSET = 0;
400 
401 	ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
402 				GFP_KERNEL);
403 	if (!ctrlpriv)
404 		return -ENOMEM;
405 
406 	dev = &pdev->dev;
407 	dev_set_drvdata(dev, ctrlpriv);
408 	ctrlpriv->pdev = pdev;
409 	nprop = pdev->dev.of_node;
410 
411 	/* Get configuration properties from device tree */
412 	/* First, get register page */
413 	ctrl = of_iomap(nprop, 0);
414 	if (ctrl == NULL) {
415 		dev_err(dev, "caam: of_iomap() failed\n");
416 		return -ENOMEM;
417 	}
418 	/* Finding the page size for using the CTPR_MS register */
419 	comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
420 	pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
421 
422 	/* Allocating the BLOCK_OFFSET based on the supported page size on
423 	 * the platform
424 	 */
425 	if (pg_size == 0)
426 		BLOCK_OFFSET = PG_SIZE_4K;
427 	else
428 		BLOCK_OFFSET = PG_SIZE_64K;
429 
430 	ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
431 	ctrlpriv->assure = (struct caam_assurance __force *)
432 			   ((uint8_t *)ctrl +
433 			    BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
434 			   );
435 	ctrlpriv->deco = (struct caam_deco __force *)
436 			 ((uint8_t *)ctrl +
437 			 BLOCK_OFFSET * DECO_BLOCK_NUMBER
438 			 );
439 
440 	/* Get the IRQ of the controller (for security violations only) */
441 	ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
442 
443 	/*
444 	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
445 	 * long pointers in master configuration register
446 	 */
447 	setbits32(&ctrl->mcr, MCFGR_WDENABLE |
448 		  (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
449 
450 	/*
451 	 *  Read the Compile Time paramters and SCFGR to determine
452 	 * if Virtualization is enabled for this platform
453 	 */
454 	scfgr = rd_reg32(&ctrl->scfgr);
455 
456 	ctrlpriv->virt_en = 0;
457 	if (comp_params & CTPR_MS_VIRT_EN_INCL) {
458 		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
459 		 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
460 		 */
461 		if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
462 		    (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
463 		       (scfgr & SCFGR_VIRT_EN)))
464 				ctrlpriv->virt_en = 1;
465 	} else {
466 		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
467 		if (comp_params & CTPR_MS_VIRT_EN_POR)
468 				ctrlpriv->virt_en = 1;
469 	}
470 
471 	if (ctrlpriv->virt_en == 1)
472 		setbits32(&ctrl->jrstart, JRSTART_JR0_START |
473 			  JRSTART_JR1_START | JRSTART_JR2_START |
474 			  JRSTART_JR3_START);
475 
476 	if (sizeof(dma_addr_t) == sizeof(u64))
477 		if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
478 			dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
479 		else
480 			dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
481 	else
482 		dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
483 
484 	/*
485 	 * Detect and enable JobRs
486 	 * First, find out how many ring spec'ed, allocate references
487 	 * for all, then go probe each one.
488 	 */
489 	rspec = 0;
490 	for_each_available_child_of_node(nprop, np)
491 		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
492 		    of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
493 			rspec++;
494 
495 	ctrlpriv->jrpdev = devm_kzalloc(&pdev->dev,
496 					sizeof(struct platform_device *) * rspec,
497 					GFP_KERNEL);
498 	if (ctrlpriv->jrpdev == NULL) {
499 		iounmap(ctrl);
500 		return -ENOMEM;
501 	}
502 
503 	ring = 0;
504 	ctrlpriv->total_jobrs = 0;
505 	for_each_available_child_of_node(nprop, np)
506 		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
507 		    of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
508 			ctrlpriv->jrpdev[ring] =
509 				of_platform_device_create(np, NULL, dev);
510 			if (!ctrlpriv->jrpdev[ring]) {
511 				pr_warn("JR%d Platform device creation error\n",
512 					ring);
513 				continue;
514 			}
515 			ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
516 					     ((uint8_t *)ctrl +
517 					     (ring + JR_BLOCK_NUMBER) *
518 					      BLOCK_OFFSET
519 					     );
520 			ctrlpriv->total_jobrs++;
521 			ring++;
522 	}
523 
524 	/* Check to see if QI present. If so, enable */
525 	ctrlpriv->qi_present =
526 			!!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
527 			   CTPR_MS_QI_MASK);
528 	if (ctrlpriv->qi_present) {
529 		ctrlpriv->qi = (struct caam_queue_if __force *)
530 			       ((uint8_t *)ctrl +
531 				 BLOCK_OFFSET * QI_BLOCK_NUMBER
532 			       );
533 		/* This is all that's required to physically enable QI */
534 		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
535 	}
536 
537 	/* If no QI and no rings specified, quit and go home */
538 	if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
539 		dev_err(dev, "no queues configured, terminating\n");
540 		caam_remove(pdev);
541 		return -ENOMEM;
542 	}
543 
544 	cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
545 
546 	/*
547 	 * If SEC has RNG version >= 4 and RNG state handle has not been
548 	 * already instantiated, do RNG instantiation
549 	 */
550 	if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
551 		ctrlpriv->rng4_sh_init =
552 			rd_reg32(&ctrl->r4tst[0].rdsta);
553 		/*
554 		 * If the secure keys (TDKEK, JDKEK, TDSK), were already
555 		 * generated, signal this to the function that is instantiating
556 		 * the state handles. An error would occur if RNG4 attempts
557 		 * to regenerate these keys before the next POR.
558 		 */
559 		gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
560 		ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
561 		do {
562 			int inst_handles =
563 				rd_reg32(&ctrl->r4tst[0].rdsta) &
564 								RDSTA_IFMASK;
565 			/*
566 			 * If either SH were instantiated by somebody else
567 			 * (e.g. u-boot) then it is assumed that the entropy
568 			 * parameters are properly set and thus the function
569 			 * setting these (kick_trng(...)) is skipped.
570 			 * Also, if a handle was instantiated, do not change
571 			 * the TRNG parameters.
572 			 */
573 			if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
574 				dev_info(dev,
575 					 "Entropy delay = %u\n",
576 					 ent_delay);
577 				kick_trng(pdev, ent_delay);
578 				ent_delay += 400;
579 			}
580 			/*
581 			 * if instantiate_rng(...) fails, the loop will rerun
582 			 * and the kick_trng(...) function will modfiy the
583 			 * upper and lower limits of the entropy sampling
584 			 * interval, leading to a sucessful initialization of
585 			 * the RNG.
586 			 */
587 			ret = instantiate_rng(dev, inst_handles,
588 					      gen_sk);
589 			if (ret == -EAGAIN)
590 				/*
591 				 * if here, the loop will rerun,
592 				 * so don't hog the CPU
593 				 */
594 				cpu_relax();
595 		} while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
596 		if (ret) {
597 			dev_err(dev, "failed to instantiate RNG");
598 			caam_remove(pdev);
599 			return ret;
600 		}
601 		/*
602 		 * Set handles init'ed by this module as the complement of the
603 		 * already initialized ones
604 		 */
605 		ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
606 
607 		/* Enable RDB bit so that RNG works faster */
608 		setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
609 	}
610 
611 	/* NOTE: RTIC detection ought to go here, around Si time */
612 
613 	caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
614 		  (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
615 
616 	/* Report "alive" for developer to see */
617 	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
618 		 caam_get_era());
619 	dev_info(dev, "job rings = %d, qi = %d\n",
620 		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
621 
622 #ifdef CONFIG_DEBUG_FS
623 	/*
624 	 * FIXME: needs better naming distinction, as some amalgamation of
625 	 * "caam" and nprop->full_name. The OF name isn't distinctive,
626 	 * but does separate instances
627 	 */
628 	perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
629 
630 	ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
631 	ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
632 
633 	/* Controller-level - performance monitor counters */
634 	ctrlpriv->ctl_rq_dequeued =
635 		debugfs_create_u64("rq_dequeued",
636 				   S_IRUSR | S_IRGRP | S_IROTH,
637 				   ctrlpriv->ctl, &perfmon->req_dequeued);
638 	ctrlpriv->ctl_ob_enc_req =
639 		debugfs_create_u64("ob_rq_encrypted",
640 				   S_IRUSR | S_IRGRP | S_IROTH,
641 				   ctrlpriv->ctl, &perfmon->ob_enc_req);
642 	ctrlpriv->ctl_ib_dec_req =
643 		debugfs_create_u64("ib_rq_decrypted",
644 				   S_IRUSR | S_IRGRP | S_IROTH,
645 				   ctrlpriv->ctl, &perfmon->ib_dec_req);
646 	ctrlpriv->ctl_ob_enc_bytes =
647 		debugfs_create_u64("ob_bytes_encrypted",
648 				   S_IRUSR | S_IRGRP | S_IROTH,
649 				   ctrlpriv->ctl, &perfmon->ob_enc_bytes);
650 	ctrlpriv->ctl_ob_prot_bytes =
651 		debugfs_create_u64("ob_bytes_protected",
652 				   S_IRUSR | S_IRGRP | S_IROTH,
653 				   ctrlpriv->ctl, &perfmon->ob_prot_bytes);
654 	ctrlpriv->ctl_ib_dec_bytes =
655 		debugfs_create_u64("ib_bytes_decrypted",
656 				   S_IRUSR | S_IRGRP | S_IROTH,
657 				   ctrlpriv->ctl, &perfmon->ib_dec_bytes);
658 	ctrlpriv->ctl_ib_valid_bytes =
659 		debugfs_create_u64("ib_bytes_validated",
660 				   S_IRUSR | S_IRGRP | S_IROTH,
661 				   ctrlpriv->ctl, &perfmon->ib_valid_bytes);
662 
663 	/* Controller level - global status values */
664 	ctrlpriv->ctl_faultaddr =
665 		debugfs_create_u64("fault_addr",
666 				   S_IRUSR | S_IRGRP | S_IROTH,
667 				   ctrlpriv->ctl, &perfmon->faultaddr);
668 	ctrlpriv->ctl_faultdetail =
669 		debugfs_create_u32("fault_detail",
670 				   S_IRUSR | S_IRGRP | S_IROTH,
671 				   ctrlpriv->ctl, &perfmon->faultdetail);
672 	ctrlpriv->ctl_faultstatus =
673 		debugfs_create_u32("fault_status",
674 				   S_IRUSR | S_IRGRP | S_IROTH,
675 				   ctrlpriv->ctl, &perfmon->status);
676 
677 	/* Internal covering keys (useful in non-secure mode only) */
678 	ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
679 	ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
680 	ctrlpriv->ctl_kek = debugfs_create_blob("kek",
681 						S_IRUSR |
682 						S_IRGRP | S_IROTH,
683 						ctrlpriv->ctl,
684 						&ctrlpriv->ctl_kek_wrap);
685 
686 	ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
687 	ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
688 	ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
689 						 S_IRUSR |
690 						 S_IRGRP | S_IROTH,
691 						 ctrlpriv->ctl,
692 						 &ctrlpriv->ctl_tkek_wrap);
693 
694 	ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
695 	ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
696 	ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
697 						 S_IRUSR |
698 						 S_IRGRP | S_IROTH,
699 						 ctrlpriv->ctl,
700 						 &ctrlpriv->ctl_tdsk_wrap);
701 #endif
702 	return 0;
703 }
704 
705 static struct of_device_id caam_match[] = {
706 	{
707 		.compatible = "fsl,sec-v4.0",
708 	},
709 	{
710 		.compatible = "fsl,sec4.0",
711 	},
712 	{},
713 };
714 MODULE_DEVICE_TABLE(of, caam_match);
715 
716 static struct platform_driver caam_driver = {
717 	.driver = {
718 		.name = "caam",
719 		.of_match_table = caam_match,
720 	},
721 	.probe       = caam_probe,
722 	.remove      = caam_remove,
723 };
724 
725 module_platform_driver(caam_driver);
726 
727 MODULE_LICENSE("GPL");
728 MODULE_DESCRIPTION("FSL CAAM request backend");
729 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
730