1 /* * CAAM control-plane driver backend 2 * Controller-level driver, kernel property detection, initialization 3 * 4 * Copyright 2008-2012 Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/of_address.h> 9 #include <linux/of_irq.h> 10 #include <linux/sys_soc.h> 11 12 #include "compat.h" 13 #include "regs.h" 14 #include "intern.h" 15 #include "jr.h" 16 #include "desc_constr.h" 17 #include "ctrl.h" 18 19 bool caam_little_end; 20 EXPORT_SYMBOL(caam_little_end); 21 bool caam_dpaa2; 22 EXPORT_SYMBOL(caam_dpaa2); 23 bool caam_imx; 24 EXPORT_SYMBOL(caam_imx); 25 26 #ifdef CONFIG_CAAM_QI 27 #include "qi.h" 28 #endif 29 30 /* 31 * i.MX targets tend to have clock control subsystems that can 32 * enable/disable clocking to our device. 33 */ 34 static inline struct clk *caam_drv_identify_clk(struct device *dev, 35 char *clk_name) 36 { 37 return caam_imx ? devm_clk_get(dev, clk_name) : NULL; 38 } 39 40 /* 41 * Descriptor to instantiate RNG State Handle 0 in normal mode and 42 * load the JDKEK, TDKEK and TDSK registers 43 */ 44 static void build_instantiation_desc(u32 *desc, int handle, int do_sk) 45 { 46 u32 *jump_cmd, op_flags; 47 48 init_job_desc(desc, 0); 49 50 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 51 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; 52 53 /* INIT RNG in non-test mode */ 54 append_operation(desc, op_flags); 55 56 if (!handle && do_sk) { 57 /* 58 * For SH0, Secure Keys must be generated as well 59 */ 60 61 /* wait for done */ 62 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); 63 set_jump_tgt_here(desc, jump_cmd); 64 65 /* 66 * load 1 to clear written reg: 67 * resets the done interrrupt and returns the RNG to idle. 68 */ 69 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); 70 71 /* Initialize State Handle */ 72 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 73 OP_ALG_AAI_RNG4_SK); 74 } 75 76 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 77 } 78 79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ 80 static void build_deinstantiation_desc(u32 *desc, int handle) 81 { 82 init_job_desc(desc, 0); 83 84 /* Uninstantiate State Handle 0 */ 85 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 86 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); 87 88 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 89 } 90 91 /* 92 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of 93 * the software (no JR/QI used). 94 * @ctrldev - pointer to device 95 * @status - descriptor status, after being run 96 * 97 * Return: - 0 if no error occurred 98 * - -ENODEV if the DECO couldn't be acquired 99 * - -EAGAIN if an error occurred while executing the descriptor 100 */ 101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, 102 u32 *status) 103 { 104 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 105 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; 106 struct caam_deco __iomem *deco = ctrlpriv->deco; 107 unsigned int timeout = 100000; 108 u32 deco_dbg_reg, flags; 109 int i; 110 111 112 if (ctrlpriv->virt_en == 1) { 113 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); 114 115 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && 116 --timeout) 117 cpu_relax(); 118 119 timeout = 100000; 120 } 121 122 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); 123 124 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && 125 --timeout) 126 cpu_relax(); 127 128 if (!timeout) { 129 dev_err(ctrldev, "failed to acquire DECO 0\n"); 130 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 131 return -ENODEV; 132 } 133 134 for (i = 0; i < desc_len(desc); i++) 135 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); 136 137 flags = DECO_JQCR_WHL; 138 /* 139 * If the descriptor length is longer than 4 words, then the 140 * FOUR bit in JRCTRL register must be set. 141 */ 142 if (desc_len(desc) >= 4) 143 flags |= DECO_JQCR_FOUR; 144 145 /* Instruct the DECO to execute it */ 146 clrsetbits_32(&deco->jr_ctl_hi, 0, flags); 147 148 timeout = 10000000; 149 do { 150 deco_dbg_reg = rd_reg32(&deco->desc_dbg); 151 /* 152 * If an error occured in the descriptor, then 153 * the DECO status field will be set to 0x0D 154 */ 155 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == 156 DESC_DBG_DECO_STAT_HOST_ERR) 157 break; 158 cpu_relax(); 159 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); 160 161 *status = rd_reg32(&deco->op_status_hi) & 162 DECO_OP_STATUS_HI_ERR_MASK; 163 164 if (ctrlpriv->virt_en == 1) 165 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); 166 167 /* Mark the DECO as free */ 168 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 169 170 if (!timeout) 171 return -EAGAIN; 172 173 return 0; 174 } 175 176 /* 177 * instantiate_rng - builds and executes a descriptor on DECO0, 178 * which initializes the RNG block. 179 * @ctrldev - pointer to device 180 * @state_handle_mask - bitmask containing the instantiation status 181 * for the RNG4 state handles which exist in 182 * the RNG4 block: 1 if it's been instantiated 183 * by an external entry, 0 otherwise. 184 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; 185 * Caution: this can be done only once; if the keys need to be 186 * regenerated, a POR is required 187 * 188 * Return: - 0 if no error occurred 189 * - -ENOMEM if there isn't enough memory to allocate the descriptor 190 * - -ENODEV if DECO0 couldn't be acquired 191 * - -EAGAIN if an error occurred when executing the descriptor 192 * f.i. there was a RNG hardware error due to not "good enough" 193 * entropy being aquired. 194 */ 195 static int instantiate_rng(struct device *ctrldev, int state_handle_mask, 196 int gen_sk) 197 { 198 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 199 struct caam_ctrl __iomem *ctrl; 200 u32 *desc, status = 0, rdsta_val; 201 int ret = 0, sh_idx; 202 203 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 204 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); 205 if (!desc) 206 return -ENOMEM; 207 208 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 209 /* 210 * If the corresponding bit is set, this state handle 211 * was initialized by somebody else, so it's left alone. 212 */ 213 if ((1 << sh_idx) & state_handle_mask) 214 continue; 215 216 /* Create the descriptor for instantiating RNG State Handle */ 217 build_instantiation_desc(desc, sh_idx, gen_sk); 218 219 /* Try to run it through DECO0 */ 220 ret = run_descriptor_deco0(ctrldev, desc, &status); 221 222 /* 223 * If ret is not 0, or descriptor status is not 0, then 224 * something went wrong. No need to try the next state 225 * handle (if available), bail out here. 226 * Also, if for some reason, the State Handle didn't get 227 * instantiated although the descriptor has finished 228 * without any error (HW optimizations for later 229 * CAAM eras), then try again. 230 */ 231 if (ret) 232 break; 233 234 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; 235 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || 236 !(rdsta_val & (1 << sh_idx))) { 237 ret = -EAGAIN; 238 break; 239 } 240 241 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); 242 /* Clear the contents before recreating the descriptor */ 243 memset(desc, 0x00, CAAM_CMD_SZ * 7); 244 } 245 246 kfree(desc); 247 248 return ret; 249 } 250 251 /* 252 * deinstantiate_rng - builds and executes a descriptor on DECO0, 253 * which deinitializes the RNG block. 254 * @ctrldev - pointer to device 255 * @state_handle_mask - bitmask containing the instantiation status 256 * for the RNG4 state handles which exist in 257 * the RNG4 block: 1 if it's been instantiated 258 * 259 * Return: - 0 if no error occurred 260 * - -ENOMEM if there isn't enough memory to allocate the descriptor 261 * - -ENODEV if DECO0 couldn't be acquired 262 * - -EAGAIN if an error occurred when executing the descriptor 263 */ 264 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) 265 { 266 u32 *desc, status; 267 int sh_idx, ret = 0; 268 269 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); 270 if (!desc) 271 return -ENOMEM; 272 273 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 274 /* 275 * If the corresponding bit is set, then it means the state 276 * handle was initialized by us, and thus it needs to be 277 * deinitialized as well 278 */ 279 if ((1 << sh_idx) & state_handle_mask) { 280 /* 281 * Create the descriptor for deinstantating this state 282 * handle 283 */ 284 build_deinstantiation_desc(desc, sh_idx); 285 286 /* Try to run it through DECO0 */ 287 ret = run_descriptor_deco0(ctrldev, desc, &status); 288 289 if (ret || 290 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) { 291 dev_err(ctrldev, 292 "Failed to deinstantiate RNG4 SH%d\n", 293 sh_idx); 294 break; 295 } 296 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); 297 } 298 } 299 300 kfree(desc); 301 302 return ret; 303 } 304 305 static int caam_remove(struct platform_device *pdev) 306 { 307 struct device *ctrldev; 308 struct caam_drv_private *ctrlpriv; 309 struct caam_ctrl __iomem *ctrl; 310 311 ctrldev = &pdev->dev; 312 ctrlpriv = dev_get_drvdata(ctrldev); 313 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 314 315 /* Remove platform devices under the crypto node */ 316 of_platform_depopulate(ctrldev); 317 318 #ifdef CONFIG_CAAM_QI 319 if (ctrlpriv->qidev) 320 caam_qi_shutdown(ctrlpriv->qidev); 321 #endif 322 323 /* 324 * De-initialize RNG state handles initialized by this driver. 325 * In case of DPAA 2.x, RNG is managed by MC firmware. 326 */ 327 if (!caam_dpaa2 && ctrlpriv->rng4_sh_init) 328 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); 329 330 /* Shut down debug views */ 331 #ifdef CONFIG_DEBUG_FS 332 debugfs_remove_recursive(ctrlpriv->dfs_root); 333 #endif 334 335 /* Unmap controller region */ 336 iounmap(ctrl); 337 338 /* shut clocks off before finalizing shutdown */ 339 clk_disable_unprepare(ctrlpriv->caam_ipg); 340 clk_disable_unprepare(ctrlpriv->caam_mem); 341 clk_disable_unprepare(ctrlpriv->caam_aclk); 342 if (ctrlpriv->caam_emi_slow) 343 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 344 return 0; 345 } 346 347 /* 348 * kick_trng - sets the various parameters for enabling the initialization 349 * of the RNG4 block in CAAM 350 * @pdev - pointer to the platform device 351 * @ent_delay - Defines the length (in system clocks) of each entropy sample. 352 */ 353 static void kick_trng(struct platform_device *pdev, int ent_delay) 354 { 355 struct device *ctrldev = &pdev->dev; 356 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 357 struct caam_ctrl __iomem *ctrl; 358 struct rng4tst __iomem *r4tst; 359 u32 val; 360 361 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 362 r4tst = &ctrl->r4tst[0]; 363 364 /* put RNG4 into program mode */ 365 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); 366 367 /* 368 * Performance-wise, it does not make sense to 369 * set the delay to a value that is lower 370 * than the last one that worked (i.e. the state handles 371 * were instantiated properly. Thus, instead of wasting 372 * time trying to set the values controlling the sample 373 * frequency, the function simply returns. 374 */ 375 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) 376 >> RTSDCTL_ENT_DLY_SHIFT; 377 if (ent_delay <= val) 378 goto start_rng; 379 380 val = rd_reg32(&r4tst->rtsdctl); 381 val = (val & ~RTSDCTL_ENT_DLY_MASK) | 382 (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 383 wr_reg32(&r4tst->rtsdctl, val); 384 /* min. freq. count, equal to 1/4 of the entropy sample length */ 385 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); 386 /* disable maximum frequency count */ 387 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); 388 /* read the control register */ 389 val = rd_reg32(&r4tst->rtmctl); 390 start_rng: 391 /* 392 * select raw sampling in both entropy shifter 393 * and statistical checker; ; put RNG4 into run mode 394 */ 395 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); 396 } 397 398 /** 399 * caam_get_era() - Return the ERA of the SEC on SoC, based 400 * on "sec-era" propery in the DTS. This property is updated by u-boot. 401 **/ 402 int caam_get_era(void) 403 { 404 struct device_node *caam_node; 405 int ret; 406 u32 prop; 407 408 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 409 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); 410 of_node_put(caam_node); 411 412 return ret ? -ENOTSUPP : prop; 413 } 414 EXPORT_SYMBOL(caam_get_era); 415 416 static const struct of_device_id caam_match[] = { 417 { 418 .compatible = "fsl,sec-v4.0", 419 }, 420 { 421 .compatible = "fsl,sec4.0", 422 }, 423 {}, 424 }; 425 MODULE_DEVICE_TABLE(of, caam_match); 426 427 /* Probe routine for CAAM top (controller) level */ 428 static int caam_probe(struct platform_device *pdev) 429 { 430 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; 431 u64 caam_id; 432 static const struct soc_device_attribute imx_soc[] = { 433 {.family = "Freescale i.MX"}, 434 {}, 435 }; 436 struct device *dev; 437 struct device_node *nprop, *np; 438 struct caam_ctrl __iomem *ctrl; 439 struct caam_drv_private *ctrlpriv; 440 struct clk *clk; 441 #ifdef CONFIG_DEBUG_FS 442 struct caam_perfmon *perfmon; 443 #endif 444 u32 scfgr, comp_params; 445 u32 cha_vid_ls; 446 int pg_size; 447 int BLOCK_OFFSET = 0; 448 449 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); 450 if (!ctrlpriv) 451 return -ENOMEM; 452 453 dev = &pdev->dev; 454 dev_set_drvdata(dev, ctrlpriv); 455 nprop = pdev->dev.of_node; 456 457 caam_imx = (bool)soc_device_match(imx_soc); 458 459 /* Enable clocking */ 460 clk = caam_drv_identify_clk(&pdev->dev, "ipg"); 461 if (IS_ERR(clk)) { 462 ret = PTR_ERR(clk); 463 dev_err(&pdev->dev, 464 "can't identify CAAM ipg clk: %d\n", ret); 465 return ret; 466 } 467 ctrlpriv->caam_ipg = clk; 468 469 clk = caam_drv_identify_clk(&pdev->dev, "mem"); 470 if (IS_ERR(clk)) { 471 ret = PTR_ERR(clk); 472 dev_err(&pdev->dev, 473 "can't identify CAAM mem clk: %d\n", ret); 474 return ret; 475 } 476 ctrlpriv->caam_mem = clk; 477 478 clk = caam_drv_identify_clk(&pdev->dev, "aclk"); 479 if (IS_ERR(clk)) { 480 ret = PTR_ERR(clk); 481 dev_err(&pdev->dev, 482 "can't identify CAAM aclk clk: %d\n", ret); 483 return ret; 484 } 485 ctrlpriv->caam_aclk = clk; 486 487 if (!of_machine_is_compatible("fsl,imx6ul")) { 488 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); 489 if (IS_ERR(clk)) { 490 ret = PTR_ERR(clk); 491 dev_err(&pdev->dev, 492 "can't identify CAAM emi_slow clk: %d\n", ret); 493 return ret; 494 } 495 ctrlpriv->caam_emi_slow = clk; 496 } 497 498 ret = clk_prepare_enable(ctrlpriv->caam_ipg); 499 if (ret < 0) { 500 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); 501 return ret; 502 } 503 504 ret = clk_prepare_enable(ctrlpriv->caam_mem); 505 if (ret < 0) { 506 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", 507 ret); 508 goto disable_caam_ipg; 509 } 510 511 ret = clk_prepare_enable(ctrlpriv->caam_aclk); 512 if (ret < 0) { 513 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); 514 goto disable_caam_mem; 515 } 516 517 if (ctrlpriv->caam_emi_slow) { 518 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); 519 if (ret < 0) { 520 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", 521 ret); 522 goto disable_caam_aclk; 523 } 524 } 525 526 /* Get configuration properties from device tree */ 527 /* First, get register page */ 528 ctrl = of_iomap(nprop, 0); 529 if (ctrl == NULL) { 530 dev_err(dev, "caam: of_iomap() failed\n"); 531 ret = -ENOMEM; 532 goto disable_caam_emi_slow; 533 } 534 535 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & 536 (CSTA_PLEND | CSTA_ALT_PLEND)); 537 538 /* Finding the page size for using the CTPR_MS register */ 539 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); 540 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; 541 542 /* Allocating the BLOCK_OFFSET based on the supported page size on 543 * the platform 544 */ 545 if (pg_size == 0) 546 BLOCK_OFFSET = PG_SIZE_4K; 547 else 548 BLOCK_OFFSET = PG_SIZE_64K; 549 550 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; 551 ctrlpriv->assure = (struct caam_assurance __iomem __force *) 552 ((__force uint8_t *)ctrl + 553 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER 554 ); 555 ctrlpriv->deco = (struct caam_deco __iomem __force *) 556 ((__force uint8_t *)ctrl + 557 BLOCK_OFFSET * DECO_BLOCK_NUMBER 558 ); 559 560 /* Get the IRQ of the controller (for security violations only) */ 561 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); 562 563 /* 564 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, 565 * long pointers in master configuration register. 566 * In case of DPAA 2.x, Management Complex firmware performs 567 * the configuration. 568 */ 569 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2); 570 if (!caam_dpaa2) 571 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR, 572 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF | 573 MCFGR_WDENABLE | MCFGR_LARGE_BURST | 574 (sizeof(dma_addr_t) == sizeof(u64) ? 575 MCFGR_LONG_PTR : 0)); 576 577 /* 578 * Read the Compile Time paramters and SCFGR to determine 579 * if Virtualization is enabled for this platform 580 */ 581 scfgr = rd_reg32(&ctrl->scfgr); 582 583 ctrlpriv->virt_en = 0; 584 if (comp_params & CTPR_MS_VIRT_EN_INCL) { 585 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or 586 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 587 */ 588 if ((comp_params & CTPR_MS_VIRT_EN_POR) || 589 (!(comp_params & CTPR_MS_VIRT_EN_POR) && 590 (scfgr & SCFGR_VIRT_EN))) 591 ctrlpriv->virt_en = 1; 592 } else { 593 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ 594 if (comp_params & CTPR_MS_VIRT_EN_POR) 595 ctrlpriv->virt_en = 1; 596 } 597 598 if (ctrlpriv->virt_en == 1) 599 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | 600 JRSTART_JR1_START | JRSTART_JR2_START | 601 JRSTART_JR3_START); 602 603 if (sizeof(dma_addr_t) == sizeof(u64)) { 604 if (caam_dpaa2) 605 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49)); 606 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) 607 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 608 else 609 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 610 } else { 611 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 612 } 613 if (ret) { 614 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); 615 goto iounmap_ctrl; 616 } 617 618 ctrlpriv->era = caam_get_era(); 619 620 ret = of_platform_populate(nprop, caam_match, NULL, dev); 621 if (ret) { 622 dev_err(dev, "JR platform devices creation error\n"); 623 goto iounmap_ctrl; 624 } 625 626 #ifdef CONFIG_DEBUG_FS 627 /* 628 * FIXME: needs better naming distinction, as some amalgamation of 629 * "caam" and nprop->full_name. The OF name isn't distinctive, 630 * but does separate instances 631 */ 632 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; 633 634 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); 635 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); 636 #endif 637 638 ring = 0; 639 for_each_available_child_of_node(nprop, np) 640 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || 641 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { 642 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) 643 ((__force uint8_t *)ctrl + 644 (ring + JR_BLOCK_NUMBER) * 645 BLOCK_OFFSET 646 ); 647 ctrlpriv->total_jobrs++; 648 ring++; 649 } 650 651 /* Check to see if (DPAA 1.x) QI present. If so, enable */ 652 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK); 653 if (ctrlpriv->qi_present && !caam_dpaa2) { 654 ctrlpriv->qi = (struct caam_queue_if __iomem __force *) 655 ((__force uint8_t *)ctrl + 656 BLOCK_OFFSET * QI_BLOCK_NUMBER 657 ); 658 /* This is all that's required to physically enable QI */ 659 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); 660 661 /* If QMAN driver is present, init CAAM-QI backend */ 662 #ifdef CONFIG_CAAM_QI 663 ret = caam_qi_init(pdev); 664 if (ret) 665 dev_err(dev, "caam qi i/f init failed: %d\n", ret); 666 #endif 667 } 668 669 /* If no QI and no rings specified, quit and go home */ 670 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { 671 dev_err(dev, "no queues configured, terminating\n"); 672 ret = -ENOMEM; 673 goto caam_remove; 674 } 675 676 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); 677 678 /* 679 * If SEC has RNG version >= 4 and RNG state handle has not been 680 * already instantiated, do RNG instantiation 681 * In case of DPAA 2.x, RNG is managed by MC firmware. 682 */ 683 if (!caam_dpaa2 && 684 (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { 685 ctrlpriv->rng4_sh_init = 686 rd_reg32(&ctrl->r4tst[0].rdsta); 687 /* 688 * If the secure keys (TDKEK, JDKEK, TDSK), were already 689 * generated, signal this to the function that is instantiating 690 * the state handles. An error would occur if RNG4 attempts 691 * to regenerate these keys before the next POR. 692 */ 693 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; 694 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; 695 do { 696 int inst_handles = 697 rd_reg32(&ctrl->r4tst[0].rdsta) & 698 RDSTA_IFMASK; 699 /* 700 * If either SH were instantiated by somebody else 701 * (e.g. u-boot) then it is assumed that the entropy 702 * parameters are properly set and thus the function 703 * setting these (kick_trng(...)) is skipped. 704 * Also, if a handle was instantiated, do not change 705 * the TRNG parameters. 706 */ 707 if (!(ctrlpriv->rng4_sh_init || inst_handles)) { 708 dev_info(dev, 709 "Entropy delay = %u\n", 710 ent_delay); 711 kick_trng(pdev, ent_delay); 712 ent_delay += 400; 713 } 714 /* 715 * if instantiate_rng(...) fails, the loop will rerun 716 * and the kick_trng(...) function will modfiy the 717 * upper and lower limits of the entropy sampling 718 * interval, leading to a sucessful initialization of 719 * the RNG. 720 */ 721 ret = instantiate_rng(dev, inst_handles, 722 gen_sk); 723 if (ret == -EAGAIN) 724 /* 725 * if here, the loop will rerun, 726 * so don't hog the CPU 727 */ 728 cpu_relax(); 729 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); 730 if (ret) { 731 dev_err(dev, "failed to instantiate RNG"); 732 goto caam_remove; 733 } 734 /* 735 * Set handles init'ed by this module as the complement of the 736 * already initialized ones 737 */ 738 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; 739 740 /* Enable RDB bit so that RNG works faster */ 741 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); 742 } 743 744 /* NOTE: RTIC detection ought to go here, around Si time */ 745 746 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | 747 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); 748 749 /* Report "alive" for developer to see */ 750 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, 751 ctrlpriv->era); 752 dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n", 753 ctrlpriv->total_jobrs, ctrlpriv->qi_present, 754 caam_dpaa2 ? "yes" : "no"); 755 756 #ifdef CONFIG_DEBUG_FS 757 debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH, 758 ctrlpriv->ctl, &perfmon->req_dequeued, 759 &caam_fops_u64_ro); 760 debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH, 761 ctrlpriv->ctl, &perfmon->ob_enc_req, 762 &caam_fops_u64_ro); 763 debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH, 764 ctrlpriv->ctl, &perfmon->ib_dec_req, 765 &caam_fops_u64_ro); 766 debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH, 767 ctrlpriv->ctl, &perfmon->ob_enc_bytes, 768 &caam_fops_u64_ro); 769 debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH, 770 ctrlpriv->ctl, &perfmon->ob_prot_bytes, 771 &caam_fops_u64_ro); 772 debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH, 773 ctrlpriv->ctl, &perfmon->ib_dec_bytes, 774 &caam_fops_u64_ro); 775 debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH, 776 ctrlpriv->ctl, &perfmon->ib_valid_bytes, 777 &caam_fops_u64_ro); 778 779 /* Controller level - global status values */ 780 debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH, 781 ctrlpriv->ctl, &perfmon->faultaddr, 782 &caam_fops_u32_ro); 783 debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH, 784 ctrlpriv->ctl, &perfmon->faultdetail, 785 &caam_fops_u32_ro); 786 debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH, 787 ctrlpriv->ctl, &perfmon->status, 788 &caam_fops_u32_ro); 789 790 /* Internal covering keys (useful in non-secure mode only) */ 791 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; 792 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 793 ctrlpriv->ctl_kek = debugfs_create_blob("kek", 794 S_IRUSR | 795 S_IRGRP | S_IROTH, 796 ctrlpriv->ctl, 797 &ctrlpriv->ctl_kek_wrap); 798 799 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0]; 800 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 801 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", 802 S_IRUSR | 803 S_IRGRP | S_IROTH, 804 ctrlpriv->ctl, 805 &ctrlpriv->ctl_tkek_wrap); 806 807 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0]; 808 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); 809 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", 810 S_IRUSR | 811 S_IRGRP | S_IROTH, 812 ctrlpriv->ctl, 813 &ctrlpriv->ctl_tdsk_wrap); 814 #endif 815 return 0; 816 817 caam_remove: 818 #ifdef CONFIG_DEBUG_FS 819 debugfs_remove_recursive(ctrlpriv->dfs_root); 820 #endif 821 caam_remove(pdev); 822 return ret; 823 824 iounmap_ctrl: 825 iounmap(ctrl); 826 disable_caam_emi_slow: 827 if (ctrlpriv->caam_emi_slow) 828 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 829 disable_caam_aclk: 830 clk_disable_unprepare(ctrlpriv->caam_aclk); 831 disable_caam_mem: 832 clk_disable_unprepare(ctrlpriv->caam_mem); 833 disable_caam_ipg: 834 clk_disable_unprepare(ctrlpriv->caam_ipg); 835 return ret; 836 } 837 838 static struct platform_driver caam_driver = { 839 .driver = { 840 .name = "caam", 841 .of_match_table = caam_match, 842 }, 843 .probe = caam_probe, 844 .remove = caam_remove, 845 }; 846 847 module_platform_driver(caam_driver); 848 849 MODULE_LICENSE("GPL"); 850 MODULE_DESCRIPTION("FSL CAAM request backend"); 851 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); 852