1 /* * CAAM control-plane driver backend 2 * Controller-level driver, kernel property detection, initialization 3 * 4 * Copyright 2008-2012 Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/of_address.h> 9 #include <linux/of_irq.h> 10 11 #include "compat.h" 12 #include "regs.h" 13 #include "intern.h" 14 #include "jr.h" 15 #include "desc_constr.h" 16 #include "ctrl.h" 17 18 bool caam_little_end; 19 EXPORT_SYMBOL(caam_little_end); 20 21 #ifdef CONFIG_CAAM_QI 22 #include "qi.h" 23 #endif 24 25 /* 26 * i.MX targets tend to have clock control subsystems that can 27 * enable/disable clocking to our device. 28 */ 29 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX 30 static inline struct clk *caam_drv_identify_clk(struct device *dev, 31 char *clk_name) 32 { 33 return devm_clk_get(dev, clk_name); 34 } 35 #else 36 static inline struct clk *caam_drv_identify_clk(struct device *dev, 37 char *clk_name) 38 { 39 return NULL; 40 } 41 #endif 42 43 /* 44 * Descriptor to instantiate RNG State Handle 0 in normal mode and 45 * load the JDKEK, TDKEK and TDSK registers 46 */ 47 static void build_instantiation_desc(u32 *desc, int handle, int do_sk) 48 { 49 u32 *jump_cmd, op_flags; 50 51 init_job_desc(desc, 0); 52 53 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 54 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; 55 56 /* INIT RNG in non-test mode */ 57 append_operation(desc, op_flags); 58 59 if (!handle && do_sk) { 60 /* 61 * For SH0, Secure Keys must be generated as well 62 */ 63 64 /* wait for done */ 65 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); 66 set_jump_tgt_here(desc, jump_cmd); 67 68 /* 69 * load 1 to clear written reg: 70 * resets the done interrrupt and returns the RNG to idle. 71 */ 72 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); 73 74 /* Initialize State Handle */ 75 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 76 OP_ALG_AAI_RNG4_SK); 77 } 78 79 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 80 } 81 82 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ 83 static void build_deinstantiation_desc(u32 *desc, int handle) 84 { 85 init_job_desc(desc, 0); 86 87 /* Uninstantiate State Handle 0 */ 88 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 89 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); 90 91 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); 92 } 93 94 /* 95 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of 96 * the software (no JR/QI used). 97 * @ctrldev - pointer to device 98 * @status - descriptor status, after being run 99 * 100 * Return: - 0 if no error occurred 101 * - -ENODEV if the DECO couldn't be acquired 102 * - -EAGAIN if an error occurred while executing the descriptor 103 */ 104 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, 105 u32 *status) 106 { 107 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 108 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; 109 struct caam_deco __iomem *deco = ctrlpriv->deco; 110 unsigned int timeout = 100000; 111 u32 deco_dbg_reg, flags; 112 int i; 113 114 115 if (ctrlpriv->virt_en == 1) { 116 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); 117 118 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && 119 --timeout) 120 cpu_relax(); 121 122 timeout = 100000; 123 } 124 125 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); 126 127 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && 128 --timeout) 129 cpu_relax(); 130 131 if (!timeout) { 132 dev_err(ctrldev, "failed to acquire DECO 0\n"); 133 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 134 return -ENODEV; 135 } 136 137 for (i = 0; i < desc_len(desc); i++) 138 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); 139 140 flags = DECO_JQCR_WHL; 141 /* 142 * If the descriptor length is longer than 4 words, then the 143 * FOUR bit in JRCTRL register must be set. 144 */ 145 if (desc_len(desc) >= 4) 146 flags |= DECO_JQCR_FOUR; 147 148 /* Instruct the DECO to execute it */ 149 clrsetbits_32(&deco->jr_ctl_hi, 0, flags); 150 151 timeout = 10000000; 152 do { 153 deco_dbg_reg = rd_reg32(&deco->desc_dbg); 154 /* 155 * If an error occured in the descriptor, then 156 * the DECO status field will be set to 0x0D 157 */ 158 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == 159 DESC_DBG_DECO_STAT_HOST_ERR) 160 break; 161 cpu_relax(); 162 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); 163 164 *status = rd_reg32(&deco->op_status_hi) & 165 DECO_OP_STATUS_HI_ERR_MASK; 166 167 if (ctrlpriv->virt_en == 1) 168 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); 169 170 /* Mark the DECO as free */ 171 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 172 173 if (!timeout) 174 return -EAGAIN; 175 176 return 0; 177 } 178 179 /* 180 * instantiate_rng - builds and executes a descriptor on DECO0, 181 * which initializes the RNG block. 182 * @ctrldev - pointer to device 183 * @state_handle_mask - bitmask containing the instantiation status 184 * for the RNG4 state handles which exist in 185 * the RNG4 block: 1 if it's been instantiated 186 * by an external entry, 0 otherwise. 187 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; 188 * Caution: this can be done only once; if the keys need to be 189 * regenerated, a POR is required 190 * 191 * Return: - 0 if no error occurred 192 * - -ENOMEM if there isn't enough memory to allocate the descriptor 193 * - -ENODEV if DECO0 couldn't be acquired 194 * - -EAGAIN if an error occurred when executing the descriptor 195 * f.i. there was a RNG hardware error due to not "good enough" 196 * entropy being aquired. 197 */ 198 static int instantiate_rng(struct device *ctrldev, int state_handle_mask, 199 int gen_sk) 200 { 201 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 202 struct caam_ctrl __iomem *ctrl; 203 u32 *desc, status = 0, rdsta_val; 204 int ret = 0, sh_idx; 205 206 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 207 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); 208 if (!desc) 209 return -ENOMEM; 210 211 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 212 /* 213 * If the corresponding bit is set, this state handle 214 * was initialized by somebody else, so it's left alone. 215 */ 216 if ((1 << sh_idx) & state_handle_mask) 217 continue; 218 219 /* Create the descriptor for instantiating RNG State Handle */ 220 build_instantiation_desc(desc, sh_idx, gen_sk); 221 222 /* Try to run it through DECO0 */ 223 ret = run_descriptor_deco0(ctrldev, desc, &status); 224 225 /* 226 * If ret is not 0, or descriptor status is not 0, then 227 * something went wrong. No need to try the next state 228 * handle (if available), bail out here. 229 * Also, if for some reason, the State Handle didn't get 230 * instantiated although the descriptor has finished 231 * without any error (HW optimizations for later 232 * CAAM eras), then try again. 233 */ 234 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; 235 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) || 236 !(rdsta_val & (1 << sh_idx))) 237 ret = -EAGAIN; 238 if (ret) 239 break; 240 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); 241 /* Clear the contents before recreating the descriptor */ 242 memset(desc, 0x00, CAAM_CMD_SZ * 7); 243 } 244 245 kfree(desc); 246 247 return ret; 248 } 249 250 /* 251 * deinstantiate_rng - builds and executes a descriptor on DECO0, 252 * which deinitializes the RNG block. 253 * @ctrldev - pointer to device 254 * @state_handle_mask - bitmask containing the instantiation status 255 * for the RNG4 state handles which exist in 256 * the RNG4 block: 1 if it's been instantiated 257 * 258 * Return: - 0 if no error occurred 259 * - -ENOMEM if there isn't enough memory to allocate the descriptor 260 * - -ENODEV if DECO0 couldn't be acquired 261 * - -EAGAIN if an error occurred when executing the descriptor 262 */ 263 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) 264 { 265 u32 *desc, status; 266 int sh_idx, ret = 0; 267 268 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); 269 if (!desc) 270 return -ENOMEM; 271 272 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { 273 /* 274 * If the corresponding bit is set, then it means the state 275 * handle was initialized by us, and thus it needs to be 276 * deinitialized as well 277 */ 278 if ((1 << sh_idx) & state_handle_mask) { 279 /* 280 * Create the descriptor for deinstantating this state 281 * handle 282 */ 283 build_deinstantiation_desc(desc, sh_idx); 284 285 /* Try to run it through DECO0 */ 286 ret = run_descriptor_deco0(ctrldev, desc, &status); 287 288 if (ret || 289 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) { 290 dev_err(ctrldev, 291 "Failed to deinstantiate RNG4 SH%d\n", 292 sh_idx); 293 break; 294 } 295 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); 296 } 297 } 298 299 kfree(desc); 300 301 return ret; 302 } 303 304 static int caam_remove(struct platform_device *pdev) 305 { 306 struct device *ctrldev; 307 struct caam_drv_private *ctrlpriv; 308 struct caam_ctrl __iomem *ctrl; 309 310 ctrldev = &pdev->dev; 311 ctrlpriv = dev_get_drvdata(ctrldev); 312 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 313 314 /* Remove platform devices under the crypto node */ 315 of_platform_depopulate(ctrldev); 316 317 #ifdef CONFIG_CAAM_QI 318 if (ctrlpriv->qidev) 319 caam_qi_shutdown(ctrlpriv->qidev); 320 #endif 321 322 /* De-initialize RNG state handles initialized by this driver. */ 323 if (ctrlpriv->rng4_sh_init) 324 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); 325 326 /* Shut down debug views */ 327 #ifdef CONFIG_DEBUG_FS 328 debugfs_remove_recursive(ctrlpriv->dfs_root); 329 #endif 330 331 /* Unmap controller region */ 332 iounmap(ctrl); 333 334 /* shut clocks off before finalizing shutdown */ 335 clk_disable_unprepare(ctrlpriv->caam_ipg); 336 clk_disable_unprepare(ctrlpriv->caam_mem); 337 clk_disable_unprepare(ctrlpriv->caam_aclk); 338 if (ctrlpriv->caam_emi_slow) 339 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 340 return 0; 341 } 342 343 /* 344 * kick_trng - sets the various parameters for enabling the initialization 345 * of the RNG4 block in CAAM 346 * @pdev - pointer to the platform device 347 * @ent_delay - Defines the length (in system clocks) of each entropy sample. 348 */ 349 static void kick_trng(struct platform_device *pdev, int ent_delay) 350 { 351 struct device *ctrldev = &pdev->dev; 352 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 353 struct caam_ctrl __iomem *ctrl; 354 struct rng4tst __iomem *r4tst; 355 u32 val; 356 357 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 358 r4tst = &ctrl->r4tst[0]; 359 360 /* put RNG4 into program mode */ 361 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); 362 363 /* 364 * Performance-wise, it does not make sense to 365 * set the delay to a value that is lower 366 * than the last one that worked (i.e. the state handles 367 * were instantiated properly. Thus, instead of wasting 368 * time trying to set the values controlling the sample 369 * frequency, the function simply returns. 370 */ 371 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) 372 >> RTSDCTL_ENT_DLY_SHIFT; 373 if (ent_delay <= val) 374 goto start_rng; 375 376 val = rd_reg32(&r4tst->rtsdctl); 377 val = (val & ~RTSDCTL_ENT_DLY_MASK) | 378 (ent_delay << RTSDCTL_ENT_DLY_SHIFT); 379 wr_reg32(&r4tst->rtsdctl, val); 380 /* min. freq. count, equal to 1/4 of the entropy sample length */ 381 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); 382 /* disable maximum frequency count */ 383 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); 384 /* read the control register */ 385 val = rd_reg32(&r4tst->rtmctl); 386 start_rng: 387 /* 388 * select raw sampling in both entropy shifter 389 * and statistical checker; ; put RNG4 into run mode 390 */ 391 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); 392 } 393 394 /** 395 * caam_get_era() - Return the ERA of the SEC on SoC, based 396 * on "sec-era" propery in the DTS. This property is updated by u-boot. 397 **/ 398 int caam_get_era(void) 399 { 400 struct device_node *caam_node; 401 int ret; 402 u32 prop; 403 404 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 405 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); 406 of_node_put(caam_node); 407 408 return ret ? -ENOTSUPP : prop; 409 } 410 EXPORT_SYMBOL(caam_get_era); 411 412 static const struct of_device_id caam_match[] = { 413 { 414 .compatible = "fsl,sec-v4.0", 415 }, 416 { 417 .compatible = "fsl,sec4.0", 418 }, 419 {}, 420 }; 421 MODULE_DEVICE_TABLE(of, caam_match); 422 423 /* Probe routine for CAAM top (controller) level */ 424 static int caam_probe(struct platform_device *pdev) 425 { 426 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; 427 u64 caam_id; 428 struct device *dev; 429 struct device_node *nprop, *np; 430 struct caam_ctrl __iomem *ctrl; 431 struct caam_drv_private *ctrlpriv; 432 struct clk *clk; 433 #ifdef CONFIG_DEBUG_FS 434 struct caam_perfmon *perfmon; 435 #endif 436 u32 scfgr, comp_params; 437 u32 cha_vid_ls; 438 int pg_size; 439 int BLOCK_OFFSET = 0; 440 441 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); 442 if (!ctrlpriv) 443 return -ENOMEM; 444 445 dev = &pdev->dev; 446 dev_set_drvdata(dev, ctrlpriv); 447 ctrlpriv->pdev = pdev; 448 nprop = pdev->dev.of_node; 449 450 /* Enable clocking */ 451 clk = caam_drv_identify_clk(&pdev->dev, "ipg"); 452 if (IS_ERR(clk)) { 453 ret = PTR_ERR(clk); 454 dev_err(&pdev->dev, 455 "can't identify CAAM ipg clk: %d\n", ret); 456 return ret; 457 } 458 ctrlpriv->caam_ipg = clk; 459 460 clk = caam_drv_identify_clk(&pdev->dev, "mem"); 461 if (IS_ERR(clk)) { 462 ret = PTR_ERR(clk); 463 dev_err(&pdev->dev, 464 "can't identify CAAM mem clk: %d\n", ret); 465 return ret; 466 } 467 ctrlpriv->caam_mem = clk; 468 469 clk = caam_drv_identify_clk(&pdev->dev, "aclk"); 470 if (IS_ERR(clk)) { 471 ret = PTR_ERR(clk); 472 dev_err(&pdev->dev, 473 "can't identify CAAM aclk clk: %d\n", ret); 474 return ret; 475 } 476 ctrlpriv->caam_aclk = clk; 477 478 if (!of_machine_is_compatible("fsl,imx6ul")) { 479 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow"); 480 if (IS_ERR(clk)) { 481 ret = PTR_ERR(clk); 482 dev_err(&pdev->dev, 483 "can't identify CAAM emi_slow clk: %d\n", ret); 484 return ret; 485 } 486 ctrlpriv->caam_emi_slow = clk; 487 } 488 489 ret = clk_prepare_enable(ctrlpriv->caam_ipg); 490 if (ret < 0) { 491 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); 492 return ret; 493 } 494 495 ret = clk_prepare_enable(ctrlpriv->caam_mem); 496 if (ret < 0) { 497 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", 498 ret); 499 goto disable_caam_ipg; 500 } 501 502 ret = clk_prepare_enable(ctrlpriv->caam_aclk); 503 if (ret < 0) { 504 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); 505 goto disable_caam_mem; 506 } 507 508 if (ctrlpriv->caam_emi_slow) { 509 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow); 510 if (ret < 0) { 511 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n", 512 ret); 513 goto disable_caam_aclk; 514 } 515 } 516 517 /* Get configuration properties from device tree */ 518 /* First, get register page */ 519 ctrl = of_iomap(nprop, 0); 520 if (ctrl == NULL) { 521 dev_err(dev, "caam: of_iomap() failed\n"); 522 ret = -ENOMEM; 523 goto disable_caam_emi_slow; 524 } 525 526 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & 527 (CSTA_PLEND | CSTA_ALT_PLEND)); 528 529 /* Finding the page size for using the CTPR_MS register */ 530 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); 531 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; 532 533 /* Allocating the BLOCK_OFFSET based on the supported page size on 534 * the platform 535 */ 536 if (pg_size == 0) 537 BLOCK_OFFSET = PG_SIZE_4K; 538 else 539 BLOCK_OFFSET = PG_SIZE_64K; 540 541 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; 542 ctrlpriv->assure = (struct caam_assurance __iomem __force *) 543 ((__force uint8_t *)ctrl + 544 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER 545 ); 546 ctrlpriv->deco = (struct caam_deco __iomem __force *) 547 ((__force uint8_t *)ctrl + 548 BLOCK_OFFSET * DECO_BLOCK_NUMBER 549 ); 550 551 /* Get the IRQ of the controller (for security violations only) */ 552 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); 553 554 /* 555 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, 556 * long pointers in master configuration register 557 */ 558 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR, 559 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF | 560 MCFGR_WDENABLE | MCFGR_LARGE_BURST | 561 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); 562 563 /* 564 * Read the Compile Time paramters and SCFGR to determine 565 * if Virtualization is enabled for this platform 566 */ 567 scfgr = rd_reg32(&ctrl->scfgr); 568 569 ctrlpriv->virt_en = 0; 570 if (comp_params & CTPR_MS_VIRT_EN_INCL) { 571 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or 572 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 573 */ 574 if ((comp_params & CTPR_MS_VIRT_EN_POR) || 575 (!(comp_params & CTPR_MS_VIRT_EN_POR) && 576 (scfgr & SCFGR_VIRT_EN))) 577 ctrlpriv->virt_en = 1; 578 } else { 579 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ 580 if (comp_params & CTPR_MS_VIRT_EN_POR) 581 ctrlpriv->virt_en = 1; 582 } 583 584 if (ctrlpriv->virt_en == 1) 585 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | 586 JRSTART_JR1_START | JRSTART_JR2_START | 587 JRSTART_JR3_START); 588 589 if (sizeof(dma_addr_t) == sizeof(u64)) { 590 if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) 591 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 592 else 593 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 594 } else { 595 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 596 } 597 if (ret) { 598 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret); 599 goto iounmap_ctrl; 600 } 601 602 ret = of_platform_populate(nprop, caam_match, NULL, dev); 603 if (ret) { 604 dev_err(dev, "JR platform devices creation error\n"); 605 goto iounmap_ctrl; 606 } 607 608 #ifdef CONFIG_DEBUG_FS 609 /* 610 * FIXME: needs better naming distinction, as some amalgamation of 611 * "caam" and nprop->full_name. The OF name isn't distinctive, 612 * but does separate instances 613 */ 614 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; 615 616 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); 617 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); 618 #endif 619 620 ring = 0; 621 for_each_available_child_of_node(nprop, np) 622 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || 623 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { 624 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) 625 ((__force uint8_t *)ctrl + 626 (ring + JR_BLOCK_NUMBER) * 627 BLOCK_OFFSET 628 ); 629 ctrlpriv->total_jobrs++; 630 ring++; 631 } 632 633 /* Check to see if QI present. If so, enable */ 634 ctrlpriv->qi_present = 635 !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & 636 CTPR_MS_QI_MASK); 637 if (ctrlpriv->qi_present) { 638 ctrlpriv->qi = (struct caam_queue_if __iomem __force *) 639 ((__force uint8_t *)ctrl + 640 BLOCK_OFFSET * QI_BLOCK_NUMBER 641 ); 642 /* This is all that's required to physically enable QI */ 643 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); 644 645 /* If QMAN driver is present, init CAAM-QI backend */ 646 #ifdef CONFIG_CAAM_QI 647 ret = caam_qi_init(pdev); 648 if (ret) 649 dev_err(dev, "caam qi i/f init failed: %d\n", ret); 650 #endif 651 } 652 653 /* If no QI and no rings specified, quit and go home */ 654 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { 655 dev_err(dev, "no queues configured, terminating\n"); 656 ret = -ENOMEM; 657 goto caam_remove; 658 } 659 660 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); 661 662 /* 663 * If SEC has RNG version >= 4 and RNG state handle has not been 664 * already instantiated, do RNG instantiation 665 */ 666 if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { 667 ctrlpriv->rng4_sh_init = 668 rd_reg32(&ctrl->r4tst[0].rdsta); 669 /* 670 * If the secure keys (TDKEK, JDKEK, TDSK), were already 671 * generated, signal this to the function that is instantiating 672 * the state handles. An error would occur if RNG4 attempts 673 * to regenerate these keys before the next POR. 674 */ 675 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; 676 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; 677 do { 678 int inst_handles = 679 rd_reg32(&ctrl->r4tst[0].rdsta) & 680 RDSTA_IFMASK; 681 /* 682 * If either SH were instantiated by somebody else 683 * (e.g. u-boot) then it is assumed that the entropy 684 * parameters are properly set and thus the function 685 * setting these (kick_trng(...)) is skipped. 686 * Also, if a handle was instantiated, do not change 687 * the TRNG parameters. 688 */ 689 if (!(ctrlpriv->rng4_sh_init || inst_handles)) { 690 dev_info(dev, 691 "Entropy delay = %u\n", 692 ent_delay); 693 kick_trng(pdev, ent_delay); 694 ent_delay += 400; 695 } 696 /* 697 * if instantiate_rng(...) fails, the loop will rerun 698 * and the kick_trng(...) function will modfiy the 699 * upper and lower limits of the entropy sampling 700 * interval, leading to a sucessful initialization of 701 * the RNG. 702 */ 703 ret = instantiate_rng(dev, inst_handles, 704 gen_sk); 705 if (ret == -EAGAIN) 706 /* 707 * if here, the loop will rerun, 708 * so don't hog the CPU 709 */ 710 cpu_relax(); 711 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); 712 if (ret) { 713 dev_err(dev, "failed to instantiate RNG"); 714 goto caam_remove; 715 } 716 /* 717 * Set handles init'ed by this module as the complement of the 718 * already initialized ones 719 */ 720 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; 721 722 /* Enable RDB bit so that RNG works faster */ 723 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); 724 } 725 726 /* NOTE: RTIC detection ought to go here, around Si time */ 727 728 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | 729 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); 730 731 /* Report "alive" for developer to see */ 732 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, 733 caam_get_era()); 734 dev_info(dev, "job rings = %d, qi = %d\n", 735 ctrlpriv->total_jobrs, ctrlpriv->qi_present); 736 737 #ifdef CONFIG_DEBUG_FS 738 739 ctrlpriv->ctl_rq_dequeued = 740 debugfs_create_file("rq_dequeued", 741 S_IRUSR | S_IRGRP | S_IROTH, 742 ctrlpriv->ctl, &perfmon->req_dequeued, 743 &caam_fops_u64_ro); 744 ctrlpriv->ctl_ob_enc_req = 745 debugfs_create_file("ob_rq_encrypted", 746 S_IRUSR | S_IRGRP | S_IROTH, 747 ctrlpriv->ctl, &perfmon->ob_enc_req, 748 &caam_fops_u64_ro); 749 ctrlpriv->ctl_ib_dec_req = 750 debugfs_create_file("ib_rq_decrypted", 751 S_IRUSR | S_IRGRP | S_IROTH, 752 ctrlpriv->ctl, &perfmon->ib_dec_req, 753 &caam_fops_u64_ro); 754 ctrlpriv->ctl_ob_enc_bytes = 755 debugfs_create_file("ob_bytes_encrypted", 756 S_IRUSR | S_IRGRP | S_IROTH, 757 ctrlpriv->ctl, &perfmon->ob_enc_bytes, 758 &caam_fops_u64_ro); 759 ctrlpriv->ctl_ob_prot_bytes = 760 debugfs_create_file("ob_bytes_protected", 761 S_IRUSR | S_IRGRP | S_IROTH, 762 ctrlpriv->ctl, &perfmon->ob_prot_bytes, 763 &caam_fops_u64_ro); 764 ctrlpriv->ctl_ib_dec_bytes = 765 debugfs_create_file("ib_bytes_decrypted", 766 S_IRUSR | S_IRGRP | S_IROTH, 767 ctrlpriv->ctl, &perfmon->ib_dec_bytes, 768 &caam_fops_u64_ro); 769 ctrlpriv->ctl_ib_valid_bytes = 770 debugfs_create_file("ib_bytes_validated", 771 S_IRUSR | S_IRGRP | S_IROTH, 772 ctrlpriv->ctl, &perfmon->ib_valid_bytes, 773 &caam_fops_u64_ro); 774 775 /* Controller level - global status values */ 776 ctrlpriv->ctl_faultaddr = 777 debugfs_create_file("fault_addr", 778 S_IRUSR | S_IRGRP | S_IROTH, 779 ctrlpriv->ctl, &perfmon->faultaddr, 780 &caam_fops_u32_ro); 781 ctrlpriv->ctl_faultdetail = 782 debugfs_create_file("fault_detail", 783 S_IRUSR | S_IRGRP | S_IROTH, 784 ctrlpriv->ctl, &perfmon->faultdetail, 785 &caam_fops_u32_ro); 786 ctrlpriv->ctl_faultstatus = 787 debugfs_create_file("fault_status", 788 S_IRUSR | S_IRGRP | S_IROTH, 789 ctrlpriv->ctl, &perfmon->status, 790 &caam_fops_u32_ro); 791 792 /* Internal covering keys (useful in non-secure mode only) */ 793 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0]; 794 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 795 ctrlpriv->ctl_kek = debugfs_create_blob("kek", 796 S_IRUSR | 797 S_IRGRP | S_IROTH, 798 ctrlpriv->ctl, 799 &ctrlpriv->ctl_kek_wrap); 800 801 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0]; 802 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 803 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", 804 S_IRUSR | 805 S_IRGRP | S_IROTH, 806 ctrlpriv->ctl, 807 &ctrlpriv->ctl_tkek_wrap); 808 809 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0]; 810 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); 811 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", 812 S_IRUSR | 813 S_IRGRP | S_IROTH, 814 ctrlpriv->ctl, 815 &ctrlpriv->ctl_tdsk_wrap); 816 #endif 817 return 0; 818 819 caam_remove: 820 #ifdef CONFIG_DEBUG_FS 821 debugfs_remove_recursive(ctrlpriv->dfs_root); 822 #endif 823 caam_remove(pdev); 824 return ret; 825 826 iounmap_ctrl: 827 iounmap(ctrl); 828 disable_caam_emi_slow: 829 if (ctrlpriv->caam_emi_slow) 830 clk_disable_unprepare(ctrlpriv->caam_emi_slow); 831 disable_caam_aclk: 832 clk_disable_unprepare(ctrlpriv->caam_aclk); 833 disable_caam_mem: 834 clk_disable_unprepare(ctrlpriv->caam_mem); 835 disable_caam_ipg: 836 clk_disable_unprepare(ctrlpriv->caam_ipg); 837 return ret; 838 } 839 840 static struct platform_driver caam_driver = { 841 .driver = { 842 .name = "caam", 843 .of_match_table = caam_match, 844 }, 845 .probe = caam_probe, 846 .remove = caam_remove, 847 }; 848 849 module_platform_driver(caam_driver); 850 851 MODULE_LICENSE("GPL"); 852 MODULE_DESCRIPTION("FSL CAAM request backend"); 853 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); 854