1 /* 2 * CAAM control-plane driver backend 3 * Controller-level driver, kernel property detection, initialization 4 * 5 * Copyright 2008-2012 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/of_address.h> 9 #include <linux/of_irq.h> 10 11 #include "compat.h" 12 #include "regs.h" 13 #include "intern.h" 14 #include "jr.h" 15 #include "desc_constr.h" 16 #include "error.h" 17 #include "ctrl.h" 18 19 static int caam_remove(struct platform_device *pdev) 20 { 21 struct device *ctrldev; 22 struct caam_drv_private *ctrlpriv; 23 struct caam_drv_private_jr *jrpriv; 24 struct caam_full __iomem *topregs; 25 int ring, ret = 0; 26 27 ctrldev = &pdev->dev; 28 ctrlpriv = dev_get_drvdata(ctrldev); 29 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; 30 31 /* shut down JobRs */ 32 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { 33 ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]); 34 jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]); 35 irq_dispose_mapping(jrpriv->irq); 36 } 37 38 /* Shut down debug views */ 39 #ifdef CONFIG_DEBUG_FS 40 debugfs_remove_recursive(ctrlpriv->dfs_root); 41 #endif 42 43 /* Unmap controller region */ 44 iounmap(&topregs->ctrl); 45 46 kfree(ctrlpriv->jrdev); 47 kfree(ctrlpriv); 48 49 return ret; 50 } 51 52 /* 53 * Descriptor to instantiate RNG State Handle 0 in normal mode and 54 * load the JDKEK, TDKEK and TDSK registers 55 */ 56 static void build_instantiation_desc(u32 *desc) 57 { 58 u32 *jump_cmd; 59 60 init_job_desc(desc, 0); 61 62 /* INIT RNG in non-test mode */ 63 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 64 OP_ALG_AS_INIT); 65 66 /* wait for done */ 67 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); 68 set_jump_tgt_here(desc, jump_cmd); 69 70 /* 71 * load 1 to clear written reg: 72 * resets the done interrupt and returns the RNG to idle. 73 */ 74 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); 75 76 /* generate secure keys (non-test) */ 77 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 78 OP_ALG_RNG4_SK); 79 } 80 81 static int instantiate_rng(struct device *ctrldev) 82 { 83 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 84 struct caam_full __iomem *topregs; 85 unsigned int timeout = 100000; 86 u32 *desc; 87 int i, ret = 0; 88 89 desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA); 90 if (!desc) { 91 dev_err(ctrldev, "can't allocate RNG init descriptor memory\n"); 92 return -ENOMEM; 93 } 94 build_instantiation_desc(desc); 95 96 /* Set the bit to request direct access to DECO0 */ 97 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; 98 setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); 99 100 while (!(rd_reg32(&topregs->ctrl.deco_rq) & DECORR_DEN0) && 101 --timeout) 102 cpu_relax(); 103 104 if (!timeout) { 105 dev_err(ctrldev, "failed to acquire DECO 0\n"); 106 ret = -EIO; 107 goto out; 108 } 109 110 for (i = 0; i < desc_len(desc); i++) 111 topregs->deco.descbuf[i] = *(desc + i); 112 113 wr_reg32(&topregs->deco.jr_ctl_hi, DECO_JQCR_WHL | DECO_JQCR_FOUR); 114 115 timeout = 10000000; 116 while ((rd_reg32(&topregs->deco.desc_dbg) & DECO_DBG_VALID) && 117 --timeout) 118 cpu_relax(); 119 120 if (!timeout) { 121 dev_err(ctrldev, "failed to instantiate RNG\n"); 122 ret = -EIO; 123 } 124 125 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); 126 out: 127 kfree(desc); 128 return ret; 129 } 130 131 /* 132 * By default, the TRNG runs for 200 clocks per sample; 133 * 1600 clocks per sample generates better entropy. 134 */ 135 static void kick_trng(struct platform_device *pdev) 136 { 137 struct device *ctrldev = &pdev->dev; 138 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 139 struct caam_full __iomem *topregs; 140 struct rng4tst __iomem *r4tst; 141 u32 val; 142 143 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; 144 r4tst = &topregs->ctrl.r4tst[0]; 145 146 /* put RNG4 into program mode */ 147 setbits32(&r4tst->rtmctl, RTMCTL_PRGM); 148 /* 1600 clocks per sample */ 149 val = rd_reg32(&r4tst->rtsdctl); 150 val = (val & ~RTSDCTL_ENT_DLY_MASK) | (1600 << RTSDCTL_ENT_DLY_SHIFT); 151 wr_reg32(&r4tst->rtsdctl, val); 152 /* min. freq. count */ 153 wr_reg32(&r4tst->rtfrqmin, 400); 154 /* max. freq. count */ 155 wr_reg32(&r4tst->rtfrqmax, 6400); 156 /* put RNG4 into run mode */ 157 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); 158 } 159 160 /** 161 * caam_get_era() - Return the ERA of the SEC on SoC, based 162 * on the SEC_VID register. 163 * Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown. 164 * @caam_id - the value of the SEC_VID register 165 **/ 166 int caam_get_era(u64 caam_id) 167 { 168 struct sec_vid *sec_vid = (struct sec_vid *)&caam_id; 169 static const struct { 170 u16 ip_id; 171 u8 maj_rev; 172 u8 era; 173 } caam_eras[] = { 174 {0x0A10, 1, 1}, 175 {0x0A10, 2, 2}, 176 {0x0A12, 1, 3}, 177 {0x0A14, 1, 3}, 178 {0x0A14, 2, 4}, 179 {0x0A16, 1, 4}, 180 {0x0A11, 1, 4} 181 }; 182 int i; 183 184 for (i = 0; i < ARRAY_SIZE(caam_eras); i++) 185 if (caam_eras[i].ip_id == sec_vid->ip_id && 186 caam_eras[i].maj_rev == sec_vid->maj_rev) 187 return caam_eras[i].era; 188 189 return -ENOTSUPP; 190 } 191 EXPORT_SYMBOL(caam_get_era); 192 193 /* Probe routine for CAAM top (controller) level */ 194 static int caam_probe(struct platform_device *pdev) 195 { 196 int ret, ring, rspec; 197 u64 caam_id; 198 struct device *dev; 199 struct device_node *nprop, *np; 200 struct caam_ctrl __iomem *ctrl; 201 struct caam_full __iomem *topregs; 202 struct caam_drv_private *ctrlpriv; 203 #ifdef CONFIG_DEBUG_FS 204 struct caam_perfmon *perfmon; 205 #endif 206 u64 cha_vid; 207 208 ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL); 209 if (!ctrlpriv) 210 return -ENOMEM; 211 212 dev = &pdev->dev; 213 dev_set_drvdata(dev, ctrlpriv); 214 ctrlpriv->pdev = pdev; 215 nprop = pdev->dev.of_node; 216 217 /* Get configuration properties from device tree */ 218 /* First, get register page */ 219 ctrl = of_iomap(nprop, 0); 220 if (ctrl == NULL) { 221 dev_err(dev, "caam: of_iomap() failed\n"); 222 return -ENOMEM; 223 } 224 ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; 225 226 /* topregs used to derive pointers to CAAM sub-blocks only */ 227 topregs = (struct caam_full __iomem *)ctrl; 228 229 /* Get the IRQ of the controller (for security violations only) */ 230 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); 231 232 /* 233 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, 234 * long pointers in master configuration register 235 */ 236 setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE | 237 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); 238 239 if (sizeof(dma_addr_t) == sizeof(u64)) 240 if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) 241 dma_set_mask(dev, DMA_BIT_MASK(40)); 242 else 243 dma_set_mask(dev, DMA_BIT_MASK(36)); 244 else 245 dma_set_mask(dev, DMA_BIT_MASK(32)); 246 247 /* 248 * Detect and enable JobRs 249 * First, find out how many ring spec'ed, allocate references 250 * for all, then go probe each one. 251 */ 252 rspec = 0; 253 for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") 254 rspec++; 255 if (!rspec) { 256 /* for backward compatible with device trees */ 257 for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") 258 rspec++; 259 } 260 261 ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL); 262 if (ctrlpriv->jrdev == NULL) { 263 iounmap(&topregs->ctrl); 264 return -ENOMEM; 265 } 266 267 ring = 0; 268 ctrlpriv->total_jobrs = 0; 269 for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") { 270 caam_jr_probe(pdev, np, ring); 271 ctrlpriv->total_jobrs++; 272 ring++; 273 } 274 if (!ring) { 275 for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") { 276 caam_jr_probe(pdev, np, ring); 277 ctrlpriv->total_jobrs++; 278 ring++; 279 } 280 } 281 282 /* Check to see if QI present. If so, enable */ 283 ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) & 284 CTPR_QI_MASK); 285 if (ctrlpriv->qi_present) { 286 ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi; 287 /* This is all that's required to physically enable QI */ 288 wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN); 289 } 290 291 /* If no QI and no rings specified, quit and go home */ 292 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { 293 dev_err(dev, "no queues configured, terminating\n"); 294 caam_remove(pdev); 295 return -ENOMEM; 296 } 297 298 cha_vid = rd_reg64(&topregs->ctrl.perfmon.cha_id); 299 300 /* 301 * If SEC has RNG version >= 4 and RNG state handle has not been 302 * already instantiated ,do RNG instantiation 303 */ 304 if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4 && 305 !(rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IF0)) { 306 kick_trng(pdev); 307 ret = instantiate_rng(dev); 308 if (ret) { 309 caam_remove(pdev); 310 return ret; 311 } 312 313 /* Enable RDB bit so that RNG works faster */ 314 setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE); 315 } 316 317 /* NOTE: RTIC detection ought to go here, around Si time */ 318 319 caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id); 320 321 /* Report "alive" for developer to see */ 322 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, 323 caam_get_era(caam_id)); 324 dev_info(dev, "job rings = %d, qi = %d\n", 325 ctrlpriv->total_jobrs, ctrlpriv->qi_present); 326 327 #ifdef CONFIG_DEBUG_FS 328 /* 329 * FIXME: needs better naming distinction, as some amalgamation of 330 * "caam" and nprop->full_name. The OF name isn't distinctive, 331 * but does separate instances 332 */ 333 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; 334 335 ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL); 336 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); 337 338 /* Controller-level - performance monitor counters */ 339 ctrlpriv->ctl_rq_dequeued = 340 debugfs_create_u64("rq_dequeued", 341 S_IRUSR | S_IRGRP | S_IROTH, 342 ctrlpriv->ctl, &perfmon->req_dequeued); 343 ctrlpriv->ctl_ob_enc_req = 344 debugfs_create_u64("ob_rq_encrypted", 345 S_IRUSR | S_IRGRP | S_IROTH, 346 ctrlpriv->ctl, &perfmon->ob_enc_req); 347 ctrlpriv->ctl_ib_dec_req = 348 debugfs_create_u64("ib_rq_decrypted", 349 S_IRUSR | S_IRGRP | S_IROTH, 350 ctrlpriv->ctl, &perfmon->ib_dec_req); 351 ctrlpriv->ctl_ob_enc_bytes = 352 debugfs_create_u64("ob_bytes_encrypted", 353 S_IRUSR | S_IRGRP | S_IROTH, 354 ctrlpriv->ctl, &perfmon->ob_enc_bytes); 355 ctrlpriv->ctl_ob_prot_bytes = 356 debugfs_create_u64("ob_bytes_protected", 357 S_IRUSR | S_IRGRP | S_IROTH, 358 ctrlpriv->ctl, &perfmon->ob_prot_bytes); 359 ctrlpriv->ctl_ib_dec_bytes = 360 debugfs_create_u64("ib_bytes_decrypted", 361 S_IRUSR | S_IRGRP | S_IROTH, 362 ctrlpriv->ctl, &perfmon->ib_dec_bytes); 363 ctrlpriv->ctl_ib_valid_bytes = 364 debugfs_create_u64("ib_bytes_validated", 365 S_IRUSR | S_IRGRP | S_IROTH, 366 ctrlpriv->ctl, &perfmon->ib_valid_bytes); 367 368 /* Controller level - global status values */ 369 ctrlpriv->ctl_faultaddr = 370 debugfs_create_u64("fault_addr", 371 S_IRUSR | S_IRGRP | S_IROTH, 372 ctrlpriv->ctl, &perfmon->faultaddr); 373 ctrlpriv->ctl_faultdetail = 374 debugfs_create_u32("fault_detail", 375 S_IRUSR | S_IRGRP | S_IROTH, 376 ctrlpriv->ctl, &perfmon->faultdetail); 377 ctrlpriv->ctl_faultstatus = 378 debugfs_create_u32("fault_status", 379 S_IRUSR | S_IRGRP | S_IROTH, 380 ctrlpriv->ctl, &perfmon->status); 381 382 /* Internal covering keys (useful in non-secure mode only) */ 383 ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0]; 384 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 385 ctrlpriv->ctl_kek = debugfs_create_blob("kek", 386 S_IRUSR | 387 S_IRGRP | S_IROTH, 388 ctrlpriv->ctl, 389 &ctrlpriv->ctl_kek_wrap); 390 391 ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0]; 392 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); 393 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", 394 S_IRUSR | 395 S_IRGRP | S_IROTH, 396 ctrlpriv->ctl, 397 &ctrlpriv->ctl_tkek_wrap); 398 399 ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0]; 400 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); 401 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", 402 S_IRUSR | 403 S_IRGRP | S_IROTH, 404 ctrlpriv->ctl, 405 &ctrlpriv->ctl_tdsk_wrap); 406 #endif 407 return 0; 408 } 409 410 static struct of_device_id caam_match[] = { 411 { 412 .compatible = "fsl,sec-v4.0", 413 }, 414 { 415 .compatible = "fsl,sec4.0", 416 }, 417 {}, 418 }; 419 MODULE_DEVICE_TABLE(of, caam_match); 420 421 static struct platform_driver caam_driver = { 422 .driver = { 423 .name = "caam", 424 .owner = THIS_MODULE, 425 .of_match_table = caam_match, 426 }, 427 .probe = caam_probe, 428 .remove = caam_remove, 429 }; 430 431 module_platform_driver(caam_driver); 432 433 MODULE_LICENSE("GPL"); 434 MODULE_DESCRIPTION("FSL CAAM request backend"); 435 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); 436