1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * Copyright 2015-2016 Freescale Semiconductor Inc.
4  * Copyright 2017-2018 NXP
5  */
6 
7 #ifndef _CAAMALG_QI2_H_
8 #define _CAAMALG_QI2_H_
9 
10 #include <soc/fsl/dpaa2-io.h>
11 #include <soc/fsl/dpaa2-fd.h>
12 #include <linux/threads.h>
13 #include "dpseci.h"
14 #include "desc_constr.h"
15 
16 #define DPAA2_CAAM_STORE_SIZE	16
17 /* NAPI weight *must* be a multiple of the store size. */
18 #define DPAA2_CAAM_NAPI_WEIGHT	64
19 
20 /* The congestion entrance threshold was chosen so that on LS2088
21  * we support the maximum throughput for the available memory
22  */
23 #define DPAA2_SEC_CONG_ENTRY_THRESH	(128 * 1024 * 1024)
24 #define DPAA2_SEC_CONG_EXIT_THRESH	(DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
25 
26 /**
27  * dpaa2_caam_priv - driver private data
28  * @dpseci_id: DPSECI object unique ID
29  * @major_ver: DPSECI major version
30  * @minor_ver: DPSECI minor version
31  * @dpseci_attr: DPSECI attributes
32  * @sec_attr: SEC engine attributes
33  * @rx_queue_attr: array of Rx queue attributes
34  * @tx_queue_attr: array of Tx queue attributes
35  * @cscn_mem: pointer to memory region containing the congestion SCN
36  *	it's size is larger than to accommodate alignment
37  * @cscn_mem_aligned: pointer to congestion SCN; it is computed as
38  *	PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
39  * @cscn_dma: dma address used by the QMAN to write CSCN messages
40  * @dev: device associated with the DPSECI object
41  * @mc_io: pointer to MC portal's I/O object
42  * @domain: IOMMU domain
43  * @ppriv: per CPU pointers to privata data
44  */
45 struct dpaa2_caam_priv {
46 	int dpsec_id;
47 
48 	u16 major_ver;
49 	u16 minor_ver;
50 
51 	struct dpseci_attr dpseci_attr;
52 	struct dpseci_sec_attr sec_attr;
53 	struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
54 	struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
55 	int num_pairs;
56 
57 	/* congestion */
58 	void *cscn_mem;
59 	void *cscn_mem_aligned;
60 	dma_addr_t cscn_dma;
61 
62 	struct device *dev;
63 	struct fsl_mc_io *mc_io;
64 	struct iommu_domain *domain;
65 
66 	struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
67 };
68 
69 /**
70  * dpaa2_caam_priv_per_cpu - per CPU private data
71  * @napi: napi structure
72  * @net_dev: netdev used by napi
73  * @req_fqid: (virtual) request (Tx / enqueue) FQID
74  * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
75  * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
76  * @nctx: notification context of response FQ
77  * @store: where dequeued frames are stored
78  * @priv: backpointer to dpaa2_caam_priv
79  * @dpio: portal used for data path operations
80  */
81 struct dpaa2_caam_priv_per_cpu {
82 	struct napi_struct napi;
83 	struct net_device net_dev;
84 	int req_fqid;
85 	int rsp_fqid;
86 	int prio;
87 	struct dpaa2_io_notification_ctx nctx;
88 	struct dpaa2_io_store *store;
89 	struct dpaa2_caam_priv *priv;
90 	struct dpaa2_io *dpio;
91 };
92 
93 /*
94  * The CAAM QI hardware constructs a job descriptor which points
95  * to shared descriptor (as pointed by context_a of FQ to CAAM).
96  * When the job descriptor is executed by deco, the whole job
97  * descriptor together with shared descriptor gets loaded in
98  * deco buffer which is 64 words long (each 32-bit).
99  *
100  * The job descriptor constructed by QI hardware has layout:
101  *
102  *	HEADER		(1 word)
103  *	Shdesc ptr	(1 or 2 words)
104  *	SEQ_OUT_PTR	(1 word)
105  *	Out ptr		(1 or 2 words)
106  *	Out length	(1 word)
107  *	SEQ_IN_PTR	(1 word)
108  *	In ptr		(1 or 2 words)
109  *	In length	(1 word)
110  *
111  * The shdesc ptr is used to fetch shared descriptor contents
112  * into deco buffer.
113  *
114  * Apart from shdesc contents, the total number of words that
115  * get loaded in deco buffer are '8' or '11'. The remaining words
116  * in deco buffer can be used for storing shared descriptor.
117  */
118 #define MAX_SDLEN	((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
119 
120 /* Length of a single buffer in the QI driver memory cache */
121 #define CAAM_QI_MEMCACHE_SIZE	512
122 
123 /*
124  * aead_edesc - s/w-extended aead descriptor
125  * @src_nents: number of segments in input scatterlist
126  * @dst_nents: number of segments in output scatterlist
127  * @iv_dma: dma address of iv for checking continuity and link table
128  * @qm_sg_bytes: length of dma mapped h/w link table
129  * @qm_sg_dma: bus physical mapped address of h/w link table
130  * @assoclen: associated data length, in CAAM endianness
131  * @assoclen_dma: bus physical mapped address of req->assoclen
132  * @sgt: the h/w link table, followed by IV
133  */
134 struct aead_edesc {
135 	int src_nents;
136 	int dst_nents;
137 	dma_addr_t iv_dma;
138 	int qm_sg_bytes;
139 	dma_addr_t qm_sg_dma;
140 	unsigned int assoclen;
141 	dma_addr_t assoclen_dma;
142 	struct dpaa2_sg_entry sgt[0];
143 };
144 
145 /*
146  * skcipher_edesc - s/w-extended skcipher descriptor
147  * @src_nents: number of segments in input scatterlist
148  * @dst_nents: number of segments in output scatterlist
149  * @iv_dma: dma address of iv for checking continuity and link table
150  * @qm_sg_bytes: length of dma mapped qm_sg space
151  * @qm_sg_dma: I/O virtual address of h/w link table
152  * @sgt: the h/w link table, followed by IV
153  */
154 struct skcipher_edesc {
155 	int src_nents;
156 	int dst_nents;
157 	dma_addr_t iv_dma;
158 	int qm_sg_bytes;
159 	dma_addr_t qm_sg_dma;
160 	struct dpaa2_sg_entry sgt[0];
161 };
162 
163 /*
164  * ahash_edesc - s/w-extended ahash descriptor
165  * @qm_sg_dma: I/O virtual address of h/w link table
166  * @src_nents: number of segments in input scatterlist
167  * @qm_sg_bytes: length of dma mapped qm_sg space
168  * @sgt: pointer to h/w link table
169  */
170 struct ahash_edesc {
171 	dma_addr_t qm_sg_dma;
172 	int src_nents;
173 	int qm_sg_bytes;
174 	struct dpaa2_sg_entry sgt[0];
175 };
176 
177 /**
178  * caam_flc - Flow Context (FLC)
179  * @flc: Flow Context options
180  * @sh_desc: Shared Descriptor
181  */
182 struct caam_flc {
183 	u32 flc[16];
184 	u32 sh_desc[MAX_SDLEN];
185 } ____cacheline_aligned;
186 
187 enum optype {
188 	ENCRYPT = 0,
189 	DECRYPT,
190 	NUM_OP
191 };
192 
193 /**
194  * caam_request - the request structure the driver application should fill while
195  *                submitting a job to driver.
196  * @fd_flt: Frame list table defining input and output
197  *          fd_flt[0] - FLE pointing to output buffer
198  *          fd_flt[1] - FLE pointing to input buffer
199  * @fd_flt_dma: DMA address for the frame list table
200  * @flc: Flow Context
201  * @flc_dma: I/O virtual address of Flow Context
202  * @cbk: Callback function to invoke when job is completed
203  * @ctx: arbit context attached with request by the application
204  * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
205  */
206 struct caam_request {
207 	struct dpaa2_fl_entry fd_flt[2];
208 	dma_addr_t fd_flt_dma;
209 	struct caam_flc *flc;
210 	dma_addr_t flc_dma;
211 	void (*cbk)(void *ctx, u32 err);
212 	void *ctx;
213 	void *edesc;
214 };
215 
216 /**
217  * dpaa2_caam_enqueue() - enqueue a crypto request
218  * @dev: device associated with the DPSECI object
219  * @req: pointer to caam_request
220  */
221 int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
222 
223 #endif	/* _CAAMALG_QI2_H_ */
224