xref: /openbmc/linux/drivers/crypto/bcm/cipher.c (revision cd6d421e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright 2016 Broadcom
4  */
5 
6 #include <linux/err.h>
7 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/errno.h>
10 #include <linux/kernel.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/scatterlist.h>
14 #include <linux/crypto.h>
15 #include <linux/kthread.h>
16 #include <linux/rtnetlink.h>
17 #include <linux/sched.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/io.h>
21 #include <linux/bitops.h>
22 
23 #include <crypto/algapi.h>
24 #include <crypto/aead.h>
25 #include <crypto/internal/aead.h>
26 #include <crypto/aes.h>
27 #include <crypto/internal/des.h>
28 #include <crypto/hmac.h>
29 #include <crypto/md5.h>
30 #include <crypto/authenc.h>
31 #include <crypto/skcipher.h>
32 #include <crypto/hash.h>
33 #include <crypto/sha1.h>
34 #include <crypto/sha2.h>
35 #include <crypto/sha3.h>
36 
37 #include "util.h"
38 #include "cipher.h"
39 #include "spu.h"
40 #include "spum.h"
41 #include "spu2.h"
42 
43 /* ================= Device Structure ================== */
44 
45 struct bcm_device_private iproc_priv;
46 
47 /* ==================== Parameters ===================== */
48 
49 int flow_debug_logging;
50 module_param(flow_debug_logging, int, 0644);
51 MODULE_PARM_DESC(flow_debug_logging, "Enable Flow Debug Logging");
52 
53 int packet_debug_logging;
54 module_param(packet_debug_logging, int, 0644);
55 MODULE_PARM_DESC(packet_debug_logging, "Enable Packet Debug Logging");
56 
57 int debug_logging_sleep;
58 module_param(debug_logging_sleep, int, 0644);
59 MODULE_PARM_DESC(debug_logging_sleep, "Packet Debug Logging Sleep");
60 
61 /*
62  * The value of these module parameters is used to set the priority for each
63  * algo type when this driver registers algos with the kernel crypto API.
64  * To use a priority other than the default, set the priority in the insmod or
65  * modprobe. Changing the module priority after init time has no effect.
66  *
67  * The default priorities are chosen to be lower (less preferred) than ARMv8 CE
68  * algos, but more preferred than generic software algos.
69  */
70 static int cipher_pri = 150;
71 module_param(cipher_pri, int, 0644);
72 MODULE_PARM_DESC(cipher_pri, "Priority for cipher algos");
73 
74 static int hash_pri = 100;
75 module_param(hash_pri, int, 0644);
76 MODULE_PARM_DESC(hash_pri, "Priority for hash algos");
77 
78 static int aead_pri = 150;
79 module_param(aead_pri, int, 0644);
80 MODULE_PARM_DESC(aead_pri, "Priority for AEAD algos");
81 
82 /* A type 3 BCM header, expected to precede the SPU header for SPU-M.
83  * Bits 3 and 4 in the first byte encode the channel number (the dma ringset).
84  * 0x60 - ring 0
85  * 0x68 - ring 1
86  * 0x70 - ring 2
87  * 0x78 - ring 3
88  */
89 static char BCMHEADER[] = { 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28 };
90 /*
91  * Some SPU hw does not use BCM header on SPU messages. So BCM_HDR_LEN
92  * is set dynamically after reading SPU type from device tree.
93  */
94 #define BCM_HDR_LEN  iproc_priv.bcm_hdr_len
95 
96 /* min and max time to sleep before retrying when mbox queue is full. usec */
97 #define MBOX_SLEEP_MIN  800
98 #define MBOX_SLEEP_MAX 1000
99 
100 /**
101  * select_channel() - Select a SPU channel to handle a crypto request. Selects
102  * channel in round robin order.
103  *
104  * Return:  channel index
105  */
106 static u8 select_channel(void)
107 {
108 	u8 chan_idx = atomic_inc_return(&iproc_priv.next_chan);
109 
110 	return chan_idx % iproc_priv.spu.num_chan;
111 }
112 
113 /**
114  * spu_skcipher_rx_sg_create() - Build up the scatterlist of buffers used to
115  * receive a SPU response message for an skcipher request. Includes buffers to
116  * catch SPU message headers and the response data.
117  * @mssg:	mailbox message containing the receive sg
118  * @rctx:	crypto request context
119  * @rx_frag_num: number of scatterlist elements required to hold the
120  *		SPU response message
121  * @chunksize:	Number of bytes of response data expected
122  * @stat_pad_len: Number of bytes required to pad the STAT field to
123  *		a 4-byte boundary
124  *
125  * The scatterlist that gets allocated here is freed in spu_chunk_cleanup()
126  * when the request completes, whether the request is handled successfully or
127  * there is an error.
128  *
129  * Returns:
130  *   0 if successful
131  *   < 0 if an error
132  */
133 static int
134 spu_skcipher_rx_sg_create(struct brcm_message *mssg,
135 			    struct iproc_reqctx_s *rctx,
136 			    u8 rx_frag_num,
137 			    unsigned int chunksize, u32 stat_pad_len)
138 {
139 	struct spu_hw *spu = &iproc_priv.spu;
140 	struct scatterlist *sg;	/* used to build sgs in mbox message */
141 	struct iproc_ctx_s *ctx = rctx->ctx;
142 	u32 datalen;		/* Number of bytes of response data expected */
143 
144 	mssg->spu.dst = kcalloc(rx_frag_num, sizeof(struct scatterlist),
145 				rctx->gfp);
146 	if (!mssg->spu.dst)
147 		return -ENOMEM;
148 
149 	sg = mssg->spu.dst;
150 	sg_init_table(sg, rx_frag_num);
151 	/* Space for SPU message header */
152 	sg_set_buf(sg++, rctx->msg_buf.spu_resp_hdr, ctx->spu_resp_hdr_len);
153 
154 	/* If XTS tweak in payload, add buffer to receive encrypted tweak */
155 	if ((ctx->cipher.mode == CIPHER_MODE_XTS) &&
156 	    spu->spu_xts_tweak_in_payload())
157 		sg_set_buf(sg++, rctx->msg_buf.c.supdt_tweak,
158 			   SPU_XTS_TWEAK_SIZE);
159 
160 	/* Copy in each dst sg entry from request, up to chunksize */
161 	datalen = spu_msg_sg_add(&sg, &rctx->dst_sg, &rctx->dst_skip,
162 				 rctx->dst_nents, chunksize);
163 	if (datalen < chunksize) {
164 		pr_err("%s(): failed to copy dst sg to mbox msg. chunksize %u, datalen %u",
165 		       __func__, chunksize, datalen);
166 		return -EFAULT;
167 	}
168 
169 	if (stat_pad_len)
170 		sg_set_buf(sg++, rctx->msg_buf.rx_stat_pad, stat_pad_len);
171 
172 	memset(rctx->msg_buf.rx_stat, 0, SPU_RX_STATUS_LEN);
173 	sg_set_buf(sg, rctx->msg_buf.rx_stat, spu->spu_rx_status_len());
174 
175 	return 0;
176 }
177 
178 /**
179  * spu_skcipher_tx_sg_create() - Build up the scatterlist of buffers used to
180  * send a SPU request message for an skcipher request. Includes SPU message
181  * headers and the request data.
182  * @mssg:	mailbox message containing the transmit sg
183  * @rctx:	crypto request context
184  * @tx_frag_num: number of scatterlist elements required to construct the
185  *		SPU request message
186  * @chunksize:	Number of bytes of request data
187  * @pad_len:	Number of pad bytes
188  *
189  * The scatterlist that gets allocated here is freed in spu_chunk_cleanup()
190  * when the request completes, whether the request is handled successfully or
191  * there is an error.
192  *
193  * Returns:
194  *   0 if successful
195  *   < 0 if an error
196  */
197 static int
198 spu_skcipher_tx_sg_create(struct brcm_message *mssg,
199 			    struct iproc_reqctx_s *rctx,
200 			    u8 tx_frag_num, unsigned int chunksize, u32 pad_len)
201 {
202 	struct spu_hw *spu = &iproc_priv.spu;
203 	struct scatterlist *sg;	/* used to build sgs in mbox message */
204 	struct iproc_ctx_s *ctx = rctx->ctx;
205 	u32 datalen;		/* Number of bytes of response data expected */
206 	u32 stat_len;
207 
208 	mssg->spu.src = kcalloc(tx_frag_num, sizeof(struct scatterlist),
209 				rctx->gfp);
210 	if (unlikely(!mssg->spu.src))
211 		return -ENOMEM;
212 
213 	sg = mssg->spu.src;
214 	sg_init_table(sg, tx_frag_num);
215 
216 	sg_set_buf(sg++, rctx->msg_buf.bcm_spu_req_hdr,
217 		   BCM_HDR_LEN + ctx->spu_req_hdr_len);
218 
219 	/* if XTS tweak in payload, copy from IV (where crypto API puts it) */
220 	if ((ctx->cipher.mode == CIPHER_MODE_XTS) &&
221 	    spu->spu_xts_tweak_in_payload())
222 		sg_set_buf(sg++, rctx->msg_buf.iv_ctr, SPU_XTS_TWEAK_SIZE);
223 
224 	/* Copy in each src sg entry from request, up to chunksize */
225 	datalen = spu_msg_sg_add(&sg, &rctx->src_sg, &rctx->src_skip,
226 				 rctx->src_nents, chunksize);
227 	if (unlikely(datalen < chunksize)) {
228 		pr_err("%s(): failed to copy src sg to mbox msg",
229 		       __func__);
230 		return -EFAULT;
231 	}
232 
233 	if (pad_len)
234 		sg_set_buf(sg++, rctx->msg_buf.spu_req_pad, pad_len);
235 
236 	stat_len = spu->spu_tx_status_len();
237 	if (stat_len) {
238 		memset(rctx->msg_buf.tx_stat, 0, stat_len);
239 		sg_set_buf(sg, rctx->msg_buf.tx_stat, stat_len);
240 	}
241 	return 0;
242 }
243 
244 static int mailbox_send_message(struct brcm_message *mssg, u32 flags,
245 				u8 chan_idx)
246 {
247 	int err;
248 	int retry_cnt = 0;
249 	struct device *dev = &(iproc_priv.pdev->dev);
250 
251 	err = mbox_send_message(iproc_priv.mbox[chan_idx], mssg);
252 	if (flags & CRYPTO_TFM_REQ_MAY_SLEEP) {
253 		while ((err == -ENOBUFS) && (retry_cnt < SPU_MB_RETRY_MAX)) {
254 			/*
255 			 * Mailbox queue is full. Since MAY_SLEEP is set, assume
256 			 * not in atomic context and we can wait and try again.
257 			 */
258 			retry_cnt++;
259 			usleep_range(MBOX_SLEEP_MIN, MBOX_SLEEP_MAX);
260 			err = mbox_send_message(iproc_priv.mbox[chan_idx],
261 						mssg);
262 			atomic_inc(&iproc_priv.mb_no_spc);
263 		}
264 	}
265 	if (err < 0) {
266 		atomic_inc(&iproc_priv.mb_send_fail);
267 		return err;
268 	}
269 
270 	/* Check error returned by mailbox controller */
271 	err = mssg->error;
272 	if (unlikely(err < 0)) {
273 		dev_err(dev, "message error %d", err);
274 		/* Signal txdone for mailbox channel */
275 	}
276 
277 	/* Signal txdone for mailbox channel */
278 	mbox_client_txdone(iproc_priv.mbox[chan_idx], err);
279 	return err;
280 }
281 
282 /**
283  * handle_skcipher_req() - Submit as much of a block cipher request as fits in
284  * a single SPU request message, starting at the current position in the request
285  * data.
286  * @rctx:	Crypto request context
287  *
288  * This may be called on the crypto API thread, or, when a request is so large
289  * it must be broken into multiple SPU messages, on the thread used to invoke
290  * the response callback. When requests are broken into multiple SPU
291  * messages, we assume subsequent messages depend on previous results, and
292  * thus always wait for previous results before submitting the next message.
293  * Because requests are submitted in lock step like this, there is no need
294  * to synchronize access to request data structures.
295  *
296  * Return: -EINPROGRESS: request has been accepted and result will be returned
297  *			 asynchronously
298  *         Any other value indicates an error
299  */
300 static int handle_skcipher_req(struct iproc_reqctx_s *rctx)
301 {
302 	struct spu_hw *spu = &iproc_priv.spu;
303 	struct crypto_async_request *areq = rctx->parent;
304 	struct skcipher_request *req =
305 	    container_of(areq, struct skcipher_request, base);
306 	struct iproc_ctx_s *ctx = rctx->ctx;
307 	struct spu_cipher_parms cipher_parms;
308 	int err;
309 	unsigned int chunksize;	/* Num bytes of request to submit */
310 	int remaining;	/* Bytes of request still to process */
311 	int chunk_start;	/* Beginning of data for current SPU msg */
312 
313 	/* IV or ctr value to use in this SPU msg */
314 	u8 local_iv_ctr[MAX_IV_SIZE];
315 	u32 stat_pad_len;	/* num bytes to align status field */
316 	u32 pad_len;		/* total length of all padding */
317 	struct brcm_message *mssg;	/* mailbox message */
318 
319 	/* number of entries in src and dst sg in mailbox message. */
320 	u8 rx_frag_num = 2;	/* response header and STATUS */
321 	u8 tx_frag_num = 1;	/* request header */
322 
323 	flow_log("%s\n", __func__);
324 
325 	cipher_parms.alg = ctx->cipher.alg;
326 	cipher_parms.mode = ctx->cipher.mode;
327 	cipher_parms.type = ctx->cipher_type;
328 	cipher_parms.key_len = ctx->enckeylen;
329 	cipher_parms.key_buf = ctx->enckey;
330 	cipher_parms.iv_buf = local_iv_ctr;
331 	cipher_parms.iv_len = rctx->iv_ctr_len;
332 
333 	mssg = &rctx->mb_mssg;
334 	chunk_start = rctx->src_sent;
335 	remaining = rctx->total_todo - chunk_start;
336 
337 	/* determine the chunk we are breaking off and update the indexes */
338 	if ((ctx->max_payload != SPU_MAX_PAYLOAD_INF) &&
339 	    (remaining > ctx->max_payload))
340 		chunksize = ctx->max_payload;
341 	else
342 		chunksize = remaining;
343 
344 	rctx->src_sent += chunksize;
345 	rctx->total_sent = rctx->src_sent;
346 
347 	/* Count number of sg entries to be included in this request */
348 	rctx->src_nents = spu_sg_count(rctx->src_sg, rctx->src_skip, chunksize);
349 	rctx->dst_nents = spu_sg_count(rctx->dst_sg, rctx->dst_skip, chunksize);
350 
351 	if ((ctx->cipher.mode == CIPHER_MODE_CBC) &&
352 	    rctx->is_encrypt && chunk_start)
353 		/*
354 		 * Encrypting non-first first chunk. Copy last block of
355 		 * previous result to IV for this chunk.
356 		 */
357 		sg_copy_part_to_buf(req->dst, rctx->msg_buf.iv_ctr,
358 				    rctx->iv_ctr_len,
359 				    chunk_start - rctx->iv_ctr_len);
360 
361 	if (rctx->iv_ctr_len) {
362 		/* get our local copy of the iv */
363 		__builtin_memcpy(local_iv_ctr, rctx->msg_buf.iv_ctr,
364 				 rctx->iv_ctr_len);
365 
366 		/* generate the next IV if possible */
367 		if ((ctx->cipher.mode == CIPHER_MODE_CBC) &&
368 		    !rctx->is_encrypt) {
369 			/*
370 			 * CBC Decrypt: next IV is the last ciphertext block in
371 			 * this chunk
372 			 */
373 			sg_copy_part_to_buf(req->src, rctx->msg_buf.iv_ctr,
374 					    rctx->iv_ctr_len,
375 					    rctx->src_sent - rctx->iv_ctr_len);
376 		} else if (ctx->cipher.mode == CIPHER_MODE_CTR) {
377 			/*
378 			 * The SPU hardware increments the counter once for
379 			 * each AES block of 16 bytes. So update the counter
380 			 * for the next chunk, if there is one. Note that for
381 			 * this chunk, the counter has already been copied to
382 			 * local_iv_ctr. We can assume a block size of 16,
383 			 * because we only support CTR mode for AES, not for
384 			 * any other cipher alg.
385 			 */
386 			add_to_ctr(rctx->msg_buf.iv_ctr, chunksize >> 4);
387 		}
388 	}
389 
390 	if (ctx->max_payload == SPU_MAX_PAYLOAD_INF)
391 		flow_log("max_payload infinite\n");
392 	else
393 		flow_log("max_payload %u\n", ctx->max_payload);
394 
395 	flow_log("sent:%u start:%u remains:%u size:%u\n",
396 		 rctx->src_sent, chunk_start, remaining, chunksize);
397 
398 	/* Copy SPU header template created at setkey time */
399 	memcpy(rctx->msg_buf.bcm_spu_req_hdr, ctx->bcm_spu_req_hdr,
400 	       sizeof(rctx->msg_buf.bcm_spu_req_hdr));
401 
402 	spu->spu_cipher_req_finish(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,
403 				   ctx->spu_req_hdr_len, !(rctx->is_encrypt),
404 				   &cipher_parms, chunksize);
405 
406 	atomic64_add(chunksize, &iproc_priv.bytes_out);
407 
408 	stat_pad_len = spu->spu_wordalign_padlen(chunksize);
409 	if (stat_pad_len)
410 		rx_frag_num++;
411 	pad_len = stat_pad_len;
412 	if (pad_len) {
413 		tx_frag_num++;
414 		spu->spu_request_pad(rctx->msg_buf.spu_req_pad, 0,
415 				     0, ctx->auth.alg, ctx->auth.mode,
416 				     rctx->total_sent, stat_pad_len);
417 	}
418 
419 	spu->spu_dump_msg_hdr(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,
420 			      ctx->spu_req_hdr_len);
421 	packet_log("payload:\n");
422 	dump_sg(rctx->src_sg, rctx->src_skip, chunksize);
423 	packet_dump("   pad: ", rctx->msg_buf.spu_req_pad, pad_len);
424 
425 	/*
426 	 * Build mailbox message containing SPU request msg and rx buffers
427 	 * to catch response message
428 	 */
429 	memset(mssg, 0, sizeof(*mssg));
430 	mssg->type = BRCM_MESSAGE_SPU;
431 	mssg->ctx = rctx;	/* Will be returned in response */
432 
433 	/* Create rx scatterlist to catch result */
434 	rx_frag_num += rctx->dst_nents;
435 
436 	if ((ctx->cipher.mode == CIPHER_MODE_XTS) &&
437 	    spu->spu_xts_tweak_in_payload())
438 		rx_frag_num++;	/* extra sg to insert tweak */
439 
440 	err = spu_skcipher_rx_sg_create(mssg, rctx, rx_frag_num, chunksize,
441 					  stat_pad_len);
442 	if (err)
443 		return err;
444 
445 	/* Create tx scatterlist containing SPU request message */
446 	tx_frag_num += rctx->src_nents;
447 	if (spu->spu_tx_status_len())
448 		tx_frag_num++;
449 
450 	if ((ctx->cipher.mode == CIPHER_MODE_XTS) &&
451 	    spu->spu_xts_tweak_in_payload())
452 		tx_frag_num++;	/* extra sg to insert tweak */
453 
454 	err = spu_skcipher_tx_sg_create(mssg, rctx, tx_frag_num, chunksize,
455 					  pad_len);
456 	if (err)
457 		return err;
458 
459 	err = mailbox_send_message(mssg, req->base.flags, rctx->chan_idx);
460 	if (unlikely(err < 0))
461 		return err;
462 
463 	return -EINPROGRESS;
464 }
465 
466 /**
467  * handle_skcipher_resp() - Process a block cipher SPU response. Updates the
468  * total received count for the request and updates global stats.
469  * @rctx:	Crypto request context
470  */
471 static void handle_skcipher_resp(struct iproc_reqctx_s *rctx)
472 {
473 	struct spu_hw *spu = &iproc_priv.spu;
474 	struct crypto_async_request *areq = rctx->parent;
475 	struct skcipher_request *req = skcipher_request_cast(areq);
476 	struct iproc_ctx_s *ctx = rctx->ctx;
477 	u32 payload_len;
478 
479 	/* See how much data was returned */
480 	payload_len = spu->spu_payload_length(rctx->msg_buf.spu_resp_hdr);
481 
482 	/*
483 	 * In XTS mode, the first SPU_XTS_TWEAK_SIZE bytes may be the
484 	 * encrypted tweak ("i") value; we don't count those.
485 	 */
486 	if ((ctx->cipher.mode == CIPHER_MODE_XTS) &&
487 	    spu->spu_xts_tweak_in_payload() &&
488 	    (payload_len >= SPU_XTS_TWEAK_SIZE))
489 		payload_len -= SPU_XTS_TWEAK_SIZE;
490 
491 	atomic64_add(payload_len, &iproc_priv.bytes_in);
492 
493 	flow_log("%s() offset: %u, bd_len: %u BD:\n",
494 		 __func__, rctx->total_received, payload_len);
495 
496 	dump_sg(req->dst, rctx->total_received, payload_len);
497 
498 	rctx->total_received += payload_len;
499 	if (rctx->total_received == rctx->total_todo) {
500 		atomic_inc(&iproc_priv.op_counts[SPU_OP_CIPHER]);
501 		atomic_inc(
502 		   &iproc_priv.cipher_cnt[ctx->cipher.alg][ctx->cipher.mode]);
503 	}
504 }
505 
506 /**
507  * spu_ahash_rx_sg_create() - Build up the scatterlist of buffers used to
508  * receive a SPU response message for an ahash request.
509  * @mssg:	mailbox message containing the receive sg
510  * @rctx:	crypto request context
511  * @rx_frag_num: number of scatterlist elements required to hold the
512  *		SPU response message
513  * @digestsize: length of hash digest, in bytes
514  * @stat_pad_len: Number of bytes required to pad the STAT field to
515  *		a 4-byte boundary
516  *
517  * The scatterlist that gets allocated here is freed in spu_chunk_cleanup()
518  * when the request completes, whether the request is handled successfully or
519  * there is an error.
520  *
521  * Return:
522  *   0 if successful
523  *   < 0 if an error
524  */
525 static int
526 spu_ahash_rx_sg_create(struct brcm_message *mssg,
527 		       struct iproc_reqctx_s *rctx,
528 		       u8 rx_frag_num, unsigned int digestsize,
529 		       u32 stat_pad_len)
530 {
531 	struct spu_hw *spu = &iproc_priv.spu;
532 	struct scatterlist *sg;	/* used to build sgs in mbox message */
533 	struct iproc_ctx_s *ctx = rctx->ctx;
534 
535 	mssg->spu.dst = kcalloc(rx_frag_num, sizeof(struct scatterlist),
536 				rctx->gfp);
537 	if (!mssg->spu.dst)
538 		return -ENOMEM;
539 
540 	sg = mssg->spu.dst;
541 	sg_init_table(sg, rx_frag_num);
542 	/* Space for SPU message header */
543 	sg_set_buf(sg++, rctx->msg_buf.spu_resp_hdr, ctx->spu_resp_hdr_len);
544 
545 	/* Space for digest */
546 	sg_set_buf(sg++, rctx->msg_buf.digest, digestsize);
547 
548 	if (stat_pad_len)
549 		sg_set_buf(sg++, rctx->msg_buf.rx_stat_pad, stat_pad_len);
550 
551 	memset(rctx->msg_buf.rx_stat, 0, SPU_RX_STATUS_LEN);
552 	sg_set_buf(sg, rctx->msg_buf.rx_stat, spu->spu_rx_status_len());
553 	return 0;
554 }
555 
556 /**
557  * spu_ahash_tx_sg_create() -  Build up the scatterlist of buffers used to send
558  * a SPU request message for an ahash request. Includes SPU message headers and
559  * the request data.
560  * @mssg:	mailbox message containing the transmit sg
561  * @rctx:	crypto request context
562  * @tx_frag_num: number of scatterlist elements required to construct the
563  *		SPU request message
564  * @spu_hdr_len: length in bytes of SPU message header
565  * @hash_carry_len: Number of bytes of data carried over from previous req
566  * @new_data_len: Number of bytes of new request data
567  * @pad_len:	Number of pad bytes
568  *
569  * The scatterlist that gets allocated here is freed in spu_chunk_cleanup()
570  * when the request completes, whether the request is handled successfully or
571  * there is an error.
572  *
573  * Return:
574  *   0 if successful
575  *   < 0 if an error
576  */
577 static int
578 spu_ahash_tx_sg_create(struct brcm_message *mssg,
579 		       struct iproc_reqctx_s *rctx,
580 		       u8 tx_frag_num,
581 		       u32 spu_hdr_len,
582 		       unsigned int hash_carry_len,
583 		       unsigned int new_data_len, u32 pad_len)
584 {
585 	struct spu_hw *spu = &iproc_priv.spu;
586 	struct scatterlist *sg;	/* used to build sgs in mbox message */
587 	u32 datalen;		/* Number of bytes of response data expected */
588 	u32 stat_len;
589 
590 	mssg->spu.src = kcalloc(tx_frag_num, sizeof(struct scatterlist),
591 				rctx->gfp);
592 	if (!mssg->spu.src)
593 		return -ENOMEM;
594 
595 	sg = mssg->spu.src;
596 	sg_init_table(sg, tx_frag_num);
597 
598 	sg_set_buf(sg++, rctx->msg_buf.bcm_spu_req_hdr,
599 		   BCM_HDR_LEN + spu_hdr_len);
600 
601 	if (hash_carry_len)
602 		sg_set_buf(sg++, rctx->hash_carry, hash_carry_len);
603 
604 	if (new_data_len) {
605 		/* Copy in each src sg entry from request, up to chunksize */
606 		datalen = spu_msg_sg_add(&sg, &rctx->src_sg, &rctx->src_skip,
607 					 rctx->src_nents, new_data_len);
608 		if (datalen < new_data_len) {
609 			pr_err("%s(): failed to copy src sg to mbox msg",
610 			       __func__);
611 			return -EFAULT;
612 		}
613 	}
614 
615 	if (pad_len)
616 		sg_set_buf(sg++, rctx->msg_buf.spu_req_pad, pad_len);
617 
618 	stat_len = spu->spu_tx_status_len();
619 	if (stat_len) {
620 		memset(rctx->msg_buf.tx_stat, 0, stat_len);
621 		sg_set_buf(sg, rctx->msg_buf.tx_stat, stat_len);
622 	}
623 
624 	return 0;
625 }
626 
627 /**
628  * handle_ahash_req() - Process an asynchronous hash request from the crypto
629  * API.
630  * @rctx:  Crypto request context
631  *
632  * Builds a SPU request message embedded in a mailbox message and submits the
633  * mailbox message on a selected mailbox channel. The SPU request message is
634  * constructed as a scatterlist, including entries from the crypto API's
635  * src scatterlist to avoid copying the data to be hashed. This function is
636  * called either on the thread from the crypto API, or, in the case that the
637  * crypto API request is too large to fit in a single SPU request message,
638  * on the thread that invokes the receive callback with a response message.
639  * Because some operations require the response from one chunk before the next
640  * chunk can be submitted, we always wait for the response for the previous
641  * chunk before submitting the next chunk. Because requests are submitted in
642  * lock step like this, there is no need to synchronize access to request data
643  * structures.
644  *
645  * Return:
646  *   -EINPROGRESS: request has been submitted to SPU and response will be
647  *		   returned asynchronously
648  *   -EAGAIN:      non-final request included a small amount of data, which for
649  *		   efficiency we did not submit to the SPU, but instead stored
650  *		   to be submitted to the SPU with the next part of the request
651  *   other:        an error code
652  */
653 static int handle_ahash_req(struct iproc_reqctx_s *rctx)
654 {
655 	struct spu_hw *spu = &iproc_priv.spu;
656 	struct crypto_async_request *areq = rctx->parent;
657 	struct ahash_request *req = ahash_request_cast(areq);
658 	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
659 	struct crypto_tfm *tfm = crypto_ahash_tfm(ahash);
660 	unsigned int blocksize = crypto_tfm_alg_blocksize(tfm);
661 	struct iproc_ctx_s *ctx = rctx->ctx;
662 
663 	/* number of bytes still to be hashed in this req */
664 	unsigned int nbytes_to_hash = 0;
665 	int err;
666 	unsigned int chunksize = 0;	/* length of hash carry + new data */
667 	/*
668 	 * length of new data, not from hash carry, to be submitted in
669 	 * this hw request
670 	 */
671 	unsigned int new_data_len;
672 
673 	unsigned int __maybe_unused chunk_start = 0;
674 	u32 db_size;	 /* Length of data field, incl gcm and hash padding */
675 	int pad_len = 0; /* total pad len, including gcm, hash, stat padding */
676 	u32 data_pad_len = 0;	/* length of GCM/CCM padding */
677 	u32 stat_pad_len = 0;	/* length of padding to align STATUS word */
678 	struct brcm_message *mssg;	/* mailbox message */
679 	struct spu_request_opts req_opts;
680 	struct spu_cipher_parms cipher_parms;
681 	struct spu_hash_parms hash_parms;
682 	struct spu_aead_parms aead_parms;
683 	unsigned int local_nbuf;
684 	u32 spu_hdr_len;
685 	unsigned int digestsize;
686 	u16 rem = 0;
687 
688 	/*
689 	 * number of entries in src and dst sg. Always includes SPU msg header.
690 	 * rx always includes a buffer to catch digest and STATUS.
691 	 */
692 	u8 rx_frag_num = 3;
693 	u8 tx_frag_num = 1;
694 
695 	flow_log("total_todo %u, total_sent %u\n",
696 		 rctx->total_todo, rctx->total_sent);
697 
698 	memset(&req_opts, 0, sizeof(req_opts));
699 	memset(&cipher_parms, 0, sizeof(cipher_parms));
700 	memset(&hash_parms, 0, sizeof(hash_parms));
701 	memset(&aead_parms, 0, sizeof(aead_parms));
702 
703 	req_opts.bd_suppress = true;
704 	hash_parms.alg = ctx->auth.alg;
705 	hash_parms.mode = ctx->auth.mode;
706 	hash_parms.type = HASH_TYPE_NONE;
707 	hash_parms.key_buf = (u8 *)ctx->authkey;
708 	hash_parms.key_len = ctx->authkeylen;
709 
710 	/*
711 	 * For hash algorithms below assignment looks bit odd but
712 	 * it's needed for AES-XCBC and AES-CMAC hash algorithms
713 	 * to differentiate between 128, 192, 256 bit key values.
714 	 * Based on the key values, hash algorithm is selected.
715 	 * For example for 128 bit key, hash algorithm is AES-128.
716 	 */
717 	cipher_parms.type = ctx->cipher_type;
718 
719 	mssg = &rctx->mb_mssg;
720 	chunk_start = rctx->src_sent;
721 
722 	/*
723 	 * Compute the amount remaining to hash. This may include data
724 	 * carried over from previous requests.
725 	 */
726 	nbytes_to_hash = rctx->total_todo - rctx->total_sent;
727 	chunksize = nbytes_to_hash;
728 	if ((ctx->max_payload != SPU_MAX_PAYLOAD_INF) &&
729 	    (chunksize > ctx->max_payload))
730 		chunksize = ctx->max_payload;
731 
732 	/*
733 	 * If this is not a final request and the request data is not a multiple
734 	 * of a full block, then simply park the extra data and prefix it to the
735 	 * data for the next request.
736 	 */
737 	if (!rctx->is_final) {
738 		u8 *dest = rctx->hash_carry + rctx->hash_carry_len;
739 		u16 new_len;  /* len of data to add to hash carry */
740 
741 		rem = chunksize % blocksize;   /* remainder */
742 		if (rem) {
743 			/* chunksize not a multiple of blocksize */
744 			chunksize -= rem;
745 			if (chunksize == 0) {
746 				/* Don't have a full block to submit to hw */
747 				new_len = rem - rctx->hash_carry_len;
748 				sg_copy_part_to_buf(req->src, dest, new_len,
749 						    rctx->src_sent);
750 				rctx->hash_carry_len = rem;
751 				flow_log("Exiting with hash carry len: %u\n",
752 					 rctx->hash_carry_len);
753 				packet_dump("  buf: ",
754 					    rctx->hash_carry,
755 					    rctx->hash_carry_len);
756 				return -EAGAIN;
757 			}
758 		}
759 	}
760 
761 	/* if we have hash carry, then prefix it to the data in this request */
762 	local_nbuf = rctx->hash_carry_len;
763 	rctx->hash_carry_len = 0;
764 	if (local_nbuf)
765 		tx_frag_num++;
766 	new_data_len = chunksize - local_nbuf;
767 
768 	/* Count number of sg entries to be used in this request */
769 	rctx->src_nents = spu_sg_count(rctx->src_sg, rctx->src_skip,
770 				       new_data_len);
771 
772 	/* AES hashing keeps key size in type field, so need to copy it here */
773 	if (hash_parms.alg == HASH_ALG_AES)
774 		hash_parms.type = (enum hash_type)cipher_parms.type;
775 	else
776 		hash_parms.type = spu->spu_hash_type(rctx->total_sent);
777 
778 	digestsize = spu->spu_digest_size(ctx->digestsize, ctx->auth.alg,
779 					  hash_parms.type);
780 	hash_parms.digestsize =	digestsize;
781 
782 	/* update the indexes */
783 	rctx->total_sent += chunksize;
784 	/* if you sent a prebuf then that wasn't from this req->src */
785 	rctx->src_sent += new_data_len;
786 
787 	if ((rctx->total_sent == rctx->total_todo) && rctx->is_final)
788 		hash_parms.pad_len = spu->spu_hash_pad_len(hash_parms.alg,
789 							   hash_parms.mode,
790 							   chunksize,
791 							   blocksize);
792 
793 	/*
794 	 * If a non-first chunk, then include the digest returned from the
795 	 * previous chunk so that hw can add to it (except for AES types).
796 	 */
797 	if ((hash_parms.type == HASH_TYPE_UPDT) &&
798 	    (hash_parms.alg != HASH_ALG_AES)) {
799 		hash_parms.key_buf = rctx->incr_hash;
800 		hash_parms.key_len = digestsize;
801 	}
802 
803 	atomic64_add(chunksize, &iproc_priv.bytes_out);
804 
805 	flow_log("%s() final: %u nbuf: %u ",
806 		 __func__, rctx->is_final, local_nbuf);
807 
808 	if (ctx->max_payload == SPU_MAX_PAYLOAD_INF)
809 		flow_log("max_payload infinite\n");
810 	else
811 		flow_log("max_payload %u\n", ctx->max_payload);
812 
813 	flow_log("chunk_start: %u chunk_size: %u\n", chunk_start, chunksize);
814 
815 	/* Prepend SPU header with type 3 BCM header */
816 	memcpy(rctx->msg_buf.bcm_spu_req_hdr, BCMHEADER, BCM_HDR_LEN);
817 
818 	hash_parms.prebuf_len = local_nbuf;
819 	spu_hdr_len = spu->spu_create_request(rctx->msg_buf.bcm_spu_req_hdr +
820 					      BCM_HDR_LEN,
821 					      &req_opts, &cipher_parms,
822 					      &hash_parms, &aead_parms,
823 					      new_data_len);
824 
825 	if (spu_hdr_len == 0) {
826 		pr_err("Failed to create SPU request header\n");
827 		return -EFAULT;
828 	}
829 
830 	/*
831 	 * Determine total length of padding required. Put all padding in one
832 	 * buffer.
833 	 */
834 	data_pad_len = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode, chunksize);
835 	db_size = spu_real_db_size(0, 0, local_nbuf, new_data_len,
836 				   0, 0, hash_parms.pad_len);
837 	if (spu->spu_tx_status_len())
838 		stat_pad_len = spu->spu_wordalign_padlen(db_size);
839 	if (stat_pad_len)
840 		rx_frag_num++;
841 	pad_len = hash_parms.pad_len + data_pad_len + stat_pad_len;
842 	if (pad_len) {
843 		tx_frag_num++;
844 		spu->spu_request_pad(rctx->msg_buf.spu_req_pad, data_pad_len,
845 				     hash_parms.pad_len, ctx->auth.alg,
846 				     ctx->auth.mode, rctx->total_sent,
847 				     stat_pad_len);
848 	}
849 
850 	spu->spu_dump_msg_hdr(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,
851 			      spu_hdr_len);
852 	packet_dump("    prebuf: ", rctx->hash_carry, local_nbuf);
853 	flow_log("Data:\n");
854 	dump_sg(rctx->src_sg, rctx->src_skip, new_data_len);
855 	packet_dump("   pad: ", rctx->msg_buf.spu_req_pad, pad_len);
856 
857 	/*
858 	 * Build mailbox message containing SPU request msg and rx buffers
859 	 * to catch response message
860 	 */
861 	memset(mssg, 0, sizeof(*mssg));
862 	mssg->type = BRCM_MESSAGE_SPU;
863 	mssg->ctx = rctx;	/* Will be returned in response */
864 
865 	/* Create rx scatterlist to catch result */
866 	err = spu_ahash_rx_sg_create(mssg, rctx, rx_frag_num, digestsize,
867 				     stat_pad_len);
868 	if (err)
869 		return err;
870 
871 	/* Create tx scatterlist containing SPU request message */
872 	tx_frag_num += rctx->src_nents;
873 	if (spu->spu_tx_status_len())
874 		tx_frag_num++;
875 	err = spu_ahash_tx_sg_create(mssg, rctx, tx_frag_num, spu_hdr_len,
876 				     local_nbuf, new_data_len, pad_len);
877 	if (err)
878 		return err;
879 
880 	err = mailbox_send_message(mssg, req->base.flags, rctx->chan_idx);
881 	if (unlikely(err < 0))
882 		return err;
883 
884 	return -EINPROGRESS;
885 }
886 
887 /**
888  * spu_hmac_outer_hash() - Request synchonous software compute of the outer hash
889  * for an HMAC request.
890  * @req:  The HMAC request from the crypto API
891  * @ctx:  The session context
892  *
893  * Return: 0 if synchronous hash operation successful
894  *         -EINVAL if the hash algo is unrecognized
895  *         any other value indicates an error
896  */
897 static int spu_hmac_outer_hash(struct ahash_request *req,
898 			       struct iproc_ctx_s *ctx)
899 {
900 	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
901 	unsigned int blocksize =
902 		crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
903 	int rc;
904 
905 	switch (ctx->auth.alg) {
906 	case HASH_ALG_MD5:
907 		rc = do_shash("md5", req->result, ctx->opad, blocksize,
908 			      req->result, ctx->digestsize, NULL, 0);
909 		break;
910 	case HASH_ALG_SHA1:
911 		rc = do_shash("sha1", req->result, ctx->opad, blocksize,
912 			      req->result, ctx->digestsize, NULL, 0);
913 		break;
914 	case HASH_ALG_SHA224:
915 		rc = do_shash("sha224", req->result, ctx->opad, blocksize,
916 			      req->result, ctx->digestsize, NULL, 0);
917 		break;
918 	case HASH_ALG_SHA256:
919 		rc = do_shash("sha256", req->result, ctx->opad, blocksize,
920 			      req->result, ctx->digestsize, NULL, 0);
921 		break;
922 	case HASH_ALG_SHA384:
923 		rc = do_shash("sha384", req->result, ctx->opad, blocksize,
924 			      req->result, ctx->digestsize, NULL, 0);
925 		break;
926 	case HASH_ALG_SHA512:
927 		rc = do_shash("sha512", req->result, ctx->opad, blocksize,
928 			      req->result, ctx->digestsize, NULL, 0);
929 		break;
930 	default:
931 		pr_err("%s() Error : unknown hmac type\n", __func__);
932 		rc = -EINVAL;
933 	}
934 	return rc;
935 }
936 
937 /**
938  * ahash_req_done() - Process a hash result from the SPU hardware.
939  * @rctx: Crypto request context
940  *
941  * Return: 0 if successful
942  *         < 0 if an error
943  */
944 static int ahash_req_done(struct iproc_reqctx_s *rctx)
945 {
946 	struct spu_hw *spu = &iproc_priv.spu;
947 	struct crypto_async_request *areq = rctx->parent;
948 	struct ahash_request *req = ahash_request_cast(areq);
949 	struct iproc_ctx_s *ctx = rctx->ctx;
950 	int err;
951 
952 	memcpy(req->result, rctx->msg_buf.digest, ctx->digestsize);
953 
954 	if (spu->spu_type == SPU_TYPE_SPUM) {
955 		/* byte swap the output from the UPDT function to network byte
956 		 * order
957 		 */
958 		if (ctx->auth.alg == HASH_ALG_MD5) {
959 			__swab32s((u32 *)req->result);
960 			__swab32s(((u32 *)req->result) + 1);
961 			__swab32s(((u32 *)req->result) + 2);
962 			__swab32s(((u32 *)req->result) + 3);
963 			__swab32s(((u32 *)req->result) + 4);
964 		}
965 	}
966 
967 	flow_dump("  digest ", req->result, ctx->digestsize);
968 
969 	/* if this an HMAC then do the outer hash */
970 	if (rctx->is_sw_hmac) {
971 		err = spu_hmac_outer_hash(req, ctx);
972 		if (err < 0)
973 			return err;
974 		flow_dump("  hmac: ", req->result, ctx->digestsize);
975 	}
976 
977 	if (rctx->is_sw_hmac || ctx->auth.mode == HASH_MODE_HMAC) {
978 		atomic_inc(&iproc_priv.op_counts[SPU_OP_HMAC]);
979 		atomic_inc(&iproc_priv.hmac_cnt[ctx->auth.alg]);
980 	} else {
981 		atomic_inc(&iproc_priv.op_counts[SPU_OP_HASH]);
982 		atomic_inc(&iproc_priv.hash_cnt[ctx->auth.alg]);
983 	}
984 
985 	return 0;
986 }
987 
988 /**
989  * handle_ahash_resp() - Process a SPU response message for a hash request.
990  * Checks if the entire crypto API request has been processed, and if so,
991  * invokes post processing on the result.
992  * @rctx: Crypto request context
993  */
994 static void handle_ahash_resp(struct iproc_reqctx_s *rctx)
995 {
996 	struct iproc_ctx_s *ctx = rctx->ctx;
997 	struct crypto_async_request *areq = rctx->parent;
998 	struct ahash_request *req = ahash_request_cast(areq);
999 	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1000 	unsigned int blocksize =
1001 		crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
1002 	/*
1003 	 * Save hash to use as input to next op if incremental. Might be copying
1004 	 * too much, but that's easier than figuring out actual digest size here
1005 	 */
1006 	memcpy(rctx->incr_hash, rctx->msg_buf.digest, MAX_DIGEST_SIZE);
1007 
1008 	flow_log("%s() blocksize:%u digestsize:%u\n",
1009 		 __func__, blocksize, ctx->digestsize);
1010 
1011 	atomic64_add(ctx->digestsize, &iproc_priv.bytes_in);
1012 
1013 	if (rctx->is_final && (rctx->total_sent == rctx->total_todo))
1014 		ahash_req_done(rctx);
1015 }
1016 
1017 /**
1018  * spu_aead_rx_sg_create() - Build up the scatterlist of buffers used to receive
1019  * a SPU response message for an AEAD request. Includes buffers to catch SPU
1020  * message headers and the response data.
1021  * @mssg:	mailbox message containing the receive sg
1022  * @rctx:	crypto request context
1023  * @rx_frag_num: number of scatterlist elements required to hold the
1024  *		SPU response message
1025  * @assoc_len:	Length of associated data included in the crypto request
1026  * @ret_iv_len: Length of IV returned in response
1027  * @resp_len:	Number of bytes of response data expected to be written to
1028  *              dst buffer from crypto API
1029  * @digestsize: Length of hash digest, in bytes
1030  * @stat_pad_len: Number of bytes required to pad the STAT field to
1031  *		a 4-byte boundary
1032  *
1033  * The scatterlist that gets allocated here is freed in spu_chunk_cleanup()
1034  * when the request completes, whether the request is handled successfully or
1035  * there is an error.
1036  *
1037  * Returns:
1038  *   0 if successful
1039  *   < 0 if an error
1040  */
1041 static int spu_aead_rx_sg_create(struct brcm_message *mssg,
1042 				 struct aead_request *req,
1043 				 struct iproc_reqctx_s *rctx,
1044 				 u8 rx_frag_num,
1045 				 unsigned int assoc_len,
1046 				 u32 ret_iv_len, unsigned int resp_len,
1047 				 unsigned int digestsize, u32 stat_pad_len)
1048 {
1049 	struct spu_hw *spu = &iproc_priv.spu;
1050 	struct scatterlist *sg;	/* used to build sgs in mbox message */
1051 	struct iproc_ctx_s *ctx = rctx->ctx;
1052 	u32 datalen;		/* Number of bytes of response data expected */
1053 	u32 assoc_buf_len;
1054 	u8 data_padlen = 0;
1055 
1056 	if (ctx->is_rfc4543) {
1057 		/* RFC4543: only pad after data, not after AAD */
1058 		data_padlen = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,
1059 							  assoc_len + resp_len);
1060 		assoc_buf_len = assoc_len;
1061 	} else {
1062 		data_padlen = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,
1063 							  resp_len);
1064 		assoc_buf_len = spu->spu_assoc_resp_len(ctx->cipher.mode,
1065 						assoc_len, ret_iv_len,
1066 						rctx->is_encrypt);
1067 	}
1068 
1069 	if (ctx->cipher.mode == CIPHER_MODE_CCM)
1070 		/* ICV (after data) must be in the next 32-bit word for CCM */
1071 		data_padlen += spu->spu_wordalign_padlen(assoc_buf_len +
1072 							 resp_len +
1073 							 data_padlen);
1074 
1075 	if (data_padlen)
1076 		/* have to catch gcm pad in separate buffer */
1077 		rx_frag_num++;
1078 
1079 	mssg->spu.dst = kcalloc(rx_frag_num, sizeof(struct scatterlist),
1080 				rctx->gfp);
1081 	if (!mssg->spu.dst)
1082 		return -ENOMEM;
1083 
1084 	sg = mssg->spu.dst;
1085 	sg_init_table(sg, rx_frag_num);
1086 
1087 	/* Space for SPU message header */
1088 	sg_set_buf(sg++, rctx->msg_buf.spu_resp_hdr, ctx->spu_resp_hdr_len);
1089 
1090 	if (assoc_buf_len) {
1091 		/*
1092 		 * Don't write directly to req->dst, because SPU may pad the
1093 		 * assoc data in the response
1094 		 */
1095 		memset(rctx->msg_buf.a.resp_aad, 0, assoc_buf_len);
1096 		sg_set_buf(sg++, rctx->msg_buf.a.resp_aad, assoc_buf_len);
1097 	}
1098 
1099 	if (resp_len) {
1100 		/*
1101 		 * Copy in each dst sg entry from request, up to chunksize.
1102 		 * dst sg catches just the data. digest caught in separate buf.
1103 		 */
1104 		datalen = spu_msg_sg_add(&sg, &rctx->dst_sg, &rctx->dst_skip,
1105 					 rctx->dst_nents, resp_len);
1106 		if (datalen < (resp_len)) {
1107 			pr_err("%s(): failed to copy dst sg to mbox msg. expected len %u, datalen %u",
1108 			       __func__, resp_len, datalen);
1109 			return -EFAULT;
1110 		}
1111 	}
1112 
1113 	/* If GCM/CCM data is padded, catch padding in separate buffer */
1114 	if (data_padlen) {
1115 		memset(rctx->msg_buf.a.gcmpad, 0, data_padlen);
1116 		sg_set_buf(sg++, rctx->msg_buf.a.gcmpad, data_padlen);
1117 	}
1118 
1119 	/* Always catch ICV in separate buffer */
1120 	sg_set_buf(sg++, rctx->msg_buf.digest, digestsize);
1121 
1122 	flow_log("stat_pad_len %u\n", stat_pad_len);
1123 	if (stat_pad_len) {
1124 		memset(rctx->msg_buf.rx_stat_pad, 0, stat_pad_len);
1125 		sg_set_buf(sg++, rctx->msg_buf.rx_stat_pad, stat_pad_len);
1126 	}
1127 
1128 	memset(rctx->msg_buf.rx_stat, 0, SPU_RX_STATUS_LEN);
1129 	sg_set_buf(sg, rctx->msg_buf.rx_stat, spu->spu_rx_status_len());
1130 
1131 	return 0;
1132 }
1133 
1134 /**
1135  * spu_aead_tx_sg_create() - Build up the scatterlist of buffers used to send a
1136  * SPU request message for an AEAD request. Includes SPU message headers and the
1137  * request data.
1138  * @mssg:	mailbox message containing the transmit sg
1139  * @rctx:	crypto request context
1140  * @tx_frag_num: number of scatterlist elements required to construct the
1141  *		SPU request message
1142  * @spu_hdr_len: length of SPU message header in bytes
1143  * @assoc:	crypto API associated data scatterlist
1144  * @assoc_len:	length of associated data
1145  * @assoc_nents: number of scatterlist entries containing assoc data
1146  * @aead_iv_len: length of AEAD IV, if included
1147  * @chunksize:	Number of bytes of request data
1148  * @aad_pad_len: Number of bytes of padding at end of AAD. For GCM/CCM.
1149  * @pad_len:	Number of pad bytes
1150  * @incl_icv:	If true, write separate ICV buffer after data and
1151  *              any padding
1152  *
1153  * The scatterlist that gets allocated here is freed in spu_chunk_cleanup()
1154  * when the request completes, whether the request is handled successfully or
1155  * there is an error.
1156  *
1157  * Return:
1158  *   0 if successful
1159  *   < 0 if an error
1160  */
1161 static int spu_aead_tx_sg_create(struct brcm_message *mssg,
1162 				 struct iproc_reqctx_s *rctx,
1163 				 u8 tx_frag_num,
1164 				 u32 spu_hdr_len,
1165 				 struct scatterlist *assoc,
1166 				 unsigned int assoc_len,
1167 				 int assoc_nents,
1168 				 unsigned int aead_iv_len,
1169 				 unsigned int chunksize,
1170 				 u32 aad_pad_len, u32 pad_len, bool incl_icv)
1171 {
1172 	struct spu_hw *spu = &iproc_priv.spu;
1173 	struct scatterlist *sg;	/* used to build sgs in mbox message */
1174 	struct scatterlist *assoc_sg = assoc;
1175 	struct iproc_ctx_s *ctx = rctx->ctx;
1176 	u32 datalen;		/* Number of bytes of data to write */
1177 	u32 written;		/* Number of bytes of data written */
1178 	u32 assoc_offset = 0;
1179 	u32 stat_len;
1180 
1181 	mssg->spu.src = kcalloc(tx_frag_num, sizeof(struct scatterlist),
1182 				rctx->gfp);
1183 	if (!mssg->spu.src)
1184 		return -ENOMEM;
1185 
1186 	sg = mssg->spu.src;
1187 	sg_init_table(sg, tx_frag_num);
1188 
1189 	sg_set_buf(sg++, rctx->msg_buf.bcm_spu_req_hdr,
1190 		   BCM_HDR_LEN + spu_hdr_len);
1191 
1192 	if (assoc_len) {
1193 		/* Copy in each associated data sg entry from request */
1194 		written = spu_msg_sg_add(&sg, &assoc_sg, &assoc_offset,
1195 					 assoc_nents, assoc_len);
1196 		if (written < assoc_len) {
1197 			pr_err("%s(): failed to copy assoc sg to mbox msg",
1198 			       __func__);
1199 			return -EFAULT;
1200 		}
1201 	}
1202 
1203 	if (aead_iv_len)
1204 		sg_set_buf(sg++, rctx->msg_buf.iv_ctr, aead_iv_len);
1205 
1206 	if (aad_pad_len) {
1207 		memset(rctx->msg_buf.a.req_aad_pad, 0, aad_pad_len);
1208 		sg_set_buf(sg++, rctx->msg_buf.a.req_aad_pad, aad_pad_len);
1209 	}
1210 
1211 	datalen = chunksize;
1212 	if ((chunksize > ctx->digestsize) && incl_icv)
1213 		datalen -= ctx->digestsize;
1214 	if (datalen) {
1215 		/* For aead, a single msg should consume the entire src sg */
1216 		written = spu_msg_sg_add(&sg, &rctx->src_sg, &rctx->src_skip,
1217 					 rctx->src_nents, datalen);
1218 		if (written < datalen) {
1219 			pr_err("%s(): failed to copy src sg to mbox msg",
1220 			       __func__);
1221 			return -EFAULT;
1222 		}
1223 	}
1224 
1225 	if (pad_len) {
1226 		memset(rctx->msg_buf.spu_req_pad, 0, pad_len);
1227 		sg_set_buf(sg++, rctx->msg_buf.spu_req_pad, pad_len);
1228 	}
1229 
1230 	if (incl_icv)
1231 		sg_set_buf(sg++, rctx->msg_buf.digest, ctx->digestsize);
1232 
1233 	stat_len = spu->spu_tx_status_len();
1234 	if (stat_len) {
1235 		memset(rctx->msg_buf.tx_stat, 0, stat_len);
1236 		sg_set_buf(sg, rctx->msg_buf.tx_stat, stat_len);
1237 	}
1238 	return 0;
1239 }
1240 
1241 /**
1242  * handle_aead_req() - Submit a SPU request message for the next chunk of the
1243  * current AEAD request.
1244  * @rctx:  Crypto request context
1245  *
1246  * Unlike other operation types, we assume the length of the request fits in
1247  * a single SPU request message. aead_enqueue() makes sure this is true.
1248  * Comments for other op types regarding threads applies here as well.
1249  *
1250  * Unlike incremental hash ops, where the spu returns the entire hash for
1251  * truncated algs like sha-224, the SPU returns just the truncated hash in
1252  * response to aead requests. So digestsize is always ctx->digestsize here.
1253  *
1254  * Return: -EINPROGRESS: crypto request has been accepted and result will be
1255  *			 returned asynchronously
1256  *         Any other value indicates an error
1257  */
1258 static int handle_aead_req(struct iproc_reqctx_s *rctx)
1259 {
1260 	struct spu_hw *spu = &iproc_priv.spu;
1261 	struct crypto_async_request *areq = rctx->parent;
1262 	struct aead_request *req = container_of(areq,
1263 						struct aead_request, base);
1264 	struct iproc_ctx_s *ctx = rctx->ctx;
1265 	int err;
1266 	unsigned int chunksize;
1267 	unsigned int resp_len;
1268 	u32 spu_hdr_len;
1269 	u32 db_size;
1270 	u32 stat_pad_len;
1271 	u32 pad_len;
1272 	struct brcm_message *mssg;	/* mailbox message */
1273 	struct spu_request_opts req_opts;
1274 	struct spu_cipher_parms cipher_parms;
1275 	struct spu_hash_parms hash_parms;
1276 	struct spu_aead_parms aead_parms;
1277 	int assoc_nents = 0;
1278 	bool incl_icv = false;
1279 	unsigned int digestsize = ctx->digestsize;
1280 
1281 	/* number of entries in src and dst sg. Always includes SPU msg header.
1282 	 */
1283 	u8 rx_frag_num = 2;	/* and STATUS */
1284 	u8 tx_frag_num = 1;
1285 
1286 	/* doing the whole thing at once */
1287 	chunksize = rctx->total_todo;
1288 
1289 	flow_log("%s: chunksize %u\n", __func__, chunksize);
1290 
1291 	memset(&req_opts, 0, sizeof(req_opts));
1292 	memset(&hash_parms, 0, sizeof(hash_parms));
1293 	memset(&aead_parms, 0, sizeof(aead_parms));
1294 
1295 	req_opts.is_inbound = !(rctx->is_encrypt);
1296 	req_opts.auth_first = ctx->auth_first;
1297 	req_opts.is_aead = true;
1298 	req_opts.is_esp = ctx->is_esp;
1299 
1300 	cipher_parms.alg = ctx->cipher.alg;
1301 	cipher_parms.mode = ctx->cipher.mode;
1302 	cipher_parms.type = ctx->cipher_type;
1303 	cipher_parms.key_buf = ctx->enckey;
1304 	cipher_parms.key_len = ctx->enckeylen;
1305 	cipher_parms.iv_buf = rctx->msg_buf.iv_ctr;
1306 	cipher_parms.iv_len = rctx->iv_ctr_len;
1307 
1308 	hash_parms.alg = ctx->auth.alg;
1309 	hash_parms.mode = ctx->auth.mode;
1310 	hash_parms.type = HASH_TYPE_NONE;
1311 	hash_parms.key_buf = (u8 *)ctx->authkey;
1312 	hash_parms.key_len = ctx->authkeylen;
1313 	hash_parms.digestsize = digestsize;
1314 
1315 	if ((ctx->auth.alg == HASH_ALG_SHA224) &&
1316 	    (ctx->authkeylen < SHA224_DIGEST_SIZE))
1317 		hash_parms.key_len = SHA224_DIGEST_SIZE;
1318 
1319 	aead_parms.assoc_size = req->assoclen;
1320 	if (ctx->is_esp && !ctx->is_rfc4543) {
1321 		/*
1322 		 * 8-byte IV is included assoc data in request. SPU2
1323 		 * expects AAD to include just SPI and seqno. So
1324 		 * subtract off the IV len.
1325 		 */
1326 		aead_parms.assoc_size -= GCM_RFC4106_IV_SIZE;
1327 
1328 		if (rctx->is_encrypt) {
1329 			aead_parms.return_iv = true;
1330 			aead_parms.ret_iv_len = GCM_RFC4106_IV_SIZE;
1331 			aead_parms.ret_iv_off = GCM_ESP_SALT_SIZE;
1332 		}
1333 	} else {
1334 		aead_parms.ret_iv_len = 0;
1335 	}
1336 
1337 	/*
1338 	 * Count number of sg entries from the crypto API request that are to
1339 	 * be included in this mailbox message. For dst sg, don't count space
1340 	 * for digest. Digest gets caught in a separate buffer and copied back
1341 	 * to dst sg when processing response.
1342 	 */
1343 	rctx->src_nents = spu_sg_count(rctx->src_sg, rctx->src_skip, chunksize);
1344 	rctx->dst_nents = spu_sg_count(rctx->dst_sg, rctx->dst_skip, chunksize);
1345 	if (aead_parms.assoc_size)
1346 		assoc_nents = spu_sg_count(rctx->assoc, 0,
1347 					   aead_parms.assoc_size);
1348 
1349 	mssg = &rctx->mb_mssg;
1350 
1351 	rctx->total_sent = chunksize;
1352 	rctx->src_sent = chunksize;
1353 	if (spu->spu_assoc_resp_len(ctx->cipher.mode,
1354 				    aead_parms.assoc_size,
1355 				    aead_parms.ret_iv_len,
1356 				    rctx->is_encrypt))
1357 		rx_frag_num++;
1358 
1359 	aead_parms.iv_len = spu->spu_aead_ivlen(ctx->cipher.mode,
1360 						rctx->iv_ctr_len);
1361 
1362 	if (ctx->auth.alg == HASH_ALG_AES)
1363 		hash_parms.type = (enum hash_type)ctx->cipher_type;
1364 
1365 	/* General case AAD padding (CCM and RFC4543 special cases below) */
1366 	aead_parms.aad_pad_len = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,
1367 						 aead_parms.assoc_size);
1368 
1369 	/* General case data padding (CCM decrypt special case below) */
1370 	aead_parms.data_pad_len = spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,
1371 							   chunksize);
1372 
1373 	if (ctx->cipher.mode == CIPHER_MODE_CCM) {
1374 		/*
1375 		 * for CCM, AAD len + 2 (rather than AAD len) needs to be
1376 		 * 128-bit aligned
1377 		 */
1378 		aead_parms.aad_pad_len = spu->spu_gcm_ccm_pad_len(
1379 					 ctx->cipher.mode,
1380 					 aead_parms.assoc_size + 2);
1381 
1382 		/*
1383 		 * And when decrypting CCM, need to pad without including
1384 		 * size of ICV which is tacked on to end of chunk
1385 		 */
1386 		if (!rctx->is_encrypt)
1387 			aead_parms.data_pad_len =
1388 				spu->spu_gcm_ccm_pad_len(ctx->cipher.mode,
1389 							chunksize - digestsize);
1390 
1391 		/* CCM also requires software to rewrite portions of IV: */
1392 		spu->spu_ccm_update_iv(digestsize, &cipher_parms, req->assoclen,
1393 				       chunksize, rctx->is_encrypt,
1394 				       ctx->is_esp);
1395 	}
1396 
1397 	if (ctx->is_rfc4543) {
1398 		/*
1399 		 * RFC4543: data is included in AAD, so don't pad after AAD
1400 		 * and pad data based on both AAD + data size
1401 		 */
1402 		aead_parms.aad_pad_len = 0;
1403 		if (!rctx->is_encrypt)
1404 			aead_parms.data_pad_len = spu->spu_gcm_ccm_pad_len(
1405 					ctx->cipher.mode,
1406 					aead_parms.assoc_size + chunksize -
1407 					digestsize);
1408 		else
1409 			aead_parms.data_pad_len = spu->spu_gcm_ccm_pad_len(
1410 					ctx->cipher.mode,
1411 					aead_parms.assoc_size + chunksize);
1412 
1413 		req_opts.is_rfc4543 = true;
1414 	}
1415 
1416 	if (spu_req_incl_icv(ctx->cipher.mode, rctx->is_encrypt)) {
1417 		incl_icv = true;
1418 		tx_frag_num++;
1419 		/* Copy ICV from end of src scatterlist to digest buf */
1420 		sg_copy_part_to_buf(req->src, rctx->msg_buf.digest, digestsize,
1421 				    req->assoclen + rctx->total_sent -
1422 				    digestsize);
1423 	}
1424 
1425 	atomic64_add(chunksize, &iproc_priv.bytes_out);
1426 
1427 	flow_log("%s()-sent chunksize:%u\n", __func__, chunksize);
1428 
1429 	/* Prepend SPU header with type 3 BCM header */
1430 	memcpy(rctx->msg_buf.bcm_spu_req_hdr, BCMHEADER, BCM_HDR_LEN);
1431 
1432 	spu_hdr_len = spu->spu_create_request(rctx->msg_buf.bcm_spu_req_hdr +
1433 					      BCM_HDR_LEN, &req_opts,
1434 					      &cipher_parms, &hash_parms,
1435 					      &aead_parms, chunksize);
1436 
1437 	/* Determine total length of padding. Put all padding in one buffer. */
1438 	db_size = spu_real_db_size(aead_parms.assoc_size, aead_parms.iv_len, 0,
1439 				   chunksize, aead_parms.aad_pad_len,
1440 				   aead_parms.data_pad_len, 0);
1441 
1442 	stat_pad_len = spu->spu_wordalign_padlen(db_size);
1443 
1444 	if (stat_pad_len)
1445 		rx_frag_num++;
1446 	pad_len = aead_parms.data_pad_len + stat_pad_len;
1447 	if (pad_len) {
1448 		tx_frag_num++;
1449 		spu->spu_request_pad(rctx->msg_buf.spu_req_pad,
1450 				     aead_parms.data_pad_len, 0,
1451 				     ctx->auth.alg, ctx->auth.mode,
1452 				     rctx->total_sent, stat_pad_len);
1453 	}
1454 
1455 	spu->spu_dump_msg_hdr(rctx->msg_buf.bcm_spu_req_hdr + BCM_HDR_LEN,
1456 			      spu_hdr_len);
1457 	dump_sg(rctx->assoc, 0, aead_parms.assoc_size);
1458 	packet_dump("    aead iv: ", rctx->msg_buf.iv_ctr, aead_parms.iv_len);
1459 	packet_log("BD:\n");
1460 	dump_sg(rctx->src_sg, rctx->src_skip, chunksize);
1461 	packet_dump("   pad: ", rctx->msg_buf.spu_req_pad, pad_len);
1462 
1463 	/*
1464 	 * Build mailbox message containing SPU request msg and rx buffers
1465 	 * to catch response message
1466 	 */
1467 	memset(mssg, 0, sizeof(*mssg));
1468 	mssg->type = BRCM_MESSAGE_SPU;
1469 	mssg->ctx = rctx;	/* Will be returned in response */
1470 
1471 	/* Create rx scatterlist to catch result */
1472 	rx_frag_num += rctx->dst_nents;
1473 	resp_len = chunksize;
1474 
1475 	/*
1476 	 * Always catch ICV in separate buffer. Have to for GCM/CCM because of
1477 	 * padding. Have to for SHA-224 and other truncated SHAs because SPU
1478 	 * sends entire digest back.
1479 	 */
1480 	rx_frag_num++;
1481 
1482 	if (((ctx->cipher.mode == CIPHER_MODE_GCM) ||
1483 	     (ctx->cipher.mode == CIPHER_MODE_CCM)) && !rctx->is_encrypt) {
1484 		/*
1485 		 * Input is ciphertxt plus ICV, but ICV not incl
1486 		 * in output.
1487 		 */
1488 		resp_len -= ctx->digestsize;
1489 		if (resp_len == 0)
1490 			/* no rx frags to catch output data */
1491 			rx_frag_num -= rctx->dst_nents;
1492 	}
1493 
1494 	err = spu_aead_rx_sg_create(mssg, req, rctx, rx_frag_num,
1495 				    aead_parms.assoc_size,
1496 				    aead_parms.ret_iv_len, resp_len, digestsize,
1497 				    stat_pad_len);
1498 	if (err)
1499 		return err;
1500 
1501 	/* Create tx scatterlist containing SPU request message */
1502 	tx_frag_num += rctx->src_nents;
1503 	tx_frag_num += assoc_nents;
1504 	if (aead_parms.aad_pad_len)
1505 		tx_frag_num++;
1506 	if (aead_parms.iv_len)
1507 		tx_frag_num++;
1508 	if (spu->spu_tx_status_len())
1509 		tx_frag_num++;
1510 	err = spu_aead_tx_sg_create(mssg, rctx, tx_frag_num, spu_hdr_len,
1511 				    rctx->assoc, aead_parms.assoc_size,
1512 				    assoc_nents, aead_parms.iv_len, chunksize,
1513 				    aead_parms.aad_pad_len, pad_len, incl_icv);
1514 	if (err)
1515 		return err;
1516 
1517 	err = mailbox_send_message(mssg, req->base.flags, rctx->chan_idx);
1518 	if (unlikely(err < 0))
1519 		return err;
1520 
1521 	return -EINPROGRESS;
1522 }
1523 
1524 /**
1525  * handle_aead_resp() - Process a SPU response message for an AEAD request.
1526  * @rctx:  Crypto request context
1527  */
1528 static void handle_aead_resp(struct iproc_reqctx_s *rctx)
1529 {
1530 	struct spu_hw *spu = &iproc_priv.spu;
1531 	struct crypto_async_request *areq = rctx->parent;
1532 	struct aead_request *req = container_of(areq,
1533 						struct aead_request, base);
1534 	struct iproc_ctx_s *ctx = rctx->ctx;
1535 	u32 payload_len;
1536 	unsigned int icv_offset;
1537 	u32 result_len;
1538 
1539 	/* See how much data was returned */
1540 	payload_len = spu->spu_payload_length(rctx->msg_buf.spu_resp_hdr);
1541 	flow_log("payload_len %u\n", payload_len);
1542 
1543 	/* only count payload */
1544 	atomic64_add(payload_len, &iproc_priv.bytes_in);
1545 
1546 	if (req->assoclen)
1547 		packet_dump("  assoc_data ", rctx->msg_buf.a.resp_aad,
1548 			    req->assoclen);
1549 
1550 	/*
1551 	 * Copy the ICV back to the destination
1552 	 * buffer. In decrypt case, SPU gives us back the digest, but crypto
1553 	 * API doesn't expect ICV in dst buffer.
1554 	 */
1555 	result_len = req->cryptlen;
1556 	if (rctx->is_encrypt) {
1557 		icv_offset = req->assoclen + rctx->total_sent;
1558 		packet_dump("  ICV: ", rctx->msg_buf.digest, ctx->digestsize);
1559 		flow_log("copying ICV to dst sg at offset %u\n", icv_offset);
1560 		sg_copy_part_from_buf(req->dst, rctx->msg_buf.digest,
1561 				      ctx->digestsize, icv_offset);
1562 		result_len += ctx->digestsize;
1563 	}
1564 
1565 	packet_log("response data:  ");
1566 	dump_sg(req->dst, req->assoclen, result_len);
1567 
1568 	atomic_inc(&iproc_priv.op_counts[SPU_OP_AEAD]);
1569 	if (ctx->cipher.alg == CIPHER_ALG_AES) {
1570 		if (ctx->cipher.mode == CIPHER_MODE_CCM)
1571 			atomic_inc(&iproc_priv.aead_cnt[AES_CCM]);
1572 		else if (ctx->cipher.mode == CIPHER_MODE_GCM)
1573 			atomic_inc(&iproc_priv.aead_cnt[AES_GCM]);
1574 		else
1575 			atomic_inc(&iproc_priv.aead_cnt[AUTHENC]);
1576 	} else {
1577 		atomic_inc(&iproc_priv.aead_cnt[AUTHENC]);
1578 	}
1579 }
1580 
1581 /**
1582  * spu_chunk_cleanup() - Do cleanup after processing one chunk of a request
1583  * @rctx:  request context
1584  *
1585  * Mailbox scatterlists are allocated for each chunk. So free them after
1586  * processing each chunk.
1587  */
1588 static void spu_chunk_cleanup(struct iproc_reqctx_s *rctx)
1589 {
1590 	/* mailbox message used to tx request */
1591 	struct brcm_message *mssg = &rctx->mb_mssg;
1592 
1593 	kfree(mssg->spu.src);
1594 	kfree(mssg->spu.dst);
1595 	memset(mssg, 0, sizeof(struct brcm_message));
1596 }
1597 
1598 /**
1599  * finish_req() - Used to invoke the complete callback from the requester when
1600  * a request has been handled asynchronously.
1601  * @rctx:  Request context
1602  * @err:   Indicates whether the request was successful or not
1603  *
1604  * Ensures that cleanup has been done for request
1605  */
1606 static void finish_req(struct iproc_reqctx_s *rctx, int err)
1607 {
1608 	struct crypto_async_request *areq = rctx->parent;
1609 
1610 	flow_log("%s() err:%d\n\n", __func__, err);
1611 
1612 	/* No harm done if already called */
1613 	spu_chunk_cleanup(rctx);
1614 
1615 	if (areq)
1616 		areq->complete(areq, err);
1617 }
1618 
1619 /**
1620  * spu_rx_callback() - Callback from mailbox framework with a SPU response.
1621  * @cl:		mailbox client structure for SPU driver
1622  * @msg:	mailbox message containing SPU response
1623  */
1624 static void spu_rx_callback(struct mbox_client *cl, void *msg)
1625 {
1626 	struct spu_hw *spu = &iproc_priv.spu;
1627 	struct brcm_message *mssg = msg;
1628 	struct iproc_reqctx_s *rctx;
1629 	int err;
1630 
1631 	rctx = mssg->ctx;
1632 	if (unlikely(!rctx)) {
1633 		/* This is fatal */
1634 		pr_err("%s(): no request context", __func__);
1635 		err = -EFAULT;
1636 		goto cb_finish;
1637 	}
1638 
1639 	/* process the SPU status */
1640 	err = spu->spu_status_process(rctx->msg_buf.rx_stat);
1641 	if (err != 0) {
1642 		if (err == SPU_INVALID_ICV)
1643 			atomic_inc(&iproc_priv.bad_icv);
1644 		err = -EBADMSG;
1645 		goto cb_finish;
1646 	}
1647 
1648 	/* Process the SPU response message */
1649 	switch (rctx->ctx->alg->type) {
1650 	case CRYPTO_ALG_TYPE_SKCIPHER:
1651 		handle_skcipher_resp(rctx);
1652 		break;
1653 	case CRYPTO_ALG_TYPE_AHASH:
1654 		handle_ahash_resp(rctx);
1655 		break;
1656 	case CRYPTO_ALG_TYPE_AEAD:
1657 		handle_aead_resp(rctx);
1658 		break;
1659 	default:
1660 		err = -EINVAL;
1661 		goto cb_finish;
1662 	}
1663 
1664 	/*
1665 	 * If this response does not complete the request, then send the next
1666 	 * request chunk.
1667 	 */
1668 	if (rctx->total_sent < rctx->total_todo) {
1669 		/* Deallocate anything specific to previous chunk */
1670 		spu_chunk_cleanup(rctx);
1671 
1672 		switch (rctx->ctx->alg->type) {
1673 		case CRYPTO_ALG_TYPE_SKCIPHER:
1674 			err = handle_skcipher_req(rctx);
1675 			break;
1676 		case CRYPTO_ALG_TYPE_AHASH:
1677 			err = handle_ahash_req(rctx);
1678 			if (err == -EAGAIN)
1679 				/*
1680 				 * we saved data in hash carry, but tell crypto
1681 				 * API we successfully completed request.
1682 				 */
1683 				err = 0;
1684 			break;
1685 		case CRYPTO_ALG_TYPE_AEAD:
1686 			err = handle_aead_req(rctx);
1687 			break;
1688 		default:
1689 			err = -EINVAL;
1690 		}
1691 
1692 		if (err == -EINPROGRESS)
1693 			/* Successfully submitted request for next chunk */
1694 			return;
1695 	}
1696 
1697 cb_finish:
1698 	finish_req(rctx, err);
1699 }
1700 
1701 /* ==================== Kernel Cryptographic API ==================== */
1702 
1703 /**
1704  * skcipher_enqueue() - Handle skcipher encrypt or decrypt request.
1705  * @req:	Crypto API request
1706  * @encrypt:	true if encrypting; false if decrypting
1707  *
1708  * Return: -EINPROGRESS if request accepted and result will be returned
1709  *			asynchronously
1710  *	   < 0 if an error
1711  */
1712 static int skcipher_enqueue(struct skcipher_request *req, bool encrypt)
1713 {
1714 	struct iproc_reqctx_s *rctx = skcipher_request_ctx(req);
1715 	struct iproc_ctx_s *ctx =
1716 	    crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
1717 	int err;
1718 
1719 	flow_log("%s() enc:%u\n", __func__, encrypt);
1720 
1721 	rctx->gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1722 		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1723 	rctx->parent = &req->base;
1724 	rctx->is_encrypt = encrypt;
1725 	rctx->bd_suppress = false;
1726 	rctx->total_todo = req->cryptlen;
1727 	rctx->src_sent = 0;
1728 	rctx->total_sent = 0;
1729 	rctx->total_received = 0;
1730 	rctx->ctx = ctx;
1731 
1732 	/* Initialize current position in src and dst scatterlists */
1733 	rctx->src_sg = req->src;
1734 	rctx->src_nents = 0;
1735 	rctx->src_skip = 0;
1736 	rctx->dst_sg = req->dst;
1737 	rctx->dst_nents = 0;
1738 	rctx->dst_skip = 0;
1739 
1740 	if (ctx->cipher.mode == CIPHER_MODE_CBC ||
1741 	    ctx->cipher.mode == CIPHER_MODE_CTR ||
1742 	    ctx->cipher.mode == CIPHER_MODE_OFB ||
1743 	    ctx->cipher.mode == CIPHER_MODE_XTS ||
1744 	    ctx->cipher.mode == CIPHER_MODE_GCM ||
1745 	    ctx->cipher.mode == CIPHER_MODE_CCM) {
1746 		rctx->iv_ctr_len =
1747 		    crypto_skcipher_ivsize(crypto_skcipher_reqtfm(req));
1748 		memcpy(rctx->msg_buf.iv_ctr, req->iv, rctx->iv_ctr_len);
1749 	} else {
1750 		rctx->iv_ctr_len = 0;
1751 	}
1752 
1753 	/* Choose a SPU to process this request */
1754 	rctx->chan_idx = select_channel();
1755 	err = handle_skcipher_req(rctx);
1756 	if (err != -EINPROGRESS)
1757 		/* synchronous result */
1758 		spu_chunk_cleanup(rctx);
1759 
1760 	return err;
1761 }
1762 
1763 static int des_setkey(struct crypto_skcipher *cipher, const u8 *key,
1764 		      unsigned int keylen)
1765 {
1766 	struct iproc_ctx_s *ctx = crypto_skcipher_ctx(cipher);
1767 	int err;
1768 
1769 	err = verify_skcipher_des_key(cipher, key);
1770 	if (err)
1771 		return err;
1772 
1773 	ctx->cipher_type = CIPHER_TYPE_DES;
1774 	return 0;
1775 }
1776 
1777 static int threedes_setkey(struct crypto_skcipher *cipher, const u8 *key,
1778 			   unsigned int keylen)
1779 {
1780 	struct iproc_ctx_s *ctx = crypto_skcipher_ctx(cipher);
1781 	int err;
1782 
1783 	err = verify_skcipher_des3_key(cipher, key);
1784 	if (err)
1785 		return err;
1786 
1787 	ctx->cipher_type = CIPHER_TYPE_3DES;
1788 	return 0;
1789 }
1790 
1791 static int aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
1792 		      unsigned int keylen)
1793 {
1794 	struct iproc_ctx_s *ctx = crypto_skcipher_ctx(cipher);
1795 
1796 	if (ctx->cipher.mode == CIPHER_MODE_XTS)
1797 		/* XTS includes two keys of equal length */
1798 		keylen = keylen / 2;
1799 
1800 	switch (keylen) {
1801 	case AES_KEYSIZE_128:
1802 		ctx->cipher_type = CIPHER_TYPE_AES128;
1803 		break;
1804 	case AES_KEYSIZE_192:
1805 		ctx->cipher_type = CIPHER_TYPE_AES192;
1806 		break;
1807 	case AES_KEYSIZE_256:
1808 		ctx->cipher_type = CIPHER_TYPE_AES256;
1809 		break;
1810 	default:
1811 		return -EINVAL;
1812 	}
1813 	WARN_ON((ctx->max_payload != SPU_MAX_PAYLOAD_INF) &&
1814 		((ctx->max_payload % AES_BLOCK_SIZE) != 0));
1815 	return 0;
1816 }
1817 
1818 static int skcipher_setkey(struct crypto_skcipher *cipher, const u8 *key,
1819 			     unsigned int keylen)
1820 {
1821 	struct spu_hw *spu = &iproc_priv.spu;
1822 	struct iproc_ctx_s *ctx = crypto_skcipher_ctx(cipher);
1823 	struct spu_cipher_parms cipher_parms;
1824 	u32 alloc_len = 0;
1825 	int err;
1826 
1827 	flow_log("skcipher_setkey() keylen: %d\n", keylen);
1828 	flow_dump("  key: ", key, keylen);
1829 
1830 	switch (ctx->cipher.alg) {
1831 	case CIPHER_ALG_DES:
1832 		err = des_setkey(cipher, key, keylen);
1833 		break;
1834 	case CIPHER_ALG_3DES:
1835 		err = threedes_setkey(cipher, key, keylen);
1836 		break;
1837 	case CIPHER_ALG_AES:
1838 		err = aes_setkey(cipher, key, keylen);
1839 		break;
1840 	default:
1841 		pr_err("%s() Error: unknown cipher alg\n", __func__);
1842 		err = -EINVAL;
1843 	}
1844 	if (err)
1845 		return err;
1846 
1847 	memcpy(ctx->enckey, key, keylen);
1848 	ctx->enckeylen = keylen;
1849 
1850 	/* SPU needs XTS keys in the reverse order the crypto API presents */
1851 	if ((ctx->cipher.alg == CIPHER_ALG_AES) &&
1852 	    (ctx->cipher.mode == CIPHER_MODE_XTS)) {
1853 		unsigned int xts_keylen = keylen / 2;
1854 
1855 		memcpy(ctx->enckey, key + xts_keylen, xts_keylen);
1856 		memcpy(ctx->enckey + xts_keylen, key, xts_keylen);
1857 	}
1858 
1859 	if (spu->spu_type == SPU_TYPE_SPUM)
1860 		alloc_len = BCM_HDR_LEN + SPU_HEADER_ALLOC_LEN;
1861 	else if (spu->spu_type == SPU_TYPE_SPU2)
1862 		alloc_len = BCM_HDR_LEN + SPU2_HEADER_ALLOC_LEN;
1863 	memset(ctx->bcm_spu_req_hdr, 0, alloc_len);
1864 	cipher_parms.iv_buf = NULL;
1865 	cipher_parms.iv_len = crypto_skcipher_ivsize(cipher);
1866 	flow_log("%s: iv_len %u\n", __func__, cipher_parms.iv_len);
1867 
1868 	cipher_parms.alg = ctx->cipher.alg;
1869 	cipher_parms.mode = ctx->cipher.mode;
1870 	cipher_parms.type = ctx->cipher_type;
1871 	cipher_parms.key_buf = ctx->enckey;
1872 	cipher_parms.key_len = ctx->enckeylen;
1873 
1874 	/* Prepend SPU request message with BCM header */
1875 	memcpy(ctx->bcm_spu_req_hdr, BCMHEADER, BCM_HDR_LEN);
1876 	ctx->spu_req_hdr_len =
1877 	    spu->spu_cipher_req_init(ctx->bcm_spu_req_hdr + BCM_HDR_LEN,
1878 				     &cipher_parms);
1879 
1880 	ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen,
1881 							  ctx->enckeylen,
1882 							  false);
1883 
1884 	atomic_inc(&iproc_priv.setkey_cnt[SPU_OP_CIPHER]);
1885 
1886 	return 0;
1887 }
1888 
1889 static int skcipher_encrypt(struct skcipher_request *req)
1890 {
1891 	flow_log("skcipher_encrypt() nbytes:%u\n", req->cryptlen);
1892 
1893 	return skcipher_enqueue(req, true);
1894 }
1895 
1896 static int skcipher_decrypt(struct skcipher_request *req)
1897 {
1898 	flow_log("skcipher_decrypt() nbytes:%u\n", req->cryptlen);
1899 	return skcipher_enqueue(req, false);
1900 }
1901 
1902 static int ahash_enqueue(struct ahash_request *req)
1903 {
1904 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
1905 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1906 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
1907 	int err;
1908 	const char *alg_name;
1909 
1910 	flow_log("ahash_enqueue() nbytes:%u\n", req->nbytes);
1911 
1912 	rctx->gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1913 		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1914 	rctx->parent = &req->base;
1915 	rctx->ctx = ctx;
1916 	rctx->bd_suppress = true;
1917 	memset(&rctx->mb_mssg, 0, sizeof(struct brcm_message));
1918 
1919 	/* Initialize position in src scatterlist */
1920 	rctx->src_sg = req->src;
1921 	rctx->src_skip = 0;
1922 	rctx->src_nents = 0;
1923 	rctx->dst_sg = NULL;
1924 	rctx->dst_skip = 0;
1925 	rctx->dst_nents = 0;
1926 
1927 	/* SPU2 hardware does not compute hash of zero length data */
1928 	if ((rctx->is_final == 1) && (rctx->total_todo == 0) &&
1929 	    (iproc_priv.spu.spu_type == SPU_TYPE_SPU2)) {
1930 		alg_name = crypto_tfm_alg_name(crypto_ahash_tfm(tfm));
1931 		flow_log("Doing %sfinal %s zero-len hash request in software\n",
1932 			 rctx->is_final ? "" : "non-", alg_name);
1933 		err = do_shash((unsigned char *)alg_name, req->result,
1934 			       NULL, 0, NULL, 0, ctx->authkey,
1935 			       ctx->authkeylen);
1936 		if (err < 0)
1937 			flow_log("Hash request failed with error %d\n", err);
1938 		return err;
1939 	}
1940 	/* Choose a SPU to process this request */
1941 	rctx->chan_idx = select_channel();
1942 
1943 	err = handle_ahash_req(rctx);
1944 	if (err != -EINPROGRESS)
1945 		/* synchronous result */
1946 		spu_chunk_cleanup(rctx);
1947 
1948 	if (err == -EAGAIN)
1949 		/*
1950 		 * we saved data in hash carry, but tell crypto API
1951 		 * we successfully completed request.
1952 		 */
1953 		err = 0;
1954 
1955 	return err;
1956 }
1957 
1958 static int __ahash_init(struct ahash_request *req)
1959 {
1960 	struct spu_hw *spu = &iproc_priv.spu;
1961 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
1962 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1963 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
1964 
1965 	flow_log("%s()\n", __func__);
1966 
1967 	/* Initialize the context */
1968 	rctx->hash_carry_len = 0;
1969 	rctx->is_final = 0;
1970 
1971 	rctx->total_todo = 0;
1972 	rctx->src_sent = 0;
1973 	rctx->total_sent = 0;
1974 	rctx->total_received = 0;
1975 
1976 	ctx->digestsize = crypto_ahash_digestsize(tfm);
1977 	/* If we add a hash whose digest is larger, catch it here. */
1978 	WARN_ON(ctx->digestsize > MAX_DIGEST_SIZE);
1979 
1980 	rctx->is_sw_hmac = false;
1981 
1982 	ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen, 0,
1983 							  true);
1984 
1985 	return 0;
1986 }
1987 
1988 /**
1989  * spu_no_incr_hash() - Determine whether incremental hashing is supported.
1990  * @ctx:  Crypto session context
1991  *
1992  * SPU-2 does not support incremental hashing (we'll have to revisit and
1993  * condition based on chip revision or device tree entry if future versions do
1994  * support incremental hash)
1995  *
1996  * SPU-M also doesn't support incremental hashing of AES-XCBC
1997  *
1998  * Return: true if incremental hashing is not supported
1999  *         false otherwise
2000  */
2001 static bool spu_no_incr_hash(struct iproc_ctx_s *ctx)
2002 {
2003 	struct spu_hw *spu = &iproc_priv.spu;
2004 
2005 	if (spu->spu_type == SPU_TYPE_SPU2)
2006 		return true;
2007 
2008 	if ((ctx->auth.alg == HASH_ALG_AES) &&
2009 	    (ctx->auth.mode == HASH_MODE_XCBC))
2010 		return true;
2011 
2012 	/* Otherwise, incremental hashing is supported */
2013 	return false;
2014 }
2015 
2016 static int ahash_init(struct ahash_request *req)
2017 {
2018 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2019 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
2020 	const char *alg_name;
2021 	struct crypto_shash *hash;
2022 	int ret;
2023 	gfp_t gfp;
2024 
2025 	if (spu_no_incr_hash(ctx)) {
2026 		/*
2027 		 * If we get an incremental hashing request and it's not
2028 		 * supported by the hardware, we need to handle it in software
2029 		 * by calling synchronous hash functions.
2030 		 */
2031 		alg_name = crypto_tfm_alg_name(crypto_ahash_tfm(tfm));
2032 		hash = crypto_alloc_shash(alg_name, 0, 0);
2033 		if (IS_ERR(hash)) {
2034 			ret = PTR_ERR(hash);
2035 			goto err;
2036 		}
2037 
2038 		gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
2039 		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
2040 		ctx->shash = kmalloc(sizeof(*ctx->shash) +
2041 				     crypto_shash_descsize(hash), gfp);
2042 		if (!ctx->shash) {
2043 			ret = -ENOMEM;
2044 			goto err_hash;
2045 		}
2046 		ctx->shash->tfm = hash;
2047 
2048 		/* Set the key using data we already have from setkey */
2049 		if (ctx->authkeylen > 0) {
2050 			ret = crypto_shash_setkey(hash, ctx->authkey,
2051 						  ctx->authkeylen);
2052 			if (ret)
2053 				goto err_shash;
2054 		}
2055 
2056 		/* Initialize hash w/ this key and other params */
2057 		ret = crypto_shash_init(ctx->shash);
2058 		if (ret)
2059 			goto err_shash;
2060 	} else {
2061 		/* Otherwise call the internal function which uses SPU hw */
2062 		ret = __ahash_init(req);
2063 	}
2064 
2065 	return ret;
2066 
2067 err_shash:
2068 	kfree(ctx->shash);
2069 err_hash:
2070 	crypto_free_shash(hash);
2071 err:
2072 	return ret;
2073 }
2074 
2075 static int __ahash_update(struct ahash_request *req)
2076 {
2077 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2078 
2079 	flow_log("ahash_update() nbytes:%u\n", req->nbytes);
2080 
2081 	if (!req->nbytes)
2082 		return 0;
2083 	rctx->total_todo += req->nbytes;
2084 	rctx->src_sent = 0;
2085 
2086 	return ahash_enqueue(req);
2087 }
2088 
2089 static int ahash_update(struct ahash_request *req)
2090 {
2091 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2092 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
2093 	u8 *tmpbuf;
2094 	int ret;
2095 	int nents;
2096 	gfp_t gfp;
2097 
2098 	if (spu_no_incr_hash(ctx)) {
2099 		/*
2100 		 * If we get an incremental hashing request and it's not
2101 		 * supported by the hardware, we need to handle it in software
2102 		 * by calling synchronous hash functions.
2103 		 */
2104 		if (req->src)
2105 			nents = sg_nents(req->src);
2106 		else
2107 			return -EINVAL;
2108 
2109 		/* Copy data from req scatterlist to tmp buffer */
2110 		gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
2111 		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
2112 		tmpbuf = kmalloc(req->nbytes, gfp);
2113 		if (!tmpbuf)
2114 			return -ENOMEM;
2115 
2116 		if (sg_copy_to_buffer(req->src, nents, tmpbuf, req->nbytes) !=
2117 				req->nbytes) {
2118 			kfree(tmpbuf);
2119 			return -EINVAL;
2120 		}
2121 
2122 		/* Call synchronous update */
2123 		ret = crypto_shash_update(ctx->shash, tmpbuf, req->nbytes);
2124 		kfree(tmpbuf);
2125 	} else {
2126 		/* Otherwise call the internal function which uses SPU hw */
2127 		ret = __ahash_update(req);
2128 	}
2129 
2130 	return ret;
2131 }
2132 
2133 static int __ahash_final(struct ahash_request *req)
2134 {
2135 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2136 
2137 	flow_log("ahash_final() nbytes:%u\n", req->nbytes);
2138 
2139 	rctx->is_final = 1;
2140 
2141 	return ahash_enqueue(req);
2142 }
2143 
2144 static int ahash_final(struct ahash_request *req)
2145 {
2146 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2147 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
2148 	int ret;
2149 
2150 	if (spu_no_incr_hash(ctx)) {
2151 		/*
2152 		 * If we get an incremental hashing request and it's not
2153 		 * supported by the hardware, we need to handle it in software
2154 		 * by calling synchronous hash functions.
2155 		 */
2156 		ret = crypto_shash_final(ctx->shash, req->result);
2157 
2158 		/* Done with hash, can deallocate it now */
2159 		crypto_free_shash(ctx->shash->tfm);
2160 		kfree(ctx->shash);
2161 
2162 	} else {
2163 		/* Otherwise call the internal function which uses SPU hw */
2164 		ret = __ahash_final(req);
2165 	}
2166 
2167 	return ret;
2168 }
2169 
2170 static int __ahash_finup(struct ahash_request *req)
2171 {
2172 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2173 
2174 	flow_log("ahash_finup() nbytes:%u\n", req->nbytes);
2175 
2176 	rctx->total_todo += req->nbytes;
2177 	rctx->src_sent = 0;
2178 	rctx->is_final = 1;
2179 
2180 	return ahash_enqueue(req);
2181 }
2182 
2183 static int ahash_finup(struct ahash_request *req)
2184 {
2185 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2186 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
2187 	u8 *tmpbuf;
2188 	int ret;
2189 	int nents;
2190 	gfp_t gfp;
2191 
2192 	if (spu_no_incr_hash(ctx)) {
2193 		/*
2194 		 * If we get an incremental hashing request and it's not
2195 		 * supported by the hardware, we need to handle it in software
2196 		 * by calling synchronous hash functions.
2197 		 */
2198 		if (req->src) {
2199 			nents = sg_nents(req->src);
2200 		} else {
2201 			ret = -EINVAL;
2202 			goto ahash_finup_exit;
2203 		}
2204 
2205 		/* Copy data from req scatterlist to tmp buffer */
2206 		gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
2207 		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
2208 		tmpbuf = kmalloc(req->nbytes, gfp);
2209 		if (!tmpbuf) {
2210 			ret = -ENOMEM;
2211 			goto ahash_finup_exit;
2212 		}
2213 
2214 		if (sg_copy_to_buffer(req->src, nents, tmpbuf, req->nbytes) !=
2215 				req->nbytes) {
2216 			ret = -EINVAL;
2217 			goto ahash_finup_free;
2218 		}
2219 
2220 		/* Call synchronous update */
2221 		ret = crypto_shash_finup(ctx->shash, tmpbuf, req->nbytes,
2222 					 req->result);
2223 	} else {
2224 		/* Otherwise call the internal function which uses SPU hw */
2225 		return __ahash_finup(req);
2226 	}
2227 ahash_finup_free:
2228 	kfree(tmpbuf);
2229 
2230 ahash_finup_exit:
2231 	/* Done with hash, can deallocate it now */
2232 	crypto_free_shash(ctx->shash->tfm);
2233 	kfree(ctx->shash);
2234 	return ret;
2235 }
2236 
2237 static int ahash_digest(struct ahash_request *req)
2238 {
2239 	int err;
2240 
2241 	flow_log("ahash_digest() nbytes:%u\n", req->nbytes);
2242 
2243 	/* whole thing at once */
2244 	err = __ahash_init(req);
2245 	if (!err)
2246 		err = __ahash_finup(req);
2247 
2248 	return err;
2249 }
2250 
2251 static int ahash_setkey(struct crypto_ahash *ahash, const u8 *key,
2252 			unsigned int keylen)
2253 {
2254 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(ahash);
2255 
2256 	flow_log("%s() ahash:%p key:%p keylen:%u\n",
2257 		 __func__, ahash, key, keylen);
2258 	flow_dump("  key: ", key, keylen);
2259 
2260 	if (ctx->auth.alg == HASH_ALG_AES) {
2261 		switch (keylen) {
2262 		case AES_KEYSIZE_128:
2263 			ctx->cipher_type = CIPHER_TYPE_AES128;
2264 			break;
2265 		case AES_KEYSIZE_192:
2266 			ctx->cipher_type = CIPHER_TYPE_AES192;
2267 			break;
2268 		case AES_KEYSIZE_256:
2269 			ctx->cipher_type = CIPHER_TYPE_AES256;
2270 			break;
2271 		default:
2272 			pr_err("%s() Error: Invalid key length\n", __func__);
2273 			return -EINVAL;
2274 		}
2275 	} else {
2276 		pr_err("%s() Error: unknown hash alg\n", __func__);
2277 		return -EINVAL;
2278 	}
2279 	memcpy(ctx->authkey, key, keylen);
2280 	ctx->authkeylen = keylen;
2281 
2282 	return 0;
2283 }
2284 
2285 static int ahash_export(struct ahash_request *req, void *out)
2286 {
2287 	const struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2288 	struct spu_hash_export_s *spu_exp = (struct spu_hash_export_s *)out;
2289 
2290 	spu_exp->total_todo = rctx->total_todo;
2291 	spu_exp->total_sent = rctx->total_sent;
2292 	spu_exp->is_sw_hmac = rctx->is_sw_hmac;
2293 	memcpy(spu_exp->hash_carry, rctx->hash_carry, sizeof(rctx->hash_carry));
2294 	spu_exp->hash_carry_len = rctx->hash_carry_len;
2295 	memcpy(spu_exp->incr_hash, rctx->incr_hash, sizeof(rctx->incr_hash));
2296 
2297 	return 0;
2298 }
2299 
2300 static int ahash_import(struct ahash_request *req, const void *in)
2301 {
2302 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2303 	struct spu_hash_export_s *spu_exp = (struct spu_hash_export_s *)in;
2304 
2305 	rctx->total_todo = spu_exp->total_todo;
2306 	rctx->total_sent = spu_exp->total_sent;
2307 	rctx->is_sw_hmac = spu_exp->is_sw_hmac;
2308 	memcpy(rctx->hash_carry, spu_exp->hash_carry, sizeof(rctx->hash_carry));
2309 	rctx->hash_carry_len = spu_exp->hash_carry_len;
2310 	memcpy(rctx->incr_hash, spu_exp->incr_hash, sizeof(rctx->incr_hash));
2311 
2312 	return 0;
2313 }
2314 
2315 static int ahash_hmac_setkey(struct crypto_ahash *ahash, const u8 *key,
2316 			     unsigned int keylen)
2317 {
2318 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(ahash);
2319 	unsigned int blocksize =
2320 		crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
2321 	unsigned int digestsize = crypto_ahash_digestsize(ahash);
2322 	unsigned int index;
2323 	int rc;
2324 
2325 	flow_log("%s() ahash:%p key:%p keylen:%u blksz:%u digestsz:%u\n",
2326 		 __func__, ahash, key, keylen, blocksize, digestsize);
2327 	flow_dump("  key: ", key, keylen);
2328 
2329 	if (keylen > blocksize) {
2330 		switch (ctx->auth.alg) {
2331 		case HASH_ALG_MD5:
2332 			rc = do_shash("md5", ctx->authkey, key, keylen, NULL,
2333 				      0, NULL, 0);
2334 			break;
2335 		case HASH_ALG_SHA1:
2336 			rc = do_shash("sha1", ctx->authkey, key, keylen, NULL,
2337 				      0, NULL, 0);
2338 			break;
2339 		case HASH_ALG_SHA224:
2340 			rc = do_shash("sha224", ctx->authkey, key, keylen, NULL,
2341 				      0, NULL, 0);
2342 			break;
2343 		case HASH_ALG_SHA256:
2344 			rc = do_shash("sha256", ctx->authkey, key, keylen, NULL,
2345 				      0, NULL, 0);
2346 			break;
2347 		case HASH_ALG_SHA384:
2348 			rc = do_shash("sha384", ctx->authkey, key, keylen, NULL,
2349 				      0, NULL, 0);
2350 			break;
2351 		case HASH_ALG_SHA512:
2352 			rc = do_shash("sha512", ctx->authkey, key, keylen, NULL,
2353 				      0, NULL, 0);
2354 			break;
2355 		case HASH_ALG_SHA3_224:
2356 			rc = do_shash("sha3-224", ctx->authkey, key, keylen,
2357 				      NULL, 0, NULL, 0);
2358 			break;
2359 		case HASH_ALG_SHA3_256:
2360 			rc = do_shash("sha3-256", ctx->authkey, key, keylen,
2361 				      NULL, 0, NULL, 0);
2362 			break;
2363 		case HASH_ALG_SHA3_384:
2364 			rc = do_shash("sha3-384", ctx->authkey, key, keylen,
2365 				      NULL, 0, NULL, 0);
2366 			break;
2367 		case HASH_ALG_SHA3_512:
2368 			rc = do_shash("sha3-512", ctx->authkey, key, keylen,
2369 				      NULL, 0, NULL, 0);
2370 			break;
2371 		default:
2372 			pr_err("%s() Error: unknown hash alg\n", __func__);
2373 			return -EINVAL;
2374 		}
2375 		if (rc < 0) {
2376 			pr_err("%s() Error %d computing shash for %s\n",
2377 			       __func__, rc, hash_alg_name[ctx->auth.alg]);
2378 			return rc;
2379 		}
2380 		ctx->authkeylen = digestsize;
2381 
2382 		flow_log("  keylen > digestsize... hashed\n");
2383 		flow_dump("  newkey: ", ctx->authkey, ctx->authkeylen);
2384 	} else {
2385 		memcpy(ctx->authkey, key, keylen);
2386 		ctx->authkeylen = keylen;
2387 	}
2388 
2389 	/*
2390 	 * Full HMAC operation in SPUM is not verified,
2391 	 * So keeping the generation of IPAD, OPAD and
2392 	 * outer hashing in software.
2393 	 */
2394 	if (iproc_priv.spu.spu_type == SPU_TYPE_SPUM) {
2395 		memcpy(ctx->ipad, ctx->authkey, ctx->authkeylen);
2396 		memset(ctx->ipad + ctx->authkeylen, 0,
2397 		       blocksize - ctx->authkeylen);
2398 		ctx->authkeylen = 0;
2399 		memcpy(ctx->opad, ctx->ipad, blocksize);
2400 
2401 		for (index = 0; index < blocksize; index++) {
2402 			ctx->ipad[index] ^= HMAC_IPAD_VALUE;
2403 			ctx->opad[index] ^= HMAC_OPAD_VALUE;
2404 		}
2405 
2406 		flow_dump("  ipad: ", ctx->ipad, blocksize);
2407 		flow_dump("  opad: ", ctx->opad, blocksize);
2408 	}
2409 	ctx->digestsize = digestsize;
2410 	atomic_inc(&iproc_priv.setkey_cnt[SPU_OP_HMAC]);
2411 
2412 	return 0;
2413 }
2414 
2415 static int ahash_hmac_init(struct ahash_request *req)
2416 {
2417 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2418 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2419 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
2420 	unsigned int blocksize =
2421 			crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
2422 
2423 	flow_log("ahash_hmac_init()\n");
2424 
2425 	/* init the context as a hash */
2426 	ahash_init(req);
2427 
2428 	if (!spu_no_incr_hash(ctx)) {
2429 		/* SPU-M can do incr hashing but needs sw for outer HMAC */
2430 		rctx->is_sw_hmac = true;
2431 		ctx->auth.mode = HASH_MODE_HASH;
2432 		/* start with a prepended ipad */
2433 		memcpy(rctx->hash_carry, ctx->ipad, blocksize);
2434 		rctx->hash_carry_len = blocksize;
2435 		rctx->total_todo += blocksize;
2436 	}
2437 
2438 	return 0;
2439 }
2440 
2441 static int ahash_hmac_update(struct ahash_request *req)
2442 {
2443 	flow_log("ahash_hmac_update() nbytes:%u\n", req->nbytes);
2444 
2445 	if (!req->nbytes)
2446 		return 0;
2447 
2448 	return ahash_update(req);
2449 }
2450 
2451 static int ahash_hmac_final(struct ahash_request *req)
2452 {
2453 	flow_log("ahash_hmac_final() nbytes:%u\n", req->nbytes);
2454 
2455 	return ahash_final(req);
2456 }
2457 
2458 static int ahash_hmac_finup(struct ahash_request *req)
2459 {
2460 	flow_log("ahash_hmac_finupl() nbytes:%u\n", req->nbytes);
2461 
2462 	return ahash_finup(req);
2463 }
2464 
2465 static int ahash_hmac_digest(struct ahash_request *req)
2466 {
2467 	struct iproc_reqctx_s *rctx = ahash_request_ctx(req);
2468 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2469 	struct iproc_ctx_s *ctx = crypto_ahash_ctx(tfm);
2470 	unsigned int blocksize =
2471 			crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
2472 
2473 	flow_log("ahash_hmac_digest() nbytes:%u\n", req->nbytes);
2474 
2475 	/* Perform initialization and then call finup */
2476 	__ahash_init(req);
2477 
2478 	if (iproc_priv.spu.spu_type == SPU_TYPE_SPU2) {
2479 		/*
2480 		 * SPU2 supports full HMAC implementation in the
2481 		 * hardware, need not to generate IPAD, OPAD and
2482 		 * outer hash in software.
2483 		 * Only for hash key len > hash block size, SPU2
2484 		 * expects to perform hashing on the key, shorten
2485 		 * it to digest size and feed it as hash key.
2486 		 */
2487 		rctx->is_sw_hmac = false;
2488 		ctx->auth.mode = HASH_MODE_HMAC;
2489 	} else {
2490 		rctx->is_sw_hmac = true;
2491 		ctx->auth.mode = HASH_MODE_HASH;
2492 		/* start with a prepended ipad */
2493 		memcpy(rctx->hash_carry, ctx->ipad, blocksize);
2494 		rctx->hash_carry_len = blocksize;
2495 		rctx->total_todo += blocksize;
2496 	}
2497 
2498 	return __ahash_finup(req);
2499 }
2500 
2501 /* aead helpers */
2502 
2503 static int aead_need_fallback(struct aead_request *req)
2504 {
2505 	struct iproc_reqctx_s *rctx = aead_request_ctx(req);
2506 	struct spu_hw *spu = &iproc_priv.spu;
2507 	struct crypto_aead *aead = crypto_aead_reqtfm(req);
2508 	struct iproc_ctx_s *ctx = crypto_aead_ctx(aead);
2509 	u32 payload_len;
2510 
2511 	/*
2512 	 * SPU hardware cannot handle the AES-GCM/CCM case where plaintext
2513 	 * and AAD are both 0 bytes long. So use fallback in this case.
2514 	 */
2515 	if (((ctx->cipher.mode == CIPHER_MODE_GCM) ||
2516 	     (ctx->cipher.mode == CIPHER_MODE_CCM)) &&
2517 	    (req->assoclen == 0)) {
2518 		if ((rctx->is_encrypt && (req->cryptlen == 0)) ||
2519 		    (!rctx->is_encrypt && (req->cryptlen == ctx->digestsize))) {
2520 			flow_log("AES GCM/CCM needs fallback for 0 len req\n");
2521 			return 1;
2522 		}
2523 	}
2524 
2525 	/* SPU-M hardware only supports CCM digest size of 8, 12, or 16 bytes */
2526 	if ((ctx->cipher.mode == CIPHER_MODE_CCM) &&
2527 	    (spu->spu_type == SPU_TYPE_SPUM) &&
2528 	    (ctx->digestsize != 8) && (ctx->digestsize != 12) &&
2529 	    (ctx->digestsize != 16)) {
2530 		flow_log("%s() AES CCM needs fallback for digest size %d\n",
2531 			 __func__, ctx->digestsize);
2532 		return 1;
2533 	}
2534 
2535 	/*
2536 	 * SPU-M on NSP has an issue where AES-CCM hash is not correct
2537 	 * when AAD size is 0
2538 	 */
2539 	if ((ctx->cipher.mode == CIPHER_MODE_CCM) &&
2540 	    (spu->spu_subtype == SPU_SUBTYPE_SPUM_NSP) &&
2541 	    (req->assoclen == 0)) {
2542 		flow_log("%s() AES_CCM needs fallback for 0 len AAD on NSP\n",
2543 			 __func__);
2544 		return 1;
2545 	}
2546 
2547 	/*
2548 	 * RFC4106 and RFC4543 cannot handle the case where AAD is other than
2549 	 * 16 or 20 bytes long. So use fallback in this case.
2550 	 */
2551 	if (ctx->cipher.mode == CIPHER_MODE_GCM &&
2552 	    ctx->cipher.alg == CIPHER_ALG_AES &&
2553 	    rctx->iv_ctr_len == GCM_RFC4106_IV_SIZE &&
2554 	    req->assoclen != 16 && req->assoclen != 20) {
2555 		flow_log("RFC4106/RFC4543 needs fallback for assoclen"
2556 			 " other than 16 or 20 bytes\n");
2557 		return 1;
2558 	}
2559 
2560 	payload_len = req->cryptlen;
2561 	if (spu->spu_type == SPU_TYPE_SPUM)
2562 		payload_len += req->assoclen;
2563 
2564 	flow_log("%s() payload len: %u\n", __func__, payload_len);
2565 
2566 	if (ctx->max_payload == SPU_MAX_PAYLOAD_INF)
2567 		return 0;
2568 	else
2569 		return payload_len > ctx->max_payload;
2570 }
2571 
2572 static void aead_complete(struct crypto_async_request *areq, int err)
2573 {
2574 	struct aead_request *req =
2575 	    container_of(areq, struct aead_request, base);
2576 	struct iproc_reqctx_s *rctx = aead_request_ctx(req);
2577 	struct crypto_aead *aead = crypto_aead_reqtfm(req);
2578 
2579 	flow_log("%s() err:%d\n", __func__, err);
2580 
2581 	areq->tfm = crypto_aead_tfm(aead);
2582 
2583 	areq->complete = rctx->old_complete;
2584 	areq->data = rctx->old_data;
2585 
2586 	areq->complete(areq, err);
2587 }
2588 
2589 static int aead_do_fallback(struct aead_request *req, bool is_encrypt)
2590 {
2591 	struct crypto_aead *aead = crypto_aead_reqtfm(req);
2592 	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
2593 	struct iproc_reqctx_s *rctx = aead_request_ctx(req);
2594 	struct iproc_ctx_s *ctx = crypto_tfm_ctx(tfm);
2595 	int err;
2596 	u32 req_flags;
2597 
2598 	flow_log("%s() enc:%u\n", __func__, is_encrypt);
2599 
2600 	if (ctx->fallback_cipher) {
2601 		/* Store the cipher tfm and then use the fallback tfm */
2602 		rctx->old_tfm = tfm;
2603 		aead_request_set_tfm(req, ctx->fallback_cipher);
2604 		/*
2605 		 * Save the callback and chain ourselves in, so we can restore
2606 		 * the tfm
2607 		 */
2608 		rctx->old_complete = req->base.complete;
2609 		rctx->old_data = req->base.data;
2610 		req_flags = aead_request_flags(req);
2611 		aead_request_set_callback(req, req_flags, aead_complete, req);
2612 		err = is_encrypt ? crypto_aead_encrypt(req) :
2613 		    crypto_aead_decrypt(req);
2614 
2615 		if (err == 0) {
2616 			/*
2617 			 * fallback was synchronous (did not return
2618 			 * -EINPROGRESS). So restore request state here.
2619 			 */
2620 			aead_request_set_callback(req, req_flags,
2621 						  rctx->old_complete, req);
2622 			req->base.data = rctx->old_data;
2623 			aead_request_set_tfm(req, aead);
2624 			flow_log("%s() fallback completed successfully\n\n",
2625 				 __func__);
2626 		}
2627 	} else {
2628 		err = -EINVAL;
2629 	}
2630 
2631 	return err;
2632 }
2633 
2634 static int aead_enqueue(struct aead_request *req, bool is_encrypt)
2635 {
2636 	struct iproc_reqctx_s *rctx = aead_request_ctx(req);
2637 	struct crypto_aead *aead = crypto_aead_reqtfm(req);
2638 	struct iproc_ctx_s *ctx = crypto_aead_ctx(aead);
2639 	int err;
2640 
2641 	flow_log("%s() enc:%u\n", __func__, is_encrypt);
2642 
2643 	if (req->assoclen > MAX_ASSOC_SIZE) {
2644 		pr_err
2645 		    ("%s() Error: associated data too long. (%u > %u bytes)\n",
2646 		     __func__, req->assoclen, MAX_ASSOC_SIZE);
2647 		return -EINVAL;
2648 	}
2649 
2650 	rctx->gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
2651 		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
2652 	rctx->parent = &req->base;
2653 	rctx->is_encrypt = is_encrypt;
2654 	rctx->bd_suppress = false;
2655 	rctx->total_todo = req->cryptlen;
2656 	rctx->src_sent = 0;
2657 	rctx->total_sent = 0;
2658 	rctx->total_received = 0;
2659 	rctx->is_sw_hmac = false;
2660 	rctx->ctx = ctx;
2661 	memset(&rctx->mb_mssg, 0, sizeof(struct brcm_message));
2662 
2663 	/* assoc data is at start of src sg */
2664 	rctx->assoc = req->src;
2665 
2666 	/*
2667 	 * Init current position in src scatterlist to be after assoc data.
2668 	 * src_skip set to buffer offset where data begins. (Assoc data could
2669 	 * end in the middle of a buffer.)
2670 	 */
2671 	if (spu_sg_at_offset(req->src, req->assoclen, &rctx->src_sg,
2672 			     &rctx->src_skip) < 0) {
2673 		pr_err("%s() Error: Unable to find start of src data\n",
2674 		       __func__);
2675 		return -EINVAL;
2676 	}
2677 
2678 	rctx->src_nents = 0;
2679 	rctx->dst_nents = 0;
2680 	if (req->dst == req->src) {
2681 		rctx->dst_sg = rctx->src_sg;
2682 		rctx->dst_skip = rctx->src_skip;
2683 	} else {
2684 		/*
2685 		 * Expect req->dst to have room for assoc data followed by
2686 		 * output data and ICV, if encrypt. So initialize dst_sg
2687 		 * to point beyond assoc len offset.
2688 		 */
2689 		if (spu_sg_at_offset(req->dst, req->assoclen, &rctx->dst_sg,
2690 				     &rctx->dst_skip) < 0) {
2691 			pr_err("%s() Error: Unable to find start of dst data\n",
2692 			       __func__);
2693 			return -EINVAL;
2694 		}
2695 	}
2696 
2697 	if (ctx->cipher.mode == CIPHER_MODE_CBC ||
2698 	    ctx->cipher.mode == CIPHER_MODE_CTR ||
2699 	    ctx->cipher.mode == CIPHER_MODE_OFB ||
2700 	    ctx->cipher.mode == CIPHER_MODE_XTS ||
2701 	    ctx->cipher.mode == CIPHER_MODE_GCM) {
2702 		rctx->iv_ctr_len =
2703 			ctx->salt_len +
2704 			crypto_aead_ivsize(crypto_aead_reqtfm(req));
2705 	} else if (ctx->cipher.mode == CIPHER_MODE_CCM) {
2706 		rctx->iv_ctr_len = CCM_AES_IV_SIZE;
2707 	} else {
2708 		rctx->iv_ctr_len = 0;
2709 	}
2710 
2711 	rctx->hash_carry_len = 0;
2712 
2713 	flow_log("  src sg: %p\n", req->src);
2714 	flow_log("  rctx->src_sg: %p, src_skip %u\n",
2715 		 rctx->src_sg, rctx->src_skip);
2716 	flow_log("  assoc:  %p, assoclen %u\n", rctx->assoc, req->assoclen);
2717 	flow_log("  dst sg: %p\n", req->dst);
2718 	flow_log("  rctx->dst_sg: %p, dst_skip %u\n",
2719 		 rctx->dst_sg, rctx->dst_skip);
2720 	flow_log("  iv_ctr_len:%u\n", rctx->iv_ctr_len);
2721 	flow_dump("  iv: ", req->iv, rctx->iv_ctr_len);
2722 	flow_log("  authkeylen:%u\n", ctx->authkeylen);
2723 	flow_log("  is_esp: %s\n", ctx->is_esp ? "yes" : "no");
2724 
2725 	if (ctx->max_payload == SPU_MAX_PAYLOAD_INF)
2726 		flow_log("  max_payload infinite");
2727 	else
2728 		flow_log("  max_payload: %u\n", ctx->max_payload);
2729 
2730 	if (unlikely(aead_need_fallback(req)))
2731 		return aead_do_fallback(req, is_encrypt);
2732 
2733 	/*
2734 	 * Do memory allocations for request after fallback check, because if we
2735 	 * do fallback, we won't call finish_req() to dealloc.
2736 	 */
2737 	if (rctx->iv_ctr_len) {
2738 		if (ctx->salt_len)
2739 			memcpy(rctx->msg_buf.iv_ctr + ctx->salt_offset,
2740 			       ctx->salt, ctx->salt_len);
2741 		memcpy(rctx->msg_buf.iv_ctr + ctx->salt_offset + ctx->salt_len,
2742 		       req->iv,
2743 		       rctx->iv_ctr_len - ctx->salt_len - ctx->salt_offset);
2744 	}
2745 
2746 	rctx->chan_idx = select_channel();
2747 	err = handle_aead_req(rctx);
2748 	if (err != -EINPROGRESS)
2749 		/* synchronous result */
2750 		spu_chunk_cleanup(rctx);
2751 
2752 	return err;
2753 }
2754 
2755 static int aead_authenc_setkey(struct crypto_aead *cipher,
2756 			       const u8 *key, unsigned int keylen)
2757 {
2758 	struct spu_hw *spu = &iproc_priv.spu;
2759 	struct iproc_ctx_s *ctx = crypto_aead_ctx(cipher);
2760 	struct crypto_tfm *tfm = crypto_aead_tfm(cipher);
2761 	struct crypto_authenc_keys keys;
2762 	int ret;
2763 
2764 	flow_log("%s() aead:%p key:%p keylen:%u\n", __func__, cipher, key,
2765 		 keylen);
2766 	flow_dump("  key: ", key, keylen);
2767 
2768 	ret = crypto_authenc_extractkeys(&keys, key, keylen);
2769 	if (ret)
2770 		goto badkey;
2771 
2772 	if (keys.enckeylen > MAX_KEY_SIZE ||
2773 	    keys.authkeylen > MAX_KEY_SIZE)
2774 		goto badkey;
2775 
2776 	ctx->enckeylen = keys.enckeylen;
2777 	ctx->authkeylen = keys.authkeylen;
2778 
2779 	memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
2780 	/* May end up padding auth key. So make sure it's zeroed. */
2781 	memset(ctx->authkey, 0, sizeof(ctx->authkey));
2782 	memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
2783 
2784 	switch (ctx->alg->cipher_info.alg) {
2785 	case CIPHER_ALG_DES:
2786 		if (verify_aead_des_key(cipher, keys.enckey, keys.enckeylen))
2787 			return -EINVAL;
2788 
2789 		ctx->cipher_type = CIPHER_TYPE_DES;
2790 		break;
2791 	case CIPHER_ALG_3DES:
2792 		if (verify_aead_des3_key(cipher, keys.enckey, keys.enckeylen))
2793 			return -EINVAL;
2794 
2795 		ctx->cipher_type = CIPHER_TYPE_3DES;
2796 		break;
2797 	case CIPHER_ALG_AES:
2798 		switch (ctx->enckeylen) {
2799 		case AES_KEYSIZE_128:
2800 			ctx->cipher_type = CIPHER_TYPE_AES128;
2801 			break;
2802 		case AES_KEYSIZE_192:
2803 			ctx->cipher_type = CIPHER_TYPE_AES192;
2804 			break;
2805 		case AES_KEYSIZE_256:
2806 			ctx->cipher_type = CIPHER_TYPE_AES256;
2807 			break;
2808 		default:
2809 			goto badkey;
2810 		}
2811 		break;
2812 	default:
2813 		pr_err("%s() Error: Unknown cipher alg\n", __func__);
2814 		return -EINVAL;
2815 	}
2816 
2817 	flow_log("  enckeylen:%u authkeylen:%u\n", ctx->enckeylen,
2818 		 ctx->authkeylen);
2819 	flow_dump("  enc: ", ctx->enckey, ctx->enckeylen);
2820 	flow_dump("  auth: ", ctx->authkey, ctx->authkeylen);
2821 
2822 	/* setkey the fallback just in case we needto use it */
2823 	if (ctx->fallback_cipher) {
2824 		flow_log("  running fallback setkey()\n");
2825 
2826 		ctx->fallback_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
2827 		ctx->fallback_cipher->base.crt_flags |=
2828 		    tfm->crt_flags & CRYPTO_TFM_REQ_MASK;
2829 		ret = crypto_aead_setkey(ctx->fallback_cipher, key, keylen);
2830 		if (ret)
2831 			flow_log("  fallback setkey() returned:%d\n", ret);
2832 	}
2833 
2834 	ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen,
2835 							  ctx->enckeylen,
2836 							  false);
2837 
2838 	atomic_inc(&iproc_priv.setkey_cnt[SPU_OP_AEAD]);
2839 
2840 	return ret;
2841 
2842 badkey:
2843 	ctx->enckeylen = 0;
2844 	ctx->authkeylen = 0;
2845 	ctx->digestsize = 0;
2846 
2847 	return -EINVAL;
2848 }
2849 
2850 static int aead_gcm_ccm_setkey(struct crypto_aead *cipher,
2851 			       const u8 *key, unsigned int keylen)
2852 {
2853 	struct spu_hw *spu = &iproc_priv.spu;
2854 	struct iproc_ctx_s *ctx = crypto_aead_ctx(cipher);
2855 	struct crypto_tfm *tfm = crypto_aead_tfm(cipher);
2856 
2857 	int ret = 0;
2858 
2859 	flow_log("%s() keylen:%u\n", __func__, keylen);
2860 	flow_dump("  key: ", key, keylen);
2861 
2862 	if (!ctx->is_esp)
2863 		ctx->digestsize = keylen;
2864 
2865 	ctx->enckeylen = keylen;
2866 	ctx->authkeylen = 0;
2867 
2868 	switch (ctx->enckeylen) {
2869 	case AES_KEYSIZE_128:
2870 		ctx->cipher_type = CIPHER_TYPE_AES128;
2871 		break;
2872 	case AES_KEYSIZE_192:
2873 		ctx->cipher_type = CIPHER_TYPE_AES192;
2874 		break;
2875 	case AES_KEYSIZE_256:
2876 		ctx->cipher_type = CIPHER_TYPE_AES256;
2877 		break;
2878 	default:
2879 		goto badkey;
2880 	}
2881 
2882 	memcpy(ctx->enckey, key, ctx->enckeylen);
2883 
2884 	flow_log("  enckeylen:%u authkeylen:%u\n", ctx->enckeylen,
2885 		 ctx->authkeylen);
2886 	flow_dump("  enc: ", ctx->enckey, ctx->enckeylen);
2887 	flow_dump("  auth: ", ctx->authkey, ctx->authkeylen);
2888 
2889 	/* setkey the fallback just in case we need to use it */
2890 	if (ctx->fallback_cipher) {
2891 		flow_log("  running fallback setkey()\n");
2892 
2893 		ctx->fallback_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
2894 		ctx->fallback_cipher->base.crt_flags |=
2895 		    tfm->crt_flags & CRYPTO_TFM_REQ_MASK;
2896 		ret = crypto_aead_setkey(ctx->fallback_cipher, key,
2897 					 keylen + ctx->salt_len);
2898 		if (ret)
2899 			flow_log("  fallback setkey() returned:%d\n", ret);
2900 	}
2901 
2902 	ctx->spu_resp_hdr_len = spu->spu_response_hdr_len(ctx->authkeylen,
2903 							  ctx->enckeylen,
2904 							  false);
2905 
2906 	atomic_inc(&iproc_priv.setkey_cnt[SPU_OP_AEAD]);
2907 
2908 	flow_log("  enckeylen:%u authkeylen:%u\n", ctx->enckeylen,
2909 		 ctx->authkeylen);
2910 
2911 	return ret;
2912 
2913 badkey:
2914 	ctx->enckeylen = 0;
2915 	ctx->authkeylen = 0;
2916 	ctx->digestsize = 0;
2917 
2918 	return -EINVAL;
2919 }
2920 
2921 /**
2922  * aead_gcm_esp_setkey() - setkey() operation for ESP variant of GCM AES.
2923  * @cipher: AEAD structure
2924  * @key:    Key followed by 4 bytes of salt
2925  * @keylen: Length of key plus salt, in bytes
2926  *
2927  * Extracts salt from key and stores it to be prepended to IV on each request.
2928  * Digest is always 16 bytes
2929  *
2930  * Return: Value from generic gcm setkey.
2931  */
2932 static int aead_gcm_esp_setkey(struct crypto_aead *cipher,
2933 			       const u8 *key, unsigned int keylen)
2934 {
2935 	struct iproc_ctx_s *ctx = crypto_aead_ctx(cipher);
2936 
2937 	flow_log("%s\n", __func__);
2938 
2939 	if (keylen < GCM_ESP_SALT_SIZE)
2940 		return -EINVAL;
2941 
2942 	ctx->salt_len = GCM_ESP_SALT_SIZE;
2943 	ctx->salt_offset = GCM_ESP_SALT_OFFSET;
2944 	memcpy(ctx->salt, key + keylen - GCM_ESP_SALT_SIZE, GCM_ESP_SALT_SIZE);
2945 	keylen -= GCM_ESP_SALT_SIZE;
2946 	ctx->digestsize = GCM_ESP_DIGESTSIZE;
2947 	ctx->is_esp = true;
2948 	flow_dump("salt: ", ctx->salt, GCM_ESP_SALT_SIZE);
2949 
2950 	return aead_gcm_ccm_setkey(cipher, key, keylen);
2951 }
2952 
2953 /**
2954  * rfc4543_gcm_esp_setkey() - setkey operation for RFC4543 variant of GCM/GMAC.
2955  * cipher: AEAD structure
2956  * key:    Key followed by 4 bytes of salt
2957  * keylen: Length of key plus salt, in bytes
2958  *
2959  * Extracts salt from key and stores it to be prepended to IV on each request.
2960  * Digest is always 16 bytes
2961  *
2962  * Return: Value from generic gcm setkey.
2963  */
2964 static int rfc4543_gcm_esp_setkey(struct crypto_aead *cipher,
2965 				  const u8 *key, unsigned int keylen)
2966 {
2967 	struct iproc_ctx_s *ctx = crypto_aead_ctx(cipher);
2968 
2969 	flow_log("%s\n", __func__);
2970 
2971 	if (keylen < GCM_ESP_SALT_SIZE)
2972 		return -EINVAL;
2973 
2974 	ctx->salt_len = GCM_ESP_SALT_SIZE;
2975 	ctx->salt_offset = GCM_ESP_SALT_OFFSET;
2976 	memcpy(ctx->salt, key + keylen - GCM_ESP_SALT_SIZE, GCM_ESP_SALT_SIZE);
2977 	keylen -= GCM_ESP_SALT_SIZE;
2978 	ctx->digestsize = GCM_ESP_DIGESTSIZE;
2979 	ctx->is_esp = true;
2980 	ctx->is_rfc4543 = true;
2981 	flow_dump("salt: ", ctx->salt, GCM_ESP_SALT_SIZE);
2982 
2983 	return aead_gcm_ccm_setkey(cipher, key, keylen);
2984 }
2985 
2986 /**
2987  * aead_ccm_esp_setkey() - setkey() operation for ESP variant of CCM AES.
2988  * @cipher: AEAD structure
2989  * @key:    Key followed by 4 bytes of salt
2990  * @keylen: Length of key plus salt, in bytes
2991  *
2992  * Extracts salt from key and stores it to be prepended to IV on each request.
2993  * Digest is always 16 bytes
2994  *
2995  * Return: Value from generic ccm setkey.
2996  */
2997 static int aead_ccm_esp_setkey(struct crypto_aead *cipher,
2998 			       const u8 *key, unsigned int keylen)
2999 {
3000 	struct iproc_ctx_s *ctx = crypto_aead_ctx(cipher);
3001 
3002 	flow_log("%s\n", __func__);
3003 
3004 	if (keylen < CCM_ESP_SALT_SIZE)
3005 		return -EINVAL;
3006 
3007 	ctx->salt_len = CCM_ESP_SALT_SIZE;
3008 	ctx->salt_offset = CCM_ESP_SALT_OFFSET;
3009 	memcpy(ctx->salt, key + keylen - CCM_ESP_SALT_SIZE, CCM_ESP_SALT_SIZE);
3010 	keylen -= CCM_ESP_SALT_SIZE;
3011 	ctx->is_esp = true;
3012 	flow_dump("salt: ", ctx->salt, CCM_ESP_SALT_SIZE);
3013 
3014 	return aead_gcm_ccm_setkey(cipher, key, keylen);
3015 }
3016 
3017 static int aead_setauthsize(struct crypto_aead *cipher, unsigned int authsize)
3018 {
3019 	struct iproc_ctx_s *ctx = crypto_aead_ctx(cipher);
3020 	int ret = 0;
3021 
3022 	flow_log("%s() authkeylen:%u authsize:%u\n",
3023 		 __func__, ctx->authkeylen, authsize);
3024 
3025 	ctx->digestsize = authsize;
3026 
3027 	/* setkey the fallback just in case we needto use it */
3028 	if (ctx->fallback_cipher) {
3029 		flow_log("  running fallback setauth()\n");
3030 
3031 		ret = crypto_aead_setauthsize(ctx->fallback_cipher, authsize);
3032 		if (ret)
3033 			flow_log("  fallback setauth() returned:%d\n", ret);
3034 	}
3035 
3036 	return ret;
3037 }
3038 
3039 static int aead_encrypt(struct aead_request *req)
3040 {
3041 	flow_log("%s() cryptlen:%u %08x\n", __func__, req->cryptlen,
3042 		 req->cryptlen);
3043 	dump_sg(req->src, 0, req->cryptlen + req->assoclen);
3044 	flow_log("  assoc_len:%u\n", req->assoclen);
3045 
3046 	return aead_enqueue(req, true);
3047 }
3048 
3049 static int aead_decrypt(struct aead_request *req)
3050 {
3051 	flow_log("%s() cryptlen:%u\n", __func__, req->cryptlen);
3052 	dump_sg(req->src, 0, req->cryptlen + req->assoclen);
3053 	flow_log("  assoc_len:%u\n", req->assoclen);
3054 
3055 	return aead_enqueue(req, false);
3056 }
3057 
3058 /* ==================== Supported Cipher Algorithms ==================== */
3059 
3060 static struct iproc_alg_s driver_algs[] = {
3061 	{
3062 	 .type = CRYPTO_ALG_TYPE_AEAD,
3063 	 .alg.aead = {
3064 		 .base = {
3065 			.cra_name = "gcm(aes)",
3066 			.cra_driver_name = "gcm-aes-iproc",
3067 			.cra_blocksize = AES_BLOCK_SIZE,
3068 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK
3069 		 },
3070 		 .setkey = aead_gcm_ccm_setkey,
3071 		 .ivsize = GCM_AES_IV_SIZE,
3072 		.maxauthsize = AES_BLOCK_SIZE,
3073 	 },
3074 	 .cipher_info = {
3075 			 .alg = CIPHER_ALG_AES,
3076 			 .mode = CIPHER_MODE_GCM,
3077 			 },
3078 	 .auth_info = {
3079 		       .alg = HASH_ALG_AES,
3080 		       .mode = HASH_MODE_GCM,
3081 		       },
3082 	 .auth_first = 0,
3083 	 },
3084 	{
3085 	 .type = CRYPTO_ALG_TYPE_AEAD,
3086 	 .alg.aead = {
3087 		 .base = {
3088 			.cra_name = "ccm(aes)",
3089 			.cra_driver_name = "ccm-aes-iproc",
3090 			.cra_blocksize = AES_BLOCK_SIZE,
3091 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK
3092 		 },
3093 		 .setkey = aead_gcm_ccm_setkey,
3094 		 .ivsize = CCM_AES_IV_SIZE,
3095 		.maxauthsize = AES_BLOCK_SIZE,
3096 	 },
3097 	 .cipher_info = {
3098 			 .alg = CIPHER_ALG_AES,
3099 			 .mode = CIPHER_MODE_CCM,
3100 			 },
3101 	 .auth_info = {
3102 		       .alg = HASH_ALG_AES,
3103 		       .mode = HASH_MODE_CCM,
3104 		       },
3105 	 .auth_first = 0,
3106 	 },
3107 	{
3108 	 .type = CRYPTO_ALG_TYPE_AEAD,
3109 	 .alg.aead = {
3110 		 .base = {
3111 			.cra_name = "rfc4106(gcm(aes))",
3112 			.cra_driver_name = "gcm-aes-esp-iproc",
3113 			.cra_blocksize = AES_BLOCK_SIZE,
3114 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK
3115 		 },
3116 		 .setkey = aead_gcm_esp_setkey,
3117 		 .ivsize = GCM_RFC4106_IV_SIZE,
3118 		 .maxauthsize = AES_BLOCK_SIZE,
3119 	 },
3120 	 .cipher_info = {
3121 			 .alg = CIPHER_ALG_AES,
3122 			 .mode = CIPHER_MODE_GCM,
3123 			 },
3124 	 .auth_info = {
3125 		       .alg = HASH_ALG_AES,
3126 		       .mode = HASH_MODE_GCM,
3127 		       },
3128 	 .auth_first = 0,
3129 	 },
3130 	{
3131 	 .type = CRYPTO_ALG_TYPE_AEAD,
3132 	 .alg.aead = {
3133 		 .base = {
3134 			.cra_name = "rfc4309(ccm(aes))",
3135 			.cra_driver_name = "ccm-aes-esp-iproc",
3136 			.cra_blocksize = AES_BLOCK_SIZE,
3137 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK
3138 		 },
3139 		 .setkey = aead_ccm_esp_setkey,
3140 		 .ivsize = CCM_AES_IV_SIZE,
3141 		 .maxauthsize = AES_BLOCK_SIZE,
3142 	 },
3143 	 .cipher_info = {
3144 			 .alg = CIPHER_ALG_AES,
3145 			 .mode = CIPHER_MODE_CCM,
3146 			 },
3147 	 .auth_info = {
3148 		       .alg = HASH_ALG_AES,
3149 		       .mode = HASH_MODE_CCM,
3150 		       },
3151 	 .auth_first = 0,
3152 	 },
3153 	{
3154 	 .type = CRYPTO_ALG_TYPE_AEAD,
3155 	 .alg.aead = {
3156 		 .base = {
3157 			.cra_name = "rfc4543(gcm(aes))",
3158 			.cra_driver_name = "gmac-aes-esp-iproc",
3159 			.cra_blocksize = AES_BLOCK_SIZE,
3160 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK
3161 		 },
3162 		 .setkey = rfc4543_gcm_esp_setkey,
3163 		 .ivsize = GCM_RFC4106_IV_SIZE,
3164 		 .maxauthsize = AES_BLOCK_SIZE,
3165 	 },
3166 	 .cipher_info = {
3167 			 .alg = CIPHER_ALG_AES,
3168 			 .mode = CIPHER_MODE_GCM,
3169 			 },
3170 	 .auth_info = {
3171 		       .alg = HASH_ALG_AES,
3172 		       .mode = HASH_MODE_GCM,
3173 		       },
3174 	 .auth_first = 0,
3175 	 },
3176 	{
3177 	 .type = CRYPTO_ALG_TYPE_AEAD,
3178 	 .alg.aead = {
3179 		 .base = {
3180 			.cra_name = "authenc(hmac(md5),cbc(aes))",
3181 			.cra_driver_name = "authenc-hmac-md5-cbc-aes-iproc",
3182 			.cra_blocksize = AES_BLOCK_SIZE,
3183 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3184 				     CRYPTO_ALG_ASYNC |
3185 				     CRYPTO_ALG_ALLOCATES_MEMORY
3186 		 },
3187 		 .setkey = aead_authenc_setkey,
3188 		.ivsize = AES_BLOCK_SIZE,
3189 		.maxauthsize = MD5_DIGEST_SIZE,
3190 	 },
3191 	 .cipher_info = {
3192 			 .alg = CIPHER_ALG_AES,
3193 			 .mode = CIPHER_MODE_CBC,
3194 			 },
3195 	 .auth_info = {
3196 		       .alg = HASH_ALG_MD5,
3197 		       .mode = HASH_MODE_HMAC,
3198 		       },
3199 	 .auth_first = 0,
3200 	 },
3201 	{
3202 	 .type = CRYPTO_ALG_TYPE_AEAD,
3203 	 .alg.aead = {
3204 		 .base = {
3205 			.cra_name = "authenc(hmac(sha1),cbc(aes))",
3206 			.cra_driver_name = "authenc-hmac-sha1-cbc-aes-iproc",
3207 			.cra_blocksize = AES_BLOCK_SIZE,
3208 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3209 				     CRYPTO_ALG_ASYNC |
3210 				     CRYPTO_ALG_ALLOCATES_MEMORY
3211 		 },
3212 		 .setkey = aead_authenc_setkey,
3213 		 .ivsize = AES_BLOCK_SIZE,
3214 		 .maxauthsize = SHA1_DIGEST_SIZE,
3215 	 },
3216 	 .cipher_info = {
3217 			 .alg = CIPHER_ALG_AES,
3218 			 .mode = CIPHER_MODE_CBC,
3219 			 },
3220 	 .auth_info = {
3221 		       .alg = HASH_ALG_SHA1,
3222 		       .mode = HASH_MODE_HMAC,
3223 		       },
3224 	 .auth_first = 0,
3225 	 },
3226 	{
3227 	 .type = CRYPTO_ALG_TYPE_AEAD,
3228 	 .alg.aead = {
3229 		 .base = {
3230 			.cra_name = "authenc(hmac(sha256),cbc(aes))",
3231 			.cra_driver_name = "authenc-hmac-sha256-cbc-aes-iproc",
3232 			.cra_blocksize = AES_BLOCK_SIZE,
3233 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3234 				     CRYPTO_ALG_ASYNC |
3235 				     CRYPTO_ALG_ALLOCATES_MEMORY
3236 		 },
3237 		 .setkey = aead_authenc_setkey,
3238 		 .ivsize = AES_BLOCK_SIZE,
3239 		 .maxauthsize = SHA256_DIGEST_SIZE,
3240 	 },
3241 	 .cipher_info = {
3242 			 .alg = CIPHER_ALG_AES,
3243 			 .mode = CIPHER_MODE_CBC,
3244 			 },
3245 	 .auth_info = {
3246 		       .alg = HASH_ALG_SHA256,
3247 		       .mode = HASH_MODE_HMAC,
3248 		       },
3249 	 .auth_first = 0,
3250 	 },
3251 	{
3252 	 .type = CRYPTO_ALG_TYPE_AEAD,
3253 	 .alg.aead = {
3254 		 .base = {
3255 			.cra_name = "authenc(hmac(md5),cbc(des))",
3256 			.cra_driver_name = "authenc-hmac-md5-cbc-des-iproc",
3257 			.cra_blocksize = DES_BLOCK_SIZE,
3258 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3259 				     CRYPTO_ALG_ASYNC |
3260 				     CRYPTO_ALG_ALLOCATES_MEMORY
3261 		 },
3262 		 .setkey = aead_authenc_setkey,
3263 		 .ivsize = DES_BLOCK_SIZE,
3264 		 .maxauthsize = MD5_DIGEST_SIZE,
3265 	 },
3266 	 .cipher_info = {
3267 			 .alg = CIPHER_ALG_DES,
3268 			 .mode = CIPHER_MODE_CBC,
3269 			 },
3270 	 .auth_info = {
3271 		       .alg = HASH_ALG_MD5,
3272 		       .mode = HASH_MODE_HMAC,
3273 		       },
3274 	 .auth_first = 0,
3275 	 },
3276 	{
3277 	 .type = CRYPTO_ALG_TYPE_AEAD,
3278 	 .alg.aead = {
3279 		 .base = {
3280 			.cra_name = "authenc(hmac(sha1),cbc(des))",
3281 			.cra_driver_name = "authenc-hmac-sha1-cbc-des-iproc",
3282 			.cra_blocksize = DES_BLOCK_SIZE,
3283 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3284 				     CRYPTO_ALG_ASYNC |
3285 				     CRYPTO_ALG_ALLOCATES_MEMORY
3286 		 },
3287 		 .setkey = aead_authenc_setkey,
3288 		 .ivsize = DES_BLOCK_SIZE,
3289 		 .maxauthsize = SHA1_DIGEST_SIZE,
3290 	 },
3291 	 .cipher_info = {
3292 			 .alg = CIPHER_ALG_DES,
3293 			 .mode = CIPHER_MODE_CBC,
3294 			 },
3295 	 .auth_info = {
3296 		       .alg = HASH_ALG_SHA1,
3297 		       .mode = HASH_MODE_HMAC,
3298 		       },
3299 	 .auth_first = 0,
3300 	 },
3301 	{
3302 	 .type = CRYPTO_ALG_TYPE_AEAD,
3303 	 .alg.aead = {
3304 		 .base = {
3305 			.cra_name = "authenc(hmac(sha224),cbc(des))",
3306 			.cra_driver_name = "authenc-hmac-sha224-cbc-des-iproc",
3307 			.cra_blocksize = DES_BLOCK_SIZE,
3308 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3309 				     CRYPTO_ALG_ASYNC |
3310 				     CRYPTO_ALG_ALLOCATES_MEMORY
3311 		 },
3312 		 .setkey = aead_authenc_setkey,
3313 		 .ivsize = DES_BLOCK_SIZE,
3314 		 .maxauthsize = SHA224_DIGEST_SIZE,
3315 	 },
3316 	 .cipher_info = {
3317 			 .alg = CIPHER_ALG_DES,
3318 			 .mode = CIPHER_MODE_CBC,
3319 			 },
3320 	 .auth_info = {
3321 		       .alg = HASH_ALG_SHA224,
3322 		       .mode = HASH_MODE_HMAC,
3323 		       },
3324 	 .auth_first = 0,
3325 	 },
3326 	{
3327 	 .type = CRYPTO_ALG_TYPE_AEAD,
3328 	 .alg.aead = {
3329 		 .base = {
3330 			.cra_name = "authenc(hmac(sha256),cbc(des))",
3331 			.cra_driver_name = "authenc-hmac-sha256-cbc-des-iproc",
3332 			.cra_blocksize = DES_BLOCK_SIZE,
3333 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3334 				     CRYPTO_ALG_ASYNC |
3335 				     CRYPTO_ALG_ALLOCATES_MEMORY
3336 		 },
3337 		 .setkey = aead_authenc_setkey,
3338 		 .ivsize = DES_BLOCK_SIZE,
3339 		 .maxauthsize = SHA256_DIGEST_SIZE,
3340 	 },
3341 	 .cipher_info = {
3342 			 .alg = CIPHER_ALG_DES,
3343 			 .mode = CIPHER_MODE_CBC,
3344 			 },
3345 	 .auth_info = {
3346 		       .alg = HASH_ALG_SHA256,
3347 		       .mode = HASH_MODE_HMAC,
3348 		       },
3349 	 .auth_first = 0,
3350 	 },
3351 	{
3352 	 .type = CRYPTO_ALG_TYPE_AEAD,
3353 	 .alg.aead = {
3354 		 .base = {
3355 			.cra_name = "authenc(hmac(sha384),cbc(des))",
3356 			.cra_driver_name = "authenc-hmac-sha384-cbc-des-iproc",
3357 			.cra_blocksize = DES_BLOCK_SIZE,
3358 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3359 				     CRYPTO_ALG_ASYNC |
3360 				     CRYPTO_ALG_ALLOCATES_MEMORY
3361 		 },
3362 		 .setkey = aead_authenc_setkey,
3363 		 .ivsize = DES_BLOCK_SIZE,
3364 		 .maxauthsize = SHA384_DIGEST_SIZE,
3365 	 },
3366 	 .cipher_info = {
3367 			 .alg = CIPHER_ALG_DES,
3368 			 .mode = CIPHER_MODE_CBC,
3369 			 },
3370 	 .auth_info = {
3371 		       .alg = HASH_ALG_SHA384,
3372 		       .mode = HASH_MODE_HMAC,
3373 		       },
3374 	 .auth_first = 0,
3375 	 },
3376 	{
3377 	 .type = CRYPTO_ALG_TYPE_AEAD,
3378 	 .alg.aead = {
3379 		 .base = {
3380 			.cra_name = "authenc(hmac(sha512),cbc(des))",
3381 			.cra_driver_name = "authenc-hmac-sha512-cbc-des-iproc",
3382 			.cra_blocksize = DES_BLOCK_SIZE,
3383 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3384 				     CRYPTO_ALG_ASYNC |
3385 				     CRYPTO_ALG_ALLOCATES_MEMORY
3386 		 },
3387 		 .setkey = aead_authenc_setkey,
3388 		 .ivsize = DES_BLOCK_SIZE,
3389 		 .maxauthsize = SHA512_DIGEST_SIZE,
3390 	 },
3391 	 .cipher_info = {
3392 			 .alg = CIPHER_ALG_DES,
3393 			 .mode = CIPHER_MODE_CBC,
3394 			 },
3395 	 .auth_info = {
3396 		       .alg = HASH_ALG_SHA512,
3397 		       .mode = HASH_MODE_HMAC,
3398 		       },
3399 	 .auth_first = 0,
3400 	 },
3401 	{
3402 	 .type = CRYPTO_ALG_TYPE_AEAD,
3403 	 .alg.aead = {
3404 		 .base = {
3405 			.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
3406 			.cra_driver_name = "authenc-hmac-md5-cbc-des3-iproc",
3407 			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3408 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3409 				     CRYPTO_ALG_ASYNC |
3410 				     CRYPTO_ALG_ALLOCATES_MEMORY
3411 		 },
3412 		 .setkey = aead_authenc_setkey,
3413 		 .ivsize = DES3_EDE_BLOCK_SIZE,
3414 		 .maxauthsize = MD5_DIGEST_SIZE,
3415 	 },
3416 	 .cipher_info = {
3417 			 .alg = CIPHER_ALG_3DES,
3418 			 .mode = CIPHER_MODE_CBC,
3419 			 },
3420 	 .auth_info = {
3421 		       .alg = HASH_ALG_MD5,
3422 		       .mode = HASH_MODE_HMAC,
3423 		       },
3424 	 .auth_first = 0,
3425 	 },
3426 	{
3427 	 .type = CRYPTO_ALG_TYPE_AEAD,
3428 	 .alg.aead = {
3429 		 .base = {
3430 			.cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
3431 			.cra_driver_name = "authenc-hmac-sha1-cbc-des3-iproc",
3432 			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3433 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3434 				     CRYPTO_ALG_ASYNC |
3435 				     CRYPTO_ALG_ALLOCATES_MEMORY
3436 		 },
3437 		 .setkey = aead_authenc_setkey,
3438 		 .ivsize = DES3_EDE_BLOCK_SIZE,
3439 		 .maxauthsize = SHA1_DIGEST_SIZE,
3440 	 },
3441 	 .cipher_info = {
3442 			 .alg = CIPHER_ALG_3DES,
3443 			 .mode = CIPHER_MODE_CBC,
3444 			 },
3445 	 .auth_info = {
3446 		       .alg = HASH_ALG_SHA1,
3447 		       .mode = HASH_MODE_HMAC,
3448 		       },
3449 	 .auth_first = 0,
3450 	 },
3451 	{
3452 	 .type = CRYPTO_ALG_TYPE_AEAD,
3453 	 .alg.aead = {
3454 		 .base = {
3455 			.cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
3456 			.cra_driver_name = "authenc-hmac-sha224-cbc-des3-iproc",
3457 			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3458 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3459 				     CRYPTO_ALG_ASYNC |
3460 				     CRYPTO_ALG_ALLOCATES_MEMORY
3461 		 },
3462 		 .setkey = aead_authenc_setkey,
3463 		 .ivsize = DES3_EDE_BLOCK_SIZE,
3464 		 .maxauthsize = SHA224_DIGEST_SIZE,
3465 	 },
3466 	 .cipher_info = {
3467 			 .alg = CIPHER_ALG_3DES,
3468 			 .mode = CIPHER_MODE_CBC,
3469 			 },
3470 	 .auth_info = {
3471 		       .alg = HASH_ALG_SHA224,
3472 		       .mode = HASH_MODE_HMAC,
3473 		       },
3474 	 .auth_first = 0,
3475 	 },
3476 	{
3477 	 .type = CRYPTO_ALG_TYPE_AEAD,
3478 	 .alg.aead = {
3479 		 .base = {
3480 			.cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
3481 			.cra_driver_name = "authenc-hmac-sha256-cbc-des3-iproc",
3482 			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3483 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3484 				     CRYPTO_ALG_ASYNC |
3485 				     CRYPTO_ALG_ALLOCATES_MEMORY
3486 		 },
3487 		 .setkey = aead_authenc_setkey,
3488 		 .ivsize = DES3_EDE_BLOCK_SIZE,
3489 		 .maxauthsize = SHA256_DIGEST_SIZE,
3490 	 },
3491 	 .cipher_info = {
3492 			 .alg = CIPHER_ALG_3DES,
3493 			 .mode = CIPHER_MODE_CBC,
3494 			 },
3495 	 .auth_info = {
3496 		       .alg = HASH_ALG_SHA256,
3497 		       .mode = HASH_MODE_HMAC,
3498 		       },
3499 	 .auth_first = 0,
3500 	 },
3501 	{
3502 	 .type = CRYPTO_ALG_TYPE_AEAD,
3503 	 .alg.aead = {
3504 		 .base = {
3505 			.cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
3506 			.cra_driver_name = "authenc-hmac-sha384-cbc-des3-iproc",
3507 			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3508 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3509 				     CRYPTO_ALG_ASYNC |
3510 				     CRYPTO_ALG_ALLOCATES_MEMORY
3511 		 },
3512 		 .setkey = aead_authenc_setkey,
3513 		 .ivsize = DES3_EDE_BLOCK_SIZE,
3514 		 .maxauthsize = SHA384_DIGEST_SIZE,
3515 	 },
3516 	 .cipher_info = {
3517 			 .alg = CIPHER_ALG_3DES,
3518 			 .mode = CIPHER_MODE_CBC,
3519 			 },
3520 	 .auth_info = {
3521 		       .alg = HASH_ALG_SHA384,
3522 		       .mode = HASH_MODE_HMAC,
3523 		       },
3524 	 .auth_first = 0,
3525 	 },
3526 	{
3527 	 .type = CRYPTO_ALG_TYPE_AEAD,
3528 	 .alg.aead = {
3529 		 .base = {
3530 			.cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
3531 			.cra_driver_name = "authenc-hmac-sha512-cbc-des3-iproc",
3532 			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3533 			.cra_flags = CRYPTO_ALG_NEED_FALLBACK |
3534 				     CRYPTO_ALG_ASYNC |
3535 				     CRYPTO_ALG_ALLOCATES_MEMORY
3536 		 },
3537 		 .setkey = aead_authenc_setkey,
3538 		 .ivsize = DES3_EDE_BLOCK_SIZE,
3539 		 .maxauthsize = SHA512_DIGEST_SIZE,
3540 	 },
3541 	 .cipher_info = {
3542 			 .alg = CIPHER_ALG_3DES,
3543 			 .mode = CIPHER_MODE_CBC,
3544 			 },
3545 	 .auth_info = {
3546 		       .alg = HASH_ALG_SHA512,
3547 		       .mode = HASH_MODE_HMAC,
3548 		       },
3549 	 .auth_first = 0,
3550 	 },
3551 
3552 /* SKCIPHER algorithms. */
3553 	{
3554 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3555 	 .alg.skcipher = {
3556 			.base.cra_name = "ofb(des)",
3557 			.base.cra_driver_name = "ofb-des-iproc",
3558 			.base.cra_blocksize = DES_BLOCK_SIZE,
3559 			.min_keysize = DES_KEY_SIZE,
3560 			.max_keysize = DES_KEY_SIZE,
3561 			.ivsize = DES_BLOCK_SIZE,
3562 			},
3563 	 .cipher_info = {
3564 			 .alg = CIPHER_ALG_DES,
3565 			 .mode = CIPHER_MODE_OFB,
3566 			 },
3567 	 .auth_info = {
3568 		       .alg = HASH_ALG_NONE,
3569 		       .mode = HASH_MODE_NONE,
3570 		       },
3571 	 },
3572 	{
3573 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3574 	 .alg.skcipher = {
3575 			.base.cra_name = "cbc(des)",
3576 			.base.cra_driver_name = "cbc-des-iproc",
3577 			.base.cra_blocksize = DES_BLOCK_SIZE,
3578 			.min_keysize = DES_KEY_SIZE,
3579 			.max_keysize = DES_KEY_SIZE,
3580 			.ivsize = DES_BLOCK_SIZE,
3581 			},
3582 	 .cipher_info = {
3583 			 .alg = CIPHER_ALG_DES,
3584 			 .mode = CIPHER_MODE_CBC,
3585 			 },
3586 	 .auth_info = {
3587 		       .alg = HASH_ALG_NONE,
3588 		       .mode = HASH_MODE_NONE,
3589 		       },
3590 	 },
3591 	{
3592 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3593 	 .alg.skcipher = {
3594 			.base.cra_name = "ecb(des)",
3595 			.base.cra_driver_name = "ecb-des-iproc",
3596 			.base.cra_blocksize = DES_BLOCK_SIZE,
3597 			.min_keysize = DES_KEY_SIZE,
3598 			.max_keysize = DES_KEY_SIZE,
3599 			.ivsize = 0,
3600 			},
3601 	 .cipher_info = {
3602 			 .alg = CIPHER_ALG_DES,
3603 			 .mode = CIPHER_MODE_ECB,
3604 			 },
3605 	 .auth_info = {
3606 		       .alg = HASH_ALG_NONE,
3607 		       .mode = HASH_MODE_NONE,
3608 		       },
3609 	 },
3610 	{
3611 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3612 	 .alg.skcipher = {
3613 			.base.cra_name = "ofb(des3_ede)",
3614 			.base.cra_driver_name = "ofb-des3-iproc",
3615 			.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3616 			.min_keysize = DES3_EDE_KEY_SIZE,
3617 			.max_keysize = DES3_EDE_KEY_SIZE,
3618 			.ivsize = DES3_EDE_BLOCK_SIZE,
3619 			},
3620 	 .cipher_info = {
3621 			 .alg = CIPHER_ALG_3DES,
3622 			 .mode = CIPHER_MODE_OFB,
3623 			 },
3624 	 .auth_info = {
3625 		       .alg = HASH_ALG_NONE,
3626 		       .mode = HASH_MODE_NONE,
3627 		       },
3628 	 },
3629 	{
3630 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3631 	 .alg.skcipher = {
3632 			.base.cra_name = "cbc(des3_ede)",
3633 			.base.cra_driver_name = "cbc-des3-iproc",
3634 			.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3635 			.min_keysize = DES3_EDE_KEY_SIZE,
3636 			.max_keysize = DES3_EDE_KEY_SIZE,
3637 			.ivsize = DES3_EDE_BLOCK_SIZE,
3638 			},
3639 	 .cipher_info = {
3640 			 .alg = CIPHER_ALG_3DES,
3641 			 .mode = CIPHER_MODE_CBC,
3642 			 },
3643 	 .auth_info = {
3644 		       .alg = HASH_ALG_NONE,
3645 		       .mode = HASH_MODE_NONE,
3646 		       },
3647 	 },
3648 	{
3649 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3650 	 .alg.skcipher = {
3651 			.base.cra_name = "ecb(des3_ede)",
3652 			.base.cra_driver_name = "ecb-des3-iproc",
3653 			.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
3654 			.min_keysize = DES3_EDE_KEY_SIZE,
3655 			.max_keysize = DES3_EDE_KEY_SIZE,
3656 			.ivsize = 0,
3657 			},
3658 	 .cipher_info = {
3659 			 .alg = CIPHER_ALG_3DES,
3660 			 .mode = CIPHER_MODE_ECB,
3661 			 },
3662 	 .auth_info = {
3663 		       .alg = HASH_ALG_NONE,
3664 		       .mode = HASH_MODE_NONE,
3665 		       },
3666 	 },
3667 	{
3668 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3669 	 .alg.skcipher = {
3670 			.base.cra_name = "ofb(aes)",
3671 			.base.cra_driver_name = "ofb-aes-iproc",
3672 			.base.cra_blocksize = AES_BLOCK_SIZE,
3673 			.min_keysize = AES_MIN_KEY_SIZE,
3674 			.max_keysize = AES_MAX_KEY_SIZE,
3675 			.ivsize = AES_BLOCK_SIZE,
3676 			},
3677 	 .cipher_info = {
3678 			 .alg = CIPHER_ALG_AES,
3679 			 .mode = CIPHER_MODE_OFB,
3680 			 },
3681 	 .auth_info = {
3682 		       .alg = HASH_ALG_NONE,
3683 		       .mode = HASH_MODE_NONE,
3684 		       },
3685 	 },
3686 	{
3687 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3688 	 .alg.skcipher = {
3689 			.base.cra_name = "cbc(aes)",
3690 			.base.cra_driver_name = "cbc-aes-iproc",
3691 			.base.cra_blocksize = AES_BLOCK_SIZE,
3692 			.min_keysize = AES_MIN_KEY_SIZE,
3693 			.max_keysize = AES_MAX_KEY_SIZE,
3694 			.ivsize = AES_BLOCK_SIZE,
3695 			},
3696 	 .cipher_info = {
3697 			 .alg = CIPHER_ALG_AES,
3698 			 .mode = CIPHER_MODE_CBC,
3699 			 },
3700 	 .auth_info = {
3701 		       .alg = HASH_ALG_NONE,
3702 		       .mode = HASH_MODE_NONE,
3703 		       },
3704 	 },
3705 	{
3706 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3707 	 .alg.skcipher = {
3708 			.base.cra_name = "ecb(aes)",
3709 			.base.cra_driver_name = "ecb-aes-iproc",
3710 			.base.cra_blocksize = AES_BLOCK_SIZE,
3711 			.min_keysize = AES_MIN_KEY_SIZE,
3712 			.max_keysize = AES_MAX_KEY_SIZE,
3713 			.ivsize = 0,
3714 			},
3715 	 .cipher_info = {
3716 			 .alg = CIPHER_ALG_AES,
3717 			 .mode = CIPHER_MODE_ECB,
3718 			 },
3719 	 .auth_info = {
3720 		       .alg = HASH_ALG_NONE,
3721 		       .mode = HASH_MODE_NONE,
3722 		       },
3723 	 },
3724 	{
3725 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3726 	 .alg.skcipher = {
3727 			.base.cra_name = "ctr(aes)",
3728 			.base.cra_driver_name = "ctr-aes-iproc",
3729 			.base.cra_blocksize = AES_BLOCK_SIZE,
3730 			.min_keysize = AES_MIN_KEY_SIZE,
3731 			.max_keysize = AES_MAX_KEY_SIZE,
3732 			.ivsize = AES_BLOCK_SIZE,
3733 			},
3734 	 .cipher_info = {
3735 			 .alg = CIPHER_ALG_AES,
3736 			 .mode = CIPHER_MODE_CTR,
3737 			 },
3738 	 .auth_info = {
3739 		       .alg = HASH_ALG_NONE,
3740 		       .mode = HASH_MODE_NONE,
3741 		       },
3742 	 },
3743 {
3744 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,
3745 	 .alg.skcipher = {
3746 			.base.cra_name = "xts(aes)",
3747 			.base.cra_driver_name = "xts-aes-iproc",
3748 			.base.cra_blocksize = AES_BLOCK_SIZE,
3749 			.min_keysize = 2 * AES_MIN_KEY_SIZE,
3750 			.max_keysize = 2 * AES_MAX_KEY_SIZE,
3751 			.ivsize = AES_BLOCK_SIZE,
3752 			},
3753 	 .cipher_info = {
3754 			 .alg = CIPHER_ALG_AES,
3755 			 .mode = CIPHER_MODE_XTS,
3756 			 },
3757 	 .auth_info = {
3758 		       .alg = HASH_ALG_NONE,
3759 		       .mode = HASH_MODE_NONE,
3760 		       },
3761 	 },
3762 
3763 /* AHASH algorithms. */
3764 	{
3765 	 .type = CRYPTO_ALG_TYPE_AHASH,
3766 	 .alg.hash = {
3767 		      .halg.digestsize = MD5_DIGEST_SIZE,
3768 		      .halg.base = {
3769 				    .cra_name = "md5",
3770 				    .cra_driver_name = "md5-iproc",
3771 				    .cra_blocksize = MD5_BLOCK_WORDS * 4,
3772 				    .cra_flags = CRYPTO_ALG_ASYNC |
3773 						 CRYPTO_ALG_ALLOCATES_MEMORY,
3774 				}
3775 		      },
3776 	 .cipher_info = {
3777 			 .alg = CIPHER_ALG_NONE,
3778 			 .mode = CIPHER_MODE_NONE,
3779 			 },
3780 	 .auth_info = {
3781 		       .alg = HASH_ALG_MD5,
3782 		       .mode = HASH_MODE_HASH,
3783 		       },
3784 	 },
3785 	{
3786 	 .type = CRYPTO_ALG_TYPE_AHASH,
3787 	 .alg.hash = {
3788 		      .halg.digestsize = MD5_DIGEST_SIZE,
3789 		      .halg.base = {
3790 				    .cra_name = "hmac(md5)",
3791 				    .cra_driver_name = "hmac-md5-iproc",
3792 				    .cra_blocksize = MD5_BLOCK_WORDS * 4,
3793 				}
3794 		      },
3795 	 .cipher_info = {
3796 			 .alg = CIPHER_ALG_NONE,
3797 			 .mode = CIPHER_MODE_NONE,
3798 			 },
3799 	 .auth_info = {
3800 		       .alg = HASH_ALG_MD5,
3801 		       .mode = HASH_MODE_HMAC,
3802 		       },
3803 	 },
3804 	{.type = CRYPTO_ALG_TYPE_AHASH,
3805 	 .alg.hash = {
3806 		      .halg.digestsize = SHA1_DIGEST_SIZE,
3807 		      .halg.base = {
3808 				    .cra_name = "sha1",
3809 				    .cra_driver_name = "sha1-iproc",
3810 				    .cra_blocksize = SHA1_BLOCK_SIZE,
3811 				}
3812 		      },
3813 	 .cipher_info = {
3814 			 .alg = CIPHER_ALG_NONE,
3815 			 .mode = CIPHER_MODE_NONE,
3816 			 },
3817 	 .auth_info = {
3818 		       .alg = HASH_ALG_SHA1,
3819 		       .mode = HASH_MODE_HASH,
3820 		       },
3821 	 },
3822 	{.type = CRYPTO_ALG_TYPE_AHASH,
3823 	 .alg.hash = {
3824 		      .halg.digestsize = SHA1_DIGEST_SIZE,
3825 		      .halg.base = {
3826 				    .cra_name = "hmac(sha1)",
3827 				    .cra_driver_name = "hmac-sha1-iproc",
3828 				    .cra_blocksize = SHA1_BLOCK_SIZE,
3829 				}
3830 		      },
3831 	 .cipher_info = {
3832 			 .alg = CIPHER_ALG_NONE,
3833 			 .mode = CIPHER_MODE_NONE,
3834 			 },
3835 	 .auth_info = {
3836 		       .alg = HASH_ALG_SHA1,
3837 		       .mode = HASH_MODE_HMAC,
3838 		       },
3839 	 },
3840 	{.type = CRYPTO_ALG_TYPE_AHASH,
3841 	 .alg.hash = {
3842 			.halg.digestsize = SHA224_DIGEST_SIZE,
3843 			.halg.base = {
3844 				    .cra_name = "sha224",
3845 				    .cra_driver_name = "sha224-iproc",
3846 				    .cra_blocksize = SHA224_BLOCK_SIZE,
3847 			}
3848 		      },
3849 	 .cipher_info = {
3850 			 .alg = CIPHER_ALG_NONE,
3851 			 .mode = CIPHER_MODE_NONE,
3852 			 },
3853 	 .auth_info = {
3854 		       .alg = HASH_ALG_SHA224,
3855 		       .mode = HASH_MODE_HASH,
3856 		       },
3857 	 },
3858 	{.type = CRYPTO_ALG_TYPE_AHASH,
3859 	 .alg.hash = {
3860 		      .halg.digestsize = SHA224_DIGEST_SIZE,
3861 		      .halg.base = {
3862 				    .cra_name = "hmac(sha224)",
3863 				    .cra_driver_name = "hmac-sha224-iproc",
3864 				    .cra_blocksize = SHA224_BLOCK_SIZE,
3865 				}
3866 		      },
3867 	 .cipher_info = {
3868 			 .alg = CIPHER_ALG_NONE,
3869 			 .mode = CIPHER_MODE_NONE,
3870 			 },
3871 	 .auth_info = {
3872 		       .alg = HASH_ALG_SHA224,
3873 		       .mode = HASH_MODE_HMAC,
3874 		       },
3875 	 },
3876 	{.type = CRYPTO_ALG_TYPE_AHASH,
3877 	 .alg.hash = {
3878 		      .halg.digestsize = SHA256_DIGEST_SIZE,
3879 		      .halg.base = {
3880 				    .cra_name = "sha256",
3881 				    .cra_driver_name = "sha256-iproc",
3882 				    .cra_blocksize = SHA256_BLOCK_SIZE,
3883 				}
3884 		      },
3885 	 .cipher_info = {
3886 			 .alg = CIPHER_ALG_NONE,
3887 			 .mode = CIPHER_MODE_NONE,
3888 			 },
3889 	 .auth_info = {
3890 		       .alg = HASH_ALG_SHA256,
3891 		       .mode = HASH_MODE_HASH,
3892 		       },
3893 	 },
3894 	{.type = CRYPTO_ALG_TYPE_AHASH,
3895 	 .alg.hash = {
3896 		      .halg.digestsize = SHA256_DIGEST_SIZE,
3897 		      .halg.base = {
3898 				    .cra_name = "hmac(sha256)",
3899 				    .cra_driver_name = "hmac-sha256-iproc",
3900 				    .cra_blocksize = SHA256_BLOCK_SIZE,
3901 				}
3902 		      },
3903 	 .cipher_info = {
3904 			 .alg = CIPHER_ALG_NONE,
3905 			 .mode = CIPHER_MODE_NONE,
3906 			 },
3907 	 .auth_info = {
3908 		       .alg = HASH_ALG_SHA256,
3909 		       .mode = HASH_MODE_HMAC,
3910 		       },
3911 	 },
3912 	{
3913 	.type = CRYPTO_ALG_TYPE_AHASH,
3914 	 .alg.hash = {
3915 		      .halg.digestsize = SHA384_DIGEST_SIZE,
3916 		      .halg.base = {
3917 				    .cra_name = "sha384",
3918 				    .cra_driver_name = "sha384-iproc",
3919 				    .cra_blocksize = SHA384_BLOCK_SIZE,
3920 				}
3921 		      },
3922 	 .cipher_info = {
3923 			 .alg = CIPHER_ALG_NONE,
3924 			 .mode = CIPHER_MODE_NONE,
3925 			 },
3926 	 .auth_info = {
3927 		       .alg = HASH_ALG_SHA384,
3928 		       .mode = HASH_MODE_HASH,
3929 		       },
3930 	 },
3931 	{
3932 	 .type = CRYPTO_ALG_TYPE_AHASH,
3933 	 .alg.hash = {
3934 		      .halg.digestsize = SHA384_DIGEST_SIZE,
3935 		      .halg.base = {
3936 				    .cra_name = "hmac(sha384)",
3937 				    .cra_driver_name = "hmac-sha384-iproc",
3938 				    .cra_blocksize = SHA384_BLOCK_SIZE,
3939 				}
3940 		      },
3941 	 .cipher_info = {
3942 			 .alg = CIPHER_ALG_NONE,
3943 			 .mode = CIPHER_MODE_NONE,
3944 			 },
3945 	 .auth_info = {
3946 		       .alg = HASH_ALG_SHA384,
3947 		       .mode = HASH_MODE_HMAC,
3948 		       },
3949 	 },
3950 	{
3951 	 .type = CRYPTO_ALG_TYPE_AHASH,
3952 	 .alg.hash = {
3953 		      .halg.digestsize = SHA512_DIGEST_SIZE,
3954 		      .halg.base = {
3955 				    .cra_name = "sha512",
3956 				    .cra_driver_name = "sha512-iproc",
3957 				    .cra_blocksize = SHA512_BLOCK_SIZE,
3958 				}
3959 		      },
3960 	 .cipher_info = {
3961 			 .alg = CIPHER_ALG_NONE,
3962 			 .mode = CIPHER_MODE_NONE,
3963 			 },
3964 	 .auth_info = {
3965 		       .alg = HASH_ALG_SHA512,
3966 		       .mode = HASH_MODE_HASH,
3967 		       },
3968 	 },
3969 	{
3970 	 .type = CRYPTO_ALG_TYPE_AHASH,
3971 	 .alg.hash = {
3972 		      .halg.digestsize = SHA512_DIGEST_SIZE,
3973 		      .halg.base = {
3974 				    .cra_name = "hmac(sha512)",
3975 				    .cra_driver_name = "hmac-sha512-iproc",
3976 				    .cra_blocksize = SHA512_BLOCK_SIZE,
3977 				}
3978 		      },
3979 	 .cipher_info = {
3980 			 .alg = CIPHER_ALG_NONE,
3981 			 .mode = CIPHER_MODE_NONE,
3982 			 },
3983 	 .auth_info = {
3984 		       .alg = HASH_ALG_SHA512,
3985 		       .mode = HASH_MODE_HMAC,
3986 		       },
3987 	 },
3988 	{
3989 	 .type = CRYPTO_ALG_TYPE_AHASH,
3990 	 .alg.hash = {
3991 		      .halg.digestsize = SHA3_224_DIGEST_SIZE,
3992 		      .halg.base = {
3993 				    .cra_name = "sha3-224",
3994 				    .cra_driver_name = "sha3-224-iproc",
3995 				    .cra_blocksize = SHA3_224_BLOCK_SIZE,
3996 				}
3997 		      },
3998 	 .cipher_info = {
3999 			 .alg = CIPHER_ALG_NONE,
4000 			 .mode = CIPHER_MODE_NONE,
4001 			 },
4002 	 .auth_info = {
4003 		       .alg = HASH_ALG_SHA3_224,
4004 		       .mode = HASH_MODE_HASH,
4005 		       },
4006 	 },
4007 	{
4008 	 .type = CRYPTO_ALG_TYPE_AHASH,
4009 	 .alg.hash = {
4010 		      .halg.digestsize = SHA3_224_DIGEST_SIZE,
4011 		      .halg.base = {
4012 				    .cra_name = "hmac(sha3-224)",
4013 				    .cra_driver_name = "hmac-sha3-224-iproc",
4014 				    .cra_blocksize = SHA3_224_BLOCK_SIZE,
4015 				}
4016 		      },
4017 	 .cipher_info = {
4018 			 .alg = CIPHER_ALG_NONE,
4019 			 .mode = CIPHER_MODE_NONE,
4020 			 },
4021 	 .auth_info = {
4022 		       .alg = HASH_ALG_SHA3_224,
4023 		       .mode = HASH_MODE_HMAC
4024 		       },
4025 	 },
4026 	{
4027 	 .type = CRYPTO_ALG_TYPE_AHASH,
4028 	 .alg.hash = {
4029 		      .halg.digestsize = SHA3_256_DIGEST_SIZE,
4030 		      .halg.base = {
4031 				    .cra_name = "sha3-256",
4032 				    .cra_driver_name = "sha3-256-iproc",
4033 				    .cra_blocksize = SHA3_256_BLOCK_SIZE,
4034 				}
4035 		      },
4036 	 .cipher_info = {
4037 			 .alg = CIPHER_ALG_NONE,
4038 			 .mode = CIPHER_MODE_NONE,
4039 			 },
4040 	 .auth_info = {
4041 		       .alg = HASH_ALG_SHA3_256,
4042 		       .mode = HASH_MODE_HASH,
4043 		       },
4044 	 },
4045 	{
4046 	 .type = CRYPTO_ALG_TYPE_AHASH,
4047 	 .alg.hash = {
4048 		      .halg.digestsize = SHA3_256_DIGEST_SIZE,
4049 		      .halg.base = {
4050 				    .cra_name = "hmac(sha3-256)",
4051 				    .cra_driver_name = "hmac-sha3-256-iproc",
4052 				    .cra_blocksize = SHA3_256_BLOCK_SIZE,
4053 				}
4054 		      },
4055 	 .cipher_info = {
4056 			 .alg = CIPHER_ALG_NONE,
4057 			 .mode = CIPHER_MODE_NONE,
4058 			 },
4059 	 .auth_info = {
4060 		       .alg = HASH_ALG_SHA3_256,
4061 		       .mode = HASH_MODE_HMAC,
4062 		       },
4063 	 },
4064 	{
4065 	 .type = CRYPTO_ALG_TYPE_AHASH,
4066 	 .alg.hash = {
4067 		      .halg.digestsize = SHA3_384_DIGEST_SIZE,
4068 		      .halg.base = {
4069 				    .cra_name = "sha3-384",
4070 				    .cra_driver_name = "sha3-384-iproc",
4071 				    .cra_blocksize = SHA3_224_BLOCK_SIZE,
4072 				}
4073 		      },
4074 	 .cipher_info = {
4075 			 .alg = CIPHER_ALG_NONE,
4076 			 .mode = CIPHER_MODE_NONE,
4077 			 },
4078 	 .auth_info = {
4079 		       .alg = HASH_ALG_SHA3_384,
4080 		       .mode = HASH_MODE_HASH,
4081 		       },
4082 	 },
4083 	{
4084 	 .type = CRYPTO_ALG_TYPE_AHASH,
4085 	 .alg.hash = {
4086 		      .halg.digestsize = SHA3_384_DIGEST_SIZE,
4087 		      .halg.base = {
4088 				    .cra_name = "hmac(sha3-384)",
4089 				    .cra_driver_name = "hmac-sha3-384-iproc",
4090 				    .cra_blocksize = SHA3_384_BLOCK_SIZE,
4091 				}
4092 		      },
4093 	 .cipher_info = {
4094 			 .alg = CIPHER_ALG_NONE,
4095 			 .mode = CIPHER_MODE_NONE,
4096 			 },
4097 	 .auth_info = {
4098 		       .alg = HASH_ALG_SHA3_384,
4099 		       .mode = HASH_MODE_HMAC,
4100 		       },
4101 	 },
4102 	{
4103 	 .type = CRYPTO_ALG_TYPE_AHASH,
4104 	 .alg.hash = {
4105 		      .halg.digestsize = SHA3_512_DIGEST_SIZE,
4106 		      .halg.base = {
4107 				    .cra_name = "sha3-512",
4108 				    .cra_driver_name = "sha3-512-iproc",
4109 				    .cra_blocksize = SHA3_512_BLOCK_SIZE,
4110 				}
4111 		      },
4112 	 .cipher_info = {
4113 			 .alg = CIPHER_ALG_NONE,
4114 			 .mode = CIPHER_MODE_NONE,
4115 			 },
4116 	 .auth_info = {
4117 		       .alg = HASH_ALG_SHA3_512,
4118 		       .mode = HASH_MODE_HASH,
4119 		       },
4120 	 },
4121 	{
4122 	 .type = CRYPTO_ALG_TYPE_AHASH,
4123 	 .alg.hash = {
4124 		      .halg.digestsize = SHA3_512_DIGEST_SIZE,
4125 		      .halg.base = {
4126 				    .cra_name = "hmac(sha3-512)",
4127 				    .cra_driver_name = "hmac-sha3-512-iproc",
4128 				    .cra_blocksize = SHA3_512_BLOCK_SIZE,
4129 				}
4130 		      },
4131 	 .cipher_info = {
4132 			 .alg = CIPHER_ALG_NONE,
4133 			 .mode = CIPHER_MODE_NONE,
4134 			 },
4135 	 .auth_info = {
4136 		       .alg = HASH_ALG_SHA3_512,
4137 		       .mode = HASH_MODE_HMAC,
4138 		       },
4139 	 },
4140 	{
4141 	 .type = CRYPTO_ALG_TYPE_AHASH,
4142 	 .alg.hash = {
4143 		      .halg.digestsize = AES_BLOCK_SIZE,
4144 		      .halg.base = {
4145 				    .cra_name = "xcbc(aes)",
4146 				    .cra_driver_name = "xcbc-aes-iproc",
4147 				    .cra_blocksize = AES_BLOCK_SIZE,
4148 				}
4149 		      },
4150 	 .cipher_info = {
4151 			 .alg = CIPHER_ALG_NONE,
4152 			 .mode = CIPHER_MODE_NONE,
4153 			 },
4154 	 .auth_info = {
4155 		       .alg = HASH_ALG_AES,
4156 		       .mode = HASH_MODE_XCBC,
4157 		       },
4158 	 },
4159 	{
4160 	 .type = CRYPTO_ALG_TYPE_AHASH,
4161 	 .alg.hash = {
4162 		      .halg.digestsize = AES_BLOCK_SIZE,
4163 		      .halg.base = {
4164 				    .cra_name = "cmac(aes)",
4165 				    .cra_driver_name = "cmac-aes-iproc",
4166 				    .cra_blocksize = AES_BLOCK_SIZE,
4167 				}
4168 		      },
4169 	 .cipher_info = {
4170 			 .alg = CIPHER_ALG_NONE,
4171 			 .mode = CIPHER_MODE_NONE,
4172 			 },
4173 	 .auth_info = {
4174 		       .alg = HASH_ALG_AES,
4175 		       .mode = HASH_MODE_CMAC,
4176 		       },
4177 	 },
4178 };
4179 
4180 static int generic_cra_init(struct crypto_tfm *tfm,
4181 			    struct iproc_alg_s *cipher_alg)
4182 {
4183 	struct spu_hw *spu = &iproc_priv.spu;
4184 	struct iproc_ctx_s *ctx = crypto_tfm_ctx(tfm);
4185 	unsigned int blocksize = crypto_tfm_alg_blocksize(tfm);
4186 
4187 	flow_log("%s()\n", __func__);
4188 
4189 	ctx->alg = cipher_alg;
4190 	ctx->cipher = cipher_alg->cipher_info;
4191 	ctx->auth = cipher_alg->auth_info;
4192 	ctx->auth_first = cipher_alg->auth_first;
4193 	ctx->max_payload = spu->spu_ctx_max_payload(ctx->cipher.alg,
4194 						    ctx->cipher.mode,
4195 						    blocksize);
4196 	ctx->fallback_cipher = NULL;
4197 
4198 	ctx->enckeylen = 0;
4199 	ctx->authkeylen = 0;
4200 
4201 	atomic_inc(&iproc_priv.stream_count);
4202 	atomic_inc(&iproc_priv.session_count);
4203 
4204 	return 0;
4205 }
4206 
4207 static int skcipher_init_tfm(struct crypto_skcipher *skcipher)
4208 {
4209 	struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
4210 	struct skcipher_alg *alg = crypto_skcipher_alg(skcipher);
4211 	struct iproc_alg_s *cipher_alg;
4212 
4213 	flow_log("%s()\n", __func__);
4214 
4215 	crypto_skcipher_set_reqsize(skcipher, sizeof(struct iproc_reqctx_s));
4216 
4217 	cipher_alg = container_of(alg, struct iproc_alg_s, alg.skcipher);
4218 	return generic_cra_init(tfm, cipher_alg);
4219 }
4220 
4221 static int ahash_cra_init(struct crypto_tfm *tfm)
4222 {
4223 	int err;
4224 	struct crypto_alg *alg = tfm->__crt_alg;
4225 	struct iproc_alg_s *cipher_alg;
4226 
4227 	cipher_alg = container_of(__crypto_ahash_alg(alg), struct iproc_alg_s,
4228 				  alg.hash);
4229 
4230 	err = generic_cra_init(tfm, cipher_alg);
4231 	flow_log("%s()\n", __func__);
4232 
4233 	/*
4234 	 * export state size has to be < 512 bytes. So don't include msg bufs
4235 	 * in state size.
4236 	 */
4237 	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
4238 				 sizeof(struct iproc_reqctx_s));
4239 
4240 	return err;
4241 }
4242 
4243 static int aead_cra_init(struct crypto_aead *aead)
4244 {
4245 	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
4246 	struct iproc_ctx_s *ctx = crypto_tfm_ctx(tfm);
4247 	struct crypto_alg *alg = tfm->__crt_alg;
4248 	struct aead_alg *aalg = container_of(alg, struct aead_alg, base);
4249 	struct iproc_alg_s *cipher_alg = container_of(aalg, struct iproc_alg_s,
4250 						      alg.aead);
4251 
4252 	int err = generic_cra_init(tfm, cipher_alg);
4253 
4254 	flow_log("%s()\n", __func__);
4255 
4256 	crypto_aead_set_reqsize(aead, sizeof(struct iproc_reqctx_s));
4257 	ctx->is_esp = false;
4258 	ctx->salt_len = 0;
4259 	ctx->salt_offset = 0;
4260 
4261 	/* random first IV */
4262 	get_random_bytes(ctx->iv, MAX_IV_SIZE);
4263 	flow_dump("  iv: ", ctx->iv, MAX_IV_SIZE);
4264 
4265 	if (!err) {
4266 		if (alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
4267 			flow_log("%s() creating fallback cipher\n", __func__);
4268 
4269 			ctx->fallback_cipher =
4270 			    crypto_alloc_aead(alg->cra_name, 0,
4271 					      CRYPTO_ALG_ASYNC |
4272 					      CRYPTO_ALG_NEED_FALLBACK);
4273 			if (IS_ERR(ctx->fallback_cipher)) {
4274 				pr_err("%s() Error: failed to allocate fallback for %s\n",
4275 				       __func__, alg->cra_name);
4276 				return PTR_ERR(ctx->fallback_cipher);
4277 			}
4278 		}
4279 	}
4280 
4281 	return err;
4282 }
4283 
4284 static void generic_cra_exit(struct crypto_tfm *tfm)
4285 {
4286 	atomic_dec(&iproc_priv.session_count);
4287 }
4288 
4289 static void skcipher_exit_tfm(struct crypto_skcipher *tfm)
4290 {
4291 	generic_cra_exit(crypto_skcipher_tfm(tfm));
4292 }
4293 
4294 static void aead_cra_exit(struct crypto_aead *aead)
4295 {
4296 	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
4297 	struct iproc_ctx_s *ctx = crypto_tfm_ctx(tfm);
4298 
4299 	generic_cra_exit(tfm);
4300 
4301 	if (ctx->fallback_cipher) {
4302 		crypto_free_aead(ctx->fallback_cipher);
4303 		ctx->fallback_cipher = NULL;
4304 	}
4305 }
4306 
4307 /**
4308  * spu_functions_register() - Specify hardware-specific SPU functions based on
4309  * SPU type read from device tree.
4310  * @dev:	device structure
4311  * @spu_type:	SPU hardware generation
4312  * @spu_subtype: SPU hardware version
4313  */
4314 static void spu_functions_register(struct device *dev,
4315 				   enum spu_spu_type spu_type,
4316 				   enum spu_spu_subtype spu_subtype)
4317 {
4318 	struct spu_hw *spu = &iproc_priv.spu;
4319 
4320 	if (spu_type == SPU_TYPE_SPUM) {
4321 		dev_dbg(dev, "Registering SPUM functions");
4322 		spu->spu_dump_msg_hdr = spum_dump_msg_hdr;
4323 		spu->spu_payload_length = spum_payload_length;
4324 		spu->spu_response_hdr_len = spum_response_hdr_len;
4325 		spu->spu_hash_pad_len = spum_hash_pad_len;
4326 		spu->spu_gcm_ccm_pad_len = spum_gcm_ccm_pad_len;
4327 		spu->spu_assoc_resp_len = spum_assoc_resp_len;
4328 		spu->spu_aead_ivlen = spum_aead_ivlen;
4329 		spu->spu_hash_type = spum_hash_type;
4330 		spu->spu_digest_size = spum_digest_size;
4331 		spu->spu_create_request = spum_create_request;
4332 		spu->spu_cipher_req_init = spum_cipher_req_init;
4333 		spu->spu_cipher_req_finish = spum_cipher_req_finish;
4334 		spu->spu_request_pad = spum_request_pad;
4335 		spu->spu_tx_status_len = spum_tx_status_len;
4336 		spu->spu_rx_status_len = spum_rx_status_len;
4337 		spu->spu_status_process = spum_status_process;
4338 		spu->spu_xts_tweak_in_payload = spum_xts_tweak_in_payload;
4339 		spu->spu_ccm_update_iv = spum_ccm_update_iv;
4340 		spu->spu_wordalign_padlen = spum_wordalign_padlen;
4341 		if (spu_subtype == SPU_SUBTYPE_SPUM_NS2)
4342 			spu->spu_ctx_max_payload = spum_ns2_ctx_max_payload;
4343 		else
4344 			spu->spu_ctx_max_payload = spum_nsp_ctx_max_payload;
4345 	} else {
4346 		dev_dbg(dev, "Registering SPU2 functions");
4347 		spu->spu_dump_msg_hdr = spu2_dump_msg_hdr;
4348 		spu->spu_ctx_max_payload = spu2_ctx_max_payload;
4349 		spu->spu_payload_length = spu2_payload_length;
4350 		spu->spu_response_hdr_len = spu2_response_hdr_len;
4351 		spu->spu_hash_pad_len = spu2_hash_pad_len;
4352 		spu->spu_gcm_ccm_pad_len = spu2_gcm_ccm_pad_len;
4353 		spu->spu_assoc_resp_len = spu2_assoc_resp_len;
4354 		spu->spu_aead_ivlen = spu2_aead_ivlen;
4355 		spu->spu_hash_type = spu2_hash_type;
4356 		spu->spu_digest_size = spu2_digest_size;
4357 		spu->spu_create_request = spu2_create_request;
4358 		spu->spu_cipher_req_init = spu2_cipher_req_init;
4359 		spu->spu_cipher_req_finish = spu2_cipher_req_finish;
4360 		spu->spu_request_pad = spu2_request_pad;
4361 		spu->spu_tx_status_len = spu2_tx_status_len;
4362 		spu->spu_rx_status_len = spu2_rx_status_len;
4363 		spu->spu_status_process = spu2_status_process;
4364 		spu->spu_xts_tweak_in_payload = spu2_xts_tweak_in_payload;
4365 		spu->spu_ccm_update_iv = spu2_ccm_update_iv;
4366 		spu->spu_wordalign_padlen = spu2_wordalign_padlen;
4367 	}
4368 }
4369 
4370 /**
4371  * spu_mb_init() - Initialize mailbox client. Request ownership of a mailbox
4372  * channel for the SPU being probed.
4373  * @dev:  SPU driver device structure
4374  *
4375  * Return: 0 if successful
4376  *	   < 0 otherwise
4377  */
4378 static int spu_mb_init(struct device *dev)
4379 {
4380 	struct mbox_client *mcl = &iproc_priv.mcl;
4381 	int err, i;
4382 
4383 	iproc_priv.mbox = devm_kcalloc(dev, iproc_priv.spu.num_chan,
4384 				  sizeof(struct mbox_chan *), GFP_KERNEL);
4385 	if (!iproc_priv.mbox)
4386 		return -ENOMEM;
4387 
4388 	mcl->dev = dev;
4389 	mcl->tx_block = false;
4390 	mcl->tx_tout = 0;
4391 	mcl->knows_txdone = true;
4392 	mcl->rx_callback = spu_rx_callback;
4393 	mcl->tx_done = NULL;
4394 
4395 	for (i = 0; i < iproc_priv.spu.num_chan; i++) {
4396 		iproc_priv.mbox[i] = mbox_request_channel(mcl, i);
4397 		if (IS_ERR(iproc_priv.mbox[i])) {
4398 			err = PTR_ERR(iproc_priv.mbox[i]);
4399 			dev_err(dev,
4400 				"Mbox channel %d request failed with err %d",
4401 				i, err);
4402 			iproc_priv.mbox[i] = NULL;
4403 			goto free_channels;
4404 		}
4405 	}
4406 
4407 	return 0;
4408 free_channels:
4409 	for (i = 0; i < iproc_priv.spu.num_chan; i++) {
4410 		if (iproc_priv.mbox[i])
4411 			mbox_free_channel(iproc_priv.mbox[i]);
4412 	}
4413 
4414 	return err;
4415 }
4416 
4417 static void spu_mb_release(struct platform_device *pdev)
4418 {
4419 	int i;
4420 
4421 	for (i = 0; i < iproc_priv.spu.num_chan; i++)
4422 		mbox_free_channel(iproc_priv.mbox[i]);
4423 }
4424 
4425 static void spu_counters_init(void)
4426 {
4427 	int i;
4428 	int j;
4429 
4430 	atomic_set(&iproc_priv.session_count, 0);
4431 	atomic_set(&iproc_priv.stream_count, 0);
4432 	atomic_set(&iproc_priv.next_chan, (int)iproc_priv.spu.num_chan);
4433 	atomic64_set(&iproc_priv.bytes_in, 0);
4434 	atomic64_set(&iproc_priv.bytes_out, 0);
4435 	for (i = 0; i < SPU_OP_NUM; i++) {
4436 		atomic_set(&iproc_priv.op_counts[i], 0);
4437 		atomic_set(&iproc_priv.setkey_cnt[i], 0);
4438 	}
4439 	for (i = 0; i < CIPHER_ALG_LAST; i++)
4440 		for (j = 0; j < CIPHER_MODE_LAST; j++)
4441 			atomic_set(&iproc_priv.cipher_cnt[i][j], 0);
4442 
4443 	for (i = 0; i < HASH_ALG_LAST; i++) {
4444 		atomic_set(&iproc_priv.hash_cnt[i], 0);
4445 		atomic_set(&iproc_priv.hmac_cnt[i], 0);
4446 	}
4447 	for (i = 0; i < AEAD_TYPE_LAST; i++)
4448 		atomic_set(&iproc_priv.aead_cnt[i], 0);
4449 
4450 	atomic_set(&iproc_priv.mb_no_spc, 0);
4451 	atomic_set(&iproc_priv.mb_send_fail, 0);
4452 	atomic_set(&iproc_priv.bad_icv, 0);
4453 }
4454 
4455 static int spu_register_skcipher(struct iproc_alg_s *driver_alg)
4456 {
4457 	struct skcipher_alg *crypto = &driver_alg->alg.skcipher;
4458 	int err;
4459 
4460 	crypto->base.cra_module = THIS_MODULE;
4461 	crypto->base.cra_priority = cipher_pri;
4462 	crypto->base.cra_alignmask = 0;
4463 	crypto->base.cra_ctxsize = sizeof(struct iproc_ctx_s);
4464 	crypto->base.cra_flags = CRYPTO_ALG_ASYNC |
4465 				 CRYPTO_ALG_ALLOCATES_MEMORY |
4466 				 CRYPTO_ALG_KERN_DRIVER_ONLY;
4467 
4468 	crypto->init = skcipher_init_tfm;
4469 	crypto->exit = skcipher_exit_tfm;
4470 	crypto->setkey = skcipher_setkey;
4471 	crypto->encrypt = skcipher_encrypt;
4472 	crypto->decrypt = skcipher_decrypt;
4473 
4474 	err = crypto_register_skcipher(crypto);
4475 	/* Mark alg as having been registered, if successful */
4476 	if (err == 0)
4477 		driver_alg->registered = true;
4478 	pr_debug("  registered skcipher %s\n", crypto->base.cra_driver_name);
4479 	return err;
4480 }
4481 
4482 static int spu_register_ahash(struct iproc_alg_s *driver_alg)
4483 {
4484 	struct spu_hw *spu = &iproc_priv.spu;
4485 	struct ahash_alg *hash = &driver_alg->alg.hash;
4486 	int err;
4487 
4488 	/* AES-XCBC is the only AES hash type currently supported on SPU-M */
4489 	if ((driver_alg->auth_info.alg == HASH_ALG_AES) &&
4490 	    (driver_alg->auth_info.mode != HASH_MODE_XCBC) &&
4491 	    (spu->spu_type == SPU_TYPE_SPUM))
4492 		return 0;
4493 
4494 	/* SHA3 algorithm variants are not registered for SPU-M or SPU2. */
4495 	if ((driver_alg->auth_info.alg >= HASH_ALG_SHA3_224) &&
4496 	    (spu->spu_subtype != SPU_SUBTYPE_SPU2_V2))
4497 		return 0;
4498 
4499 	hash->halg.base.cra_module = THIS_MODULE;
4500 	hash->halg.base.cra_priority = hash_pri;
4501 	hash->halg.base.cra_alignmask = 0;
4502 	hash->halg.base.cra_ctxsize = sizeof(struct iproc_ctx_s);
4503 	hash->halg.base.cra_init = ahash_cra_init;
4504 	hash->halg.base.cra_exit = generic_cra_exit;
4505 	hash->halg.base.cra_flags = CRYPTO_ALG_ASYNC |
4506 				    CRYPTO_ALG_ALLOCATES_MEMORY;
4507 	hash->halg.statesize = sizeof(struct spu_hash_export_s);
4508 
4509 	if (driver_alg->auth_info.mode != HASH_MODE_HMAC) {
4510 		hash->init = ahash_init;
4511 		hash->update = ahash_update;
4512 		hash->final = ahash_final;
4513 		hash->finup = ahash_finup;
4514 		hash->digest = ahash_digest;
4515 		if ((driver_alg->auth_info.alg == HASH_ALG_AES) &&
4516 		    ((driver_alg->auth_info.mode == HASH_MODE_XCBC) ||
4517 		    (driver_alg->auth_info.mode == HASH_MODE_CMAC))) {
4518 			hash->setkey = ahash_setkey;
4519 		}
4520 	} else {
4521 		hash->setkey = ahash_hmac_setkey;
4522 		hash->init = ahash_hmac_init;
4523 		hash->update = ahash_hmac_update;
4524 		hash->final = ahash_hmac_final;
4525 		hash->finup = ahash_hmac_finup;
4526 		hash->digest = ahash_hmac_digest;
4527 	}
4528 	hash->export = ahash_export;
4529 	hash->import = ahash_import;
4530 
4531 	err = crypto_register_ahash(hash);
4532 	/* Mark alg as having been registered, if successful */
4533 	if (err == 0)
4534 		driver_alg->registered = true;
4535 	pr_debug("  registered ahash %s\n",
4536 		 hash->halg.base.cra_driver_name);
4537 	return err;
4538 }
4539 
4540 static int spu_register_aead(struct iproc_alg_s *driver_alg)
4541 {
4542 	struct aead_alg *aead = &driver_alg->alg.aead;
4543 	int err;
4544 
4545 	aead->base.cra_module = THIS_MODULE;
4546 	aead->base.cra_priority = aead_pri;
4547 	aead->base.cra_alignmask = 0;
4548 	aead->base.cra_ctxsize = sizeof(struct iproc_ctx_s);
4549 
4550 	aead->base.cra_flags |= CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY;
4551 	/* setkey set in alg initialization */
4552 	aead->setauthsize = aead_setauthsize;
4553 	aead->encrypt = aead_encrypt;
4554 	aead->decrypt = aead_decrypt;
4555 	aead->init = aead_cra_init;
4556 	aead->exit = aead_cra_exit;
4557 
4558 	err = crypto_register_aead(aead);
4559 	/* Mark alg as having been registered, if successful */
4560 	if (err == 0)
4561 		driver_alg->registered = true;
4562 	pr_debug("  registered aead %s\n", aead->base.cra_driver_name);
4563 	return err;
4564 }
4565 
4566 /* register crypto algorithms the device supports */
4567 static int spu_algs_register(struct device *dev)
4568 {
4569 	int i, j;
4570 	int err;
4571 
4572 	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
4573 		switch (driver_algs[i].type) {
4574 		case CRYPTO_ALG_TYPE_SKCIPHER:
4575 			err = spu_register_skcipher(&driver_algs[i]);
4576 			break;
4577 		case CRYPTO_ALG_TYPE_AHASH:
4578 			err = spu_register_ahash(&driver_algs[i]);
4579 			break;
4580 		case CRYPTO_ALG_TYPE_AEAD:
4581 			err = spu_register_aead(&driver_algs[i]);
4582 			break;
4583 		default:
4584 			dev_err(dev,
4585 				"iproc-crypto: unknown alg type: %d",
4586 				driver_algs[i].type);
4587 			err = -EINVAL;
4588 		}
4589 
4590 		if (err) {
4591 			dev_err(dev, "alg registration failed with error %d\n",
4592 				err);
4593 			goto err_algs;
4594 		}
4595 	}
4596 
4597 	return 0;
4598 
4599 err_algs:
4600 	for (j = 0; j < i; j++) {
4601 		/* Skip any algorithm not registered */
4602 		if (!driver_algs[j].registered)
4603 			continue;
4604 		switch (driver_algs[j].type) {
4605 		case CRYPTO_ALG_TYPE_SKCIPHER:
4606 			crypto_unregister_skcipher(&driver_algs[j].alg.skcipher);
4607 			driver_algs[j].registered = false;
4608 			break;
4609 		case CRYPTO_ALG_TYPE_AHASH:
4610 			crypto_unregister_ahash(&driver_algs[j].alg.hash);
4611 			driver_algs[j].registered = false;
4612 			break;
4613 		case CRYPTO_ALG_TYPE_AEAD:
4614 			crypto_unregister_aead(&driver_algs[j].alg.aead);
4615 			driver_algs[j].registered = false;
4616 			break;
4617 		}
4618 	}
4619 	return err;
4620 }
4621 
4622 /* ==================== Kernel Platform API ==================== */
4623 
4624 static struct spu_type_subtype spum_ns2_types = {
4625 	SPU_TYPE_SPUM, SPU_SUBTYPE_SPUM_NS2
4626 };
4627 
4628 static struct spu_type_subtype spum_nsp_types = {
4629 	SPU_TYPE_SPUM, SPU_SUBTYPE_SPUM_NSP
4630 };
4631 
4632 static struct spu_type_subtype spu2_types = {
4633 	SPU_TYPE_SPU2, SPU_SUBTYPE_SPU2_V1
4634 };
4635 
4636 static struct spu_type_subtype spu2_v2_types = {
4637 	SPU_TYPE_SPU2, SPU_SUBTYPE_SPU2_V2
4638 };
4639 
4640 static const struct of_device_id bcm_spu_dt_ids[] = {
4641 	{
4642 		.compatible = "brcm,spum-crypto",
4643 		.data = &spum_ns2_types,
4644 	},
4645 	{
4646 		.compatible = "brcm,spum-nsp-crypto",
4647 		.data = &spum_nsp_types,
4648 	},
4649 	{
4650 		.compatible = "brcm,spu2-crypto",
4651 		.data = &spu2_types,
4652 	},
4653 	{
4654 		.compatible = "brcm,spu2-v2-crypto",
4655 		.data = &spu2_v2_types,
4656 	},
4657 	{ /* sentinel */ }
4658 };
4659 
4660 MODULE_DEVICE_TABLE(of, bcm_spu_dt_ids);
4661 
4662 static int spu_dt_read(struct platform_device *pdev)
4663 {
4664 	struct device *dev = &pdev->dev;
4665 	struct spu_hw *spu = &iproc_priv.spu;
4666 	struct resource *spu_ctrl_regs;
4667 	const struct spu_type_subtype *matched_spu_type;
4668 	struct device_node *dn = pdev->dev.of_node;
4669 	int err, i;
4670 
4671 	/* Count number of mailbox channels */
4672 	spu->num_chan = of_count_phandle_with_args(dn, "mboxes", "#mbox-cells");
4673 
4674 	matched_spu_type = of_device_get_match_data(dev);
4675 	if (!matched_spu_type) {
4676 		dev_err(dev, "Failed to match device\n");
4677 		return -ENODEV;
4678 	}
4679 
4680 	spu->spu_type = matched_spu_type->type;
4681 	spu->spu_subtype = matched_spu_type->subtype;
4682 
4683 	for (i = 0; (i < MAX_SPUS) && ((spu_ctrl_regs =
4684 		platform_get_resource(pdev, IORESOURCE_MEM, i)) != NULL); i++) {
4685 
4686 		spu->reg_vbase[i] = devm_ioremap_resource(dev, spu_ctrl_regs);
4687 		if (IS_ERR(spu->reg_vbase[i])) {
4688 			err = PTR_ERR(spu->reg_vbase[i]);
4689 			dev_err(dev, "Failed to map registers: %d\n",
4690 				err);
4691 			spu->reg_vbase[i] = NULL;
4692 			return err;
4693 		}
4694 	}
4695 	spu->num_spu = i;
4696 	dev_dbg(dev, "Device has %d SPUs", spu->num_spu);
4697 
4698 	return 0;
4699 }
4700 
4701 static int bcm_spu_probe(struct platform_device *pdev)
4702 {
4703 	struct device *dev = &pdev->dev;
4704 	struct spu_hw *spu = &iproc_priv.spu;
4705 	int err;
4706 
4707 	iproc_priv.pdev  = pdev;
4708 	platform_set_drvdata(iproc_priv.pdev,
4709 			     &iproc_priv);
4710 
4711 	err = spu_dt_read(pdev);
4712 	if (err < 0)
4713 		goto failure;
4714 
4715 	err = spu_mb_init(dev);
4716 	if (err < 0)
4717 		goto failure;
4718 
4719 	if (spu->spu_type == SPU_TYPE_SPUM)
4720 		iproc_priv.bcm_hdr_len = 8;
4721 	else if (spu->spu_type == SPU_TYPE_SPU2)
4722 		iproc_priv.bcm_hdr_len = 0;
4723 
4724 	spu_functions_register(dev, spu->spu_type, spu->spu_subtype);
4725 
4726 	spu_counters_init();
4727 
4728 	spu_setup_debugfs();
4729 
4730 	err = spu_algs_register(dev);
4731 	if (err < 0)
4732 		goto fail_reg;
4733 
4734 	return 0;
4735 
4736 fail_reg:
4737 	spu_free_debugfs();
4738 failure:
4739 	spu_mb_release(pdev);
4740 	dev_err(dev, "%s failed with error %d.\n", __func__, err);
4741 
4742 	return err;
4743 }
4744 
4745 static int bcm_spu_remove(struct platform_device *pdev)
4746 {
4747 	int i;
4748 	struct device *dev = &pdev->dev;
4749 	char *cdn;
4750 
4751 	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
4752 		/*
4753 		 * Not all algorithms were registered, depending on whether
4754 		 * hardware is SPU or SPU2.  So here we make sure to skip
4755 		 * those algorithms that were not previously registered.
4756 		 */
4757 		if (!driver_algs[i].registered)
4758 			continue;
4759 
4760 		switch (driver_algs[i].type) {
4761 		case CRYPTO_ALG_TYPE_SKCIPHER:
4762 			crypto_unregister_skcipher(&driver_algs[i].alg.skcipher);
4763 			dev_dbg(dev, "  unregistered cipher %s\n",
4764 				driver_algs[i].alg.skcipher.base.cra_driver_name);
4765 			driver_algs[i].registered = false;
4766 			break;
4767 		case CRYPTO_ALG_TYPE_AHASH:
4768 			crypto_unregister_ahash(&driver_algs[i].alg.hash);
4769 			cdn = driver_algs[i].alg.hash.halg.base.cra_driver_name;
4770 			dev_dbg(dev, "  unregistered hash %s\n", cdn);
4771 			driver_algs[i].registered = false;
4772 			break;
4773 		case CRYPTO_ALG_TYPE_AEAD:
4774 			crypto_unregister_aead(&driver_algs[i].alg.aead);
4775 			dev_dbg(dev, "  unregistered aead %s\n",
4776 				driver_algs[i].alg.aead.base.cra_driver_name);
4777 			driver_algs[i].registered = false;
4778 			break;
4779 		}
4780 	}
4781 	spu_free_debugfs();
4782 	spu_mb_release(pdev);
4783 	return 0;
4784 }
4785 
4786 /* ===== Kernel Module API ===== */
4787 
4788 static struct platform_driver bcm_spu_pdriver = {
4789 	.driver = {
4790 		   .name = "brcm-spu-crypto",
4791 		   .of_match_table = of_match_ptr(bcm_spu_dt_ids),
4792 		   },
4793 	.probe = bcm_spu_probe,
4794 	.remove = bcm_spu_remove,
4795 };
4796 module_platform_driver(bcm_spu_pdriver);
4797 
4798 MODULE_AUTHOR("Rob Rice <rob.rice@broadcom.com>");
4799 MODULE_DESCRIPTION("Broadcom symmetric crypto offload driver");
4800 MODULE_LICENSE("GPL v2");
4801