1 /* 2 * Cryptographic API. 3 * 4 * Support for ATMEL DES/TDES HW acceleration. 5 * 6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL 7 * Author: Nicolas Royer <nicolas@eukrea.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 * 13 * Some ideas are from omap-aes.c drivers. 14 */ 15 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/hw_random.h> 24 #include <linux/platform_device.h> 25 26 #include <linux/device.h> 27 #include <linux/init.h> 28 #include <linux/errno.h> 29 #include <linux/interrupt.h> 30 #include <linux/irq.h> 31 #include <linux/scatterlist.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/of_device.h> 34 #include <linux/delay.h> 35 #include <linux/crypto.h> 36 #include <linux/cryptohash.h> 37 #include <crypto/scatterwalk.h> 38 #include <crypto/algapi.h> 39 #include <crypto/des.h> 40 #include <crypto/hash.h> 41 #include <crypto/internal/hash.h> 42 #include <linux/platform_data/crypto-atmel.h> 43 #include "atmel-tdes-regs.h" 44 45 /* TDES flags */ 46 #define TDES_FLAGS_MODE_MASK 0x00ff 47 #define TDES_FLAGS_ENCRYPT BIT(0) 48 #define TDES_FLAGS_CBC BIT(1) 49 #define TDES_FLAGS_CFB BIT(2) 50 #define TDES_FLAGS_CFB8 BIT(3) 51 #define TDES_FLAGS_CFB16 BIT(4) 52 #define TDES_FLAGS_CFB32 BIT(5) 53 #define TDES_FLAGS_CFB64 BIT(6) 54 #define TDES_FLAGS_OFB BIT(7) 55 56 #define TDES_FLAGS_INIT BIT(16) 57 #define TDES_FLAGS_FAST BIT(17) 58 #define TDES_FLAGS_BUSY BIT(18) 59 #define TDES_FLAGS_DMA BIT(19) 60 61 #define ATMEL_TDES_QUEUE_LENGTH 50 62 63 #define CFB8_BLOCK_SIZE 1 64 #define CFB16_BLOCK_SIZE 2 65 #define CFB32_BLOCK_SIZE 4 66 67 struct atmel_tdes_caps { 68 bool has_dma; 69 u32 has_cfb_3keys; 70 }; 71 72 struct atmel_tdes_dev; 73 74 struct atmel_tdes_ctx { 75 struct atmel_tdes_dev *dd; 76 77 int keylen; 78 u32 key[3*DES_KEY_SIZE / sizeof(u32)]; 79 unsigned long flags; 80 81 u16 block_size; 82 }; 83 84 struct atmel_tdes_reqctx { 85 unsigned long mode; 86 }; 87 88 struct atmel_tdes_dma { 89 struct dma_chan *chan; 90 struct dma_slave_config dma_conf; 91 }; 92 93 struct atmel_tdes_dev { 94 struct list_head list; 95 unsigned long phys_base; 96 void __iomem *io_base; 97 98 struct atmel_tdes_ctx *ctx; 99 struct device *dev; 100 struct clk *iclk; 101 int irq; 102 103 unsigned long flags; 104 int err; 105 106 spinlock_t lock; 107 struct crypto_queue queue; 108 109 struct tasklet_struct done_task; 110 struct tasklet_struct queue_task; 111 112 struct ablkcipher_request *req; 113 size_t total; 114 115 struct scatterlist *in_sg; 116 unsigned int nb_in_sg; 117 size_t in_offset; 118 struct scatterlist *out_sg; 119 unsigned int nb_out_sg; 120 size_t out_offset; 121 122 size_t buflen; 123 size_t dma_size; 124 125 void *buf_in; 126 int dma_in; 127 dma_addr_t dma_addr_in; 128 struct atmel_tdes_dma dma_lch_in; 129 130 void *buf_out; 131 int dma_out; 132 dma_addr_t dma_addr_out; 133 struct atmel_tdes_dma dma_lch_out; 134 135 struct atmel_tdes_caps caps; 136 137 u32 hw_version; 138 }; 139 140 struct atmel_tdes_drv { 141 struct list_head dev_list; 142 spinlock_t lock; 143 }; 144 145 static struct atmel_tdes_drv atmel_tdes = { 146 .dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list), 147 .lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock), 148 }; 149 150 static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset, 151 void *buf, size_t buflen, size_t total, int out) 152 { 153 size_t count, off = 0; 154 155 while (buflen && total) { 156 count = min((*sg)->length - *offset, total); 157 count = min(count, buflen); 158 159 if (!count) 160 return off; 161 162 scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out); 163 164 off += count; 165 buflen -= count; 166 *offset += count; 167 total -= count; 168 169 if (*offset == (*sg)->length) { 170 *sg = sg_next(*sg); 171 if (*sg) 172 *offset = 0; 173 else 174 total = 0; 175 } 176 } 177 178 return off; 179 } 180 181 static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset) 182 { 183 return readl_relaxed(dd->io_base + offset); 184 } 185 186 static inline void atmel_tdes_write(struct atmel_tdes_dev *dd, 187 u32 offset, u32 value) 188 { 189 writel_relaxed(value, dd->io_base + offset); 190 } 191 192 static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset, 193 u32 *value, int count) 194 { 195 for (; count--; value++, offset += 4) 196 atmel_tdes_write(dd, offset, *value); 197 } 198 199 static struct atmel_tdes_dev *atmel_tdes_find_dev(struct atmel_tdes_ctx *ctx) 200 { 201 struct atmel_tdes_dev *tdes_dd = NULL; 202 struct atmel_tdes_dev *tmp; 203 204 spin_lock_bh(&atmel_tdes.lock); 205 if (!ctx->dd) { 206 list_for_each_entry(tmp, &atmel_tdes.dev_list, list) { 207 tdes_dd = tmp; 208 break; 209 } 210 ctx->dd = tdes_dd; 211 } else { 212 tdes_dd = ctx->dd; 213 } 214 spin_unlock_bh(&atmel_tdes.lock); 215 216 return tdes_dd; 217 } 218 219 static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd) 220 { 221 int err; 222 223 err = clk_prepare_enable(dd->iclk); 224 if (err) 225 return err; 226 227 if (!(dd->flags & TDES_FLAGS_INIT)) { 228 atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST); 229 dd->flags |= TDES_FLAGS_INIT; 230 dd->err = 0; 231 } 232 233 return 0; 234 } 235 236 static inline unsigned int atmel_tdes_get_version(struct atmel_tdes_dev *dd) 237 { 238 return atmel_tdes_read(dd, TDES_HW_VERSION) & 0x00000fff; 239 } 240 241 static void atmel_tdes_hw_version_init(struct atmel_tdes_dev *dd) 242 { 243 atmel_tdes_hw_init(dd); 244 245 dd->hw_version = atmel_tdes_get_version(dd); 246 247 dev_info(dd->dev, 248 "version: 0x%x\n", dd->hw_version); 249 250 clk_disable_unprepare(dd->iclk); 251 } 252 253 static void atmel_tdes_dma_callback(void *data) 254 { 255 struct atmel_tdes_dev *dd = data; 256 257 /* dma_lch_out - completed */ 258 tasklet_schedule(&dd->done_task); 259 } 260 261 static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd) 262 { 263 int err; 264 u32 valcr = 0, valmr = TDES_MR_SMOD_PDC; 265 266 err = atmel_tdes_hw_init(dd); 267 268 if (err) 269 return err; 270 271 if (!dd->caps.has_dma) 272 atmel_tdes_write(dd, TDES_PTCR, 273 TDES_PTCR_TXTDIS | TDES_PTCR_RXTDIS); 274 275 /* MR register must be set before IV registers */ 276 if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) { 277 valmr |= TDES_MR_KEYMOD_3KEY; 278 valmr |= TDES_MR_TDESMOD_TDES; 279 } else if (dd->ctx->keylen > DES_KEY_SIZE) { 280 valmr |= TDES_MR_KEYMOD_2KEY; 281 valmr |= TDES_MR_TDESMOD_TDES; 282 } else { 283 valmr |= TDES_MR_TDESMOD_DES; 284 } 285 286 if (dd->flags & TDES_FLAGS_CBC) { 287 valmr |= TDES_MR_OPMOD_CBC; 288 } else if (dd->flags & TDES_FLAGS_CFB) { 289 valmr |= TDES_MR_OPMOD_CFB; 290 291 if (dd->flags & TDES_FLAGS_CFB8) 292 valmr |= TDES_MR_CFBS_8b; 293 else if (dd->flags & TDES_FLAGS_CFB16) 294 valmr |= TDES_MR_CFBS_16b; 295 else if (dd->flags & TDES_FLAGS_CFB32) 296 valmr |= TDES_MR_CFBS_32b; 297 else if (dd->flags & TDES_FLAGS_CFB64) 298 valmr |= TDES_MR_CFBS_64b; 299 } else if (dd->flags & TDES_FLAGS_OFB) { 300 valmr |= TDES_MR_OPMOD_OFB; 301 } 302 303 if ((dd->flags & TDES_FLAGS_ENCRYPT) || (dd->flags & TDES_FLAGS_OFB)) 304 valmr |= TDES_MR_CYPHER_ENC; 305 306 atmel_tdes_write(dd, TDES_CR, valcr); 307 atmel_tdes_write(dd, TDES_MR, valmr); 308 309 atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key, 310 dd->ctx->keylen >> 2); 311 312 if (((dd->flags & TDES_FLAGS_CBC) || (dd->flags & TDES_FLAGS_CFB) || 313 (dd->flags & TDES_FLAGS_OFB)) && dd->req->info) { 314 atmel_tdes_write_n(dd, TDES_IV1R, dd->req->info, 2); 315 } 316 317 return 0; 318 } 319 320 static int atmel_tdes_crypt_pdc_stop(struct atmel_tdes_dev *dd) 321 { 322 int err = 0; 323 size_t count; 324 325 atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS); 326 327 if (dd->flags & TDES_FLAGS_FAST) { 328 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); 329 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 330 } else { 331 dma_sync_single_for_device(dd->dev, dd->dma_addr_out, 332 dd->dma_size, DMA_FROM_DEVICE); 333 334 /* copy data */ 335 count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset, 336 dd->buf_out, dd->buflen, dd->dma_size, 1); 337 if (count != dd->dma_size) { 338 err = -EINVAL; 339 pr_err("not all data converted: %zu\n", count); 340 } 341 } 342 343 return err; 344 } 345 346 static int atmel_tdes_buff_init(struct atmel_tdes_dev *dd) 347 { 348 int err = -ENOMEM; 349 350 dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0); 351 dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0); 352 dd->buflen = PAGE_SIZE; 353 dd->buflen &= ~(DES_BLOCK_SIZE - 1); 354 355 if (!dd->buf_in || !dd->buf_out) { 356 dev_err(dd->dev, "unable to alloc pages.\n"); 357 goto err_alloc; 358 } 359 360 /* MAP here */ 361 dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, 362 dd->buflen, DMA_TO_DEVICE); 363 if (dma_mapping_error(dd->dev, dd->dma_addr_in)) { 364 dev_err(dd->dev, "dma %zd bytes error\n", dd->buflen); 365 err = -EINVAL; 366 goto err_map_in; 367 } 368 369 dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, 370 dd->buflen, DMA_FROM_DEVICE); 371 if (dma_mapping_error(dd->dev, dd->dma_addr_out)) { 372 dev_err(dd->dev, "dma %zd bytes error\n", dd->buflen); 373 err = -EINVAL; 374 goto err_map_out; 375 } 376 377 return 0; 378 379 err_map_out: 380 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, 381 DMA_TO_DEVICE); 382 err_map_in: 383 err_alloc: 384 free_page((unsigned long)dd->buf_out); 385 free_page((unsigned long)dd->buf_in); 386 if (err) 387 pr_err("error: %d\n", err); 388 return err; 389 } 390 391 static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd) 392 { 393 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen, 394 DMA_FROM_DEVICE); 395 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, 396 DMA_TO_DEVICE); 397 free_page((unsigned long)dd->buf_out); 398 free_page((unsigned long)dd->buf_in); 399 } 400 401 static int atmel_tdes_crypt_pdc(struct crypto_tfm *tfm, dma_addr_t dma_addr_in, 402 dma_addr_t dma_addr_out, int length) 403 { 404 struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm); 405 struct atmel_tdes_dev *dd = ctx->dd; 406 int len32; 407 408 dd->dma_size = length; 409 410 if (!(dd->flags & TDES_FLAGS_FAST)) { 411 dma_sync_single_for_device(dd->dev, dma_addr_in, length, 412 DMA_TO_DEVICE); 413 } 414 415 if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB8)) 416 len32 = DIV_ROUND_UP(length, sizeof(u8)); 417 else if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB16)) 418 len32 = DIV_ROUND_UP(length, sizeof(u16)); 419 else 420 len32 = DIV_ROUND_UP(length, sizeof(u32)); 421 422 atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS); 423 atmel_tdes_write(dd, TDES_TPR, dma_addr_in); 424 atmel_tdes_write(dd, TDES_TCR, len32); 425 atmel_tdes_write(dd, TDES_RPR, dma_addr_out); 426 atmel_tdes_write(dd, TDES_RCR, len32); 427 428 /* Enable Interrupt */ 429 atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX); 430 431 /* Start DMA transfer */ 432 atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN); 433 434 return 0; 435 } 436 437 static int atmel_tdes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in, 438 dma_addr_t dma_addr_out, int length) 439 { 440 struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm); 441 struct atmel_tdes_dev *dd = ctx->dd; 442 struct scatterlist sg[2]; 443 struct dma_async_tx_descriptor *in_desc, *out_desc; 444 445 dd->dma_size = length; 446 447 if (!(dd->flags & TDES_FLAGS_FAST)) { 448 dma_sync_single_for_device(dd->dev, dma_addr_in, length, 449 DMA_TO_DEVICE); 450 } 451 452 if (dd->flags & TDES_FLAGS_CFB8) { 453 dd->dma_lch_in.dma_conf.dst_addr_width = 454 DMA_SLAVE_BUSWIDTH_1_BYTE; 455 dd->dma_lch_out.dma_conf.src_addr_width = 456 DMA_SLAVE_BUSWIDTH_1_BYTE; 457 } else if (dd->flags & TDES_FLAGS_CFB16) { 458 dd->dma_lch_in.dma_conf.dst_addr_width = 459 DMA_SLAVE_BUSWIDTH_2_BYTES; 460 dd->dma_lch_out.dma_conf.src_addr_width = 461 DMA_SLAVE_BUSWIDTH_2_BYTES; 462 } else { 463 dd->dma_lch_in.dma_conf.dst_addr_width = 464 DMA_SLAVE_BUSWIDTH_4_BYTES; 465 dd->dma_lch_out.dma_conf.src_addr_width = 466 DMA_SLAVE_BUSWIDTH_4_BYTES; 467 } 468 469 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf); 470 dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf); 471 472 dd->flags |= TDES_FLAGS_DMA; 473 474 sg_init_table(&sg[0], 1); 475 sg_dma_address(&sg[0]) = dma_addr_in; 476 sg_dma_len(&sg[0]) = length; 477 478 sg_init_table(&sg[1], 1); 479 sg_dma_address(&sg[1]) = dma_addr_out; 480 sg_dma_len(&sg[1]) = length; 481 482 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0], 483 1, DMA_MEM_TO_DEV, 484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 485 if (!in_desc) 486 return -EINVAL; 487 488 out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1], 489 1, DMA_DEV_TO_MEM, 490 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 491 if (!out_desc) 492 return -EINVAL; 493 494 out_desc->callback = atmel_tdes_dma_callback; 495 out_desc->callback_param = dd; 496 497 dmaengine_submit(out_desc); 498 dma_async_issue_pending(dd->dma_lch_out.chan); 499 500 dmaengine_submit(in_desc); 501 dma_async_issue_pending(dd->dma_lch_in.chan); 502 503 return 0; 504 } 505 506 static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd) 507 { 508 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 509 crypto_ablkcipher_reqtfm(dd->req)); 510 int err, fast = 0, in, out; 511 size_t count; 512 dma_addr_t addr_in, addr_out; 513 514 if ((!dd->in_offset) && (!dd->out_offset)) { 515 /* check for alignment */ 516 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)) && 517 IS_ALIGNED(dd->in_sg->length, dd->ctx->block_size); 518 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)) && 519 IS_ALIGNED(dd->out_sg->length, dd->ctx->block_size); 520 fast = in && out; 521 522 if (sg_dma_len(dd->in_sg) != sg_dma_len(dd->out_sg)) 523 fast = 0; 524 } 525 526 527 if (fast) { 528 count = min_t(size_t, dd->total, sg_dma_len(dd->in_sg)); 529 count = min_t(size_t, count, sg_dma_len(dd->out_sg)); 530 531 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 532 if (!err) { 533 dev_err(dd->dev, "dma_map_sg() error\n"); 534 return -EINVAL; 535 } 536 537 err = dma_map_sg(dd->dev, dd->out_sg, 1, 538 DMA_FROM_DEVICE); 539 if (!err) { 540 dev_err(dd->dev, "dma_map_sg() error\n"); 541 dma_unmap_sg(dd->dev, dd->in_sg, 1, 542 DMA_TO_DEVICE); 543 return -EINVAL; 544 } 545 546 addr_in = sg_dma_address(dd->in_sg); 547 addr_out = sg_dma_address(dd->out_sg); 548 549 dd->flags |= TDES_FLAGS_FAST; 550 551 } else { 552 /* use cache buffers */ 553 count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset, 554 dd->buf_in, dd->buflen, dd->total, 0); 555 556 addr_in = dd->dma_addr_in; 557 addr_out = dd->dma_addr_out; 558 559 dd->flags &= ~TDES_FLAGS_FAST; 560 } 561 562 dd->total -= count; 563 564 if (dd->caps.has_dma) 565 err = atmel_tdes_crypt_dma(tfm, addr_in, addr_out, count); 566 else 567 err = atmel_tdes_crypt_pdc(tfm, addr_in, addr_out, count); 568 569 if (err && (dd->flags & TDES_FLAGS_FAST)) { 570 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 571 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE); 572 } 573 574 return err; 575 } 576 577 static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err) 578 { 579 struct ablkcipher_request *req = dd->req; 580 581 clk_disable_unprepare(dd->iclk); 582 583 dd->flags &= ~TDES_FLAGS_BUSY; 584 585 req->base.complete(&req->base, err); 586 } 587 588 static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd, 589 struct ablkcipher_request *req) 590 { 591 struct crypto_async_request *async_req, *backlog; 592 struct atmel_tdes_ctx *ctx; 593 struct atmel_tdes_reqctx *rctx; 594 unsigned long flags; 595 int err, ret = 0; 596 597 spin_lock_irqsave(&dd->lock, flags); 598 if (req) 599 ret = ablkcipher_enqueue_request(&dd->queue, req); 600 if (dd->flags & TDES_FLAGS_BUSY) { 601 spin_unlock_irqrestore(&dd->lock, flags); 602 return ret; 603 } 604 backlog = crypto_get_backlog(&dd->queue); 605 async_req = crypto_dequeue_request(&dd->queue); 606 if (async_req) 607 dd->flags |= TDES_FLAGS_BUSY; 608 spin_unlock_irqrestore(&dd->lock, flags); 609 610 if (!async_req) 611 return ret; 612 613 if (backlog) 614 backlog->complete(backlog, -EINPROGRESS); 615 616 req = ablkcipher_request_cast(async_req); 617 618 /* assign new request to device */ 619 dd->req = req; 620 dd->total = req->nbytes; 621 dd->in_offset = 0; 622 dd->in_sg = req->src; 623 dd->out_offset = 0; 624 dd->out_sg = req->dst; 625 626 rctx = ablkcipher_request_ctx(req); 627 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 628 rctx->mode &= TDES_FLAGS_MODE_MASK; 629 dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode; 630 dd->ctx = ctx; 631 ctx->dd = dd; 632 633 err = atmel_tdes_write_ctrl(dd); 634 if (!err) 635 err = atmel_tdes_crypt_start(dd); 636 if (err) { 637 /* des_task will not finish it, so do it here */ 638 atmel_tdes_finish_req(dd, err); 639 tasklet_schedule(&dd->queue_task); 640 } 641 642 return ret; 643 } 644 645 static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd) 646 { 647 int err = -EINVAL; 648 size_t count; 649 650 if (dd->flags & TDES_FLAGS_DMA) { 651 err = 0; 652 if (dd->flags & TDES_FLAGS_FAST) { 653 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); 654 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 655 } else { 656 dma_sync_single_for_device(dd->dev, dd->dma_addr_out, 657 dd->dma_size, DMA_FROM_DEVICE); 658 659 /* copy data */ 660 count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset, 661 dd->buf_out, dd->buflen, dd->dma_size, 1); 662 if (count != dd->dma_size) { 663 err = -EINVAL; 664 pr_err("not all data converted: %zu\n", count); 665 } 666 } 667 } 668 return err; 669 } 670 671 static int atmel_tdes_crypt(struct ablkcipher_request *req, unsigned long mode) 672 { 673 struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx( 674 crypto_ablkcipher_reqtfm(req)); 675 struct atmel_tdes_reqctx *rctx = ablkcipher_request_ctx(req); 676 677 if (mode & TDES_FLAGS_CFB8) { 678 if (!IS_ALIGNED(req->nbytes, CFB8_BLOCK_SIZE)) { 679 pr_err("request size is not exact amount of CFB8 blocks\n"); 680 return -EINVAL; 681 } 682 ctx->block_size = CFB8_BLOCK_SIZE; 683 } else if (mode & TDES_FLAGS_CFB16) { 684 if (!IS_ALIGNED(req->nbytes, CFB16_BLOCK_SIZE)) { 685 pr_err("request size is not exact amount of CFB16 blocks\n"); 686 return -EINVAL; 687 } 688 ctx->block_size = CFB16_BLOCK_SIZE; 689 } else if (mode & TDES_FLAGS_CFB32) { 690 if (!IS_ALIGNED(req->nbytes, CFB32_BLOCK_SIZE)) { 691 pr_err("request size is not exact amount of CFB32 blocks\n"); 692 return -EINVAL; 693 } 694 ctx->block_size = CFB32_BLOCK_SIZE; 695 } else { 696 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) { 697 pr_err("request size is not exact amount of DES blocks\n"); 698 return -EINVAL; 699 } 700 ctx->block_size = DES_BLOCK_SIZE; 701 } 702 703 rctx->mode = mode; 704 705 return atmel_tdes_handle_queue(ctx->dd, req); 706 } 707 708 static bool atmel_tdes_filter(struct dma_chan *chan, void *slave) 709 { 710 struct at_dma_slave *sl = slave; 711 712 if (sl && sl->dma_dev == chan->device->dev) { 713 chan->private = sl; 714 return true; 715 } else { 716 return false; 717 } 718 } 719 720 static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd, 721 struct crypto_platform_data *pdata) 722 { 723 dma_cap_mask_t mask; 724 725 dma_cap_zero(mask); 726 dma_cap_set(DMA_SLAVE, mask); 727 728 /* Try to grab 2 DMA channels */ 729 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask, 730 atmel_tdes_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); 731 if (!dd->dma_lch_in.chan) 732 goto err_dma_in; 733 734 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; 735 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + 736 TDES_IDATA1R; 737 dd->dma_lch_in.dma_conf.src_maxburst = 1; 738 dd->dma_lch_in.dma_conf.src_addr_width = 739 DMA_SLAVE_BUSWIDTH_4_BYTES; 740 dd->dma_lch_in.dma_conf.dst_maxburst = 1; 741 dd->dma_lch_in.dma_conf.dst_addr_width = 742 DMA_SLAVE_BUSWIDTH_4_BYTES; 743 dd->dma_lch_in.dma_conf.device_fc = false; 744 745 dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask, 746 atmel_tdes_filter, &pdata->dma_slave->txdata, dd->dev, "rx"); 747 if (!dd->dma_lch_out.chan) 748 goto err_dma_out; 749 750 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM; 751 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base + 752 TDES_ODATA1R; 753 dd->dma_lch_out.dma_conf.src_maxburst = 1; 754 dd->dma_lch_out.dma_conf.src_addr_width = 755 DMA_SLAVE_BUSWIDTH_4_BYTES; 756 dd->dma_lch_out.dma_conf.dst_maxburst = 1; 757 dd->dma_lch_out.dma_conf.dst_addr_width = 758 DMA_SLAVE_BUSWIDTH_4_BYTES; 759 dd->dma_lch_out.dma_conf.device_fc = false; 760 761 return 0; 762 763 err_dma_out: 764 dma_release_channel(dd->dma_lch_in.chan); 765 err_dma_in: 766 dev_warn(dd->dev, "no DMA channel available\n"); 767 return -ENODEV; 768 } 769 770 static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd) 771 { 772 dma_release_channel(dd->dma_lch_in.chan); 773 dma_release_channel(dd->dma_lch_out.chan); 774 } 775 776 static int atmel_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 777 unsigned int keylen) 778 { 779 u32 tmp[DES_EXPKEY_WORDS]; 780 int err; 781 struct crypto_tfm *ctfm = crypto_ablkcipher_tfm(tfm); 782 783 struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 784 785 if (keylen != DES_KEY_SIZE) { 786 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 787 return -EINVAL; 788 } 789 790 err = des_ekey(tmp, key); 791 if (err == 0 && (ctfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) { 792 ctfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; 793 return -EINVAL; 794 } 795 796 memcpy(ctx->key, key, keylen); 797 ctx->keylen = keylen; 798 799 return 0; 800 } 801 802 static int atmel_tdes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 803 unsigned int keylen) 804 { 805 struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 806 const char *alg_name; 807 808 alg_name = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm)); 809 810 /* 811 * HW bug in cfb 3-keys mode. 812 */ 813 if (!ctx->dd->caps.has_cfb_3keys && strstr(alg_name, "cfb") 814 && (keylen != 2*DES_KEY_SIZE)) { 815 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 816 return -EINVAL; 817 } else if ((keylen != 2*DES_KEY_SIZE) && (keylen != 3*DES_KEY_SIZE)) { 818 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 819 return -EINVAL; 820 } 821 822 memcpy(ctx->key, key, keylen); 823 ctx->keylen = keylen; 824 825 return 0; 826 } 827 828 static int atmel_tdes_ecb_encrypt(struct ablkcipher_request *req) 829 { 830 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT); 831 } 832 833 static int atmel_tdes_ecb_decrypt(struct ablkcipher_request *req) 834 { 835 return atmel_tdes_crypt(req, 0); 836 } 837 838 static int atmel_tdes_cbc_encrypt(struct ablkcipher_request *req) 839 { 840 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CBC); 841 } 842 843 static int atmel_tdes_cbc_decrypt(struct ablkcipher_request *req) 844 { 845 return atmel_tdes_crypt(req, TDES_FLAGS_CBC); 846 } 847 static int atmel_tdes_cfb_encrypt(struct ablkcipher_request *req) 848 { 849 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB); 850 } 851 852 static int atmel_tdes_cfb_decrypt(struct ablkcipher_request *req) 853 { 854 return atmel_tdes_crypt(req, TDES_FLAGS_CFB); 855 } 856 857 static int atmel_tdes_cfb8_encrypt(struct ablkcipher_request *req) 858 { 859 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB | 860 TDES_FLAGS_CFB8); 861 } 862 863 static int atmel_tdes_cfb8_decrypt(struct ablkcipher_request *req) 864 { 865 return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB8); 866 } 867 868 static int atmel_tdes_cfb16_encrypt(struct ablkcipher_request *req) 869 { 870 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB | 871 TDES_FLAGS_CFB16); 872 } 873 874 static int atmel_tdes_cfb16_decrypt(struct ablkcipher_request *req) 875 { 876 return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB16); 877 } 878 879 static int atmel_tdes_cfb32_encrypt(struct ablkcipher_request *req) 880 { 881 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB | 882 TDES_FLAGS_CFB32); 883 } 884 885 static int atmel_tdes_cfb32_decrypt(struct ablkcipher_request *req) 886 { 887 return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB32); 888 } 889 890 static int atmel_tdes_ofb_encrypt(struct ablkcipher_request *req) 891 { 892 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_OFB); 893 } 894 895 static int atmel_tdes_ofb_decrypt(struct ablkcipher_request *req) 896 { 897 return atmel_tdes_crypt(req, TDES_FLAGS_OFB); 898 } 899 900 static int atmel_tdes_cra_init(struct crypto_tfm *tfm) 901 { 902 struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm); 903 struct atmel_tdes_dev *dd; 904 905 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_tdes_reqctx); 906 907 dd = atmel_tdes_find_dev(ctx); 908 if (!dd) 909 return -ENODEV; 910 911 return 0; 912 } 913 914 static struct crypto_alg tdes_algs[] = { 915 { 916 .cra_name = "ecb(des)", 917 .cra_driver_name = "atmel-ecb-des", 918 .cra_priority = 100, 919 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 920 .cra_blocksize = DES_BLOCK_SIZE, 921 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 922 .cra_alignmask = 0x7, 923 .cra_type = &crypto_ablkcipher_type, 924 .cra_module = THIS_MODULE, 925 .cra_init = atmel_tdes_cra_init, 926 .cra_u.ablkcipher = { 927 .min_keysize = DES_KEY_SIZE, 928 .max_keysize = DES_KEY_SIZE, 929 .setkey = atmel_des_setkey, 930 .encrypt = atmel_tdes_ecb_encrypt, 931 .decrypt = atmel_tdes_ecb_decrypt, 932 } 933 }, 934 { 935 .cra_name = "cbc(des)", 936 .cra_driver_name = "atmel-cbc-des", 937 .cra_priority = 100, 938 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 939 .cra_blocksize = DES_BLOCK_SIZE, 940 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 941 .cra_alignmask = 0x7, 942 .cra_type = &crypto_ablkcipher_type, 943 .cra_module = THIS_MODULE, 944 .cra_init = atmel_tdes_cra_init, 945 .cra_u.ablkcipher = { 946 .min_keysize = DES_KEY_SIZE, 947 .max_keysize = DES_KEY_SIZE, 948 .ivsize = DES_BLOCK_SIZE, 949 .setkey = atmel_des_setkey, 950 .encrypt = atmel_tdes_cbc_encrypt, 951 .decrypt = atmel_tdes_cbc_decrypt, 952 } 953 }, 954 { 955 .cra_name = "cfb(des)", 956 .cra_driver_name = "atmel-cfb-des", 957 .cra_priority = 100, 958 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 959 .cra_blocksize = DES_BLOCK_SIZE, 960 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 961 .cra_alignmask = 0x7, 962 .cra_type = &crypto_ablkcipher_type, 963 .cra_module = THIS_MODULE, 964 .cra_init = atmel_tdes_cra_init, 965 .cra_u.ablkcipher = { 966 .min_keysize = DES_KEY_SIZE, 967 .max_keysize = DES_KEY_SIZE, 968 .ivsize = DES_BLOCK_SIZE, 969 .setkey = atmel_des_setkey, 970 .encrypt = atmel_tdes_cfb_encrypt, 971 .decrypt = atmel_tdes_cfb_decrypt, 972 } 973 }, 974 { 975 .cra_name = "cfb8(des)", 976 .cra_driver_name = "atmel-cfb8-des", 977 .cra_priority = 100, 978 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 979 .cra_blocksize = CFB8_BLOCK_SIZE, 980 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 981 .cra_alignmask = 0, 982 .cra_type = &crypto_ablkcipher_type, 983 .cra_module = THIS_MODULE, 984 .cra_init = atmel_tdes_cra_init, 985 .cra_u.ablkcipher = { 986 .min_keysize = DES_KEY_SIZE, 987 .max_keysize = DES_KEY_SIZE, 988 .ivsize = DES_BLOCK_SIZE, 989 .setkey = atmel_des_setkey, 990 .encrypt = atmel_tdes_cfb8_encrypt, 991 .decrypt = atmel_tdes_cfb8_decrypt, 992 } 993 }, 994 { 995 .cra_name = "cfb16(des)", 996 .cra_driver_name = "atmel-cfb16-des", 997 .cra_priority = 100, 998 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 999 .cra_blocksize = CFB16_BLOCK_SIZE, 1000 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1001 .cra_alignmask = 0x1, 1002 .cra_type = &crypto_ablkcipher_type, 1003 .cra_module = THIS_MODULE, 1004 .cra_init = atmel_tdes_cra_init, 1005 .cra_u.ablkcipher = { 1006 .min_keysize = DES_KEY_SIZE, 1007 .max_keysize = DES_KEY_SIZE, 1008 .ivsize = DES_BLOCK_SIZE, 1009 .setkey = atmel_des_setkey, 1010 .encrypt = atmel_tdes_cfb16_encrypt, 1011 .decrypt = atmel_tdes_cfb16_decrypt, 1012 } 1013 }, 1014 { 1015 .cra_name = "cfb32(des)", 1016 .cra_driver_name = "atmel-cfb32-des", 1017 .cra_priority = 100, 1018 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1019 .cra_blocksize = CFB32_BLOCK_SIZE, 1020 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1021 .cra_alignmask = 0x3, 1022 .cra_type = &crypto_ablkcipher_type, 1023 .cra_module = THIS_MODULE, 1024 .cra_init = atmel_tdes_cra_init, 1025 .cra_u.ablkcipher = { 1026 .min_keysize = DES_KEY_SIZE, 1027 .max_keysize = DES_KEY_SIZE, 1028 .ivsize = DES_BLOCK_SIZE, 1029 .setkey = atmel_des_setkey, 1030 .encrypt = atmel_tdes_cfb32_encrypt, 1031 .decrypt = atmel_tdes_cfb32_decrypt, 1032 } 1033 }, 1034 { 1035 .cra_name = "ofb(des)", 1036 .cra_driver_name = "atmel-ofb-des", 1037 .cra_priority = 100, 1038 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1039 .cra_blocksize = DES_BLOCK_SIZE, 1040 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1041 .cra_alignmask = 0x7, 1042 .cra_type = &crypto_ablkcipher_type, 1043 .cra_module = THIS_MODULE, 1044 .cra_init = atmel_tdes_cra_init, 1045 .cra_u.ablkcipher = { 1046 .min_keysize = DES_KEY_SIZE, 1047 .max_keysize = DES_KEY_SIZE, 1048 .ivsize = DES_BLOCK_SIZE, 1049 .setkey = atmel_des_setkey, 1050 .encrypt = atmel_tdes_ofb_encrypt, 1051 .decrypt = atmel_tdes_ofb_decrypt, 1052 } 1053 }, 1054 { 1055 .cra_name = "ecb(des3_ede)", 1056 .cra_driver_name = "atmel-ecb-tdes", 1057 .cra_priority = 100, 1058 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1059 .cra_blocksize = DES_BLOCK_SIZE, 1060 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1061 .cra_alignmask = 0x7, 1062 .cra_type = &crypto_ablkcipher_type, 1063 .cra_module = THIS_MODULE, 1064 .cra_init = atmel_tdes_cra_init, 1065 .cra_u.ablkcipher = { 1066 .min_keysize = 2 * DES_KEY_SIZE, 1067 .max_keysize = 3 * DES_KEY_SIZE, 1068 .setkey = atmel_tdes_setkey, 1069 .encrypt = atmel_tdes_ecb_encrypt, 1070 .decrypt = atmel_tdes_ecb_decrypt, 1071 } 1072 }, 1073 { 1074 .cra_name = "cbc(des3_ede)", 1075 .cra_driver_name = "atmel-cbc-tdes", 1076 .cra_priority = 100, 1077 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1078 .cra_blocksize = DES_BLOCK_SIZE, 1079 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1080 .cra_alignmask = 0x7, 1081 .cra_type = &crypto_ablkcipher_type, 1082 .cra_module = THIS_MODULE, 1083 .cra_init = atmel_tdes_cra_init, 1084 .cra_u.ablkcipher = { 1085 .min_keysize = 2*DES_KEY_SIZE, 1086 .max_keysize = 3*DES_KEY_SIZE, 1087 .ivsize = DES_BLOCK_SIZE, 1088 .setkey = atmel_tdes_setkey, 1089 .encrypt = atmel_tdes_cbc_encrypt, 1090 .decrypt = atmel_tdes_cbc_decrypt, 1091 } 1092 }, 1093 { 1094 .cra_name = "cfb(des3_ede)", 1095 .cra_driver_name = "atmel-cfb-tdes", 1096 .cra_priority = 100, 1097 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1098 .cra_blocksize = DES_BLOCK_SIZE, 1099 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1100 .cra_alignmask = 0x7, 1101 .cra_type = &crypto_ablkcipher_type, 1102 .cra_module = THIS_MODULE, 1103 .cra_init = atmel_tdes_cra_init, 1104 .cra_u.ablkcipher = { 1105 .min_keysize = 2*DES_KEY_SIZE, 1106 .max_keysize = 2*DES_KEY_SIZE, 1107 .ivsize = DES_BLOCK_SIZE, 1108 .setkey = atmel_tdes_setkey, 1109 .encrypt = atmel_tdes_cfb_encrypt, 1110 .decrypt = atmel_tdes_cfb_decrypt, 1111 } 1112 }, 1113 { 1114 .cra_name = "cfb8(des3_ede)", 1115 .cra_driver_name = "atmel-cfb8-tdes", 1116 .cra_priority = 100, 1117 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1118 .cra_blocksize = CFB8_BLOCK_SIZE, 1119 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1120 .cra_alignmask = 0, 1121 .cra_type = &crypto_ablkcipher_type, 1122 .cra_module = THIS_MODULE, 1123 .cra_init = atmel_tdes_cra_init, 1124 .cra_u.ablkcipher = { 1125 .min_keysize = 2*DES_KEY_SIZE, 1126 .max_keysize = 2*DES_KEY_SIZE, 1127 .ivsize = DES_BLOCK_SIZE, 1128 .setkey = atmel_tdes_setkey, 1129 .encrypt = atmel_tdes_cfb8_encrypt, 1130 .decrypt = atmel_tdes_cfb8_decrypt, 1131 } 1132 }, 1133 { 1134 .cra_name = "cfb16(des3_ede)", 1135 .cra_driver_name = "atmel-cfb16-tdes", 1136 .cra_priority = 100, 1137 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1138 .cra_blocksize = CFB16_BLOCK_SIZE, 1139 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1140 .cra_alignmask = 0x1, 1141 .cra_type = &crypto_ablkcipher_type, 1142 .cra_module = THIS_MODULE, 1143 .cra_init = atmel_tdes_cra_init, 1144 .cra_u.ablkcipher = { 1145 .min_keysize = 2*DES_KEY_SIZE, 1146 .max_keysize = 2*DES_KEY_SIZE, 1147 .ivsize = DES_BLOCK_SIZE, 1148 .setkey = atmel_tdes_setkey, 1149 .encrypt = atmel_tdes_cfb16_encrypt, 1150 .decrypt = atmel_tdes_cfb16_decrypt, 1151 } 1152 }, 1153 { 1154 .cra_name = "cfb32(des3_ede)", 1155 .cra_driver_name = "atmel-cfb32-tdes", 1156 .cra_priority = 100, 1157 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1158 .cra_blocksize = CFB32_BLOCK_SIZE, 1159 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1160 .cra_alignmask = 0x3, 1161 .cra_type = &crypto_ablkcipher_type, 1162 .cra_module = THIS_MODULE, 1163 .cra_init = atmel_tdes_cra_init, 1164 .cra_u.ablkcipher = { 1165 .min_keysize = 2*DES_KEY_SIZE, 1166 .max_keysize = 2*DES_KEY_SIZE, 1167 .ivsize = DES_BLOCK_SIZE, 1168 .setkey = atmel_tdes_setkey, 1169 .encrypt = atmel_tdes_cfb32_encrypt, 1170 .decrypt = atmel_tdes_cfb32_decrypt, 1171 } 1172 }, 1173 { 1174 .cra_name = "ofb(des3_ede)", 1175 .cra_driver_name = "atmel-ofb-tdes", 1176 .cra_priority = 100, 1177 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1178 .cra_blocksize = DES_BLOCK_SIZE, 1179 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1180 .cra_alignmask = 0x7, 1181 .cra_type = &crypto_ablkcipher_type, 1182 .cra_module = THIS_MODULE, 1183 .cra_init = atmel_tdes_cra_init, 1184 .cra_u.ablkcipher = { 1185 .min_keysize = 2*DES_KEY_SIZE, 1186 .max_keysize = 3*DES_KEY_SIZE, 1187 .ivsize = DES_BLOCK_SIZE, 1188 .setkey = atmel_tdes_setkey, 1189 .encrypt = atmel_tdes_ofb_encrypt, 1190 .decrypt = atmel_tdes_ofb_decrypt, 1191 } 1192 }, 1193 }; 1194 1195 static void atmel_tdes_queue_task(unsigned long data) 1196 { 1197 struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data; 1198 1199 atmel_tdes_handle_queue(dd, NULL); 1200 } 1201 1202 static void atmel_tdes_done_task(unsigned long data) 1203 { 1204 struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data; 1205 int err; 1206 1207 if (!(dd->flags & TDES_FLAGS_DMA)) 1208 err = atmel_tdes_crypt_pdc_stop(dd); 1209 else 1210 err = atmel_tdes_crypt_dma_stop(dd); 1211 1212 err = dd->err ? : err; 1213 1214 if (dd->total && !err) { 1215 if (dd->flags & TDES_FLAGS_FAST) { 1216 dd->in_sg = sg_next(dd->in_sg); 1217 dd->out_sg = sg_next(dd->out_sg); 1218 if (!dd->in_sg || !dd->out_sg) 1219 err = -EINVAL; 1220 } 1221 if (!err) 1222 err = atmel_tdes_crypt_start(dd); 1223 if (!err) 1224 return; /* DMA started. Not fininishing. */ 1225 } 1226 1227 atmel_tdes_finish_req(dd, err); 1228 atmel_tdes_handle_queue(dd, NULL); 1229 } 1230 1231 static irqreturn_t atmel_tdes_irq(int irq, void *dev_id) 1232 { 1233 struct atmel_tdes_dev *tdes_dd = dev_id; 1234 u32 reg; 1235 1236 reg = atmel_tdes_read(tdes_dd, TDES_ISR); 1237 if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) { 1238 atmel_tdes_write(tdes_dd, TDES_IDR, reg); 1239 if (TDES_FLAGS_BUSY & tdes_dd->flags) 1240 tasklet_schedule(&tdes_dd->done_task); 1241 else 1242 dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n"); 1243 return IRQ_HANDLED; 1244 } 1245 1246 return IRQ_NONE; 1247 } 1248 1249 static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd) 1250 { 1251 int i; 1252 1253 for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) 1254 crypto_unregister_alg(&tdes_algs[i]); 1255 } 1256 1257 static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd) 1258 { 1259 int err, i, j; 1260 1261 for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) { 1262 err = crypto_register_alg(&tdes_algs[i]); 1263 if (err) 1264 goto err_tdes_algs; 1265 } 1266 1267 return 0; 1268 1269 err_tdes_algs: 1270 for (j = 0; j < i; j++) 1271 crypto_unregister_alg(&tdes_algs[j]); 1272 1273 return err; 1274 } 1275 1276 static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd) 1277 { 1278 1279 dd->caps.has_dma = 0; 1280 dd->caps.has_cfb_3keys = 0; 1281 1282 /* keep only major version number */ 1283 switch (dd->hw_version & 0xf00) { 1284 case 0x700: 1285 dd->caps.has_dma = 1; 1286 dd->caps.has_cfb_3keys = 1; 1287 break; 1288 case 0x600: 1289 break; 1290 default: 1291 dev_warn(dd->dev, 1292 "Unmanaged tdes version, set minimum capabilities\n"); 1293 break; 1294 } 1295 } 1296 1297 #if defined(CONFIG_OF) 1298 static const struct of_device_id atmel_tdes_dt_ids[] = { 1299 { .compatible = "atmel,at91sam9g46-tdes" }, 1300 { /* sentinel */ } 1301 }; 1302 MODULE_DEVICE_TABLE(of, atmel_tdes_dt_ids); 1303 1304 static struct crypto_platform_data *atmel_tdes_of_init(struct platform_device *pdev) 1305 { 1306 struct device_node *np = pdev->dev.of_node; 1307 struct crypto_platform_data *pdata; 1308 1309 if (!np) { 1310 dev_err(&pdev->dev, "device node not found\n"); 1311 return ERR_PTR(-EINVAL); 1312 } 1313 1314 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1315 if (!pdata) 1316 return ERR_PTR(-ENOMEM); 1317 1318 pdata->dma_slave = devm_kzalloc(&pdev->dev, 1319 sizeof(*(pdata->dma_slave)), 1320 GFP_KERNEL); 1321 if (!pdata->dma_slave) 1322 return ERR_PTR(-ENOMEM); 1323 1324 return pdata; 1325 } 1326 #else /* CONFIG_OF */ 1327 static inline struct crypto_platform_data *atmel_tdes_of_init(struct platform_device *pdev) 1328 { 1329 return ERR_PTR(-EINVAL); 1330 } 1331 #endif 1332 1333 static int atmel_tdes_probe(struct platform_device *pdev) 1334 { 1335 struct atmel_tdes_dev *tdes_dd; 1336 struct crypto_platform_data *pdata; 1337 struct device *dev = &pdev->dev; 1338 struct resource *tdes_res; 1339 int err; 1340 1341 tdes_dd = devm_kmalloc(&pdev->dev, sizeof(*tdes_dd), GFP_KERNEL); 1342 if (tdes_dd == NULL) { 1343 err = -ENOMEM; 1344 goto tdes_dd_err; 1345 } 1346 1347 tdes_dd->dev = dev; 1348 1349 platform_set_drvdata(pdev, tdes_dd); 1350 1351 INIT_LIST_HEAD(&tdes_dd->list); 1352 spin_lock_init(&tdes_dd->lock); 1353 1354 tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task, 1355 (unsigned long)tdes_dd); 1356 tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task, 1357 (unsigned long)tdes_dd); 1358 1359 crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH); 1360 1361 /* Get the base address */ 1362 tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1363 if (!tdes_res) { 1364 dev_err(dev, "no MEM resource info\n"); 1365 err = -ENODEV; 1366 goto res_err; 1367 } 1368 tdes_dd->phys_base = tdes_res->start; 1369 1370 /* Get the IRQ */ 1371 tdes_dd->irq = platform_get_irq(pdev, 0); 1372 if (tdes_dd->irq < 0) { 1373 dev_err(dev, "no IRQ resource info\n"); 1374 err = tdes_dd->irq; 1375 goto res_err; 1376 } 1377 1378 err = devm_request_irq(&pdev->dev, tdes_dd->irq, atmel_tdes_irq, 1379 IRQF_SHARED, "atmel-tdes", tdes_dd); 1380 if (err) { 1381 dev_err(dev, "unable to request tdes irq.\n"); 1382 goto res_err; 1383 } 1384 1385 /* Initializing the clock */ 1386 tdes_dd->iclk = devm_clk_get(&pdev->dev, "tdes_clk"); 1387 if (IS_ERR(tdes_dd->iclk)) { 1388 dev_err(dev, "clock initialization failed.\n"); 1389 err = PTR_ERR(tdes_dd->iclk); 1390 goto res_err; 1391 } 1392 1393 tdes_dd->io_base = devm_ioremap_resource(&pdev->dev, tdes_res); 1394 if (IS_ERR(tdes_dd->io_base)) { 1395 dev_err(dev, "can't ioremap\n"); 1396 err = PTR_ERR(tdes_dd->io_base); 1397 goto res_err; 1398 } 1399 1400 atmel_tdes_hw_version_init(tdes_dd); 1401 1402 atmel_tdes_get_cap(tdes_dd); 1403 1404 err = atmel_tdes_buff_init(tdes_dd); 1405 if (err) 1406 goto err_tdes_buff; 1407 1408 if (tdes_dd->caps.has_dma) { 1409 pdata = pdev->dev.platform_data; 1410 if (!pdata) { 1411 pdata = atmel_tdes_of_init(pdev); 1412 if (IS_ERR(pdata)) { 1413 dev_err(&pdev->dev, "platform data not available\n"); 1414 err = PTR_ERR(pdata); 1415 goto err_pdata; 1416 } 1417 } 1418 if (!pdata->dma_slave) { 1419 err = -ENXIO; 1420 goto err_pdata; 1421 } 1422 err = atmel_tdes_dma_init(tdes_dd, pdata); 1423 if (err) 1424 goto err_tdes_dma; 1425 1426 dev_info(dev, "using %s, %s for DMA transfers\n", 1427 dma_chan_name(tdes_dd->dma_lch_in.chan), 1428 dma_chan_name(tdes_dd->dma_lch_out.chan)); 1429 } 1430 1431 spin_lock(&atmel_tdes.lock); 1432 list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list); 1433 spin_unlock(&atmel_tdes.lock); 1434 1435 err = atmel_tdes_register_algs(tdes_dd); 1436 if (err) 1437 goto err_algs; 1438 1439 dev_info(dev, "Atmel DES/TDES\n"); 1440 1441 return 0; 1442 1443 err_algs: 1444 spin_lock(&atmel_tdes.lock); 1445 list_del(&tdes_dd->list); 1446 spin_unlock(&atmel_tdes.lock); 1447 if (tdes_dd->caps.has_dma) 1448 atmel_tdes_dma_cleanup(tdes_dd); 1449 err_tdes_dma: 1450 err_pdata: 1451 atmel_tdes_buff_cleanup(tdes_dd); 1452 err_tdes_buff: 1453 res_err: 1454 tasklet_kill(&tdes_dd->done_task); 1455 tasklet_kill(&tdes_dd->queue_task); 1456 tdes_dd_err: 1457 dev_err(dev, "initialization failed.\n"); 1458 1459 return err; 1460 } 1461 1462 static int atmel_tdes_remove(struct platform_device *pdev) 1463 { 1464 struct atmel_tdes_dev *tdes_dd; 1465 1466 tdes_dd = platform_get_drvdata(pdev); 1467 if (!tdes_dd) 1468 return -ENODEV; 1469 spin_lock(&atmel_tdes.lock); 1470 list_del(&tdes_dd->list); 1471 spin_unlock(&atmel_tdes.lock); 1472 1473 atmel_tdes_unregister_algs(tdes_dd); 1474 1475 tasklet_kill(&tdes_dd->done_task); 1476 tasklet_kill(&tdes_dd->queue_task); 1477 1478 if (tdes_dd->caps.has_dma) 1479 atmel_tdes_dma_cleanup(tdes_dd); 1480 1481 atmel_tdes_buff_cleanup(tdes_dd); 1482 1483 return 0; 1484 } 1485 1486 static struct platform_driver atmel_tdes_driver = { 1487 .probe = atmel_tdes_probe, 1488 .remove = atmel_tdes_remove, 1489 .driver = { 1490 .name = "atmel_tdes", 1491 .of_match_table = of_match_ptr(atmel_tdes_dt_ids), 1492 }, 1493 }; 1494 1495 module_platform_driver(atmel_tdes_driver); 1496 1497 MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support."); 1498 MODULE_LICENSE("GPL v2"); 1499 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); 1500