1 /* 2 * Cryptographic API. 3 * 4 * Support for ATMEL DES/TDES HW acceleration. 5 * 6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL 7 * Author: Nicolas Royer <nicolas@eukrea.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 * 13 * Some ideas are from omap-aes.c drivers. 14 */ 15 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/hw_random.h> 24 #include <linux/platform_device.h> 25 26 #include <linux/device.h> 27 #include <linux/init.h> 28 #include <linux/errno.h> 29 #include <linux/interrupt.h> 30 #include <linux/irq.h> 31 #include <linux/scatterlist.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/delay.h> 34 #include <linux/crypto.h> 35 #include <linux/cryptohash.h> 36 #include <crypto/scatterwalk.h> 37 #include <crypto/algapi.h> 38 #include <crypto/des.h> 39 #include <crypto/hash.h> 40 #include <crypto/internal/hash.h> 41 #include <linux/platform_data/crypto-atmel.h> 42 #include "atmel-tdes-regs.h" 43 44 /* TDES flags */ 45 #define TDES_FLAGS_MODE_MASK 0x00ff 46 #define TDES_FLAGS_ENCRYPT BIT(0) 47 #define TDES_FLAGS_CBC BIT(1) 48 #define TDES_FLAGS_CFB BIT(2) 49 #define TDES_FLAGS_CFB8 BIT(3) 50 #define TDES_FLAGS_CFB16 BIT(4) 51 #define TDES_FLAGS_CFB32 BIT(5) 52 #define TDES_FLAGS_CFB64 BIT(6) 53 #define TDES_FLAGS_OFB BIT(7) 54 55 #define TDES_FLAGS_INIT BIT(16) 56 #define TDES_FLAGS_FAST BIT(17) 57 #define TDES_FLAGS_BUSY BIT(18) 58 #define TDES_FLAGS_DMA BIT(19) 59 60 #define ATMEL_TDES_QUEUE_LENGTH 50 61 62 #define CFB8_BLOCK_SIZE 1 63 #define CFB16_BLOCK_SIZE 2 64 #define CFB32_BLOCK_SIZE 4 65 66 struct atmel_tdes_caps { 67 bool has_dma; 68 u32 has_cfb_3keys; 69 }; 70 71 struct atmel_tdes_dev; 72 73 struct atmel_tdes_ctx { 74 struct atmel_tdes_dev *dd; 75 76 int keylen; 77 u32 key[3*DES_KEY_SIZE / sizeof(u32)]; 78 unsigned long flags; 79 80 u16 block_size; 81 }; 82 83 struct atmel_tdes_reqctx { 84 unsigned long mode; 85 }; 86 87 struct atmel_tdes_dma { 88 struct dma_chan *chan; 89 struct dma_slave_config dma_conf; 90 }; 91 92 struct atmel_tdes_dev { 93 struct list_head list; 94 unsigned long phys_base; 95 void __iomem *io_base; 96 97 struct atmel_tdes_ctx *ctx; 98 struct device *dev; 99 struct clk *iclk; 100 int irq; 101 102 unsigned long flags; 103 int err; 104 105 spinlock_t lock; 106 struct crypto_queue queue; 107 108 struct tasklet_struct done_task; 109 struct tasklet_struct queue_task; 110 111 struct ablkcipher_request *req; 112 size_t total; 113 114 struct scatterlist *in_sg; 115 unsigned int nb_in_sg; 116 size_t in_offset; 117 struct scatterlist *out_sg; 118 unsigned int nb_out_sg; 119 size_t out_offset; 120 121 size_t buflen; 122 size_t dma_size; 123 124 void *buf_in; 125 int dma_in; 126 dma_addr_t dma_addr_in; 127 struct atmel_tdes_dma dma_lch_in; 128 129 void *buf_out; 130 int dma_out; 131 dma_addr_t dma_addr_out; 132 struct atmel_tdes_dma dma_lch_out; 133 134 struct atmel_tdes_caps caps; 135 136 u32 hw_version; 137 }; 138 139 struct atmel_tdes_drv { 140 struct list_head dev_list; 141 spinlock_t lock; 142 }; 143 144 static struct atmel_tdes_drv atmel_tdes = { 145 .dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list), 146 .lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock), 147 }; 148 149 static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset, 150 void *buf, size_t buflen, size_t total, int out) 151 { 152 unsigned int count, off = 0; 153 154 while (buflen && total) { 155 count = min((*sg)->length - *offset, total); 156 count = min(count, buflen); 157 158 if (!count) 159 return off; 160 161 scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out); 162 163 off += count; 164 buflen -= count; 165 *offset += count; 166 total -= count; 167 168 if (*offset == (*sg)->length) { 169 *sg = sg_next(*sg); 170 if (*sg) 171 *offset = 0; 172 else 173 total = 0; 174 } 175 } 176 177 return off; 178 } 179 180 static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset) 181 { 182 return readl_relaxed(dd->io_base + offset); 183 } 184 185 static inline void atmel_tdes_write(struct atmel_tdes_dev *dd, 186 u32 offset, u32 value) 187 { 188 writel_relaxed(value, dd->io_base + offset); 189 } 190 191 static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset, 192 u32 *value, int count) 193 { 194 for (; count--; value++, offset += 4) 195 atmel_tdes_write(dd, offset, *value); 196 } 197 198 static struct atmel_tdes_dev *atmel_tdes_find_dev(struct atmel_tdes_ctx *ctx) 199 { 200 struct atmel_tdes_dev *tdes_dd = NULL; 201 struct atmel_tdes_dev *tmp; 202 203 spin_lock_bh(&atmel_tdes.lock); 204 if (!ctx->dd) { 205 list_for_each_entry(tmp, &atmel_tdes.dev_list, list) { 206 tdes_dd = tmp; 207 break; 208 } 209 ctx->dd = tdes_dd; 210 } else { 211 tdes_dd = ctx->dd; 212 } 213 spin_unlock_bh(&atmel_tdes.lock); 214 215 return tdes_dd; 216 } 217 218 static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd) 219 { 220 clk_prepare_enable(dd->iclk); 221 222 if (!(dd->flags & TDES_FLAGS_INIT)) { 223 atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST); 224 dd->flags |= TDES_FLAGS_INIT; 225 dd->err = 0; 226 } 227 228 return 0; 229 } 230 231 static inline unsigned int atmel_tdes_get_version(struct atmel_tdes_dev *dd) 232 { 233 return atmel_tdes_read(dd, TDES_HW_VERSION) & 0x00000fff; 234 } 235 236 static void atmel_tdes_hw_version_init(struct atmel_tdes_dev *dd) 237 { 238 atmel_tdes_hw_init(dd); 239 240 dd->hw_version = atmel_tdes_get_version(dd); 241 242 dev_info(dd->dev, 243 "version: 0x%x\n", dd->hw_version); 244 245 clk_disable_unprepare(dd->iclk); 246 } 247 248 static void atmel_tdes_dma_callback(void *data) 249 { 250 struct atmel_tdes_dev *dd = data; 251 252 /* dma_lch_out - completed */ 253 tasklet_schedule(&dd->done_task); 254 } 255 256 static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd) 257 { 258 int err; 259 u32 valcr = 0, valmr = TDES_MR_SMOD_PDC; 260 261 err = atmel_tdes_hw_init(dd); 262 263 if (err) 264 return err; 265 266 if (!dd->caps.has_dma) 267 atmel_tdes_write(dd, TDES_PTCR, 268 TDES_PTCR_TXTDIS | TDES_PTCR_RXTDIS); 269 270 /* MR register must be set before IV registers */ 271 if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) { 272 valmr |= TDES_MR_KEYMOD_3KEY; 273 valmr |= TDES_MR_TDESMOD_TDES; 274 } else if (dd->ctx->keylen > DES_KEY_SIZE) { 275 valmr |= TDES_MR_KEYMOD_2KEY; 276 valmr |= TDES_MR_TDESMOD_TDES; 277 } else { 278 valmr |= TDES_MR_TDESMOD_DES; 279 } 280 281 if (dd->flags & TDES_FLAGS_CBC) { 282 valmr |= TDES_MR_OPMOD_CBC; 283 } else if (dd->flags & TDES_FLAGS_CFB) { 284 valmr |= TDES_MR_OPMOD_CFB; 285 286 if (dd->flags & TDES_FLAGS_CFB8) 287 valmr |= TDES_MR_CFBS_8b; 288 else if (dd->flags & TDES_FLAGS_CFB16) 289 valmr |= TDES_MR_CFBS_16b; 290 else if (dd->flags & TDES_FLAGS_CFB32) 291 valmr |= TDES_MR_CFBS_32b; 292 else if (dd->flags & TDES_FLAGS_CFB64) 293 valmr |= TDES_MR_CFBS_64b; 294 } else if (dd->flags & TDES_FLAGS_OFB) { 295 valmr |= TDES_MR_OPMOD_OFB; 296 } 297 298 if ((dd->flags & TDES_FLAGS_ENCRYPT) || (dd->flags & TDES_FLAGS_OFB)) 299 valmr |= TDES_MR_CYPHER_ENC; 300 301 atmel_tdes_write(dd, TDES_CR, valcr); 302 atmel_tdes_write(dd, TDES_MR, valmr); 303 304 atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key, 305 dd->ctx->keylen >> 2); 306 307 if (((dd->flags & TDES_FLAGS_CBC) || (dd->flags & TDES_FLAGS_CFB) || 308 (dd->flags & TDES_FLAGS_OFB)) && dd->req->info) { 309 atmel_tdes_write_n(dd, TDES_IV1R, dd->req->info, 2); 310 } 311 312 return 0; 313 } 314 315 static int atmel_tdes_crypt_pdc_stop(struct atmel_tdes_dev *dd) 316 { 317 int err = 0; 318 size_t count; 319 320 atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS); 321 322 if (dd->flags & TDES_FLAGS_FAST) { 323 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); 324 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 325 } else { 326 dma_sync_single_for_device(dd->dev, dd->dma_addr_out, 327 dd->dma_size, DMA_FROM_DEVICE); 328 329 /* copy data */ 330 count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset, 331 dd->buf_out, dd->buflen, dd->dma_size, 1); 332 if (count != dd->dma_size) { 333 err = -EINVAL; 334 pr_err("not all data converted: %u\n", count); 335 } 336 } 337 338 return err; 339 } 340 341 static int atmel_tdes_buff_init(struct atmel_tdes_dev *dd) 342 { 343 int err = -ENOMEM; 344 345 dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0); 346 dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0); 347 dd->buflen = PAGE_SIZE; 348 dd->buflen &= ~(DES_BLOCK_SIZE - 1); 349 350 if (!dd->buf_in || !dd->buf_out) { 351 dev_err(dd->dev, "unable to alloc pages.\n"); 352 goto err_alloc; 353 } 354 355 /* MAP here */ 356 dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, 357 dd->buflen, DMA_TO_DEVICE); 358 if (dma_mapping_error(dd->dev, dd->dma_addr_in)) { 359 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen); 360 err = -EINVAL; 361 goto err_map_in; 362 } 363 364 dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, 365 dd->buflen, DMA_FROM_DEVICE); 366 if (dma_mapping_error(dd->dev, dd->dma_addr_out)) { 367 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen); 368 err = -EINVAL; 369 goto err_map_out; 370 } 371 372 return 0; 373 374 err_map_out: 375 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, 376 DMA_TO_DEVICE); 377 err_map_in: 378 free_page((unsigned long)dd->buf_out); 379 free_page((unsigned long)dd->buf_in); 380 err_alloc: 381 if (err) 382 pr_err("error: %d\n", err); 383 return err; 384 } 385 386 static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd) 387 { 388 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen, 389 DMA_FROM_DEVICE); 390 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, 391 DMA_TO_DEVICE); 392 free_page((unsigned long)dd->buf_out); 393 free_page((unsigned long)dd->buf_in); 394 } 395 396 static int atmel_tdes_crypt_pdc(struct crypto_tfm *tfm, dma_addr_t dma_addr_in, 397 dma_addr_t dma_addr_out, int length) 398 { 399 struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm); 400 struct atmel_tdes_dev *dd = ctx->dd; 401 int len32; 402 403 dd->dma_size = length; 404 405 if (!(dd->flags & TDES_FLAGS_FAST)) { 406 dma_sync_single_for_device(dd->dev, dma_addr_in, length, 407 DMA_TO_DEVICE); 408 } 409 410 if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB8)) 411 len32 = DIV_ROUND_UP(length, sizeof(u8)); 412 else if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB16)) 413 len32 = DIV_ROUND_UP(length, sizeof(u16)); 414 else 415 len32 = DIV_ROUND_UP(length, sizeof(u32)); 416 417 atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS); 418 atmel_tdes_write(dd, TDES_TPR, dma_addr_in); 419 atmel_tdes_write(dd, TDES_TCR, len32); 420 atmel_tdes_write(dd, TDES_RPR, dma_addr_out); 421 atmel_tdes_write(dd, TDES_RCR, len32); 422 423 /* Enable Interrupt */ 424 atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX); 425 426 /* Start DMA transfer */ 427 atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN); 428 429 return 0; 430 } 431 432 static int atmel_tdes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in, 433 dma_addr_t dma_addr_out, int length) 434 { 435 struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm); 436 struct atmel_tdes_dev *dd = ctx->dd; 437 struct scatterlist sg[2]; 438 struct dma_async_tx_descriptor *in_desc, *out_desc; 439 440 dd->dma_size = length; 441 442 if (!(dd->flags & TDES_FLAGS_FAST)) { 443 dma_sync_single_for_device(dd->dev, dma_addr_in, length, 444 DMA_TO_DEVICE); 445 } 446 447 if (dd->flags & TDES_FLAGS_CFB8) { 448 dd->dma_lch_in.dma_conf.dst_addr_width = 449 DMA_SLAVE_BUSWIDTH_1_BYTE; 450 dd->dma_lch_out.dma_conf.src_addr_width = 451 DMA_SLAVE_BUSWIDTH_1_BYTE; 452 } else if (dd->flags & TDES_FLAGS_CFB16) { 453 dd->dma_lch_in.dma_conf.dst_addr_width = 454 DMA_SLAVE_BUSWIDTH_2_BYTES; 455 dd->dma_lch_out.dma_conf.src_addr_width = 456 DMA_SLAVE_BUSWIDTH_2_BYTES; 457 } else { 458 dd->dma_lch_in.dma_conf.dst_addr_width = 459 DMA_SLAVE_BUSWIDTH_4_BYTES; 460 dd->dma_lch_out.dma_conf.src_addr_width = 461 DMA_SLAVE_BUSWIDTH_4_BYTES; 462 } 463 464 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf); 465 dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf); 466 467 dd->flags |= TDES_FLAGS_DMA; 468 469 sg_init_table(&sg[0], 1); 470 sg_dma_address(&sg[0]) = dma_addr_in; 471 sg_dma_len(&sg[0]) = length; 472 473 sg_init_table(&sg[1], 1); 474 sg_dma_address(&sg[1]) = dma_addr_out; 475 sg_dma_len(&sg[1]) = length; 476 477 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0], 478 1, DMA_MEM_TO_DEV, 479 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 480 if (!in_desc) 481 return -EINVAL; 482 483 out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1], 484 1, DMA_DEV_TO_MEM, 485 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 486 if (!out_desc) 487 return -EINVAL; 488 489 out_desc->callback = atmel_tdes_dma_callback; 490 out_desc->callback_param = dd; 491 492 dmaengine_submit(out_desc); 493 dma_async_issue_pending(dd->dma_lch_out.chan); 494 495 dmaengine_submit(in_desc); 496 dma_async_issue_pending(dd->dma_lch_in.chan); 497 498 return 0; 499 } 500 501 static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd) 502 { 503 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 504 crypto_ablkcipher_reqtfm(dd->req)); 505 int err, fast = 0, in, out; 506 size_t count; 507 dma_addr_t addr_in, addr_out; 508 509 if ((!dd->in_offset) && (!dd->out_offset)) { 510 /* check for alignment */ 511 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)) && 512 IS_ALIGNED(dd->in_sg->length, dd->ctx->block_size); 513 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)) && 514 IS_ALIGNED(dd->out_sg->length, dd->ctx->block_size); 515 fast = in && out; 516 517 if (sg_dma_len(dd->in_sg) != sg_dma_len(dd->out_sg)) 518 fast = 0; 519 } 520 521 522 if (fast) { 523 count = min(dd->total, sg_dma_len(dd->in_sg)); 524 count = min(count, sg_dma_len(dd->out_sg)); 525 526 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 527 if (!err) { 528 dev_err(dd->dev, "dma_map_sg() error\n"); 529 return -EINVAL; 530 } 531 532 err = dma_map_sg(dd->dev, dd->out_sg, 1, 533 DMA_FROM_DEVICE); 534 if (!err) { 535 dev_err(dd->dev, "dma_map_sg() error\n"); 536 dma_unmap_sg(dd->dev, dd->in_sg, 1, 537 DMA_TO_DEVICE); 538 return -EINVAL; 539 } 540 541 addr_in = sg_dma_address(dd->in_sg); 542 addr_out = sg_dma_address(dd->out_sg); 543 544 dd->flags |= TDES_FLAGS_FAST; 545 546 } else { 547 /* use cache buffers */ 548 count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset, 549 dd->buf_in, dd->buflen, dd->total, 0); 550 551 addr_in = dd->dma_addr_in; 552 addr_out = dd->dma_addr_out; 553 554 dd->flags &= ~TDES_FLAGS_FAST; 555 } 556 557 dd->total -= count; 558 559 if (dd->caps.has_dma) 560 err = atmel_tdes_crypt_dma(tfm, addr_in, addr_out, count); 561 else 562 err = atmel_tdes_crypt_pdc(tfm, addr_in, addr_out, count); 563 564 if (err && (dd->flags & TDES_FLAGS_FAST)) { 565 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 566 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE); 567 } 568 569 return err; 570 } 571 572 static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err) 573 { 574 struct ablkcipher_request *req = dd->req; 575 576 clk_disable_unprepare(dd->iclk); 577 578 dd->flags &= ~TDES_FLAGS_BUSY; 579 580 req->base.complete(&req->base, err); 581 } 582 583 static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd, 584 struct ablkcipher_request *req) 585 { 586 struct crypto_async_request *async_req, *backlog; 587 struct atmel_tdes_ctx *ctx; 588 struct atmel_tdes_reqctx *rctx; 589 unsigned long flags; 590 int err, ret = 0; 591 592 spin_lock_irqsave(&dd->lock, flags); 593 if (req) 594 ret = ablkcipher_enqueue_request(&dd->queue, req); 595 if (dd->flags & TDES_FLAGS_BUSY) { 596 spin_unlock_irqrestore(&dd->lock, flags); 597 return ret; 598 } 599 backlog = crypto_get_backlog(&dd->queue); 600 async_req = crypto_dequeue_request(&dd->queue); 601 if (async_req) 602 dd->flags |= TDES_FLAGS_BUSY; 603 spin_unlock_irqrestore(&dd->lock, flags); 604 605 if (!async_req) 606 return ret; 607 608 if (backlog) 609 backlog->complete(backlog, -EINPROGRESS); 610 611 req = ablkcipher_request_cast(async_req); 612 613 /* assign new request to device */ 614 dd->req = req; 615 dd->total = req->nbytes; 616 dd->in_offset = 0; 617 dd->in_sg = req->src; 618 dd->out_offset = 0; 619 dd->out_sg = req->dst; 620 621 rctx = ablkcipher_request_ctx(req); 622 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 623 rctx->mode &= TDES_FLAGS_MODE_MASK; 624 dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode; 625 dd->ctx = ctx; 626 ctx->dd = dd; 627 628 err = atmel_tdes_write_ctrl(dd); 629 if (!err) 630 err = atmel_tdes_crypt_start(dd); 631 if (err) { 632 /* des_task will not finish it, so do it here */ 633 atmel_tdes_finish_req(dd, err); 634 tasklet_schedule(&dd->queue_task); 635 } 636 637 return ret; 638 } 639 640 static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd) 641 { 642 int err = -EINVAL; 643 size_t count; 644 645 if (dd->flags & TDES_FLAGS_DMA) { 646 err = 0; 647 if (dd->flags & TDES_FLAGS_FAST) { 648 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); 649 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); 650 } else { 651 dma_sync_single_for_device(dd->dev, dd->dma_addr_out, 652 dd->dma_size, DMA_FROM_DEVICE); 653 654 /* copy data */ 655 count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset, 656 dd->buf_out, dd->buflen, dd->dma_size, 1); 657 if (count != dd->dma_size) { 658 err = -EINVAL; 659 pr_err("not all data converted: %u\n", count); 660 } 661 } 662 } 663 return err; 664 } 665 666 static int atmel_tdes_crypt(struct ablkcipher_request *req, unsigned long mode) 667 { 668 struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx( 669 crypto_ablkcipher_reqtfm(req)); 670 struct atmel_tdes_reqctx *rctx = ablkcipher_request_ctx(req); 671 672 if (mode & TDES_FLAGS_CFB8) { 673 if (!IS_ALIGNED(req->nbytes, CFB8_BLOCK_SIZE)) { 674 pr_err("request size is not exact amount of CFB8 blocks\n"); 675 return -EINVAL; 676 } 677 ctx->block_size = CFB8_BLOCK_SIZE; 678 } else if (mode & TDES_FLAGS_CFB16) { 679 if (!IS_ALIGNED(req->nbytes, CFB16_BLOCK_SIZE)) { 680 pr_err("request size is not exact amount of CFB16 blocks\n"); 681 return -EINVAL; 682 } 683 ctx->block_size = CFB16_BLOCK_SIZE; 684 } else if (mode & TDES_FLAGS_CFB32) { 685 if (!IS_ALIGNED(req->nbytes, CFB32_BLOCK_SIZE)) { 686 pr_err("request size is not exact amount of CFB32 blocks\n"); 687 return -EINVAL; 688 } 689 ctx->block_size = CFB32_BLOCK_SIZE; 690 } else { 691 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) { 692 pr_err("request size is not exact amount of DES blocks\n"); 693 return -EINVAL; 694 } 695 ctx->block_size = DES_BLOCK_SIZE; 696 } 697 698 rctx->mode = mode; 699 700 return atmel_tdes_handle_queue(ctx->dd, req); 701 } 702 703 static bool atmel_tdes_filter(struct dma_chan *chan, void *slave) 704 { 705 struct at_dma_slave *sl = slave; 706 707 if (sl && sl->dma_dev == chan->device->dev) { 708 chan->private = sl; 709 return true; 710 } else { 711 return false; 712 } 713 } 714 715 static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd, 716 struct crypto_platform_data *pdata) 717 { 718 int err = -ENOMEM; 719 dma_cap_mask_t mask_in, mask_out; 720 721 if (pdata && pdata->dma_slave->txdata.dma_dev && 722 pdata->dma_slave->rxdata.dma_dev) { 723 724 /* Try to grab 2 DMA channels */ 725 dma_cap_zero(mask_in); 726 dma_cap_set(DMA_SLAVE, mask_in); 727 728 dd->dma_lch_in.chan = dma_request_channel(mask_in, 729 atmel_tdes_filter, &pdata->dma_slave->rxdata); 730 731 if (!dd->dma_lch_in.chan) 732 goto err_dma_in; 733 734 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; 735 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + 736 TDES_IDATA1R; 737 dd->dma_lch_in.dma_conf.src_maxburst = 1; 738 dd->dma_lch_in.dma_conf.src_addr_width = 739 DMA_SLAVE_BUSWIDTH_4_BYTES; 740 dd->dma_lch_in.dma_conf.dst_maxburst = 1; 741 dd->dma_lch_in.dma_conf.dst_addr_width = 742 DMA_SLAVE_BUSWIDTH_4_BYTES; 743 dd->dma_lch_in.dma_conf.device_fc = false; 744 745 dma_cap_zero(mask_out); 746 dma_cap_set(DMA_SLAVE, mask_out); 747 dd->dma_lch_out.chan = dma_request_channel(mask_out, 748 atmel_tdes_filter, &pdata->dma_slave->txdata); 749 750 if (!dd->dma_lch_out.chan) 751 goto err_dma_out; 752 753 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM; 754 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base + 755 TDES_ODATA1R; 756 dd->dma_lch_out.dma_conf.src_maxburst = 1; 757 dd->dma_lch_out.dma_conf.src_addr_width = 758 DMA_SLAVE_BUSWIDTH_4_BYTES; 759 dd->dma_lch_out.dma_conf.dst_maxburst = 1; 760 dd->dma_lch_out.dma_conf.dst_addr_width = 761 DMA_SLAVE_BUSWIDTH_4_BYTES; 762 dd->dma_lch_out.dma_conf.device_fc = false; 763 764 return 0; 765 } else { 766 return -ENODEV; 767 } 768 769 err_dma_out: 770 dma_release_channel(dd->dma_lch_in.chan); 771 err_dma_in: 772 return err; 773 } 774 775 static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd) 776 { 777 dma_release_channel(dd->dma_lch_in.chan); 778 dma_release_channel(dd->dma_lch_out.chan); 779 } 780 781 static int atmel_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 782 unsigned int keylen) 783 { 784 u32 tmp[DES_EXPKEY_WORDS]; 785 int err; 786 struct crypto_tfm *ctfm = crypto_ablkcipher_tfm(tfm); 787 788 struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 789 790 if (keylen != DES_KEY_SIZE) { 791 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 792 return -EINVAL; 793 } 794 795 err = des_ekey(tmp, key); 796 if (err == 0 && (ctfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) { 797 ctfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; 798 return -EINVAL; 799 } 800 801 memcpy(ctx->key, key, keylen); 802 ctx->keylen = keylen; 803 804 return 0; 805 } 806 807 static int atmel_tdes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 808 unsigned int keylen) 809 { 810 struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm); 811 const char *alg_name; 812 813 alg_name = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm)); 814 815 /* 816 * HW bug in cfb 3-keys mode. 817 */ 818 if (!ctx->dd->caps.has_cfb_3keys && strstr(alg_name, "cfb") 819 && (keylen != 2*DES_KEY_SIZE)) { 820 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 821 return -EINVAL; 822 } else if ((keylen != 2*DES_KEY_SIZE) && (keylen != 3*DES_KEY_SIZE)) { 823 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 824 return -EINVAL; 825 } 826 827 memcpy(ctx->key, key, keylen); 828 ctx->keylen = keylen; 829 830 return 0; 831 } 832 833 static int atmel_tdes_ecb_encrypt(struct ablkcipher_request *req) 834 { 835 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT); 836 } 837 838 static int atmel_tdes_ecb_decrypt(struct ablkcipher_request *req) 839 { 840 return atmel_tdes_crypt(req, 0); 841 } 842 843 static int atmel_tdes_cbc_encrypt(struct ablkcipher_request *req) 844 { 845 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CBC); 846 } 847 848 static int atmel_tdes_cbc_decrypt(struct ablkcipher_request *req) 849 { 850 return atmel_tdes_crypt(req, TDES_FLAGS_CBC); 851 } 852 static int atmel_tdes_cfb_encrypt(struct ablkcipher_request *req) 853 { 854 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB); 855 } 856 857 static int atmel_tdes_cfb_decrypt(struct ablkcipher_request *req) 858 { 859 return atmel_tdes_crypt(req, TDES_FLAGS_CFB); 860 } 861 862 static int atmel_tdes_cfb8_encrypt(struct ablkcipher_request *req) 863 { 864 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB | 865 TDES_FLAGS_CFB8); 866 } 867 868 static int atmel_tdes_cfb8_decrypt(struct ablkcipher_request *req) 869 { 870 return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB8); 871 } 872 873 static int atmel_tdes_cfb16_encrypt(struct ablkcipher_request *req) 874 { 875 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB | 876 TDES_FLAGS_CFB16); 877 } 878 879 static int atmel_tdes_cfb16_decrypt(struct ablkcipher_request *req) 880 { 881 return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB16); 882 } 883 884 static int atmel_tdes_cfb32_encrypt(struct ablkcipher_request *req) 885 { 886 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB | 887 TDES_FLAGS_CFB32); 888 } 889 890 static int atmel_tdes_cfb32_decrypt(struct ablkcipher_request *req) 891 { 892 return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB32); 893 } 894 895 static int atmel_tdes_ofb_encrypt(struct ablkcipher_request *req) 896 { 897 return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_OFB); 898 } 899 900 static int atmel_tdes_ofb_decrypt(struct ablkcipher_request *req) 901 { 902 return atmel_tdes_crypt(req, TDES_FLAGS_OFB); 903 } 904 905 static int atmel_tdes_cra_init(struct crypto_tfm *tfm) 906 { 907 struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm); 908 struct atmel_tdes_dev *dd; 909 910 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_tdes_reqctx); 911 912 dd = atmel_tdes_find_dev(ctx); 913 if (!dd) 914 return -ENODEV; 915 916 return 0; 917 } 918 919 static void atmel_tdes_cra_exit(struct crypto_tfm *tfm) 920 { 921 } 922 923 static struct crypto_alg tdes_algs[] = { 924 { 925 .cra_name = "ecb(des)", 926 .cra_driver_name = "atmel-ecb-des", 927 .cra_priority = 100, 928 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 929 .cra_blocksize = DES_BLOCK_SIZE, 930 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 931 .cra_alignmask = 0x7, 932 .cra_type = &crypto_ablkcipher_type, 933 .cra_module = THIS_MODULE, 934 .cra_init = atmel_tdes_cra_init, 935 .cra_exit = atmel_tdes_cra_exit, 936 .cra_u.ablkcipher = { 937 .min_keysize = DES_KEY_SIZE, 938 .max_keysize = DES_KEY_SIZE, 939 .setkey = atmel_des_setkey, 940 .encrypt = atmel_tdes_ecb_encrypt, 941 .decrypt = atmel_tdes_ecb_decrypt, 942 } 943 }, 944 { 945 .cra_name = "cbc(des)", 946 .cra_driver_name = "atmel-cbc-des", 947 .cra_priority = 100, 948 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 949 .cra_blocksize = DES_BLOCK_SIZE, 950 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 951 .cra_alignmask = 0x7, 952 .cra_type = &crypto_ablkcipher_type, 953 .cra_module = THIS_MODULE, 954 .cra_init = atmel_tdes_cra_init, 955 .cra_exit = atmel_tdes_cra_exit, 956 .cra_u.ablkcipher = { 957 .min_keysize = DES_KEY_SIZE, 958 .max_keysize = DES_KEY_SIZE, 959 .ivsize = DES_BLOCK_SIZE, 960 .setkey = atmel_des_setkey, 961 .encrypt = atmel_tdes_cbc_encrypt, 962 .decrypt = atmel_tdes_cbc_decrypt, 963 } 964 }, 965 { 966 .cra_name = "cfb(des)", 967 .cra_driver_name = "atmel-cfb-des", 968 .cra_priority = 100, 969 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 970 .cra_blocksize = DES_BLOCK_SIZE, 971 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 972 .cra_alignmask = 0x7, 973 .cra_type = &crypto_ablkcipher_type, 974 .cra_module = THIS_MODULE, 975 .cra_init = atmel_tdes_cra_init, 976 .cra_exit = atmel_tdes_cra_exit, 977 .cra_u.ablkcipher = { 978 .min_keysize = DES_KEY_SIZE, 979 .max_keysize = DES_KEY_SIZE, 980 .ivsize = DES_BLOCK_SIZE, 981 .setkey = atmel_des_setkey, 982 .encrypt = atmel_tdes_cfb_encrypt, 983 .decrypt = atmel_tdes_cfb_decrypt, 984 } 985 }, 986 { 987 .cra_name = "cfb8(des)", 988 .cra_driver_name = "atmel-cfb8-des", 989 .cra_priority = 100, 990 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 991 .cra_blocksize = CFB8_BLOCK_SIZE, 992 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 993 .cra_alignmask = 0, 994 .cra_type = &crypto_ablkcipher_type, 995 .cra_module = THIS_MODULE, 996 .cra_init = atmel_tdes_cra_init, 997 .cra_exit = atmel_tdes_cra_exit, 998 .cra_u.ablkcipher = { 999 .min_keysize = DES_KEY_SIZE, 1000 .max_keysize = DES_KEY_SIZE, 1001 .ivsize = DES_BLOCK_SIZE, 1002 .setkey = atmel_des_setkey, 1003 .encrypt = atmel_tdes_cfb8_encrypt, 1004 .decrypt = atmel_tdes_cfb8_decrypt, 1005 } 1006 }, 1007 { 1008 .cra_name = "cfb16(des)", 1009 .cra_driver_name = "atmel-cfb16-des", 1010 .cra_priority = 100, 1011 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1012 .cra_blocksize = CFB16_BLOCK_SIZE, 1013 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1014 .cra_alignmask = 0x1, 1015 .cra_type = &crypto_ablkcipher_type, 1016 .cra_module = THIS_MODULE, 1017 .cra_init = atmel_tdes_cra_init, 1018 .cra_exit = atmel_tdes_cra_exit, 1019 .cra_u.ablkcipher = { 1020 .min_keysize = DES_KEY_SIZE, 1021 .max_keysize = DES_KEY_SIZE, 1022 .ivsize = DES_BLOCK_SIZE, 1023 .setkey = atmel_des_setkey, 1024 .encrypt = atmel_tdes_cfb16_encrypt, 1025 .decrypt = atmel_tdes_cfb16_decrypt, 1026 } 1027 }, 1028 { 1029 .cra_name = "cfb32(des)", 1030 .cra_driver_name = "atmel-cfb32-des", 1031 .cra_priority = 100, 1032 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1033 .cra_blocksize = CFB32_BLOCK_SIZE, 1034 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1035 .cra_alignmask = 0x3, 1036 .cra_type = &crypto_ablkcipher_type, 1037 .cra_module = THIS_MODULE, 1038 .cra_init = atmel_tdes_cra_init, 1039 .cra_exit = atmel_tdes_cra_exit, 1040 .cra_u.ablkcipher = { 1041 .min_keysize = DES_KEY_SIZE, 1042 .max_keysize = DES_KEY_SIZE, 1043 .ivsize = DES_BLOCK_SIZE, 1044 .setkey = atmel_des_setkey, 1045 .encrypt = atmel_tdes_cfb32_encrypt, 1046 .decrypt = atmel_tdes_cfb32_decrypt, 1047 } 1048 }, 1049 { 1050 .cra_name = "ofb(des)", 1051 .cra_driver_name = "atmel-ofb-des", 1052 .cra_priority = 100, 1053 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1054 .cra_blocksize = DES_BLOCK_SIZE, 1055 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1056 .cra_alignmask = 0x7, 1057 .cra_type = &crypto_ablkcipher_type, 1058 .cra_module = THIS_MODULE, 1059 .cra_init = atmel_tdes_cra_init, 1060 .cra_exit = atmel_tdes_cra_exit, 1061 .cra_u.ablkcipher = { 1062 .min_keysize = DES_KEY_SIZE, 1063 .max_keysize = DES_KEY_SIZE, 1064 .ivsize = DES_BLOCK_SIZE, 1065 .setkey = atmel_des_setkey, 1066 .encrypt = atmel_tdes_ofb_encrypt, 1067 .decrypt = atmel_tdes_ofb_decrypt, 1068 } 1069 }, 1070 { 1071 .cra_name = "ecb(des3_ede)", 1072 .cra_driver_name = "atmel-ecb-tdes", 1073 .cra_priority = 100, 1074 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1075 .cra_blocksize = DES_BLOCK_SIZE, 1076 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1077 .cra_alignmask = 0x7, 1078 .cra_type = &crypto_ablkcipher_type, 1079 .cra_module = THIS_MODULE, 1080 .cra_init = atmel_tdes_cra_init, 1081 .cra_exit = atmel_tdes_cra_exit, 1082 .cra_u.ablkcipher = { 1083 .min_keysize = 2 * DES_KEY_SIZE, 1084 .max_keysize = 3 * DES_KEY_SIZE, 1085 .setkey = atmel_tdes_setkey, 1086 .encrypt = atmel_tdes_ecb_encrypt, 1087 .decrypt = atmel_tdes_ecb_decrypt, 1088 } 1089 }, 1090 { 1091 .cra_name = "cbc(des3_ede)", 1092 .cra_driver_name = "atmel-cbc-tdes", 1093 .cra_priority = 100, 1094 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1095 .cra_blocksize = DES_BLOCK_SIZE, 1096 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1097 .cra_alignmask = 0x7, 1098 .cra_type = &crypto_ablkcipher_type, 1099 .cra_module = THIS_MODULE, 1100 .cra_init = atmel_tdes_cra_init, 1101 .cra_exit = atmel_tdes_cra_exit, 1102 .cra_u.ablkcipher = { 1103 .min_keysize = 2*DES_KEY_SIZE, 1104 .max_keysize = 3*DES_KEY_SIZE, 1105 .ivsize = DES_BLOCK_SIZE, 1106 .setkey = atmel_tdes_setkey, 1107 .encrypt = atmel_tdes_cbc_encrypt, 1108 .decrypt = atmel_tdes_cbc_decrypt, 1109 } 1110 }, 1111 { 1112 .cra_name = "cfb(des3_ede)", 1113 .cra_driver_name = "atmel-cfb-tdes", 1114 .cra_priority = 100, 1115 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1116 .cra_blocksize = DES_BLOCK_SIZE, 1117 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1118 .cra_alignmask = 0x7, 1119 .cra_type = &crypto_ablkcipher_type, 1120 .cra_module = THIS_MODULE, 1121 .cra_init = atmel_tdes_cra_init, 1122 .cra_exit = atmel_tdes_cra_exit, 1123 .cra_u.ablkcipher = { 1124 .min_keysize = 2*DES_KEY_SIZE, 1125 .max_keysize = 2*DES_KEY_SIZE, 1126 .ivsize = DES_BLOCK_SIZE, 1127 .setkey = atmel_tdes_setkey, 1128 .encrypt = atmel_tdes_cfb_encrypt, 1129 .decrypt = atmel_tdes_cfb_decrypt, 1130 } 1131 }, 1132 { 1133 .cra_name = "cfb8(des3_ede)", 1134 .cra_driver_name = "atmel-cfb8-tdes", 1135 .cra_priority = 100, 1136 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1137 .cra_blocksize = CFB8_BLOCK_SIZE, 1138 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1139 .cra_alignmask = 0, 1140 .cra_type = &crypto_ablkcipher_type, 1141 .cra_module = THIS_MODULE, 1142 .cra_init = atmel_tdes_cra_init, 1143 .cra_exit = atmel_tdes_cra_exit, 1144 .cra_u.ablkcipher = { 1145 .min_keysize = 2*DES_KEY_SIZE, 1146 .max_keysize = 2*DES_KEY_SIZE, 1147 .ivsize = DES_BLOCK_SIZE, 1148 .setkey = atmel_tdes_setkey, 1149 .encrypt = atmel_tdes_cfb8_encrypt, 1150 .decrypt = atmel_tdes_cfb8_decrypt, 1151 } 1152 }, 1153 { 1154 .cra_name = "cfb16(des3_ede)", 1155 .cra_driver_name = "atmel-cfb16-tdes", 1156 .cra_priority = 100, 1157 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1158 .cra_blocksize = CFB16_BLOCK_SIZE, 1159 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1160 .cra_alignmask = 0x1, 1161 .cra_type = &crypto_ablkcipher_type, 1162 .cra_module = THIS_MODULE, 1163 .cra_init = atmel_tdes_cra_init, 1164 .cra_exit = atmel_tdes_cra_exit, 1165 .cra_u.ablkcipher = { 1166 .min_keysize = 2*DES_KEY_SIZE, 1167 .max_keysize = 2*DES_KEY_SIZE, 1168 .ivsize = DES_BLOCK_SIZE, 1169 .setkey = atmel_tdes_setkey, 1170 .encrypt = atmel_tdes_cfb16_encrypt, 1171 .decrypt = atmel_tdes_cfb16_decrypt, 1172 } 1173 }, 1174 { 1175 .cra_name = "cfb32(des3_ede)", 1176 .cra_driver_name = "atmel-cfb32-tdes", 1177 .cra_priority = 100, 1178 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1179 .cra_blocksize = CFB32_BLOCK_SIZE, 1180 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1181 .cra_alignmask = 0x3, 1182 .cra_type = &crypto_ablkcipher_type, 1183 .cra_module = THIS_MODULE, 1184 .cra_init = atmel_tdes_cra_init, 1185 .cra_exit = atmel_tdes_cra_exit, 1186 .cra_u.ablkcipher = { 1187 .min_keysize = 2*DES_KEY_SIZE, 1188 .max_keysize = 2*DES_KEY_SIZE, 1189 .ivsize = DES_BLOCK_SIZE, 1190 .setkey = atmel_tdes_setkey, 1191 .encrypt = atmel_tdes_cfb32_encrypt, 1192 .decrypt = atmel_tdes_cfb32_decrypt, 1193 } 1194 }, 1195 { 1196 .cra_name = "ofb(des3_ede)", 1197 .cra_driver_name = "atmel-ofb-tdes", 1198 .cra_priority = 100, 1199 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1200 .cra_blocksize = DES_BLOCK_SIZE, 1201 .cra_ctxsize = sizeof(struct atmel_tdes_ctx), 1202 .cra_alignmask = 0x7, 1203 .cra_type = &crypto_ablkcipher_type, 1204 .cra_module = THIS_MODULE, 1205 .cra_init = atmel_tdes_cra_init, 1206 .cra_exit = atmel_tdes_cra_exit, 1207 .cra_u.ablkcipher = { 1208 .min_keysize = 2*DES_KEY_SIZE, 1209 .max_keysize = 3*DES_KEY_SIZE, 1210 .ivsize = DES_BLOCK_SIZE, 1211 .setkey = atmel_tdes_setkey, 1212 .encrypt = atmel_tdes_ofb_encrypt, 1213 .decrypt = atmel_tdes_ofb_decrypt, 1214 } 1215 }, 1216 }; 1217 1218 static void atmel_tdes_queue_task(unsigned long data) 1219 { 1220 struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data; 1221 1222 atmel_tdes_handle_queue(dd, NULL); 1223 } 1224 1225 static void atmel_tdes_done_task(unsigned long data) 1226 { 1227 struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data; 1228 int err; 1229 1230 if (!(dd->flags & TDES_FLAGS_DMA)) 1231 err = atmel_tdes_crypt_pdc_stop(dd); 1232 else 1233 err = atmel_tdes_crypt_dma_stop(dd); 1234 1235 err = dd->err ? : err; 1236 1237 if (dd->total && !err) { 1238 if (dd->flags & TDES_FLAGS_FAST) { 1239 dd->in_sg = sg_next(dd->in_sg); 1240 dd->out_sg = sg_next(dd->out_sg); 1241 if (!dd->in_sg || !dd->out_sg) 1242 err = -EINVAL; 1243 } 1244 if (!err) 1245 err = atmel_tdes_crypt_start(dd); 1246 if (!err) 1247 return; /* DMA started. Not fininishing. */ 1248 } 1249 1250 atmel_tdes_finish_req(dd, err); 1251 atmel_tdes_handle_queue(dd, NULL); 1252 } 1253 1254 static irqreturn_t atmel_tdes_irq(int irq, void *dev_id) 1255 { 1256 struct atmel_tdes_dev *tdes_dd = dev_id; 1257 u32 reg; 1258 1259 reg = atmel_tdes_read(tdes_dd, TDES_ISR); 1260 if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) { 1261 atmel_tdes_write(tdes_dd, TDES_IDR, reg); 1262 if (TDES_FLAGS_BUSY & tdes_dd->flags) 1263 tasklet_schedule(&tdes_dd->done_task); 1264 else 1265 dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n"); 1266 return IRQ_HANDLED; 1267 } 1268 1269 return IRQ_NONE; 1270 } 1271 1272 static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd) 1273 { 1274 int i; 1275 1276 for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) 1277 crypto_unregister_alg(&tdes_algs[i]); 1278 } 1279 1280 static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd) 1281 { 1282 int err, i, j; 1283 1284 for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) { 1285 err = crypto_register_alg(&tdes_algs[i]); 1286 if (err) 1287 goto err_tdes_algs; 1288 } 1289 1290 return 0; 1291 1292 err_tdes_algs: 1293 for (j = 0; j < i; j++) 1294 crypto_unregister_alg(&tdes_algs[j]); 1295 1296 return err; 1297 } 1298 1299 static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd) 1300 { 1301 1302 dd->caps.has_dma = 0; 1303 dd->caps.has_cfb_3keys = 0; 1304 1305 /* keep only major version number */ 1306 switch (dd->hw_version & 0xf00) { 1307 case 0x700: 1308 dd->caps.has_dma = 1; 1309 dd->caps.has_cfb_3keys = 1; 1310 break; 1311 case 0x600: 1312 break; 1313 default: 1314 dev_warn(dd->dev, 1315 "Unmanaged tdes version, set minimum capabilities\n"); 1316 break; 1317 } 1318 } 1319 1320 static int atmel_tdes_probe(struct platform_device *pdev) 1321 { 1322 struct atmel_tdes_dev *tdes_dd; 1323 struct crypto_platform_data *pdata; 1324 struct device *dev = &pdev->dev; 1325 struct resource *tdes_res; 1326 unsigned long tdes_phys_size; 1327 int err; 1328 1329 tdes_dd = kzalloc(sizeof(struct atmel_tdes_dev), GFP_KERNEL); 1330 if (tdes_dd == NULL) { 1331 dev_err(dev, "unable to alloc data struct.\n"); 1332 err = -ENOMEM; 1333 goto tdes_dd_err; 1334 } 1335 1336 tdes_dd->dev = dev; 1337 1338 platform_set_drvdata(pdev, tdes_dd); 1339 1340 INIT_LIST_HEAD(&tdes_dd->list); 1341 1342 tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task, 1343 (unsigned long)tdes_dd); 1344 tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task, 1345 (unsigned long)tdes_dd); 1346 1347 crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH); 1348 1349 tdes_dd->irq = -1; 1350 1351 /* Get the base address */ 1352 tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1353 if (!tdes_res) { 1354 dev_err(dev, "no MEM resource info\n"); 1355 err = -ENODEV; 1356 goto res_err; 1357 } 1358 tdes_dd->phys_base = tdes_res->start; 1359 tdes_phys_size = resource_size(tdes_res); 1360 1361 /* Get the IRQ */ 1362 tdes_dd->irq = platform_get_irq(pdev, 0); 1363 if (tdes_dd->irq < 0) { 1364 dev_err(dev, "no IRQ resource info\n"); 1365 err = tdes_dd->irq; 1366 goto res_err; 1367 } 1368 1369 err = request_irq(tdes_dd->irq, atmel_tdes_irq, IRQF_SHARED, 1370 "atmel-tdes", tdes_dd); 1371 if (err) { 1372 dev_err(dev, "unable to request tdes irq.\n"); 1373 goto tdes_irq_err; 1374 } 1375 1376 /* Initializing the clock */ 1377 tdes_dd->iclk = clk_get(&pdev->dev, "tdes_clk"); 1378 if (IS_ERR(tdes_dd->iclk)) { 1379 dev_err(dev, "clock intialization failed.\n"); 1380 err = PTR_ERR(tdes_dd->iclk); 1381 goto clk_err; 1382 } 1383 1384 tdes_dd->io_base = ioremap(tdes_dd->phys_base, tdes_phys_size); 1385 if (!tdes_dd->io_base) { 1386 dev_err(dev, "can't ioremap\n"); 1387 err = -ENOMEM; 1388 goto tdes_io_err; 1389 } 1390 1391 atmel_tdes_hw_version_init(tdes_dd); 1392 1393 atmel_tdes_get_cap(tdes_dd); 1394 1395 err = atmel_tdes_buff_init(tdes_dd); 1396 if (err) 1397 goto err_tdes_buff; 1398 1399 if (tdes_dd->caps.has_dma) { 1400 pdata = pdev->dev.platform_data; 1401 if (!pdata) { 1402 dev_err(&pdev->dev, "platform data not available\n"); 1403 err = -ENXIO; 1404 goto err_pdata; 1405 } 1406 err = atmel_tdes_dma_init(tdes_dd, pdata); 1407 if (err) 1408 goto err_tdes_dma; 1409 } 1410 1411 spin_lock(&atmel_tdes.lock); 1412 list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list); 1413 spin_unlock(&atmel_tdes.lock); 1414 1415 err = atmel_tdes_register_algs(tdes_dd); 1416 if (err) 1417 goto err_algs; 1418 1419 dev_info(dev, "Atmel DES/TDES\n"); 1420 1421 return 0; 1422 1423 err_algs: 1424 spin_lock(&atmel_tdes.lock); 1425 list_del(&tdes_dd->list); 1426 spin_unlock(&atmel_tdes.lock); 1427 if (tdes_dd->caps.has_dma) 1428 atmel_tdes_dma_cleanup(tdes_dd); 1429 err_tdes_dma: 1430 err_pdata: 1431 atmel_tdes_buff_cleanup(tdes_dd); 1432 err_tdes_buff: 1433 iounmap(tdes_dd->io_base); 1434 tdes_io_err: 1435 clk_put(tdes_dd->iclk); 1436 clk_err: 1437 free_irq(tdes_dd->irq, tdes_dd); 1438 tdes_irq_err: 1439 res_err: 1440 tasklet_kill(&tdes_dd->done_task); 1441 tasklet_kill(&tdes_dd->queue_task); 1442 kfree(tdes_dd); 1443 tdes_dd = NULL; 1444 tdes_dd_err: 1445 dev_err(dev, "initialization failed.\n"); 1446 1447 return err; 1448 } 1449 1450 static int atmel_tdes_remove(struct platform_device *pdev) 1451 { 1452 static struct atmel_tdes_dev *tdes_dd; 1453 1454 tdes_dd = platform_get_drvdata(pdev); 1455 if (!tdes_dd) 1456 return -ENODEV; 1457 spin_lock(&atmel_tdes.lock); 1458 list_del(&tdes_dd->list); 1459 spin_unlock(&atmel_tdes.lock); 1460 1461 atmel_tdes_unregister_algs(tdes_dd); 1462 1463 tasklet_kill(&tdes_dd->done_task); 1464 tasklet_kill(&tdes_dd->queue_task); 1465 1466 if (tdes_dd->caps.has_dma) 1467 atmel_tdes_dma_cleanup(tdes_dd); 1468 1469 atmel_tdes_buff_cleanup(tdes_dd); 1470 1471 iounmap(tdes_dd->io_base); 1472 1473 clk_put(tdes_dd->iclk); 1474 1475 if (tdes_dd->irq >= 0) 1476 free_irq(tdes_dd->irq, tdes_dd); 1477 1478 kfree(tdes_dd); 1479 tdes_dd = NULL; 1480 1481 return 0; 1482 } 1483 1484 static struct platform_driver atmel_tdes_driver = { 1485 .probe = atmel_tdes_probe, 1486 .remove = atmel_tdes_remove, 1487 .driver = { 1488 .name = "atmel_tdes", 1489 .owner = THIS_MODULE, 1490 }, 1491 }; 1492 1493 module_platform_driver(atmel_tdes_driver); 1494 1495 MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support."); 1496 MODULE_LICENSE("GPL v2"); 1497 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); 1498