1 /* 2 * Cryptographic API. 3 * 4 * Support for ATMEL SHA1/SHA256 HW acceleration. 5 * 6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL 7 * Author: Nicolas Royer <nicolas@eukrea.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 * 13 * Some ideas are from omap-sham.c drivers. 14 */ 15 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/hw_random.h> 24 #include <linux/platform_device.h> 25 26 #include <linux/device.h> 27 #include <linux/init.h> 28 #include <linux/errno.h> 29 #include <linux/interrupt.h> 30 #include <linux/irq.h> 31 #include <linux/scatterlist.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/of_device.h> 34 #include <linux/delay.h> 35 #include <linux/crypto.h> 36 #include <linux/cryptohash.h> 37 #include <crypto/scatterwalk.h> 38 #include <crypto/algapi.h> 39 #include <crypto/sha.h> 40 #include <crypto/hash.h> 41 #include <crypto/internal/hash.h> 42 #include <linux/platform_data/crypto-atmel.h> 43 #include "atmel-sha-regs.h" 44 #include "atmel-authenc.h" 45 46 /* SHA flags */ 47 #define SHA_FLAGS_BUSY BIT(0) 48 #define SHA_FLAGS_FINAL BIT(1) 49 #define SHA_FLAGS_DMA_ACTIVE BIT(2) 50 #define SHA_FLAGS_OUTPUT_READY BIT(3) 51 #define SHA_FLAGS_INIT BIT(4) 52 #define SHA_FLAGS_CPU BIT(5) 53 #define SHA_FLAGS_DMA_READY BIT(6) 54 #define SHA_FLAGS_DUMP_REG BIT(7) 55 56 /* bits[11:8] are reserved. */ 57 58 #define SHA_FLAGS_FINUP BIT(16) 59 #define SHA_FLAGS_SG BIT(17) 60 #define SHA_FLAGS_ERROR BIT(23) 61 #define SHA_FLAGS_PAD BIT(24) 62 #define SHA_FLAGS_RESTORE BIT(25) 63 #define SHA_FLAGS_IDATAR0 BIT(26) 64 #define SHA_FLAGS_WAIT_DATARDY BIT(27) 65 66 #define SHA_OP_INIT 0 67 #define SHA_OP_UPDATE 1 68 #define SHA_OP_FINAL 2 69 #define SHA_OP_DIGEST 3 70 71 #define SHA_BUFFER_LEN (PAGE_SIZE / 16) 72 73 #define ATMEL_SHA_DMA_THRESHOLD 56 74 75 struct atmel_sha_caps { 76 bool has_dma; 77 bool has_dualbuff; 78 bool has_sha224; 79 bool has_sha_384_512; 80 bool has_uihv; 81 bool has_hmac; 82 }; 83 84 struct atmel_sha_dev; 85 86 /* 87 * .statesize = sizeof(struct atmel_sha_reqctx) must be <= PAGE_SIZE / 8 as 88 * tested by the ahash_prepare_alg() function. 89 */ 90 struct atmel_sha_reqctx { 91 struct atmel_sha_dev *dd; 92 unsigned long flags; 93 unsigned long op; 94 95 u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32)); 96 u64 digcnt[2]; 97 size_t bufcnt; 98 size_t buflen; 99 dma_addr_t dma_addr; 100 101 /* walk state */ 102 struct scatterlist *sg; 103 unsigned int offset; /* offset in current sg */ 104 unsigned int total; /* total request */ 105 106 size_t block_size; 107 size_t hash_size; 108 109 u8 buffer[SHA_BUFFER_LEN + SHA512_BLOCK_SIZE] __aligned(sizeof(u32)); 110 }; 111 112 typedef int (*atmel_sha_fn_t)(struct atmel_sha_dev *); 113 114 struct atmel_sha_ctx { 115 struct atmel_sha_dev *dd; 116 atmel_sha_fn_t start; 117 118 unsigned long flags; 119 }; 120 121 #define ATMEL_SHA_QUEUE_LENGTH 50 122 123 struct atmel_sha_dma { 124 struct dma_chan *chan; 125 struct dma_slave_config dma_conf; 126 struct scatterlist *sg; 127 int nents; 128 unsigned int last_sg_length; 129 }; 130 131 struct atmel_sha_dev { 132 struct list_head list; 133 unsigned long phys_base; 134 struct device *dev; 135 struct clk *iclk; 136 int irq; 137 void __iomem *io_base; 138 139 spinlock_t lock; 140 int err; 141 struct tasklet_struct done_task; 142 struct tasklet_struct queue_task; 143 144 unsigned long flags; 145 struct crypto_queue queue; 146 struct ahash_request *req; 147 bool is_async; 148 bool force_complete; 149 atmel_sha_fn_t resume; 150 atmel_sha_fn_t cpu_transfer_complete; 151 152 struct atmel_sha_dma dma_lch_in; 153 154 struct atmel_sha_caps caps; 155 156 struct scatterlist tmp; 157 158 u32 hw_version; 159 }; 160 161 struct atmel_sha_drv { 162 struct list_head dev_list; 163 spinlock_t lock; 164 }; 165 166 static struct atmel_sha_drv atmel_sha = { 167 .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list), 168 .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock), 169 }; 170 171 #ifdef VERBOSE_DEBUG 172 static const char *atmel_sha_reg_name(u32 offset, char *tmp, size_t sz, bool wr) 173 { 174 switch (offset) { 175 case SHA_CR: 176 return "CR"; 177 178 case SHA_MR: 179 return "MR"; 180 181 case SHA_IER: 182 return "IER"; 183 184 case SHA_IDR: 185 return "IDR"; 186 187 case SHA_IMR: 188 return "IMR"; 189 190 case SHA_ISR: 191 return "ISR"; 192 193 case SHA_MSR: 194 return "MSR"; 195 196 case SHA_BCR: 197 return "BCR"; 198 199 case SHA_REG_DIN(0): 200 case SHA_REG_DIN(1): 201 case SHA_REG_DIN(2): 202 case SHA_REG_DIN(3): 203 case SHA_REG_DIN(4): 204 case SHA_REG_DIN(5): 205 case SHA_REG_DIN(6): 206 case SHA_REG_DIN(7): 207 case SHA_REG_DIN(8): 208 case SHA_REG_DIN(9): 209 case SHA_REG_DIN(10): 210 case SHA_REG_DIN(11): 211 case SHA_REG_DIN(12): 212 case SHA_REG_DIN(13): 213 case SHA_REG_DIN(14): 214 case SHA_REG_DIN(15): 215 snprintf(tmp, sz, "IDATAR[%u]", (offset - SHA_REG_DIN(0)) >> 2); 216 break; 217 218 case SHA_REG_DIGEST(0): 219 case SHA_REG_DIGEST(1): 220 case SHA_REG_DIGEST(2): 221 case SHA_REG_DIGEST(3): 222 case SHA_REG_DIGEST(4): 223 case SHA_REG_DIGEST(5): 224 case SHA_REG_DIGEST(6): 225 case SHA_REG_DIGEST(7): 226 case SHA_REG_DIGEST(8): 227 case SHA_REG_DIGEST(9): 228 case SHA_REG_DIGEST(10): 229 case SHA_REG_DIGEST(11): 230 case SHA_REG_DIGEST(12): 231 case SHA_REG_DIGEST(13): 232 case SHA_REG_DIGEST(14): 233 case SHA_REG_DIGEST(15): 234 if (wr) 235 snprintf(tmp, sz, "IDATAR[%u]", 236 16u + ((offset - SHA_REG_DIGEST(0)) >> 2)); 237 else 238 snprintf(tmp, sz, "ODATAR[%u]", 239 (offset - SHA_REG_DIGEST(0)) >> 2); 240 break; 241 242 case SHA_HW_VERSION: 243 return "HWVER"; 244 245 default: 246 snprintf(tmp, sz, "0x%02x", offset); 247 break; 248 } 249 250 return tmp; 251 } 252 253 #endif /* VERBOSE_DEBUG */ 254 255 static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset) 256 { 257 u32 value = readl_relaxed(dd->io_base + offset); 258 259 #ifdef VERBOSE_DEBUG 260 if (dd->flags & SHA_FLAGS_DUMP_REG) { 261 char tmp[16]; 262 263 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value, 264 atmel_sha_reg_name(offset, tmp, sizeof(tmp), false)); 265 } 266 #endif /* VERBOSE_DEBUG */ 267 268 return value; 269 } 270 271 static inline void atmel_sha_write(struct atmel_sha_dev *dd, 272 u32 offset, u32 value) 273 { 274 #ifdef VERBOSE_DEBUG 275 if (dd->flags & SHA_FLAGS_DUMP_REG) { 276 char tmp[16]; 277 278 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value, 279 atmel_sha_reg_name(offset, tmp, sizeof(tmp), true)); 280 } 281 #endif /* VERBOSE_DEBUG */ 282 283 writel_relaxed(value, dd->io_base + offset); 284 } 285 286 static inline int atmel_sha_complete(struct atmel_sha_dev *dd, int err) 287 { 288 struct ahash_request *req = dd->req; 289 290 dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU | 291 SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY | 292 SHA_FLAGS_DUMP_REG); 293 294 clk_disable(dd->iclk); 295 296 if ((dd->is_async || dd->force_complete) && req->base.complete) 297 req->base.complete(&req->base, err); 298 299 /* handle new request */ 300 tasklet_schedule(&dd->queue_task); 301 302 return err; 303 } 304 305 static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx) 306 { 307 size_t count; 308 309 while ((ctx->bufcnt < ctx->buflen) && ctx->total) { 310 count = min(ctx->sg->length - ctx->offset, ctx->total); 311 count = min(count, ctx->buflen - ctx->bufcnt); 312 313 if (count <= 0) { 314 /* 315 * Check if count <= 0 because the buffer is full or 316 * because the sg length is 0. In the latest case, 317 * check if there is another sg in the list, a 0 length 318 * sg doesn't necessarily mean the end of the sg list. 319 */ 320 if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) { 321 ctx->sg = sg_next(ctx->sg); 322 continue; 323 } else { 324 break; 325 } 326 } 327 328 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg, 329 ctx->offset, count, 0); 330 331 ctx->bufcnt += count; 332 ctx->offset += count; 333 ctx->total -= count; 334 335 if (ctx->offset == ctx->sg->length) { 336 ctx->sg = sg_next(ctx->sg); 337 if (ctx->sg) 338 ctx->offset = 0; 339 else 340 ctx->total = 0; 341 } 342 } 343 344 return 0; 345 } 346 347 /* 348 * The purpose of this padding is to ensure that the padded message is a 349 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512). 350 * The bit "1" is appended at the end of the message followed by 351 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or 352 * 128 bits block (SHA384/SHA512) equals to the message length in bits 353 * is appended. 354 * 355 * For SHA1/SHA224/SHA256, padlen is calculated as followed: 356 * - if message length < 56 bytes then padlen = 56 - message length 357 * - else padlen = 64 + 56 - message length 358 * 359 * For SHA384/SHA512, padlen is calculated as followed: 360 * - if message length < 112 bytes then padlen = 112 - message length 361 * - else padlen = 128 + 112 - message length 362 */ 363 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length) 364 { 365 unsigned int index, padlen; 366 u64 bits[2]; 367 u64 size[2]; 368 369 size[0] = ctx->digcnt[0]; 370 size[1] = ctx->digcnt[1]; 371 372 size[0] += ctx->bufcnt; 373 if (size[0] < ctx->bufcnt) 374 size[1]++; 375 376 size[0] += length; 377 if (size[0] < length) 378 size[1]++; 379 380 bits[1] = cpu_to_be64(size[0] << 3); 381 bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61); 382 383 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { 384 case SHA_FLAGS_SHA384: 385 case SHA_FLAGS_SHA512: 386 index = ctx->bufcnt & 0x7f; 387 padlen = (index < 112) ? (112 - index) : ((128+112) - index); 388 *(ctx->buffer + ctx->bufcnt) = 0x80; 389 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); 390 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16); 391 ctx->bufcnt += padlen + 16; 392 ctx->flags |= SHA_FLAGS_PAD; 393 break; 394 395 default: 396 index = ctx->bufcnt & 0x3f; 397 padlen = (index < 56) ? (56 - index) : ((64+56) - index); 398 *(ctx->buffer + ctx->bufcnt) = 0x80; 399 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1); 400 memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8); 401 ctx->bufcnt += padlen + 8; 402 ctx->flags |= SHA_FLAGS_PAD; 403 break; 404 } 405 } 406 407 static struct atmel_sha_dev *atmel_sha_find_dev(struct atmel_sha_ctx *tctx) 408 { 409 struct atmel_sha_dev *dd = NULL; 410 struct atmel_sha_dev *tmp; 411 412 spin_lock_bh(&atmel_sha.lock); 413 if (!tctx->dd) { 414 list_for_each_entry(tmp, &atmel_sha.dev_list, list) { 415 dd = tmp; 416 break; 417 } 418 tctx->dd = dd; 419 } else { 420 dd = tctx->dd; 421 } 422 423 spin_unlock_bh(&atmel_sha.lock); 424 425 return dd; 426 } 427 428 static int atmel_sha_init(struct ahash_request *req) 429 { 430 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 431 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm); 432 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 433 struct atmel_sha_dev *dd = atmel_sha_find_dev(tctx); 434 435 ctx->dd = dd; 436 437 ctx->flags = 0; 438 439 dev_dbg(dd->dev, "init: digest size: %d\n", 440 crypto_ahash_digestsize(tfm)); 441 442 switch (crypto_ahash_digestsize(tfm)) { 443 case SHA1_DIGEST_SIZE: 444 ctx->flags |= SHA_FLAGS_SHA1; 445 ctx->block_size = SHA1_BLOCK_SIZE; 446 break; 447 case SHA224_DIGEST_SIZE: 448 ctx->flags |= SHA_FLAGS_SHA224; 449 ctx->block_size = SHA224_BLOCK_SIZE; 450 break; 451 case SHA256_DIGEST_SIZE: 452 ctx->flags |= SHA_FLAGS_SHA256; 453 ctx->block_size = SHA256_BLOCK_SIZE; 454 break; 455 case SHA384_DIGEST_SIZE: 456 ctx->flags |= SHA_FLAGS_SHA384; 457 ctx->block_size = SHA384_BLOCK_SIZE; 458 break; 459 case SHA512_DIGEST_SIZE: 460 ctx->flags |= SHA_FLAGS_SHA512; 461 ctx->block_size = SHA512_BLOCK_SIZE; 462 break; 463 default: 464 return -EINVAL; 465 break; 466 } 467 468 ctx->bufcnt = 0; 469 ctx->digcnt[0] = 0; 470 ctx->digcnt[1] = 0; 471 ctx->buflen = SHA_BUFFER_LEN; 472 473 return 0; 474 } 475 476 static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma) 477 { 478 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 479 u32 valmr = SHA_MR_MODE_AUTO; 480 unsigned int i, hashsize = 0; 481 482 if (likely(dma)) { 483 if (!dd->caps.has_dma) 484 atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE); 485 valmr = SHA_MR_MODE_PDC; 486 if (dd->caps.has_dualbuff) 487 valmr |= SHA_MR_DUALBUFF; 488 } else { 489 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); 490 } 491 492 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { 493 case SHA_FLAGS_SHA1: 494 valmr |= SHA_MR_ALGO_SHA1; 495 hashsize = SHA1_DIGEST_SIZE; 496 break; 497 498 case SHA_FLAGS_SHA224: 499 valmr |= SHA_MR_ALGO_SHA224; 500 hashsize = SHA256_DIGEST_SIZE; 501 break; 502 503 case SHA_FLAGS_SHA256: 504 valmr |= SHA_MR_ALGO_SHA256; 505 hashsize = SHA256_DIGEST_SIZE; 506 break; 507 508 case SHA_FLAGS_SHA384: 509 valmr |= SHA_MR_ALGO_SHA384; 510 hashsize = SHA512_DIGEST_SIZE; 511 break; 512 513 case SHA_FLAGS_SHA512: 514 valmr |= SHA_MR_ALGO_SHA512; 515 hashsize = SHA512_DIGEST_SIZE; 516 break; 517 518 default: 519 break; 520 } 521 522 /* Setting CR_FIRST only for the first iteration */ 523 if (!(ctx->digcnt[0] || ctx->digcnt[1])) { 524 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); 525 } else if (dd->caps.has_uihv && (ctx->flags & SHA_FLAGS_RESTORE)) { 526 const u32 *hash = (const u32 *)ctx->digest; 527 528 /* 529 * Restore the hardware context: update the User Initialize 530 * Hash Value (UIHV) with the value saved when the latest 531 * 'update' operation completed on this very same crypto 532 * request. 533 */ 534 ctx->flags &= ~SHA_FLAGS_RESTORE; 535 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV); 536 for (i = 0; i < hashsize / sizeof(u32); ++i) 537 atmel_sha_write(dd, SHA_REG_DIN(i), hash[i]); 538 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); 539 valmr |= SHA_MR_UIHV; 540 } 541 /* 542 * WARNING: If the UIHV feature is not available, the hardware CANNOT 543 * process concurrent requests: the internal registers used to store 544 * the hash/digest are still set to the partial digest output values 545 * computed during the latest round. 546 */ 547 548 atmel_sha_write(dd, SHA_MR, valmr); 549 } 550 551 static inline int atmel_sha_wait_for_data_ready(struct atmel_sha_dev *dd, 552 atmel_sha_fn_t resume) 553 { 554 u32 isr = atmel_sha_read(dd, SHA_ISR); 555 556 if (unlikely(isr & SHA_INT_DATARDY)) 557 return resume(dd); 558 559 dd->resume = resume; 560 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); 561 return -EINPROGRESS; 562 } 563 564 static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf, 565 size_t length, int final) 566 { 567 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 568 int count, len32; 569 const u32 *buffer = (const u32 *)buf; 570 571 dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n", 572 ctx->digcnt[1], ctx->digcnt[0], length, final); 573 574 atmel_sha_write_ctrl(dd, 0); 575 576 /* should be non-zero before next lines to disable clocks later */ 577 ctx->digcnt[0] += length; 578 if (ctx->digcnt[0] < length) 579 ctx->digcnt[1]++; 580 581 if (final) 582 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ 583 584 len32 = DIV_ROUND_UP(length, sizeof(u32)); 585 586 dd->flags |= SHA_FLAGS_CPU; 587 588 for (count = 0; count < len32; count++) 589 atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]); 590 591 return -EINPROGRESS; 592 } 593 594 static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, 595 size_t length1, dma_addr_t dma_addr2, size_t length2, int final) 596 { 597 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 598 int len32; 599 600 dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n", 601 ctx->digcnt[1], ctx->digcnt[0], length1, final); 602 603 len32 = DIV_ROUND_UP(length1, sizeof(u32)); 604 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS); 605 atmel_sha_write(dd, SHA_TPR, dma_addr1); 606 atmel_sha_write(dd, SHA_TCR, len32); 607 608 len32 = DIV_ROUND_UP(length2, sizeof(u32)); 609 atmel_sha_write(dd, SHA_TNPR, dma_addr2); 610 atmel_sha_write(dd, SHA_TNCR, len32); 611 612 atmel_sha_write_ctrl(dd, 1); 613 614 /* should be non-zero before next lines to disable clocks later */ 615 ctx->digcnt[0] += length1; 616 if (ctx->digcnt[0] < length1) 617 ctx->digcnt[1]++; 618 619 if (final) 620 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ 621 622 dd->flags |= SHA_FLAGS_DMA_ACTIVE; 623 624 /* Start DMA transfer */ 625 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN); 626 627 return -EINPROGRESS; 628 } 629 630 static void atmel_sha_dma_callback(void *data) 631 { 632 struct atmel_sha_dev *dd = data; 633 634 dd->is_async = true; 635 636 /* dma_lch_in - completed - wait DATRDY */ 637 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); 638 } 639 640 static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, 641 size_t length1, dma_addr_t dma_addr2, size_t length2, int final) 642 { 643 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 644 struct dma_async_tx_descriptor *in_desc; 645 struct scatterlist sg[2]; 646 647 dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n", 648 ctx->digcnt[1], ctx->digcnt[0], length1, final); 649 650 dd->dma_lch_in.dma_conf.src_maxburst = 16; 651 dd->dma_lch_in.dma_conf.dst_maxburst = 16; 652 653 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf); 654 655 if (length2) { 656 sg_init_table(sg, 2); 657 sg_dma_address(&sg[0]) = dma_addr1; 658 sg_dma_len(&sg[0]) = length1; 659 sg_dma_address(&sg[1]) = dma_addr2; 660 sg_dma_len(&sg[1]) = length2; 661 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2, 662 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 663 } else { 664 sg_init_table(sg, 1); 665 sg_dma_address(&sg[0]) = dma_addr1; 666 sg_dma_len(&sg[0]) = length1; 667 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1, 668 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 669 } 670 if (!in_desc) 671 return atmel_sha_complete(dd, -EINVAL); 672 673 in_desc->callback = atmel_sha_dma_callback; 674 in_desc->callback_param = dd; 675 676 atmel_sha_write_ctrl(dd, 1); 677 678 /* should be non-zero before next lines to disable clocks later */ 679 ctx->digcnt[0] += length1; 680 if (ctx->digcnt[0] < length1) 681 ctx->digcnt[1]++; 682 683 if (final) 684 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */ 685 686 dd->flags |= SHA_FLAGS_DMA_ACTIVE; 687 688 /* Start DMA transfer */ 689 dmaengine_submit(in_desc); 690 dma_async_issue_pending(dd->dma_lch_in.chan); 691 692 return -EINPROGRESS; 693 } 694 695 static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1, 696 size_t length1, dma_addr_t dma_addr2, size_t length2, int final) 697 { 698 if (dd->caps.has_dma) 699 return atmel_sha_xmit_dma(dd, dma_addr1, length1, 700 dma_addr2, length2, final); 701 else 702 return atmel_sha_xmit_pdc(dd, dma_addr1, length1, 703 dma_addr2, length2, final); 704 } 705 706 static int atmel_sha_update_cpu(struct atmel_sha_dev *dd) 707 { 708 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 709 int bufcnt; 710 711 atmel_sha_append_sg(ctx); 712 atmel_sha_fill_padding(ctx, 0); 713 bufcnt = ctx->bufcnt; 714 ctx->bufcnt = 0; 715 716 return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1); 717 } 718 719 static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd, 720 struct atmel_sha_reqctx *ctx, 721 size_t length, int final) 722 { 723 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, 724 ctx->buflen + ctx->block_size, DMA_TO_DEVICE); 725 if (dma_mapping_error(dd->dev, ctx->dma_addr)) { 726 dev_err(dd->dev, "dma %zu bytes error\n", ctx->buflen + 727 ctx->block_size); 728 return atmel_sha_complete(dd, -EINVAL); 729 } 730 731 ctx->flags &= ~SHA_FLAGS_SG; 732 733 /* next call does not fail... so no unmap in the case of error */ 734 return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final); 735 } 736 737 static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd) 738 { 739 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 740 unsigned int final; 741 size_t count; 742 743 atmel_sha_append_sg(ctx); 744 745 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; 746 747 dev_dbg(dd->dev, "slow: bufcnt: %zu, digcnt: 0x%llx 0x%llx, final: %d\n", 748 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final); 749 750 if (final) 751 atmel_sha_fill_padding(ctx, 0); 752 753 if (final || (ctx->bufcnt == ctx->buflen)) { 754 count = ctx->bufcnt; 755 ctx->bufcnt = 0; 756 return atmel_sha_xmit_dma_map(dd, ctx, count, final); 757 } 758 759 return 0; 760 } 761 762 static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd) 763 { 764 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 765 unsigned int length, final, tail; 766 struct scatterlist *sg; 767 unsigned int count; 768 769 if (!ctx->total) 770 return 0; 771 772 if (ctx->bufcnt || ctx->offset) 773 return atmel_sha_update_dma_slow(dd); 774 775 dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %zd, total: %u\n", 776 ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total); 777 778 sg = ctx->sg; 779 780 if (!IS_ALIGNED(sg->offset, sizeof(u32))) 781 return atmel_sha_update_dma_slow(dd); 782 783 if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size)) 784 /* size is not ctx->block_size aligned */ 785 return atmel_sha_update_dma_slow(dd); 786 787 length = min(ctx->total, sg->length); 788 789 if (sg_is_last(sg)) { 790 if (!(ctx->flags & SHA_FLAGS_FINUP)) { 791 /* not last sg must be ctx->block_size aligned */ 792 tail = length & (ctx->block_size - 1); 793 length -= tail; 794 } 795 } 796 797 ctx->total -= length; 798 ctx->offset = length; /* offset where to start slow */ 799 800 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total; 801 802 /* Add padding */ 803 if (final) { 804 tail = length & (ctx->block_size - 1); 805 length -= tail; 806 ctx->total += tail; 807 ctx->offset = length; /* offset where to start slow */ 808 809 sg = ctx->sg; 810 atmel_sha_append_sg(ctx); 811 812 atmel_sha_fill_padding(ctx, length); 813 814 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, 815 ctx->buflen + ctx->block_size, DMA_TO_DEVICE); 816 if (dma_mapping_error(dd->dev, ctx->dma_addr)) { 817 dev_err(dd->dev, "dma %zu bytes error\n", 818 ctx->buflen + ctx->block_size); 819 return atmel_sha_complete(dd, -EINVAL); 820 } 821 822 if (length == 0) { 823 ctx->flags &= ~SHA_FLAGS_SG; 824 count = ctx->bufcnt; 825 ctx->bufcnt = 0; 826 return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0, 827 0, final); 828 } else { 829 ctx->sg = sg; 830 if (!dma_map_sg(dd->dev, ctx->sg, 1, 831 DMA_TO_DEVICE)) { 832 dev_err(dd->dev, "dma_map_sg error\n"); 833 return atmel_sha_complete(dd, -EINVAL); 834 } 835 836 ctx->flags |= SHA_FLAGS_SG; 837 838 count = ctx->bufcnt; 839 ctx->bufcnt = 0; 840 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), 841 length, ctx->dma_addr, count, final); 842 } 843 } 844 845 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { 846 dev_err(dd->dev, "dma_map_sg error\n"); 847 return atmel_sha_complete(dd, -EINVAL); 848 } 849 850 ctx->flags |= SHA_FLAGS_SG; 851 852 /* next call does not fail... so no unmap in the case of error */ 853 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0, 854 0, final); 855 } 856 857 static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd) 858 { 859 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req); 860 861 if (ctx->flags & SHA_FLAGS_SG) { 862 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); 863 if (ctx->sg->length == ctx->offset) { 864 ctx->sg = sg_next(ctx->sg); 865 if (ctx->sg) 866 ctx->offset = 0; 867 } 868 if (ctx->flags & SHA_FLAGS_PAD) { 869 dma_unmap_single(dd->dev, ctx->dma_addr, 870 ctx->buflen + ctx->block_size, DMA_TO_DEVICE); 871 } 872 } else { 873 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen + 874 ctx->block_size, DMA_TO_DEVICE); 875 } 876 877 return 0; 878 } 879 880 static int atmel_sha_update_req(struct atmel_sha_dev *dd) 881 { 882 struct ahash_request *req = dd->req; 883 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 884 int err; 885 886 dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n", 887 ctx->total, ctx->digcnt[1], ctx->digcnt[0]); 888 889 if (ctx->flags & SHA_FLAGS_CPU) 890 err = atmel_sha_update_cpu(dd); 891 else 892 err = atmel_sha_update_dma_start(dd); 893 894 /* wait for dma completion before can take more data */ 895 dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n", 896 err, ctx->digcnt[1], ctx->digcnt[0]); 897 898 return err; 899 } 900 901 static int atmel_sha_final_req(struct atmel_sha_dev *dd) 902 { 903 struct ahash_request *req = dd->req; 904 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 905 int err = 0; 906 int count; 907 908 if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) { 909 atmel_sha_fill_padding(ctx, 0); 910 count = ctx->bufcnt; 911 ctx->bufcnt = 0; 912 err = atmel_sha_xmit_dma_map(dd, ctx, count, 1); 913 } 914 /* faster to handle last block with cpu */ 915 else { 916 atmel_sha_fill_padding(ctx, 0); 917 count = ctx->bufcnt; 918 ctx->bufcnt = 0; 919 err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1); 920 } 921 922 dev_dbg(dd->dev, "final_req: err: %d\n", err); 923 924 return err; 925 } 926 927 static void atmel_sha_copy_hash(struct ahash_request *req) 928 { 929 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 930 u32 *hash = (u32 *)ctx->digest; 931 unsigned int i, hashsize; 932 933 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { 934 case SHA_FLAGS_SHA1: 935 hashsize = SHA1_DIGEST_SIZE; 936 break; 937 938 case SHA_FLAGS_SHA224: 939 case SHA_FLAGS_SHA256: 940 hashsize = SHA256_DIGEST_SIZE; 941 break; 942 943 case SHA_FLAGS_SHA384: 944 case SHA_FLAGS_SHA512: 945 hashsize = SHA512_DIGEST_SIZE; 946 break; 947 948 default: 949 /* Should not happen... */ 950 return; 951 } 952 953 for (i = 0; i < hashsize / sizeof(u32); ++i) 954 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i)); 955 ctx->flags |= SHA_FLAGS_RESTORE; 956 } 957 958 static void atmel_sha_copy_ready_hash(struct ahash_request *req) 959 { 960 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 961 962 if (!req->result) 963 return; 964 965 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { 966 default: 967 case SHA_FLAGS_SHA1: 968 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE); 969 break; 970 971 case SHA_FLAGS_SHA224: 972 memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE); 973 break; 974 975 case SHA_FLAGS_SHA256: 976 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE); 977 break; 978 979 case SHA_FLAGS_SHA384: 980 memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE); 981 break; 982 983 case SHA_FLAGS_SHA512: 984 memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE); 985 break; 986 } 987 } 988 989 static int atmel_sha_finish(struct ahash_request *req) 990 { 991 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 992 struct atmel_sha_dev *dd = ctx->dd; 993 994 if (ctx->digcnt[0] || ctx->digcnt[1]) 995 atmel_sha_copy_ready_hash(req); 996 997 dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %zd\n", ctx->digcnt[1], 998 ctx->digcnt[0], ctx->bufcnt); 999 1000 return 0; 1001 } 1002 1003 static void atmel_sha_finish_req(struct ahash_request *req, int err) 1004 { 1005 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1006 struct atmel_sha_dev *dd = ctx->dd; 1007 1008 if (!err) { 1009 atmel_sha_copy_hash(req); 1010 if (SHA_FLAGS_FINAL & dd->flags) 1011 err = atmel_sha_finish(req); 1012 } else { 1013 ctx->flags |= SHA_FLAGS_ERROR; 1014 } 1015 1016 /* atomic operation is not needed here */ 1017 (void)atmel_sha_complete(dd, err); 1018 } 1019 1020 static int atmel_sha_hw_init(struct atmel_sha_dev *dd) 1021 { 1022 int err; 1023 1024 err = clk_enable(dd->iclk); 1025 if (err) 1026 return err; 1027 1028 if (!(SHA_FLAGS_INIT & dd->flags)) { 1029 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST); 1030 dd->flags |= SHA_FLAGS_INIT; 1031 dd->err = 0; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd) 1038 { 1039 return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff; 1040 } 1041 1042 static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd) 1043 { 1044 atmel_sha_hw_init(dd); 1045 1046 dd->hw_version = atmel_sha_get_version(dd); 1047 1048 dev_info(dd->dev, 1049 "version: 0x%x\n", dd->hw_version); 1050 1051 clk_disable(dd->iclk); 1052 } 1053 1054 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd, 1055 struct ahash_request *req) 1056 { 1057 struct crypto_async_request *async_req, *backlog; 1058 struct atmel_sha_ctx *ctx; 1059 unsigned long flags; 1060 bool start_async; 1061 int err = 0, ret = 0; 1062 1063 spin_lock_irqsave(&dd->lock, flags); 1064 if (req) 1065 ret = ahash_enqueue_request(&dd->queue, req); 1066 1067 if (SHA_FLAGS_BUSY & dd->flags) { 1068 spin_unlock_irqrestore(&dd->lock, flags); 1069 return ret; 1070 } 1071 1072 backlog = crypto_get_backlog(&dd->queue); 1073 async_req = crypto_dequeue_request(&dd->queue); 1074 if (async_req) 1075 dd->flags |= SHA_FLAGS_BUSY; 1076 1077 spin_unlock_irqrestore(&dd->lock, flags); 1078 1079 if (!async_req) 1080 return ret; 1081 1082 if (backlog) 1083 backlog->complete(backlog, -EINPROGRESS); 1084 1085 ctx = crypto_tfm_ctx(async_req->tfm); 1086 1087 dd->req = ahash_request_cast(async_req); 1088 start_async = (dd->req != req); 1089 dd->is_async = start_async; 1090 dd->force_complete = false; 1091 1092 /* WARNING: ctx->start() MAY change dd->is_async. */ 1093 err = ctx->start(dd); 1094 return (start_async) ? ret : err; 1095 } 1096 1097 static int atmel_sha_done(struct atmel_sha_dev *dd); 1098 1099 static int atmel_sha_start(struct atmel_sha_dev *dd) 1100 { 1101 struct ahash_request *req = dd->req; 1102 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1103 int err; 1104 1105 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1106 ctx->op, req->nbytes); 1107 1108 err = atmel_sha_hw_init(dd); 1109 if (err) 1110 return atmel_sha_complete(dd, err); 1111 1112 /* 1113 * atmel_sha_update_req() and atmel_sha_final_req() can return either: 1114 * -EINPROGRESS: the hardware is busy and the SHA driver will resume 1115 * its job later in the done_task. 1116 * This is the main path. 1117 * 1118 * 0: the SHA driver can continue its job then release the hardware 1119 * later, if needed, with atmel_sha_finish_req(). 1120 * This is the alternate path. 1121 * 1122 * < 0: an error has occurred so atmel_sha_complete(dd, err) has already 1123 * been called, hence the hardware has been released. 1124 * The SHA driver must stop its job without calling 1125 * atmel_sha_finish_req(), otherwise atmel_sha_complete() would be 1126 * called a second time. 1127 * 1128 * Please note that currently, atmel_sha_final_req() never returns 0. 1129 */ 1130 1131 dd->resume = atmel_sha_done; 1132 if (ctx->op == SHA_OP_UPDATE) { 1133 err = atmel_sha_update_req(dd); 1134 if (!err && (ctx->flags & SHA_FLAGS_FINUP)) 1135 /* no final() after finup() */ 1136 err = atmel_sha_final_req(dd); 1137 } else if (ctx->op == SHA_OP_FINAL) { 1138 err = atmel_sha_final_req(dd); 1139 } 1140 1141 if (!err) 1142 /* done_task will not finish it, so do it here */ 1143 atmel_sha_finish_req(req, err); 1144 1145 dev_dbg(dd->dev, "exit, err: %d\n", err); 1146 1147 return err; 1148 } 1149 1150 static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op) 1151 { 1152 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1153 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1154 struct atmel_sha_dev *dd = tctx->dd; 1155 1156 ctx->op = op; 1157 1158 return atmel_sha_handle_queue(dd, req); 1159 } 1160 1161 static int atmel_sha_update(struct ahash_request *req) 1162 { 1163 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1164 1165 if (!req->nbytes) 1166 return 0; 1167 1168 ctx->total = req->nbytes; 1169 ctx->sg = req->src; 1170 ctx->offset = 0; 1171 1172 if (ctx->flags & SHA_FLAGS_FINUP) { 1173 if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD) 1174 /* faster to use CPU for short transfers */ 1175 ctx->flags |= SHA_FLAGS_CPU; 1176 } else if (ctx->bufcnt + ctx->total < ctx->buflen) { 1177 atmel_sha_append_sg(ctx); 1178 return 0; 1179 } 1180 return atmel_sha_enqueue(req, SHA_OP_UPDATE); 1181 } 1182 1183 static int atmel_sha_final(struct ahash_request *req) 1184 { 1185 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1186 1187 ctx->flags |= SHA_FLAGS_FINUP; 1188 1189 if (ctx->flags & SHA_FLAGS_ERROR) 1190 return 0; /* uncompleted hash is not needed */ 1191 1192 if (ctx->flags & SHA_FLAGS_PAD) 1193 /* copy ready hash (+ finalize hmac) */ 1194 return atmel_sha_finish(req); 1195 1196 return atmel_sha_enqueue(req, SHA_OP_FINAL); 1197 } 1198 1199 static int atmel_sha_finup(struct ahash_request *req) 1200 { 1201 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1202 int err1, err2; 1203 1204 ctx->flags |= SHA_FLAGS_FINUP; 1205 1206 err1 = atmel_sha_update(req); 1207 if (err1 == -EINPROGRESS || 1208 (err1 == -EBUSY && (ahash_request_flags(req) & 1209 CRYPTO_TFM_REQ_MAY_BACKLOG))) 1210 return err1; 1211 1212 /* 1213 * final() has to be always called to cleanup resources 1214 * even if udpate() failed, except EINPROGRESS 1215 */ 1216 err2 = atmel_sha_final(req); 1217 1218 return err1 ?: err2; 1219 } 1220 1221 static int atmel_sha_digest(struct ahash_request *req) 1222 { 1223 return atmel_sha_init(req) ?: atmel_sha_finup(req); 1224 } 1225 1226 1227 static int atmel_sha_export(struct ahash_request *req, void *out) 1228 { 1229 const struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1230 1231 memcpy(out, ctx, sizeof(*ctx)); 1232 return 0; 1233 } 1234 1235 static int atmel_sha_import(struct ahash_request *req, const void *in) 1236 { 1237 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1238 1239 memcpy(ctx, in, sizeof(*ctx)); 1240 return 0; 1241 } 1242 1243 static int atmel_sha_cra_init(struct crypto_tfm *tfm) 1244 { 1245 struct atmel_sha_ctx *ctx = crypto_tfm_ctx(tfm); 1246 1247 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1248 sizeof(struct atmel_sha_reqctx)); 1249 ctx->start = atmel_sha_start; 1250 1251 return 0; 1252 } 1253 1254 static struct ahash_alg sha_1_256_algs[] = { 1255 { 1256 .init = atmel_sha_init, 1257 .update = atmel_sha_update, 1258 .final = atmel_sha_final, 1259 .finup = atmel_sha_finup, 1260 .digest = atmel_sha_digest, 1261 .export = atmel_sha_export, 1262 .import = atmel_sha_import, 1263 .halg = { 1264 .digestsize = SHA1_DIGEST_SIZE, 1265 .statesize = sizeof(struct atmel_sha_reqctx), 1266 .base = { 1267 .cra_name = "sha1", 1268 .cra_driver_name = "atmel-sha1", 1269 .cra_priority = 100, 1270 .cra_flags = CRYPTO_ALG_ASYNC, 1271 .cra_blocksize = SHA1_BLOCK_SIZE, 1272 .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1273 .cra_alignmask = 0, 1274 .cra_module = THIS_MODULE, 1275 .cra_init = atmel_sha_cra_init, 1276 } 1277 } 1278 }, 1279 { 1280 .init = atmel_sha_init, 1281 .update = atmel_sha_update, 1282 .final = atmel_sha_final, 1283 .finup = atmel_sha_finup, 1284 .digest = atmel_sha_digest, 1285 .export = atmel_sha_export, 1286 .import = atmel_sha_import, 1287 .halg = { 1288 .digestsize = SHA256_DIGEST_SIZE, 1289 .statesize = sizeof(struct atmel_sha_reqctx), 1290 .base = { 1291 .cra_name = "sha256", 1292 .cra_driver_name = "atmel-sha256", 1293 .cra_priority = 100, 1294 .cra_flags = CRYPTO_ALG_ASYNC, 1295 .cra_blocksize = SHA256_BLOCK_SIZE, 1296 .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1297 .cra_alignmask = 0, 1298 .cra_module = THIS_MODULE, 1299 .cra_init = atmel_sha_cra_init, 1300 } 1301 } 1302 }, 1303 }; 1304 1305 static struct ahash_alg sha_224_alg = { 1306 .init = atmel_sha_init, 1307 .update = atmel_sha_update, 1308 .final = atmel_sha_final, 1309 .finup = atmel_sha_finup, 1310 .digest = atmel_sha_digest, 1311 .export = atmel_sha_export, 1312 .import = atmel_sha_import, 1313 .halg = { 1314 .digestsize = SHA224_DIGEST_SIZE, 1315 .statesize = sizeof(struct atmel_sha_reqctx), 1316 .base = { 1317 .cra_name = "sha224", 1318 .cra_driver_name = "atmel-sha224", 1319 .cra_priority = 100, 1320 .cra_flags = CRYPTO_ALG_ASYNC, 1321 .cra_blocksize = SHA224_BLOCK_SIZE, 1322 .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1323 .cra_alignmask = 0, 1324 .cra_module = THIS_MODULE, 1325 .cra_init = atmel_sha_cra_init, 1326 } 1327 } 1328 }; 1329 1330 static struct ahash_alg sha_384_512_algs[] = { 1331 { 1332 .init = atmel_sha_init, 1333 .update = atmel_sha_update, 1334 .final = atmel_sha_final, 1335 .finup = atmel_sha_finup, 1336 .digest = atmel_sha_digest, 1337 .export = atmel_sha_export, 1338 .import = atmel_sha_import, 1339 .halg = { 1340 .digestsize = SHA384_DIGEST_SIZE, 1341 .statesize = sizeof(struct atmel_sha_reqctx), 1342 .base = { 1343 .cra_name = "sha384", 1344 .cra_driver_name = "atmel-sha384", 1345 .cra_priority = 100, 1346 .cra_flags = CRYPTO_ALG_ASYNC, 1347 .cra_blocksize = SHA384_BLOCK_SIZE, 1348 .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1349 .cra_alignmask = 0x3, 1350 .cra_module = THIS_MODULE, 1351 .cra_init = atmel_sha_cra_init, 1352 } 1353 } 1354 }, 1355 { 1356 .init = atmel_sha_init, 1357 .update = atmel_sha_update, 1358 .final = atmel_sha_final, 1359 .finup = atmel_sha_finup, 1360 .digest = atmel_sha_digest, 1361 .export = atmel_sha_export, 1362 .import = atmel_sha_import, 1363 .halg = { 1364 .digestsize = SHA512_DIGEST_SIZE, 1365 .statesize = sizeof(struct atmel_sha_reqctx), 1366 .base = { 1367 .cra_name = "sha512", 1368 .cra_driver_name = "atmel-sha512", 1369 .cra_priority = 100, 1370 .cra_flags = CRYPTO_ALG_ASYNC, 1371 .cra_blocksize = SHA512_BLOCK_SIZE, 1372 .cra_ctxsize = sizeof(struct atmel_sha_ctx), 1373 .cra_alignmask = 0x3, 1374 .cra_module = THIS_MODULE, 1375 .cra_init = atmel_sha_cra_init, 1376 } 1377 } 1378 }, 1379 }; 1380 1381 static void atmel_sha_queue_task(unsigned long data) 1382 { 1383 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; 1384 1385 atmel_sha_handle_queue(dd, NULL); 1386 } 1387 1388 static int atmel_sha_done(struct atmel_sha_dev *dd) 1389 { 1390 int err = 0; 1391 1392 if (SHA_FLAGS_CPU & dd->flags) { 1393 if (SHA_FLAGS_OUTPUT_READY & dd->flags) { 1394 dd->flags &= ~SHA_FLAGS_OUTPUT_READY; 1395 goto finish; 1396 } 1397 } else if (SHA_FLAGS_DMA_READY & dd->flags) { 1398 if (SHA_FLAGS_DMA_ACTIVE & dd->flags) { 1399 dd->flags &= ~SHA_FLAGS_DMA_ACTIVE; 1400 atmel_sha_update_dma_stop(dd); 1401 if (dd->err) { 1402 err = dd->err; 1403 goto finish; 1404 } 1405 } 1406 if (SHA_FLAGS_OUTPUT_READY & dd->flags) { 1407 /* hash or semi-hash ready */ 1408 dd->flags &= ~(SHA_FLAGS_DMA_READY | 1409 SHA_FLAGS_OUTPUT_READY); 1410 err = atmel_sha_update_dma_start(dd); 1411 if (err != -EINPROGRESS) 1412 goto finish; 1413 } 1414 } 1415 return err; 1416 1417 finish: 1418 /* finish curent request */ 1419 atmel_sha_finish_req(dd->req, err); 1420 1421 return err; 1422 } 1423 1424 static void atmel_sha_done_task(unsigned long data) 1425 { 1426 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data; 1427 1428 dd->is_async = true; 1429 (void)dd->resume(dd); 1430 } 1431 1432 static irqreturn_t atmel_sha_irq(int irq, void *dev_id) 1433 { 1434 struct atmel_sha_dev *sha_dd = dev_id; 1435 u32 reg; 1436 1437 reg = atmel_sha_read(sha_dd, SHA_ISR); 1438 if (reg & atmel_sha_read(sha_dd, SHA_IMR)) { 1439 atmel_sha_write(sha_dd, SHA_IDR, reg); 1440 if (SHA_FLAGS_BUSY & sha_dd->flags) { 1441 sha_dd->flags |= SHA_FLAGS_OUTPUT_READY; 1442 if (!(SHA_FLAGS_CPU & sha_dd->flags)) 1443 sha_dd->flags |= SHA_FLAGS_DMA_READY; 1444 tasklet_schedule(&sha_dd->done_task); 1445 } else { 1446 dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n"); 1447 } 1448 return IRQ_HANDLED; 1449 } 1450 1451 return IRQ_NONE; 1452 } 1453 1454 1455 /* DMA transfer functions */ 1456 1457 static bool atmel_sha_dma_check_aligned(struct atmel_sha_dev *dd, 1458 struct scatterlist *sg, 1459 size_t len) 1460 { 1461 struct atmel_sha_dma *dma = &dd->dma_lch_in; 1462 struct ahash_request *req = dd->req; 1463 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1464 size_t bs = ctx->block_size; 1465 int nents; 1466 1467 for (nents = 0; sg; sg = sg_next(sg), ++nents) { 1468 if (!IS_ALIGNED(sg->offset, sizeof(u32))) 1469 return false; 1470 1471 /* 1472 * This is the last sg, the only one that is allowed to 1473 * have an unaligned length. 1474 */ 1475 if (len <= sg->length) { 1476 dma->nents = nents + 1; 1477 dma->last_sg_length = sg->length; 1478 sg->length = ALIGN(len, sizeof(u32)); 1479 return true; 1480 } 1481 1482 /* All other sg lengths MUST be aligned to the block size. */ 1483 if (!IS_ALIGNED(sg->length, bs)) 1484 return false; 1485 1486 len -= sg->length; 1487 } 1488 1489 return false; 1490 } 1491 1492 static void atmel_sha_dma_callback2(void *data) 1493 { 1494 struct atmel_sha_dev *dd = data; 1495 struct atmel_sha_dma *dma = &dd->dma_lch_in; 1496 struct scatterlist *sg; 1497 int nents; 1498 1499 dmaengine_terminate_all(dma->chan); 1500 dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE); 1501 1502 sg = dma->sg; 1503 for (nents = 0; nents < dma->nents - 1; ++nents) 1504 sg = sg_next(sg); 1505 sg->length = dma->last_sg_length; 1506 1507 dd->is_async = true; 1508 (void)atmel_sha_wait_for_data_ready(dd, dd->resume); 1509 } 1510 1511 static int atmel_sha_dma_start(struct atmel_sha_dev *dd, 1512 struct scatterlist *src, 1513 size_t len, 1514 atmel_sha_fn_t resume) 1515 { 1516 struct atmel_sha_dma *dma = &dd->dma_lch_in; 1517 struct dma_slave_config *config = &dma->dma_conf; 1518 struct dma_chan *chan = dma->chan; 1519 struct dma_async_tx_descriptor *desc; 1520 dma_cookie_t cookie; 1521 unsigned int sg_len; 1522 int err; 1523 1524 dd->resume = resume; 1525 1526 /* 1527 * dma->nents has already been initialized by 1528 * atmel_sha_dma_check_aligned(). 1529 */ 1530 dma->sg = src; 1531 sg_len = dma_map_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE); 1532 if (!sg_len) { 1533 err = -ENOMEM; 1534 goto exit; 1535 } 1536 1537 config->src_maxburst = 16; 1538 config->dst_maxburst = 16; 1539 err = dmaengine_slave_config(chan, config); 1540 if (err) 1541 goto unmap_sg; 1542 1543 desc = dmaengine_prep_slave_sg(chan, dma->sg, sg_len, DMA_MEM_TO_DEV, 1544 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1545 if (!desc) { 1546 err = -ENOMEM; 1547 goto unmap_sg; 1548 } 1549 1550 desc->callback = atmel_sha_dma_callback2; 1551 desc->callback_param = dd; 1552 cookie = dmaengine_submit(desc); 1553 err = dma_submit_error(cookie); 1554 if (err) 1555 goto unmap_sg; 1556 1557 dma_async_issue_pending(chan); 1558 1559 return -EINPROGRESS; 1560 1561 unmap_sg: 1562 dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE); 1563 exit: 1564 return atmel_sha_complete(dd, err); 1565 } 1566 1567 1568 /* CPU transfer functions */ 1569 1570 static int atmel_sha_cpu_transfer(struct atmel_sha_dev *dd) 1571 { 1572 struct ahash_request *req = dd->req; 1573 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1574 const u32 *words = (const u32 *)ctx->buffer; 1575 size_t i, num_words; 1576 u32 isr, din, din_inc; 1577 1578 din_inc = (ctx->flags & SHA_FLAGS_IDATAR0) ? 0 : 1; 1579 for (;;) { 1580 /* Write data into the Input Data Registers. */ 1581 num_words = DIV_ROUND_UP(ctx->bufcnt, sizeof(u32)); 1582 for (i = 0, din = 0; i < num_words; ++i, din += din_inc) 1583 atmel_sha_write(dd, SHA_REG_DIN(din), words[i]); 1584 1585 ctx->offset += ctx->bufcnt; 1586 ctx->total -= ctx->bufcnt; 1587 1588 if (!ctx->total) 1589 break; 1590 1591 /* 1592 * Prepare next block: 1593 * Fill ctx->buffer now with the next data to be written into 1594 * IDATARx: it gives time for the SHA hardware to process 1595 * the current data so the SHA_INT_DATARDY flag might be set 1596 * in SHA_ISR when polling this register at the beginning of 1597 * the next loop. 1598 */ 1599 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total); 1600 scatterwalk_map_and_copy(ctx->buffer, ctx->sg, 1601 ctx->offset, ctx->bufcnt, 0); 1602 1603 /* Wait for hardware to be ready again. */ 1604 isr = atmel_sha_read(dd, SHA_ISR); 1605 if (!(isr & SHA_INT_DATARDY)) { 1606 /* Not ready yet. */ 1607 dd->resume = atmel_sha_cpu_transfer; 1608 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY); 1609 return -EINPROGRESS; 1610 } 1611 } 1612 1613 if (unlikely(!(ctx->flags & SHA_FLAGS_WAIT_DATARDY))) 1614 return dd->cpu_transfer_complete(dd); 1615 1616 return atmel_sha_wait_for_data_ready(dd, dd->cpu_transfer_complete); 1617 } 1618 1619 static int atmel_sha_cpu_start(struct atmel_sha_dev *dd, 1620 struct scatterlist *sg, 1621 unsigned int len, 1622 bool idatar0_only, 1623 bool wait_data_ready, 1624 atmel_sha_fn_t resume) 1625 { 1626 struct ahash_request *req = dd->req; 1627 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1628 1629 if (!len) 1630 return resume(dd); 1631 1632 ctx->flags &= ~(SHA_FLAGS_IDATAR0 | SHA_FLAGS_WAIT_DATARDY); 1633 1634 if (idatar0_only) 1635 ctx->flags |= SHA_FLAGS_IDATAR0; 1636 1637 if (wait_data_ready) 1638 ctx->flags |= SHA_FLAGS_WAIT_DATARDY; 1639 1640 ctx->sg = sg; 1641 ctx->total = len; 1642 ctx->offset = 0; 1643 1644 /* Prepare the first block to be written. */ 1645 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total); 1646 scatterwalk_map_and_copy(ctx->buffer, ctx->sg, 1647 ctx->offset, ctx->bufcnt, 0); 1648 1649 dd->cpu_transfer_complete = resume; 1650 return atmel_sha_cpu_transfer(dd); 1651 } 1652 1653 static int atmel_sha_cpu_hash(struct atmel_sha_dev *dd, 1654 const void *data, unsigned int datalen, 1655 bool auto_padding, 1656 atmel_sha_fn_t resume) 1657 { 1658 struct ahash_request *req = dd->req; 1659 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1660 u32 msglen = (auto_padding) ? datalen : 0; 1661 u32 mr = SHA_MR_MODE_AUTO; 1662 1663 if (!(IS_ALIGNED(datalen, ctx->block_size) || auto_padding)) 1664 return atmel_sha_complete(dd, -EINVAL); 1665 1666 mr |= (ctx->flags & SHA_FLAGS_ALGO_MASK); 1667 atmel_sha_write(dd, SHA_MR, mr); 1668 atmel_sha_write(dd, SHA_MSR, msglen); 1669 atmel_sha_write(dd, SHA_BCR, msglen); 1670 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); 1671 1672 sg_init_one(&dd->tmp, data, datalen); 1673 return atmel_sha_cpu_start(dd, &dd->tmp, datalen, false, true, resume); 1674 } 1675 1676 1677 /* hmac functions */ 1678 1679 struct atmel_sha_hmac_key { 1680 bool valid; 1681 unsigned int keylen; 1682 u8 buffer[SHA512_BLOCK_SIZE]; 1683 u8 *keydup; 1684 }; 1685 1686 static inline void atmel_sha_hmac_key_init(struct atmel_sha_hmac_key *hkey) 1687 { 1688 memset(hkey, 0, sizeof(*hkey)); 1689 } 1690 1691 static inline void atmel_sha_hmac_key_release(struct atmel_sha_hmac_key *hkey) 1692 { 1693 kfree(hkey->keydup); 1694 memset(hkey, 0, sizeof(*hkey)); 1695 } 1696 1697 static inline int atmel_sha_hmac_key_set(struct atmel_sha_hmac_key *hkey, 1698 const u8 *key, 1699 unsigned int keylen) 1700 { 1701 atmel_sha_hmac_key_release(hkey); 1702 1703 if (keylen > sizeof(hkey->buffer)) { 1704 hkey->keydup = kmemdup(key, keylen, GFP_KERNEL); 1705 if (!hkey->keydup) 1706 return -ENOMEM; 1707 1708 } else { 1709 memcpy(hkey->buffer, key, keylen); 1710 } 1711 1712 hkey->valid = true; 1713 hkey->keylen = keylen; 1714 return 0; 1715 } 1716 1717 static inline bool atmel_sha_hmac_key_get(const struct atmel_sha_hmac_key *hkey, 1718 const u8 **key, 1719 unsigned int *keylen) 1720 { 1721 if (!hkey->valid) 1722 return false; 1723 1724 *keylen = hkey->keylen; 1725 *key = (hkey->keydup) ? hkey->keydup : hkey->buffer; 1726 return true; 1727 } 1728 1729 1730 struct atmel_sha_hmac_ctx { 1731 struct atmel_sha_ctx base; 1732 1733 struct atmel_sha_hmac_key hkey; 1734 u32 ipad[SHA512_BLOCK_SIZE / sizeof(u32)]; 1735 u32 opad[SHA512_BLOCK_SIZE / sizeof(u32)]; 1736 atmel_sha_fn_t resume; 1737 }; 1738 1739 static int atmel_sha_hmac_setup(struct atmel_sha_dev *dd, 1740 atmel_sha_fn_t resume); 1741 static int atmel_sha_hmac_prehash_key(struct atmel_sha_dev *dd, 1742 const u8 *key, unsigned int keylen); 1743 static int atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev *dd); 1744 static int atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev *dd); 1745 static int atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev *dd); 1746 static int atmel_sha_hmac_setup_done(struct atmel_sha_dev *dd); 1747 1748 static int atmel_sha_hmac_init_done(struct atmel_sha_dev *dd); 1749 static int atmel_sha_hmac_final(struct atmel_sha_dev *dd); 1750 static int atmel_sha_hmac_final_done(struct atmel_sha_dev *dd); 1751 static int atmel_sha_hmac_digest2(struct atmel_sha_dev *dd); 1752 1753 static int atmel_sha_hmac_setup(struct atmel_sha_dev *dd, 1754 atmel_sha_fn_t resume) 1755 { 1756 struct ahash_request *req = dd->req; 1757 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1758 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1759 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1760 unsigned int keylen; 1761 const u8 *key; 1762 size_t bs; 1763 1764 hmac->resume = resume; 1765 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { 1766 case SHA_FLAGS_SHA1: 1767 ctx->block_size = SHA1_BLOCK_SIZE; 1768 ctx->hash_size = SHA1_DIGEST_SIZE; 1769 break; 1770 1771 case SHA_FLAGS_SHA224: 1772 ctx->block_size = SHA224_BLOCK_SIZE; 1773 ctx->hash_size = SHA256_DIGEST_SIZE; 1774 break; 1775 1776 case SHA_FLAGS_SHA256: 1777 ctx->block_size = SHA256_BLOCK_SIZE; 1778 ctx->hash_size = SHA256_DIGEST_SIZE; 1779 break; 1780 1781 case SHA_FLAGS_SHA384: 1782 ctx->block_size = SHA384_BLOCK_SIZE; 1783 ctx->hash_size = SHA512_DIGEST_SIZE; 1784 break; 1785 1786 case SHA_FLAGS_SHA512: 1787 ctx->block_size = SHA512_BLOCK_SIZE; 1788 ctx->hash_size = SHA512_DIGEST_SIZE; 1789 break; 1790 1791 default: 1792 return atmel_sha_complete(dd, -EINVAL); 1793 } 1794 bs = ctx->block_size; 1795 1796 if (likely(!atmel_sha_hmac_key_get(&hmac->hkey, &key, &keylen))) 1797 return resume(dd); 1798 1799 /* Compute K' from K. */ 1800 if (unlikely(keylen > bs)) 1801 return atmel_sha_hmac_prehash_key(dd, key, keylen); 1802 1803 /* Prepare ipad. */ 1804 memcpy((u8 *)hmac->ipad, key, keylen); 1805 memset((u8 *)hmac->ipad + keylen, 0, bs - keylen); 1806 return atmel_sha_hmac_compute_ipad_hash(dd); 1807 } 1808 1809 static int atmel_sha_hmac_prehash_key(struct atmel_sha_dev *dd, 1810 const u8 *key, unsigned int keylen) 1811 { 1812 return atmel_sha_cpu_hash(dd, key, keylen, true, 1813 atmel_sha_hmac_prehash_key_done); 1814 } 1815 1816 static int atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev *dd) 1817 { 1818 struct ahash_request *req = dd->req; 1819 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1820 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1821 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1822 size_t ds = crypto_ahash_digestsize(tfm); 1823 size_t bs = ctx->block_size; 1824 size_t i, num_words = ds / sizeof(u32); 1825 1826 /* Prepare ipad. */ 1827 for (i = 0; i < num_words; ++i) 1828 hmac->ipad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i)); 1829 memset((u8 *)hmac->ipad + ds, 0, bs - ds); 1830 return atmel_sha_hmac_compute_ipad_hash(dd); 1831 } 1832 1833 static int atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev *dd) 1834 { 1835 struct ahash_request *req = dd->req; 1836 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1837 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1838 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1839 size_t bs = ctx->block_size; 1840 size_t i, num_words = bs / sizeof(u32); 1841 1842 memcpy(hmac->opad, hmac->ipad, bs); 1843 for (i = 0; i < num_words; ++i) { 1844 hmac->ipad[i] ^= 0x36363636; 1845 hmac->opad[i] ^= 0x5c5c5c5c; 1846 } 1847 1848 return atmel_sha_cpu_hash(dd, hmac->ipad, bs, false, 1849 atmel_sha_hmac_compute_opad_hash); 1850 } 1851 1852 static int atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev *dd) 1853 { 1854 struct ahash_request *req = dd->req; 1855 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1856 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1857 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1858 size_t bs = ctx->block_size; 1859 size_t hs = ctx->hash_size; 1860 size_t i, num_words = hs / sizeof(u32); 1861 1862 for (i = 0; i < num_words; ++i) 1863 hmac->ipad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i)); 1864 return atmel_sha_cpu_hash(dd, hmac->opad, bs, false, 1865 atmel_sha_hmac_setup_done); 1866 } 1867 1868 static int atmel_sha_hmac_setup_done(struct atmel_sha_dev *dd) 1869 { 1870 struct ahash_request *req = dd->req; 1871 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1872 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1873 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1874 size_t hs = ctx->hash_size; 1875 size_t i, num_words = hs / sizeof(u32); 1876 1877 for (i = 0; i < num_words; ++i) 1878 hmac->opad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i)); 1879 atmel_sha_hmac_key_release(&hmac->hkey); 1880 return hmac->resume(dd); 1881 } 1882 1883 static int atmel_sha_hmac_start(struct atmel_sha_dev *dd) 1884 { 1885 struct ahash_request *req = dd->req; 1886 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1887 int err; 1888 1889 err = atmel_sha_hw_init(dd); 1890 if (err) 1891 return atmel_sha_complete(dd, err); 1892 1893 switch (ctx->op) { 1894 case SHA_OP_INIT: 1895 err = atmel_sha_hmac_setup(dd, atmel_sha_hmac_init_done); 1896 break; 1897 1898 case SHA_OP_UPDATE: 1899 dd->resume = atmel_sha_done; 1900 err = atmel_sha_update_req(dd); 1901 break; 1902 1903 case SHA_OP_FINAL: 1904 dd->resume = atmel_sha_hmac_final; 1905 err = atmel_sha_final_req(dd); 1906 break; 1907 1908 case SHA_OP_DIGEST: 1909 err = atmel_sha_hmac_setup(dd, atmel_sha_hmac_digest2); 1910 break; 1911 1912 default: 1913 return atmel_sha_complete(dd, -EINVAL); 1914 } 1915 1916 return err; 1917 } 1918 1919 static int atmel_sha_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, 1920 unsigned int keylen) 1921 { 1922 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1923 1924 if (atmel_sha_hmac_key_set(&hmac->hkey, key, keylen)) { 1925 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 1926 return -EINVAL; 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int atmel_sha_hmac_init(struct ahash_request *req) 1933 { 1934 int err; 1935 1936 err = atmel_sha_init(req); 1937 if (err) 1938 return err; 1939 1940 return atmel_sha_enqueue(req, SHA_OP_INIT); 1941 } 1942 1943 static int atmel_sha_hmac_init_done(struct atmel_sha_dev *dd) 1944 { 1945 struct ahash_request *req = dd->req; 1946 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1947 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1948 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1949 size_t bs = ctx->block_size; 1950 size_t hs = ctx->hash_size; 1951 1952 ctx->bufcnt = 0; 1953 ctx->digcnt[0] = bs; 1954 ctx->digcnt[1] = 0; 1955 ctx->flags |= SHA_FLAGS_RESTORE; 1956 memcpy(ctx->digest, hmac->ipad, hs); 1957 return atmel_sha_complete(dd, 0); 1958 } 1959 1960 static int atmel_sha_hmac_final(struct atmel_sha_dev *dd) 1961 { 1962 struct ahash_request *req = dd->req; 1963 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 1964 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1965 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 1966 u32 *digest = (u32 *)ctx->digest; 1967 size_t ds = crypto_ahash_digestsize(tfm); 1968 size_t bs = ctx->block_size; 1969 size_t hs = ctx->hash_size; 1970 size_t i, num_words; 1971 u32 mr; 1972 1973 /* Save d = SHA((K' + ipad) | msg). */ 1974 num_words = ds / sizeof(u32); 1975 for (i = 0; i < num_words; ++i) 1976 digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i)); 1977 1978 /* Restore context to finish computing SHA((K' + opad) | d). */ 1979 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV); 1980 num_words = hs / sizeof(u32); 1981 for (i = 0; i < num_words; ++i) 1982 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]); 1983 1984 mr = SHA_MR_MODE_AUTO | SHA_MR_UIHV; 1985 mr |= (ctx->flags & SHA_FLAGS_ALGO_MASK); 1986 atmel_sha_write(dd, SHA_MR, mr); 1987 atmel_sha_write(dd, SHA_MSR, bs + ds); 1988 atmel_sha_write(dd, SHA_BCR, ds); 1989 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); 1990 1991 sg_init_one(&dd->tmp, digest, ds); 1992 return atmel_sha_cpu_start(dd, &dd->tmp, ds, false, true, 1993 atmel_sha_hmac_final_done); 1994 } 1995 1996 static int atmel_sha_hmac_final_done(struct atmel_sha_dev *dd) 1997 { 1998 /* 1999 * req->result might not be sizeof(u32) aligned, so copy the 2000 * digest into ctx->digest[] before memcpy() the data into 2001 * req->result. 2002 */ 2003 atmel_sha_copy_hash(dd->req); 2004 atmel_sha_copy_ready_hash(dd->req); 2005 return atmel_sha_complete(dd, 0); 2006 } 2007 2008 static int atmel_sha_hmac_digest(struct ahash_request *req) 2009 { 2010 int err; 2011 2012 err = atmel_sha_init(req); 2013 if (err) 2014 return err; 2015 2016 return atmel_sha_enqueue(req, SHA_OP_DIGEST); 2017 } 2018 2019 static int atmel_sha_hmac_digest2(struct atmel_sha_dev *dd) 2020 { 2021 struct ahash_request *req = dd->req; 2022 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req); 2023 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 2024 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 2025 size_t hs = ctx->hash_size; 2026 size_t i, num_words = hs / sizeof(u32); 2027 bool use_dma = false; 2028 u32 mr; 2029 2030 /* Special case for empty message. */ 2031 if (!req->nbytes) 2032 return atmel_sha_complete(dd, -EINVAL); // TODO: 2033 2034 /* Check DMA threshold and alignment. */ 2035 if (req->nbytes > ATMEL_SHA_DMA_THRESHOLD && 2036 atmel_sha_dma_check_aligned(dd, req->src, req->nbytes)) 2037 use_dma = true; 2038 2039 /* Write both initial hash values to compute a HMAC. */ 2040 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV); 2041 for (i = 0; i < num_words; ++i) 2042 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->ipad[i]); 2043 2044 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIEHV); 2045 for (i = 0; i < num_words; ++i) 2046 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]); 2047 2048 /* Write the Mode, Message Size, Bytes Count then Control Registers. */ 2049 mr = (SHA_MR_HMAC | SHA_MR_DUALBUFF); 2050 mr |= ctx->flags & SHA_FLAGS_ALGO_MASK; 2051 if (use_dma) 2052 mr |= SHA_MR_MODE_IDATAR0; 2053 else 2054 mr |= SHA_MR_MODE_AUTO; 2055 atmel_sha_write(dd, SHA_MR, mr); 2056 2057 atmel_sha_write(dd, SHA_MSR, req->nbytes); 2058 atmel_sha_write(dd, SHA_BCR, req->nbytes); 2059 2060 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); 2061 2062 /* Process data. */ 2063 if (use_dma) 2064 return atmel_sha_dma_start(dd, req->src, req->nbytes, 2065 atmel_sha_hmac_final_done); 2066 2067 return atmel_sha_cpu_start(dd, req->src, req->nbytes, false, true, 2068 atmel_sha_hmac_final_done); 2069 } 2070 2071 static int atmel_sha_hmac_cra_init(struct crypto_tfm *tfm) 2072 { 2073 struct atmel_sha_hmac_ctx *hmac = crypto_tfm_ctx(tfm); 2074 2075 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 2076 sizeof(struct atmel_sha_reqctx)); 2077 hmac->base.start = atmel_sha_hmac_start; 2078 atmel_sha_hmac_key_init(&hmac->hkey); 2079 2080 return 0; 2081 } 2082 2083 static void atmel_sha_hmac_cra_exit(struct crypto_tfm *tfm) 2084 { 2085 struct atmel_sha_hmac_ctx *hmac = crypto_tfm_ctx(tfm); 2086 2087 atmel_sha_hmac_key_release(&hmac->hkey); 2088 } 2089 2090 static struct ahash_alg sha_hmac_algs[] = { 2091 { 2092 .init = atmel_sha_hmac_init, 2093 .update = atmel_sha_update, 2094 .final = atmel_sha_final, 2095 .digest = atmel_sha_hmac_digest, 2096 .setkey = atmel_sha_hmac_setkey, 2097 .export = atmel_sha_export, 2098 .import = atmel_sha_import, 2099 .halg = { 2100 .digestsize = SHA1_DIGEST_SIZE, 2101 .statesize = sizeof(struct atmel_sha_reqctx), 2102 .base = { 2103 .cra_name = "hmac(sha1)", 2104 .cra_driver_name = "atmel-hmac-sha1", 2105 .cra_priority = 100, 2106 .cra_flags = CRYPTO_ALG_ASYNC, 2107 .cra_blocksize = SHA1_BLOCK_SIZE, 2108 .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2109 .cra_alignmask = 0, 2110 .cra_module = THIS_MODULE, 2111 .cra_init = atmel_sha_hmac_cra_init, 2112 .cra_exit = atmel_sha_hmac_cra_exit, 2113 } 2114 } 2115 }, 2116 { 2117 .init = atmel_sha_hmac_init, 2118 .update = atmel_sha_update, 2119 .final = atmel_sha_final, 2120 .digest = atmel_sha_hmac_digest, 2121 .setkey = atmel_sha_hmac_setkey, 2122 .export = atmel_sha_export, 2123 .import = atmel_sha_import, 2124 .halg = { 2125 .digestsize = SHA224_DIGEST_SIZE, 2126 .statesize = sizeof(struct atmel_sha_reqctx), 2127 .base = { 2128 .cra_name = "hmac(sha224)", 2129 .cra_driver_name = "atmel-hmac-sha224", 2130 .cra_priority = 100, 2131 .cra_flags = CRYPTO_ALG_ASYNC, 2132 .cra_blocksize = SHA224_BLOCK_SIZE, 2133 .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2134 .cra_alignmask = 0, 2135 .cra_module = THIS_MODULE, 2136 .cra_init = atmel_sha_hmac_cra_init, 2137 .cra_exit = atmel_sha_hmac_cra_exit, 2138 } 2139 } 2140 }, 2141 { 2142 .init = atmel_sha_hmac_init, 2143 .update = atmel_sha_update, 2144 .final = atmel_sha_final, 2145 .digest = atmel_sha_hmac_digest, 2146 .setkey = atmel_sha_hmac_setkey, 2147 .export = atmel_sha_export, 2148 .import = atmel_sha_import, 2149 .halg = { 2150 .digestsize = SHA256_DIGEST_SIZE, 2151 .statesize = sizeof(struct atmel_sha_reqctx), 2152 .base = { 2153 .cra_name = "hmac(sha256)", 2154 .cra_driver_name = "atmel-hmac-sha256", 2155 .cra_priority = 100, 2156 .cra_flags = CRYPTO_ALG_ASYNC, 2157 .cra_blocksize = SHA256_BLOCK_SIZE, 2158 .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2159 .cra_alignmask = 0, 2160 .cra_module = THIS_MODULE, 2161 .cra_init = atmel_sha_hmac_cra_init, 2162 .cra_exit = atmel_sha_hmac_cra_exit, 2163 } 2164 } 2165 }, 2166 { 2167 .init = atmel_sha_hmac_init, 2168 .update = atmel_sha_update, 2169 .final = atmel_sha_final, 2170 .digest = atmel_sha_hmac_digest, 2171 .setkey = atmel_sha_hmac_setkey, 2172 .export = atmel_sha_export, 2173 .import = atmel_sha_import, 2174 .halg = { 2175 .digestsize = SHA384_DIGEST_SIZE, 2176 .statesize = sizeof(struct atmel_sha_reqctx), 2177 .base = { 2178 .cra_name = "hmac(sha384)", 2179 .cra_driver_name = "atmel-hmac-sha384", 2180 .cra_priority = 100, 2181 .cra_flags = CRYPTO_ALG_ASYNC, 2182 .cra_blocksize = SHA384_BLOCK_SIZE, 2183 .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2184 .cra_alignmask = 0, 2185 .cra_module = THIS_MODULE, 2186 .cra_init = atmel_sha_hmac_cra_init, 2187 .cra_exit = atmel_sha_hmac_cra_exit, 2188 } 2189 } 2190 }, 2191 { 2192 .init = atmel_sha_hmac_init, 2193 .update = atmel_sha_update, 2194 .final = atmel_sha_final, 2195 .digest = atmel_sha_hmac_digest, 2196 .setkey = atmel_sha_hmac_setkey, 2197 .export = atmel_sha_export, 2198 .import = atmel_sha_import, 2199 .halg = { 2200 .digestsize = SHA512_DIGEST_SIZE, 2201 .statesize = sizeof(struct atmel_sha_reqctx), 2202 .base = { 2203 .cra_name = "hmac(sha512)", 2204 .cra_driver_name = "atmel-hmac-sha512", 2205 .cra_priority = 100, 2206 .cra_flags = CRYPTO_ALG_ASYNC, 2207 .cra_blocksize = SHA512_BLOCK_SIZE, 2208 .cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx), 2209 .cra_alignmask = 0, 2210 .cra_module = THIS_MODULE, 2211 .cra_init = atmel_sha_hmac_cra_init, 2212 .cra_exit = atmel_sha_hmac_cra_exit, 2213 } 2214 } 2215 }, 2216 }; 2217 2218 #ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC 2219 /* authenc functions */ 2220 2221 static int atmel_sha_authenc_init2(struct atmel_sha_dev *dd); 2222 static int atmel_sha_authenc_init_done(struct atmel_sha_dev *dd); 2223 static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd); 2224 2225 2226 struct atmel_sha_authenc_ctx { 2227 struct crypto_ahash *tfm; 2228 }; 2229 2230 struct atmel_sha_authenc_reqctx { 2231 struct atmel_sha_reqctx base; 2232 2233 atmel_aes_authenc_fn_t cb; 2234 struct atmel_aes_dev *aes_dev; 2235 2236 /* _init() parameters. */ 2237 struct scatterlist *assoc; 2238 u32 assoclen; 2239 u32 textlen; 2240 2241 /* _final() parameters. */ 2242 u32 *digest; 2243 unsigned int digestlen; 2244 }; 2245 2246 static void atmel_sha_authenc_complete(struct crypto_async_request *areq, 2247 int err) 2248 { 2249 struct ahash_request *req = areq->data; 2250 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2251 2252 authctx->cb(authctx->aes_dev, err, authctx->base.dd->is_async); 2253 } 2254 2255 static int atmel_sha_authenc_start(struct atmel_sha_dev *dd) 2256 { 2257 struct ahash_request *req = dd->req; 2258 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2259 int err; 2260 2261 /* 2262 * Force atmel_sha_complete() to call req->base.complete(), ie 2263 * atmel_sha_authenc_complete(), which in turn calls authctx->cb(). 2264 */ 2265 dd->force_complete = true; 2266 2267 err = atmel_sha_hw_init(dd); 2268 return authctx->cb(authctx->aes_dev, err, dd->is_async); 2269 } 2270 2271 bool atmel_sha_authenc_is_ready(void) 2272 { 2273 struct atmel_sha_ctx dummy; 2274 2275 dummy.dd = NULL; 2276 return (atmel_sha_find_dev(&dummy) != NULL); 2277 } 2278 EXPORT_SYMBOL_GPL(atmel_sha_authenc_is_ready); 2279 2280 unsigned int atmel_sha_authenc_get_reqsize(void) 2281 { 2282 return sizeof(struct atmel_sha_authenc_reqctx); 2283 } 2284 EXPORT_SYMBOL_GPL(atmel_sha_authenc_get_reqsize); 2285 2286 struct atmel_sha_authenc_ctx *atmel_sha_authenc_spawn(unsigned long mode) 2287 { 2288 struct atmel_sha_authenc_ctx *auth; 2289 struct crypto_ahash *tfm; 2290 struct atmel_sha_ctx *tctx; 2291 const char *name; 2292 int err = -EINVAL; 2293 2294 switch (mode & SHA_FLAGS_MODE_MASK) { 2295 case SHA_FLAGS_HMAC_SHA1: 2296 name = "atmel-hmac-sha1"; 2297 break; 2298 2299 case SHA_FLAGS_HMAC_SHA224: 2300 name = "atmel-hmac-sha224"; 2301 break; 2302 2303 case SHA_FLAGS_HMAC_SHA256: 2304 name = "atmel-hmac-sha256"; 2305 break; 2306 2307 case SHA_FLAGS_HMAC_SHA384: 2308 name = "atmel-hmac-sha384"; 2309 break; 2310 2311 case SHA_FLAGS_HMAC_SHA512: 2312 name = "atmel-hmac-sha512"; 2313 break; 2314 2315 default: 2316 goto error; 2317 } 2318 2319 tfm = crypto_alloc_ahash(name, 2320 CRYPTO_ALG_TYPE_AHASH, 2321 CRYPTO_ALG_TYPE_AHASH_MASK); 2322 if (IS_ERR(tfm)) { 2323 err = PTR_ERR(tfm); 2324 goto error; 2325 } 2326 tctx = crypto_ahash_ctx(tfm); 2327 tctx->start = atmel_sha_authenc_start; 2328 tctx->flags = mode; 2329 2330 auth = kzalloc(sizeof(*auth), GFP_KERNEL); 2331 if (!auth) { 2332 err = -ENOMEM; 2333 goto err_free_ahash; 2334 } 2335 auth->tfm = tfm; 2336 2337 return auth; 2338 2339 err_free_ahash: 2340 crypto_free_ahash(tfm); 2341 error: 2342 return ERR_PTR(err); 2343 } 2344 EXPORT_SYMBOL_GPL(atmel_sha_authenc_spawn); 2345 2346 void atmel_sha_authenc_free(struct atmel_sha_authenc_ctx *auth) 2347 { 2348 if (auth) 2349 crypto_free_ahash(auth->tfm); 2350 kfree(auth); 2351 } 2352 EXPORT_SYMBOL_GPL(atmel_sha_authenc_free); 2353 2354 int atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx *auth, 2355 const u8 *key, unsigned int keylen, 2356 u32 *flags) 2357 { 2358 struct crypto_ahash *tfm = auth->tfm; 2359 int err; 2360 2361 crypto_ahash_clear_flags(tfm, CRYPTO_TFM_REQ_MASK); 2362 crypto_ahash_set_flags(tfm, *flags & CRYPTO_TFM_REQ_MASK); 2363 err = crypto_ahash_setkey(tfm, key, keylen); 2364 *flags = crypto_ahash_get_flags(tfm); 2365 2366 return err; 2367 } 2368 EXPORT_SYMBOL_GPL(atmel_sha_authenc_setkey); 2369 2370 int atmel_sha_authenc_schedule(struct ahash_request *req, 2371 struct atmel_sha_authenc_ctx *auth, 2372 atmel_aes_authenc_fn_t cb, 2373 struct atmel_aes_dev *aes_dev) 2374 { 2375 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2376 struct atmel_sha_reqctx *ctx = &authctx->base; 2377 struct crypto_ahash *tfm = auth->tfm; 2378 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm); 2379 struct atmel_sha_dev *dd; 2380 2381 /* Reset request context (MUST be done first). */ 2382 memset(authctx, 0, sizeof(*authctx)); 2383 2384 /* Get SHA device. */ 2385 dd = atmel_sha_find_dev(tctx); 2386 if (!dd) 2387 return cb(aes_dev, -ENODEV, false); 2388 2389 /* Init request context. */ 2390 ctx->dd = dd; 2391 ctx->buflen = SHA_BUFFER_LEN; 2392 authctx->cb = cb; 2393 authctx->aes_dev = aes_dev; 2394 ahash_request_set_tfm(req, tfm); 2395 ahash_request_set_callback(req, 0, atmel_sha_authenc_complete, req); 2396 2397 return atmel_sha_handle_queue(dd, req); 2398 } 2399 EXPORT_SYMBOL_GPL(atmel_sha_authenc_schedule); 2400 2401 int atmel_sha_authenc_init(struct ahash_request *req, 2402 struct scatterlist *assoc, unsigned int assoclen, 2403 unsigned int textlen, 2404 atmel_aes_authenc_fn_t cb, 2405 struct atmel_aes_dev *aes_dev) 2406 { 2407 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2408 struct atmel_sha_reqctx *ctx = &authctx->base; 2409 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 2410 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 2411 struct atmel_sha_dev *dd = ctx->dd; 2412 2413 if (unlikely(!IS_ALIGNED(assoclen, sizeof(u32)))) 2414 return atmel_sha_complete(dd, -EINVAL); 2415 2416 authctx->cb = cb; 2417 authctx->aes_dev = aes_dev; 2418 authctx->assoc = assoc; 2419 authctx->assoclen = assoclen; 2420 authctx->textlen = textlen; 2421 2422 ctx->flags = hmac->base.flags; 2423 return atmel_sha_hmac_setup(dd, atmel_sha_authenc_init2); 2424 } 2425 EXPORT_SYMBOL_GPL(atmel_sha_authenc_init); 2426 2427 static int atmel_sha_authenc_init2(struct atmel_sha_dev *dd) 2428 { 2429 struct ahash_request *req = dd->req; 2430 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2431 struct atmel_sha_reqctx *ctx = &authctx->base; 2432 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 2433 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm); 2434 size_t hs = ctx->hash_size; 2435 size_t i, num_words = hs / sizeof(u32); 2436 u32 mr, msg_size; 2437 2438 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV); 2439 for (i = 0; i < num_words; ++i) 2440 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->ipad[i]); 2441 2442 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIEHV); 2443 for (i = 0; i < num_words; ++i) 2444 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]); 2445 2446 mr = (SHA_MR_MODE_IDATAR0 | 2447 SHA_MR_HMAC | 2448 SHA_MR_DUALBUFF); 2449 mr |= ctx->flags & SHA_FLAGS_ALGO_MASK; 2450 atmel_sha_write(dd, SHA_MR, mr); 2451 2452 msg_size = authctx->assoclen + authctx->textlen; 2453 atmel_sha_write(dd, SHA_MSR, msg_size); 2454 atmel_sha_write(dd, SHA_BCR, msg_size); 2455 2456 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST); 2457 2458 /* Process assoc data. */ 2459 return atmel_sha_cpu_start(dd, authctx->assoc, authctx->assoclen, 2460 true, false, 2461 atmel_sha_authenc_init_done); 2462 } 2463 2464 static int atmel_sha_authenc_init_done(struct atmel_sha_dev *dd) 2465 { 2466 struct ahash_request *req = dd->req; 2467 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2468 2469 return authctx->cb(authctx->aes_dev, 0, dd->is_async); 2470 } 2471 2472 int atmel_sha_authenc_final(struct ahash_request *req, 2473 u32 *digest, unsigned int digestlen, 2474 atmel_aes_authenc_fn_t cb, 2475 struct atmel_aes_dev *aes_dev) 2476 { 2477 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2478 struct atmel_sha_reqctx *ctx = &authctx->base; 2479 struct atmel_sha_dev *dd = ctx->dd; 2480 2481 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) { 2482 case SHA_FLAGS_SHA1: 2483 authctx->digestlen = SHA1_DIGEST_SIZE; 2484 break; 2485 2486 case SHA_FLAGS_SHA224: 2487 authctx->digestlen = SHA224_DIGEST_SIZE; 2488 break; 2489 2490 case SHA_FLAGS_SHA256: 2491 authctx->digestlen = SHA256_DIGEST_SIZE; 2492 break; 2493 2494 case SHA_FLAGS_SHA384: 2495 authctx->digestlen = SHA384_DIGEST_SIZE; 2496 break; 2497 2498 case SHA_FLAGS_SHA512: 2499 authctx->digestlen = SHA512_DIGEST_SIZE; 2500 break; 2501 2502 default: 2503 return atmel_sha_complete(dd, -EINVAL); 2504 } 2505 if (authctx->digestlen > digestlen) 2506 authctx->digestlen = digestlen; 2507 2508 authctx->cb = cb; 2509 authctx->aes_dev = aes_dev; 2510 authctx->digest = digest; 2511 return atmel_sha_wait_for_data_ready(dd, 2512 atmel_sha_authenc_final_done); 2513 } 2514 EXPORT_SYMBOL_GPL(atmel_sha_authenc_final); 2515 2516 static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd) 2517 { 2518 struct ahash_request *req = dd->req; 2519 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2520 size_t i, num_words = authctx->digestlen / sizeof(u32); 2521 2522 for (i = 0; i < num_words; ++i) 2523 authctx->digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i)); 2524 2525 return atmel_sha_complete(dd, 0); 2526 } 2527 2528 void atmel_sha_authenc_abort(struct ahash_request *req) 2529 { 2530 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req); 2531 struct atmel_sha_reqctx *ctx = &authctx->base; 2532 struct atmel_sha_dev *dd = ctx->dd; 2533 2534 /* Prevent atmel_sha_complete() from calling req->base.complete(). */ 2535 dd->is_async = false; 2536 dd->force_complete = false; 2537 (void)atmel_sha_complete(dd, 0); 2538 } 2539 EXPORT_SYMBOL_GPL(atmel_sha_authenc_abort); 2540 2541 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */ 2542 2543 2544 static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd) 2545 { 2546 int i; 2547 2548 if (dd->caps.has_hmac) 2549 for (i = 0; i < ARRAY_SIZE(sha_hmac_algs); i++) 2550 crypto_unregister_ahash(&sha_hmac_algs[i]); 2551 2552 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) 2553 crypto_unregister_ahash(&sha_1_256_algs[i]); 2554 2555 if (dd->caps.has_sha224) 2556 crypto_unregister_ahash(&sha_224_alg); 2557 2558 if (dd->caps.has_sha_384_512) { 2559 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) 2560 crypto_unregister_ahash(&sha_384_512_algs[i]); 2561 } 2562 } 2563 2564 static int atmel_sha_register_algs(struct atmel_sha_dev *dd) 2565 { 2566 int err, i, j; 2567 2568 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) { 2569 err = crypto_register_ahash(&sha_1_256_algs[i]); 2570 if (err) 2571 goto err_sha_1_256_algs; 2572 } 2573 2574 if (dd->caps.has_sha224) { 2575 err = crypto_register_ahash(&sha_224_alg); 2576 if (err) 2577 goto err_sha_224_algs; 2578 } 2579 2580 if (dd->caps.has_sha_384_512) { 2581 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) { 2582 err = crypto_register_ahash(&sha_384_512_algs[i]); 2583 if (err) 2584 goto err_sha_384_512_algs; 2585 } 2586 } 2587 2588 if (dd->caps.has_hmac) { 2589 for (i = 0; i < ARRAY_SIZE(sha_hmac_algs); i++) { 2590 err = crypto_register_ahash(&sha_hmac_algs[i]); 2591 if (err) 2592 goto err_sha_hmac_algs; 2593 } 2594 } 2595 2596 return 0; 2597 2598 /*i = ARRAY_SIZE(sha_hmac_algs);*/ 2599 err_sha_hmac_algs: 2600 for (j = 0; j < i; j++) 2601 crypto_unregister_ahash(&sha_hmac_algs[j]); 2602 i = ARRAY_SIZE(sha_384_512_algs); 2603 err_sha_384_512_algs: 2604 for (j = 0; j < i; j++) 2605 crypto_unregister_ahash(&sha_384_512_algs[j]); 2606 crypto_unregister_ahash(&sha_224_alg); 2607 err_sha_224_algs: 2608 i = ARRAY_SIZE(sha_1_256_algs); 2609 err_sha_1_256_algs: 2610 for (j = 0; j < i; j++) 2611 crypto_unregister_ahash(&sha_1_256_algs[j]); 2612 2613 return err; 2614 } 2615 2616 static bool atmel_sha_filter(struct dma_chan *chan, void *slave) 2617 { 2618 struct at_dma_slave *sl = slave; 2619 2620 if (sl && sl->dma_dev == chan->device->dev) { 2621 chan->private = sl; 2622 return true; 2623 } else { 2624 return false; 2625 } 2626 } 2627 2628 static int atmel_sha_dma_init(struct atmel_sha_dev *dd, 2629 struct crypto_platform_data *pdata) 2630 { 2631 dma_cap_mask_t mask_in; 2632 2633 /* Try to grab DMA channel */ 2634 dma_cap_zero(mask_in); 2635 dma_cap_set(DMA_SLAVE, mask_in); 2636 2637 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in, 2638 atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); 2639 if (!dd->dma_lch_in.chan) { 2640 dev_warn(dd->dev, "no DMA channel available\n"); 2641 return -ENODEV; 2642 } 2643 2644 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; 2645 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + 2646 SHA_REG_DIN(0); 2647 dd->dma_lch_in.dma_conf.src_maxburst = 1; 2648 dd->dma_lch_in.dma_conf.src_addr_width = 2649 DMA_SLAVE_BUSWIDTH_4_BYTES; 2650 dd->dma_lch_in.dma_conf.dst_maxburst = 1; 2651 dd->dma_lch_in.dma_conf.dst_addr_width = 2652 DMA_SLAVE_BUSWIDTH_4_BYTES; 2653 dd->dma_lch_in.dma_conf.device_fc = false; 2654 2655 return 0; 2656 } 2657 2658 static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) 2659 { 2660 dma_release_channel(dd->dma_lch_in.chan); 2661 } 2662 2663 static void atmel_sha_get_cap(struct atmel_sha_dev *dd) 2664 { 2665 2666 dd->caps.has_dma = 0; 2667 dd->caps.has_dualbuff = 0; 2668 dd->caps.has_sha224 = 0; 2669 dd->caps.has_sha_384_512 = 0; 2670 dd->caps.has_uihv = 0; 2671 dd->caps.has_hmac = 0; 2672 2673 /* keep only major version number */ 2674 switch (dd->hw_version & 0xff0) { 2675 case 0x510: 2676 dd->caps.has_dma = 1; 2677 dd->caps.has_dualbuff = 1; 2678 dd->caps.has_sha224 = 1; 2679 dd->caps.has_sha_384_512 = 1; 2680 dd->caps.has_uihv = 1; 2681 dd->caps.has_hmac = 1; 2682 break; 2683 case 0x420: 2684 dd->caps.has_dma = 1; 2685 dd->caps.has_dualbuff = 1; 2686 dd->caps.has_sha224 = 1; 2687 dd->caps.has_sha_384_512 = 1; 2688 dd->caps.has_uihv = 1; 2689 break; 2690 case 0x410: 2691 dd->caps.has_dma = 1; 2692 dd->caps.has_dualbuff = 1; 2693 dd->caps.has_sha224 = 1; 2694 dd->caps.has_sha_384_512 = 1; 2695 break; 2696 case 0x400: 2697 dd->caps.has_dma = 1; 2698 dd->caps.has_dualbuff = 1; 2699 dd->caps.has_sha224 = 1; 2700 break; 2701 case 0x320: 2702 break; 2703 default: 2704 dev_warn(dd->dev, 2705 "Unmanaged sha version, set minimum capabilities\n"); 2706 break; 2707 } 2708 } 2709 2710 #if defined(CONFIG_OF) 2711 static const struct of_device_id atmel_sha_dt_ids[] = { 2712 { .compatible = "atmel,at91sam9g46-sha" }, 2713 { /* sentinel */ } 2714 }; 2715 2716 MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids); 2717 2718 static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev) 2719 { 2720 struct device_node *np = pdev->dev.of_node; 2721 struct crypto_platform_data *pdata; 2722 2723 if (!np) { 2724 dev_err(&pdev->dev, "device node not found\n"); 2725 return ERR_PTR(-EINVAL); 2726 } 2727 2728 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 2729 if (!pdata) 2730 return ERR_PTR(-ENOMEM); 2731 2732 pdata->dma_slave = devm_kzalloc(&pdev->dev, 2733 sizeof(*(pdata->dma_slave)), 2734 GFP_KERNEL); 2735 if (!pdata->dma_slave) 2736 return ERR_PTR(-ENOMEM); 2737 2738 return pdata; 2739 } 2740 #else /* CONFIG_OF */ 2741 static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev) 2742 { 2743 return ERR_PTR(-EINVAL); 2744 } 2745 #endif 2746 2747 static int atmel_sha_probe(struct platform_device *pdev) 2748 { 2749 struct atmel_sha_dev *sha_dd; 2750 struct crypto_platform_data *pdata; 2751 struct device *dev = &pdev->dev; 2752 struct resource *sha_res; 2753 int err; 2754 2755 sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL); 2756 if (sha_dd == NULL) { 2757 err = -ENOMEM; 2758 goto sha_dd_err; 2759 } 2760 2761 sha_dd->dev = dev; 2762 2763 platform_set_drvdata(pdev, sha_dd); 2764 2765 INIT_LIST_HEAD(&sha_dd->list); 2766 spin_lock_init(&sha_dd->lock); 2767 2768 tasklet_init(&sha_dd->done_task, atmel_sha_done_task, 2769 (unsigned long)sha_dd); 2770 tasklet_init(&sha_dd->queue_task, atmel_sha_queue_task, 2771 (unsigned long)sha_dd); 2772 2773 crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH); 2774 2775 /* Get the base address */ 2776 sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2777 if (!sha_res) { 2778 dev_err(dev, "no MEM resource info\n"); 2779 err = -ENODEV; 2780 goto res_err; 2781 } 2782 sha_dd->phys_base = sha_res->start; 2783 2784 /* Get the IRQ */ 2785 sha_dd->irq = platform_get_irq(pdev, 0); 2786 if (sha_dd->irq < 0) { 2787 dev_err(dev, "no IRQ resource info\n"); 2788 err = sha_dd->irq; 2789 goto res_err; 2790 } 2791 2792 err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq, 2793 IRQF_SHARED, "atmel-sha", sha_dd); 2794 if (err) { 2795 dev_err(dev, "unable to request sha irq.\n"); 2796 goto res_err; 2797 } 2798 2799 /* Initializing the clock */ 2800 sha_dd->iclk = devm_clk_get(&pdev->dev, "sha_clk"); 2801 if (IS_ERR(sha_dd->iclk)) { 2802 dev_err(dev, "clock initialization failed.\n"); 2803 err = PTR_ERR(sha_dd->iclk); 2804 goto res_err; 2805 } 2806 2807 sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res); 2808 if (IS_ERR(sha_dd->io_base)) { 2809 dev_err(dev, "can't ioremap\n"); 2810 err = PTR_ERR(sha_dd->io_base); 2811 goto res_err; 2812 } 2813 2814 err = clk_prepare(sha_dd->iclk); 2815 if (err) 2816 goto res_err; 2817 2818 atmel_sha_hw_version_init(sha_dd); 2819 2820 atmel_sha_get_cap(sha_dd); 2821 2822 if (sha_dd->caps.has_dma) { 2823 pdata = pdev->dev.platform_data; 2824 if (!pdata) { 2825 pdata = atmel_sha_of_init(pdev); 2826 if (IS_ERR(pdata)) { 2827 dev_err(&pdev->dev, "platform data not available\n"); 2828 err = PTR_ERR(pdata); 2829 goto iclk_unprepare; 2830 } 2831 } 2832 if (!pdata->dma_slave) { 2833 err = -ENXIO; 2834 goto iclk_unprepare; 2835 } 2836 err = atmel_sha_dma_init(sha_dd, pdata); 2837 if (err) 2838 goto err_sha_dma; 2839 2840 dev_info(dev, "using %s for DMA transfers\n", 2841 dma_chan_name(sha_dd->dma_lch_in.chan)); 2842 } 2843 2844 spin_lock(&atmel_sha.lock); 2845 list_add_tail(&sha_dd->list, &atmel_sha.dev_list); 2846 spin_unlock(&atmel_sha.lock); 2847 2848 err = atmel_sha_register_algs(sha_dd); 2849 if (err) 2850 goto err_algs; 2851 2852 dev_info(dev, "Atmel SHA1/SHA256%s%s\n", 2853 sha_dd->caps.has_sha224 ? "/SHA224" : "", 2854 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : ""); 2855 2856 return 0; 2857 2858 err_algs: 2859 spin_lock(&atmel_sha.lock); 2860 list_del(&sha_dd->list); 2861 spin_unlock(&atmel_sha.lock); 2862 if (sha_dd->caps.has_dma) 2863 atmel_sha_dma_cleanup(sha_dd); 2864 err_sha_dma: 2865 iclk_unprepare: 2866 clk_unprepare(sha_dd->iclk); 2867 res_err: 2868 tasklet_kill(&sha_dd->queue_task); 2869 tasklet_kill(&sha_dd->done_task); 2870 sha_dd_err: 2871 dev_err(dev, "initialization failed.\n"); 2872 2873 return err; 2874 } 2875 2876 static int atmel_sha_remove(struct platform_device *pdev) 2877 { 2878 struct atmel_sha_dev *sha_dd; 2879 2880 sha_dd = platform_get_drvdata(pdev); 2881 if (!sha_dd) 2882 return -ENODEV; 2883 spin_lock(&atmel_sha.lock); 2884 list_del(&sha_dd->list); 2885 spin_unlock(&atmel_sha.lock); 2886 2887 atmel_sha_unregister_algs(sha_dd); 2888 2889 tasklet_kill(&sha_dd->queue_task); 2890 tasklet_kill(&sha_dd->done_task); 2891 2892 if (sha_dd->caps.has_dma) 2893 atmel_sha_dma_cleanup(sha_dd); 2894 2895 clk_unprepare(sha_dd->iclk); 2896 2897 return 0; 2898 } 2899 2900 static struct platform_driver atmel_sha_driver = { 2901 .probe = atmel_sha_probe, 2902 .remove = atmel_sha_remove, 2903 .driver = { 2904 .name = "atmel_sha", 2905 .of_match_table = of_match_ptr(atmel_sha_dt_ids), 2906 }, 2907 }; 2908 2909 module_platform_driver(atmel_sha_driver); 2910 2911 MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support."); 2912 MODULE_LICENSE("GPL v2"); 2913 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique"); 2914