1 /** 2 * AMCC SoC PPC4xx Crypto Driver 3 * 4 * Copyright (c) 2008 Applied Micro Circuits Corporation. 5 * All rights reserved. James Hsiao <jhsiao@amcc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * This filr defines the register set for Security Subsystem 18 */ 19 20 #ifndef __CRYPTO4XX_REG_DEF_H__ 21 #define __CRYPTO4XX_REG_DEF_H__ 22 23 /* CRYPTO4XX Register offset */ 24 #define CRYPTO4XX_DESCRIPTOR 0x00000000 25 #define CRYPTO4XX_CTRL_STAT 0x00000000 26 #define CRYPTO4XX_SOURCE 0x00000004 27 #define CRYPTO4XX_DEST 0x00000008 28 #define CRYPTO4XX_SA 0x0000000C 29 #define CRYPTO4XX_SA_LENGTH 0x00000010 30 #define CRYPTO4XX_LENGTH 0x00000014 31 32 #define CRYPTO4XX_PE_DMA_CFG 0x00000040 33 #define CRYPTO4XX_PE_DMA_STAT 0x00000044 34 #define CRYPTO4XX_PDR_BASE 0x00000048 35 #define CRYPTO4XX_RDR_BASE 0x0000004c 36 #define CRYPTO4XX_RING_SIZE 0x00000050 37 #define CRYPTO4XX_RING_CTRL 0x00000054 38 #define CRYPTO4XX_INT_RING_STAT 0x00000058 39 #define CRYPTO4XX_EXT_RING_STAT 0x0000005c 40 #define CRYPTO4XX_IO_THRESHOLD 0x00000060 41 #define CRYPTO4XX_GATH_RING_BASE 0x00000064 42 #define CRYPTO4XX_SCAT_RING_BASE 0x00000068 43 #define CRYPTO4XX_PART_RING_SIZE 0x0000006c 44 #define CRYPTO4XX_PART_RING_CFG 0x00000070 45 46 #define CRYPTO4XX_PDR_BASE_UADDR 0x00000080 47 #define CRYPTO4XX_RDR_BASE_UADDR 0x00000084 48 #define CRYPTO4XX_PKT_SRC_UADDR 0x00000088 49 #define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c 50 #define CRYPTO4XX_SA_UADDR 0x00000090 51 #define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0 52 #define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4 53 54 #define CRYPTO4XX_SEQ_RD 0x00000408 55 #define CRYPTO4XX_SEQ_MASK_RD 0x0000040C 56 57 #define CRYPTO4XX_SA_CMD_0 0x00010600 58 #define CRYPTO4XX_SA_CMD_1 0x00010604 59 60 #define CRYPTO4XX_STATE_PTR 0x000106dc 61 #define CRYPTO4XX_STATE_IV 0x00010700 62 #define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710 63 #define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714 64 65 #define CRYPTO4XX_STATE_IDIGEST_0 0x00010718 66 #define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c 67 68 #define CRYPTO4XX_DATA_IN 0x00018000 69 #define CRYPTO4XX_DATA_OUT 0x0001c000 70 71 #define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0 72 #define CRYPTO4XX_INT_MASK_STAT 0x000500a4 73 #define CRYPTO4XX_INT_CLR 0x000500a4 74 #define CRYPTO4XX_INT_EN 0x000500a8 75 76 #define CRYPTO4XX_INT_PKA 0x00000002 77 #define CRYPTO4XX_INT_PDR_DONE 0x00008000 78 #define CRYPTO4XX_INT_MA_WR_ERR 0x00020000 79 #define CRYPTO4XX_INT_MA_RD_ERR 0x00010000 80 #define CRYPTO4XX_INT_PE_ERR 0x00000200 81 #define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040 82 #define CRYPTO4XX_INT_SLAVE_ERR 0x00000010 83 #define CRYPTO4XX_INT_MASTER_ERR 0x00000008 84 #define CRYPTO4XX_INT_ERROR 0x00030258 85 86 #define CRYPTO4XX_INT_CFG 0x000500ac 87 #define CRYPTO4XX_INT_DESCR_RD 0x000500b0 88 #define CRYPTO4XX_INT_DESCR_CNT 0x000500b4 89 #define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8 90 91 #define CRYPTO4XX_DEVICE_CTRL 0x00060080 92 #define CRYPTO4XX_DEVICE_ID 0x00060084 93 #define CRYPTO4XX_DEVICE_INFO 0x00060088 94 #define CRYPTO4XX_DMA_USER_SRC 0x00060094 95 #define CRYPTO4XX_DMA_USER_DEST 0x00060098 96 #define CRYPTO4XX_DMA_USER_CMD 0x0006009C 97 98 #define CRYPTO4XX_DMA_CFG 0x000600d4 99 #define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8 100 #define CRYPTO4XX_ENDIAN_CFG 0x000600d8 101 102 #define CRYPTO4XX_PRNG_STAT 0x00070000 103 #define CRYPTO4XX_PRNG_STAT_BUSY 0x1 104 #define CRYPTO4XX_PRNG_CTRL 0x00070004 105 #define CRYPTO4XX_PRNG_SEED_L 0x00070008 106 #define CRYPTO4XX_PRNG_SEED_H 0x0007000c 107 108 #define CRYPTO4XX_PRNG_RES_0 0x00070020 109 #define CRYPTO4XX_PRNG_RES_1 0x00070024 110 #define CRYPTO4XX_PRNG_RES_2 0x00070028 111 #define CRYPTO4XX_PRNG_RES_3 0x0007002C 112 113 #define CRYPTO4XX_PRNG_LFSR_L 0x00070030 114 #define CRYPTO4XX_PRNG_LFSR_H 0x00070034 115 116 /** 117 * Initialize CRYPTO ENGINE registers, and memory bases. 118 */ 119 #define PPC4XX_PDR_POLL 0x3ff 120 #define PPC4XX_OUTPUT_THRESHOLD 2 121 #define PPC4XX_INPUT_THRESHOLD 2 122 #define PPC4XX_PD_SIZE 6 123 #define PPC4XX_CTX_DONE_INT 0x2000 124 #define PPC4XX_PD_DONE_INT 0x8000 125 #define PPC4XX_TMO_ERR_INT 0x40000 126 #define PPC4XX_BYTE_ORDER 0x22222 127 #define PPC4XX_INTERRUPT_CLR 0x3ffff 128 #define PPC4XX_PRNG_CTRL_AUTO_EN 0x3 129 #define PPC4XX_DC_3DES_EN 1 130 #define PPC4XX_TRNG_EN 0x00020000 131 #define PPC4XX_INT_DESCR_CNT 7 132 #define PPC4XX_INT_TIMEOUT_CNT 0 133 #define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF 134 #define PPC4XX_INT_CFG 1 135 /** 136 * all follow define are ad hoc 137 */ 138 #define PPC4XX_RING_RETRY 100 139 #define PPC4XX_RING_POLL 100 140 #define PPC4XX_SDR_SIZE PPC4XX_NUM_SD 141 #define PPC4XX_GDR_SIZE PPC4XX_NUM_GD 142 143 /** 144 * Generic Security Association (SA) with all possible fields. These will 145 * never likely used except for reference purpose. These structure format 146 * can be not changed as the hardware expects them to be layout as defined. 147 * Field can be removed or reduced but ordering can not be changed. 148 */ 149 #define CRYPTO4XX_DMA_CFG_OFFSET 0x40 150 union ce_pe_dma_cfg { 151 struct { 152 u32 rsv:7; 153 u32 dir_host:1; 154 u32 rsv1:2; 155 u32 bo_td_en:1; 156 u32 dis_pdr_upd:1; 157 u32 bo_sgpd_en:1; 158 u32 bo_data_en:1; 159 u32 bo_sa_en:1; 160 u32 bo_pd_en:1; 161 u32 rsv2:4; 162 u32 dynamic_sa_en:1; 163 u32 pdr_mode:2; 164 u32 pe_mode:1; 165 u32 rsv3:5; 166 u32 reset_sg:1; 167 u32 reset_pdr:1; 168 u32 reset_pe:1; 169 } bf; 170 u32 w; 171 } __attribute__((packed)); 172 173 #define CRYPTO4XX_PDR_BASE_OFFSET 0x48 174 #define CRYPTO4XX_RDR_BASE_OFFSET 0x4c 175 #define CRYPTO4XX_RING_SIZE_OFFSET 0x50 176 union ce_ring_size { 177 struct { 178 u32 ring_offset:16; 179 u32 rsv:6; 180 u32 ring_size:10; 181 } bf; 182 u32 w; 183 } __attribute__((packed)); 184 185 #define CRYPTO4XX_RING_CONTROL_OFFSET 0x54 186 union ce_ring_control { 187 struct { 188 u32 continuous:1; 189 u32 rsv:5; 190 u32 ring_retry_divisor:10; 191 u32 rsv1:4; 192 u32 ring_poll_divisor:10; 193 } bf; 194 u32 w; 195 } __attribute__((packed)); 196 197 #define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60 198 union ce_io_threshold { 199 struct { 200 u32 rsv:6; 201 u32 output_threshold:10; 202 u32 rsv1:6; 203 u32 input_threshold:10; 204 } bf; 205 u32 w; 206 } __attribute__((packed)); 207 208 #define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64 209 #define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68 210 211 union ce_part_ring_size { 212 struct { 213 u32 sdr_size:16; 214 u32 gdr_size:16; 215 } bf; 216 u32 w; 217 } __attribute__((packed)); 218 219 #define MAX_BURST_SIZE_32 0 220 #define MAX_BURST_SIZE_64 1 221 #define MAX_BURST_SIZE_128 2 222 #define MAX_BURST_SIZE_256 3 223 224 /* gather descriptor control length */ 225 struct gd_ctl_len { 226 u32 len:16; 227 u32 rsv:14; 228 u32 done:1; 229 u32 ready:1; 230 } __attribute__((packed)); 231 232 struct ce_gd { 233 u32 ptr; 234 struct gd_ctl_len ctl_len; 235 } __attribute__((packed)); 236 237 struct sd_ctl { 238 u32 ctl:30; 239 u32 done:1; 240 u32 rdy:1; 241 } __attribute__((packed)); 242 243 struct ce_sd { 244 u32 ptr; 245 struct sd_ctl ctl; 246 } __attribute__((packed)); 247 248 #define PD_PAD_CTL_32 0x10 249 #define PD_PAD_CTL_64 0x20 250 #define PD_PAD_CTL_128 0x40 251 #define PD_PAD_CTL_256 0x80 252 union ce_pd_ctl { 253 struct { 254 u32 pd_pad_ctl:8; 255 u32 status:8; 256 u32 next_hdr:8; 257 u32 rsv:2; 258 u32 cached_sa:1; 259 u32 hash_final:1; 260 u32 init_arc4:1; 261 u32 rsv1:1; 262 u32 pe_done:1; 263 u32 host_ready:1; 264 } bf; 265 u32 w; 266 } __attribute__((packed)); 267 #define PD_CTL_HASH_FINAL BIT(4) 268 #define PD_CTL_PE_DONE BIT(1) 269 #define PD_CTL_HOST_READY BIT(0) 270 271 union ce_pd_ctl_len { 272 struct { 273 u32 bypass:8; 274 u32 pe_done:1; 275 u32 host_ready:1; 276 u32 rsv:2; 277 u32 pkt_len:20; 278 } bf; 279 u32 w; 280 } __attribute__((packed)); 281 282 struct ce_pd { 283 union ce_pd_ctl pd_ctl; 284 u32 src; 285 u32 dest; 286 u32 sa; /* get from ctx->sa_dma_addr */ 287 u32 sa_len; /* only if dynamic sa is used */ 288 union ce_pd_ctl_len pd_ctl_len; 289 290 } __attribute__((packed)); 291 #endif 292