1 /** 2 * AMCC SoC PPC4xx Crypto Driver 3 * 4 * Copyright (c) 2008 Applied Micro Circuits Corporation. 5 * All rights reserved. James Hsiao <jhsiao@amcc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * This file implements AMCC crypto offload Linux device driver for use with 18 * Linux CryptoAPI. 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/interrupt.h> 23 #include <linux/spinlock_types.h> 24 #include <linux/random.h> 25 #include <linux/scatterlist.h> 26 #include <linux/crypto.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/platform_device.h> 29 #include <linux/init.h> 30 #include <linux/module.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/of_platform.h> 34 #include <linux/slab.h> 35 #include <asm/dcr.h> 36 #include <asm/dcr-regs.h> 37 #include <asm/cacheflush.h> 38 #include <crypto/aead.h> 39 #include <crypto/aes.h> 40 #include <crypto/ctr.h> 41 #include <crypto/gcm.h> 42 #include <crypto/sha.h> 43 #include <crypto/scatterwalk.h> 44 #include <crypto/internal/aead.h> 45 #include <crypto/internal/skcipher.h> 46 #include "crypto4xx_reg_def.h" 47 #include "crypto4xx_core.h" 48 #include "crypto4xx_sa.h" 49 #include "crypto4xx_trng.h" 50 51 #define PPC4XX_SEC_VERSION_STR "0.5" 52 53 /** 54 * PPC4xx Crypto Engine Initialization Routine 55 */ 56 static void crypto4xx_hw_init(struct crypto4xx_device *dev) 57 { 58 union ce_ring_size ring_size; 59 union ce_ring_control ring_ctrl; 60 union ce_part_ring_size part_ring_size; 61 union ce_io_threshold io_threshold; 62 u32 rand_num; 63 union ce_pe_dma_cfg pe_dma_cfg; 64 u32 device_ctrl; 65 66 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG); 67 /* setup pe dma, include reset sg, pdr and pe, then release reset */ 68 pe_dma_cfg.w = 0; 69 pe_dma_cfg.bf.bo_sgpd_en = 1; 70 pe_dma_cfg.bf.bo_data_en = 0; 71 pe_dma_cfg.bf.bo_sa_en = 1; 72 pe_dma_cfg.bf.bo_pd_en = 1; 73 pe_dma_cfg.bf.dynamic_sa_en = 1; 74 pe_dma_cfg.bf.reset_sg = 1; 75 pe_dma_cfg.bf.reset_pdr = 1; 76 pe_dma_cfg.bf.reset_pe = 1; 77 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG); 78 /* un reset pe,sg and pdr */ 79 pe_dma_cfg.bf.pe_mode = 0; 80 pe_dma_cfg.bf.reset_sg = 0; 81 pe_dma_cfg.bf.reset_pdr = 0; 82 pe_dma_cfg.bf.reset_pe = 0; 83 pe_dma_cfg.bf.bo_td_en = 0; 84 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG); 85 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE); 86 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE); 87 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL); 88 get_random_bytes(&rand_num, sizeof(rand_num)); 89 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L); 90 get_random_bytes(&rand_num, sizeof(rand_num)); 91 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H); 92 ring_size.w = 0; 93 ring_size.bf.ring_offset = PPC4XX_PD_SIZE; 94 ring_size.bf.ring_size = PPC4XX_NUM_PD; 95 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE); 96 ring_ctrl.w = 0; 97 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL); 98 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL); 99 device_ctrl |= PPC4XX_DC_3DES_EN; 100 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL); 101 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE); 102 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE); 103 part_ring_size.w = 0; 104 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE; 105 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE; 106 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE); 107 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG); 108 io_threshold.w = 0; 109 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD; 110 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD; 111 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD); 112 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR); 113 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR); 114 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR); 115 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR); 116 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR); 117 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR); 118 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR); 119 /* un reset pe,sg and pdr */ 120 pe_dma_cfg.bf.pe_mode = 1; 121 pe_dma_cfg.bf.reset_sg = 0; 122 pe_dma_cfg.bf.reset_pdr = 0; 123 pe_dma_cfg.bf.reset_pe = 0; 124 pe_dma_cfg.bf.bo_td_en = 0; 125 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG); 126 /*clear all pending interrupt*/ 127 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR); 128 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT); 129 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT); 130 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG); 131 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN); 132 } 133 134 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size) 135 { 136 ctx->sa_in = kzalloc(size * 4, GFP_ATOMIC); 137 if (ctx->sa_in == NULL) 138 return -ENOMEM; 139 140 ctx->sa_out = kzalloc(size * 4, GFP_ATOMIC); 141 if (ctx->sa_out == NULL) { 142 kfree(ctx->sa_in); 143 ctx->sa_in = NULL; 144 return -ENOMEM; 145 } 146 147 ctx->sa_len = size; 148 149 return 0; 150 } 151 152 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx) 153 { 154 kfree(ctx->sa_in); 155 ctx->sa_in = NULL; 156 kfree(ctx->sa_out); 157 ctx->sa_out = NULL; 158 ctx->sa_len = 0; 159 } 160 161 /** 162 * alloc memory for the gather ring 163 * no need to alloc buf for the ring 164 * gdr_tail, gdr_head and gdr_count are initialized by this function 165 */ 166 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev) 167 { 168 int i; 169 dev->pdr = dma_alloc_coherent(dev->core_dev->device, 170 sizeof(struct ce_pd) * PPC4XX_NUM_PD, 171 &dev->pdr_pa, GFP_ATOMIC); 172 if (!dev->pdr) 173 return -ENOMEM; 174 175 dev->pdr_uinfo = kzalloc(sizeof(struct pd_uinfo) * PPC4XX_NUM_PD, 176 GFP_KERNEL); 177 if (!dev->pdr_uinfo) { 178 dma_free_coherent(dev->core_dev->device, 179 sizeof(struct ce_pd) * PPC4XX_NUM_PD, 180 dev->pdr, 181 dev->pdr_pa); 182 return -ENOMEM; 183 } 184 memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD); 185 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device, 186 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD, 187 &dev->shadow_sa_pool_pa, 188 GFP_ATOMIC); 189 if (!dev->shadow_sa_pool) 190 return -ENOMEM; 191 192 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device, 193 sizeof(struct sa_state_record) * PPC4XX_NUM_PD, 194 &dev->shadow_sr_pool_pa, GFP_ATOMIC); 195 if (!dev->shadow_sr_pool) 196 return -ENOMEM; 197 for (i = 0; i < PPC4XX_NUM_PD; i++) { 198 struct ce_pd *pd = &dev->pdr[i]; 199 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[i]; 200 201 pd->sa = dev->shadow_sa_pool_pa + 202 sizeof(union shadow_sa_buf) * i; 203 204 /* alloc 256 bytes which is enough for any kind of dynamic sa */ 205 pd_uinfo->sa_va = &dev->shadow_sa_pool[i].sa; 206 207 /* alloc state record */ 208 pd_uinfo->sr_va = &dev->shadow_sr_pool[i]; 209 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa + 210 sizeof(struct sa_state_record) * i; 211 } 212 213 return 0; 214 } 215 216 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev) 217 { 218 if (dev->pdr) 219 dma_free_coherent(dev->core_dev->device, 220 sizeof(struct ce_pd) * PPC4XX_NUM_PD, 221 dev->pdr, dev->pdr_pa); 222 223 if (dev->shadow_sa_pool) 224 dma_free_coherent(dev->core_dev->device, 225 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD, 226 dev->shadow_sa_pool, dev->shadow_sa_pool_pa); 227 228 if (dev->shadow_sr_pool) 229 dma_free_coherent(dev->core_dev->device, 230 sizeof(struct sa_state_record) * PPC4XX_NUM_PD, 231 dev->shadow_sr_pool, dev->shadow_sr_pool_pa); 232 233 kfree(dev->pdr_uinfo); 234 } 235 236 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev) 237 { 238 u32 retval; 239 u32 tmp; 240 241 retval = dev->pdr_head; 242 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD; 243 244 if (tmp == dev->pdr_tail) 245 return ERING_WAS_FULL; 246 247 dev->pdr_head = tmp; 248 249 return retval; 250 } 251 252 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx) 253 { 254 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx]; 255 u32 tail; 256 unsigned long flags; 257 258 spin_lock_irqsave(&dev->core_dev->lock, flags); 259 pd_uinfo->state = PD_ENTRY_FREE; 260 261 if (dev->pdr_tail != PPC4XX_LAST_PD) 262 dev->pdr_tail++; 263 else 264 dev->pdr_tail = 0; 265 tail = dev->pdr_tail; 266 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 267 268 return tail; 269 } 270 271 /** 272 * alloc memory for the gather ring 273 * no need to alloc buf for the ring 274 * gdr_tail, gdr_head and gdr_count are initialized by this function 275 */ 276 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev) 277 { 278 dev->gdr = dma_alloc_coherent(dev->core_dev->device, 279 sizeof(struct ce_gd) * PPC4XX_NUM_GD, 280 &dev->gdr_pa, GFP_ATOMIC); 281 if (!dev->gdr) 282 return -ENOMEM; 283 284 memset(dev->gdr, 0, sizeof(struct ce_gd) * PPC4XX_NUM_GD); 285 286 return 0; 287 } 288 289 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev) 290 { 291 dma_free_coherent(dev->core_dev->device, 292 sizeof(struct ce_gd) * PPC4XX_NUM_GD, 293 dev->gdr, dev->gdr_pa); 294 } 295 296 /* 297 * when this function is called. 298 * preemption or interrupt must be disabled 299 */ 300 static u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n) 301 { 302 u32 retval; 303 u32 tmp; 304 305 if (n >= PPC4XX_NUM_GD) 306 return ERING_WAS_FULL; 307 308 retval = dev->gdr_head; 309 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD; 310 if (dev->gdr_head > dev->gdr_tail) { 311 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail) 312 return ERING_WAS_FULL; 313 } else if (dev->gdr_head < dev->gdr_tail) { 314 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail) 315 return ERING_WAS_FULL; 316 } 317 dev->gdr_head = tmp; 318 319 return retval; 320 } 321 322 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev) 323 { 324 unsigned long flags; 325 326 spin_lock_irqsave(&dev->core_dev->lock, flags); 327 if (dev->gdr_tail == dev->gdr_head) { 328 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 329 return 0; 330 } 331 332 if (dev->gdr_tail != PPC4XX_LAST_GD) 333 dev->gdr_tail++; 334 else 335 dev->gdr_tail = 0; 336 337 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 338 339 return 0; 340 } 341 342 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev, 343 dma_addr_t *gd_dma, u32 idx) 344 { 345 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx; 346 347 return &dev->gdr[idx]; 348 } 349 350 /** 351 * alloc memory for the scatter ring 352 * need to alloc buf for the ring 353 * sdr_tail, sdr_head and sdr_count are initialized by this function 354 */ 355 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev) 356 { 357 int i; 358 359 /* alloc memory for scatter descriptor ring */ 360 dev->sdr = dma_alloc_coherent(dev->core_dev->device, 361 sizeof(struct ce_sd) * PPC4XX_NUM_SD, 362 &dev->sdr_pa, GFP_ATOMIC); 363 if (!dev->sdr) 364 return -ENOMEM; 365 366 dev->scatter_buffer_va = 367 dma_alloc_coherent(dev->core_dev->device, 368 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD, 369 &dev->scatter_buffer_pa, GFP_ATOMIC); 370 if (!dev->scatter_buffer_va) { 371 dma_free_coherent(dev->core_dev->device, 372 sizeof(struct ce_sd) * PPC4XX_NUM_SD, 373 dev->sdr, dev->sdr_pa); 374 return -ENOMEM; 375 } 376 377 for (i = 0; i < PPC4XX_NUM_SD; i++) { 378 dev->sdr[i].ptr = dev->scatter_buffer_pa + 379 PPC4XX_SD_BUFFER_SIZE * i; 380 } 381 382 return 0; 383 } 384 385 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev) 386 { 387 if (dev->sdr) 388 dma_free_coherent(dev->core_dev->device, 389 sizeof(struct ce_sd) * PPC4XX_NUM_SD, 390 dev->sdr, dev->sdr_pa); 391 392 if (dev->scatter_buffer_va) 393 dma_free_coherent(dev->core_dev->device, 394 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD, 395 dev->scatter_buffer_va, 396 dev->scatter_buffer_pa); 397 } 398 399 /* 400 * when this function is called. 401 * preemption or interrupt must be disabled 402 */ 403 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n) 404 { 405 u32 retval; 406 u32 tmp; 407 408 if (n >= PPC4XX_NUM_SD) 409 return ERING_WAS_FULL; 410 411 retval = dev->sdr_head; 412 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD; 413 if (dev->sdr_head > dev->gdr_tail) { 414 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail) 415 return ERING_WAS_FULL; 416 } else if (dev->sdr_head < dev->sdr_tail) { 417 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail) 418 return ERING_WAS_FULL; 419 } /* the head = tail, or empty case is already take cared */ 420 dev->sdr_head = tmp; 421 422 return retval; 423 } 424 425 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev) 426 { 427 unsigned long flags; 428 429 spin_lock_irqsave(&dev->core_dev->lock, flags); 430 if (dev->sdr_tail == dev->sdr_head) { 431 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 432 return 0; 433 } 434 if (dev->sdr_tail != PPC4XX_LAST_SD) 435 dev->sdr_tail++; 436 else 437 dev->sdr_tail = 0; 438 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 439 440 return 0; 441 } 442 443 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev, 444 dma_addr_t *sd_dma, u32 idx) 445 { 446 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx; 447 448 return &dev->sdr[idx]; 449 } 450 451 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev, 452 struct ce_pd *pd, 453 struct pd_uinfo *pd_uinfo, 454 u32 nbytes, 455 struct scatterlist *dst) 456 { 457 unsigned int first_sd = pd_uinfo->first_sd; 458 unsigned int last_sd; 459 unsigned int overflow = 0; 460 unsigned int to_copy; 461 unsigned int dst_start = 0; 462 463 /* 464 * Because the scatter buffers are all neatly organized in one 465 * big continuous ringbuffer; scatterwalk_map_and_copy() can 466 * be instructed to copy a range of buffers in one go. 467 */ 468 469 last_sd = (first_sd + pd_uinfo->num_sd); 470 if (last_sd > PPC4XX_LAST_SD) { 471 last_sd = PPC4XX_LAST_SD; 472 overflow = last_sd % PPC4XX_NUM_SD; 473 } 474 475 while (nbytes) { 476 void *buf = dev->scatter_buffer_va + 477 first_sd * PPC4XX_SD_BUFFER_SIZE; 478 479 to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE * 480 (1 + last_sd - first_sd)); 481 scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1); 482 nbytes -= to_copy; 483 484 if (overflow) { 485 first_sd = 0; 486 last_sd = overflow; 487 dst_start += to_copy; 488 overflow = 0; 489 } 490 } 491 } 492 493 static void crypto4xx_copy_digest_to_dst(void *dst, 494 struct pd_uinfo *pd_uinfo, 495 struct crypto4xx_ctx *ctx) 496 { 497 struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in; 498 499 if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) { 500 memcpy(dst, pd_uinfo->sr_va->save_digest, 501 SA_HASH_ALG_SHA1_DIGEST_SIZE); 502 } 503 } 504 505 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev, 506 struct pd_uinfo *pd_uinfo) 507 { 508 int i; 509 if (pd_uinfo->num_gd) { 510 for (i = 0; i < pd_uinfo->num_gd; i++) 511 crypto4xx_put_gd_to_gdr(dev); 512 pd_uinfo->first_gd = 0xffffffff; 513 pd_uinfo->num_gd = 0; 514 } 515 if (pd_uinfo->num_sd) { 516 for (i = 0; i < pd_uinfo->num_sd; i++) 517 crypto4xx_put_sd_to_sdr(dev); 518 519 pd_uinfo->first_sd = 0xffffffff; 520 pd_uinfo->num_sd = 0; 521 } 522 } 523 524 static void crypto4xx_ablkcipher_done(struct crypto4xx_device *dev, 525 struct pd_uinfo *pd_uinfo, 526 struct ce_pd *pd) 527 { 528 struct crypto4xx_ctx *ctx; 529 struct ablkcipher_request *ablk_req; 530 struct scatterlist *dst; 531 dma_addr_t addr; 532 533 ablk_req = ablkcipher_request_cast(pd_uinfo->async_req); 534 ctx = crypto_tfm_ctx(ablk_req->base.tfm); 535 536 if (pd_uinfo->using_sd) { 537 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, ablk_req->nbytes, 538 ablk_req->dst); 539 } else { 540 dst = pd_uinfo->dest_va; 541 addr = dma_map_page(dev->core_dev->device, sg_page(dst), 542 dst->offset, dst->length, DMA_FROM_DEVICE); 543 } 544 crypto4xx_ret_sg_desc(dev, pd_uinfo); 545 546 if (pd_uinfo->state & PD_ENTRY_BUSY) 547 ablkcipher_request_complete(ablk_req, -EINPROGRESS); 548 ablkcipher_request_complete(ablk_req, 0); 549 } 550 551 static void crypto4xx_ahash_done(struct crypto4xx_device *dev, 552 struct pd_uinfo *pd_uinfo) 553 { 554 struct crypto4xx_ctx *ctx; 555 struct ahash_request *ahash_req; 556 557 ahash_req = ahash_request_cast(pd_uinfo->async_req); 558 ctx = crypto_tfm_ctx(ahash_req->base.tfm); 559 560 crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, 561 crypto_tfm_ctx(ahash_req->base.tfm)); 562 crypto4xx_ret_sg_desc(dev, pd_uinfo); 563 564 if (pd_uinfo->state & PD_ENTRY_BUSY) 565 ahash_request_complete(ahash_req, -EINPROGRESS); 566 ahash_request_complete(ahash_req, 0); 567 } 568 569 static void crypto4xx_aead_done(struct crypto4xx_device *dev, 570 struct pd_uinfo *pd_uinfo, 571 struct ce_pd *pd) 572 { 573 struct aead_request *aead_req; 574 struct crypto4xx_ctx *ctx; 575 struct scatterlist *dst = pd_uinfo->dest_va; 576 int err = 0; 577 578 aead_req = container_of(pd_uinfo->async_req, struct aead_request, 579 base); 580 ctx = crypto_tfm_ctx(aead_req->base.tfm); 581 582 if (pd_uinfo->using_sd) { 583 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, 584 pd->pd_ctl_len.bf.pkt_len, 585 dst); 586 } else { 587 __dma_sync_page(sg_page(dst), dst->offset, dst->length, 588 DMA_FROM_DEVICE); 589 } 590 591 if (pd_uinfo->sa_va->sa_command_0.bf.dir == DIR_OUTBOUND) { 592 /* append icv at the end */ 593 size_t cp_len = crypto_aead_authsize( 594 crypto_aead_reqtfm(aead_req)); 595 u32 icv[cp_len]; 596 597 crypto4xx_memcpy_from_le32(icv, pd_uinfo->sr_va->save_digest, 598 cp_len); 599 600 scatterwalk_map_and_copy(icv, dst, aead_req->cryptlen, 601 cp_len, 1); 602 } 603 604 crypto4xx_ret_sg_desc(dev, pd_uinfo); 605 606 if (pd->pd_ctl.bf.status & 0xff) { 607 if (pd->pd_ctl.bf.status & 0x1) { 608 /* authentication error */ 609 err = -EBADMSG; 610 } else { 611 if (!__ratelimit(&dev->aead_ratelimit)) { 612 if (pd->pd_ctl.bf.status & 2) 613 pr_err("pad fail error\n"); 614 if (pd->pd_ctl.bf.status & 4) 615 pr_err("seqnum fail\n"); 616 if (pd->pd_ctl.bf.status & 8) 617 pr_err("error _notify\n"); 618 pr_err("aead return err status = 0x%02x\n", 619 pd->pd_ctl.bf.status & 0xff); 620 pr_err("pd pad_ctl = 0x%08x\n", 621 pd->pd_ctl.bf.pd_pad_ctl); 622 } 623 err = -EINVAL; 624 } 625 } 626 627 if (pd_uinfo->state & PD_ENTRY_BUSY) 628 aead_request_complete(aead_req, -EINPROGRESS); 629 630 aead_request_complete(aead_req, err); 631 } 632 633 static void crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx) 634 { 635 struct ce_pd *pd = &dev->pdr[idx]; 636 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx]; 637 638 switch (crypto_tfm_alg_type(pd_uinfo->async_req->tfm)) { 639 case CRYPTO_ALG_TYPE_ABLKCIPHER: 640 crypto4xx_ablkcipher_done(dev, pd_uinfo, pd); 641 break; 642 case CRYPTO_ALG_TYPE_AEAD: 643 crypto4xx_aead_done(dev, pd_uinfo, pd); 644 break; 645 case CRYPTO_ALG_TYPE_AHASH: 646 crypto4xx_ahash_done(dev, pd_uinfo); 647 break; 648 } 649 } 650 651 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev) 652 { 653 crypto4xx_destroy_pdr(core_dev->dev); 654 crypto4xx_destroy_gdr(core_dev->dev); 655 crypto4xx_destroy_sdr(core_dev->dev); 656 iounmap(core_dev->dev->ce_base); 657 kfree(core_dev->dev); 658 kfree(core_dev); 659 } 660 661 static u32 get_next_gd(u32 current) 662 { 663 if (current != PPC4XX_LAST_GD) 664 return current + 1; 665 else 666 return 0; 667 } 668 669 static u32 get_next_sd(u32 current) 670 { 671 if (current != PPC4XX_LAST_SD) 672 return current + 1; 673 else 674 return 0; 675 } 676 677 int crypto4xx_build_pd(struct crypto_async_request *req, 678 struct crypto4xx_ctx *ctx, 679 struct scatterlist *src, 680 struct scatterlist *dst, 681 const unsigned int datalen, 682 const __le32 *iv, const u32 iv_len, 683 const struct dynamic_sa_ctl *req_sa, 684 const unsigned int sa_len, 685 const unsigned int assoclen) 686 { 687 struct scatterlist _dst[2]; 688 struct crypto4xx_device *dev = ctx->dev; 689 struct dynamic_sa_ctl *sa; 690 struct ce_gd *gd; 691 struct ce_pd *pd; 692 u32 num_gd, num_sd; 693 u32 fst_gd = 0xffffffff; 694 u32 fst_sd = 0xffffffff; 695 u32 pd_entry; 696 unsigned long flags; 697 struct pd_uinfo *pd_uinfo; 698 unsigned int nbytes = datalen; 699 size_t offset_to_sr_ptr; 700 u32 gd_idx = 0; 701 int tmp; 702 bool is_busy; 703 704 /* figure how many gd are needed */ 705 tmp = sg_nents_for_len(src, assoclen + datalen); 706 if (tmp < 0) { 707 dev_err(dev->core_dev->device, "Invalid number of src SG.\n"); 708 return tmp; 709 } 710 if (tmp == 1) 711 tmp = 0; 712 num_gd = tmp; 713 714 if (assoclen) { 715 nbytes += assoclen; 716 dst = scatterwalk_ffwd(_dst, dst, assoclen); 717 } 718 719 /* figure how many sd are needed */ 720 if (sg_is_last(dst)) { 721 num_sd = 0; 722 } else { 723 if (datalen > PPC4XX_SD_BUFFER_SIZE) { 724 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE; 725 if (datalen % PPC4XX_SD_BUFFER_SIZE) 726 num_sd++; 727 } else { 728 num_sd = 1; 729 } 730 } 731 732 /* 733 * The follow section of code needs to be protected 734 * The gather ring and scatter ring needs to be consecutive 735 * In case of run out of any kind of descriptor, the descriptor 736 * already got must be return the original place. 737 */ 738 spin_lock_irqsave(&dev->core_dev->lock, flags); 739 /* 740 * Let the caller know to slow down, once more than 13/16ths = 81% 741 * of the available data contexts are being used simultaneously. 742 * 743 * With PPC4XX_NUM_PD = 256, this will leave a "backlog queue" for 744 * 31 more contexts. Before new requests have to be rejected. 745 */ 746 if (req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG) { 747 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >= 748 ((PPC4XX_NUM_PD * 13) / 16); 749 } else { 750 /* 751 * To fix contention issues between ipsec (no blacklog) and 752 * dm-crypto (backlog) reserve 32 entries for "no backlog" 753 * data contexts. 754 */ 755 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >= 756 ((PPC4XX_NUM_PD * 15) / 16); 757 758 if (is_busy) { 759 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 760 return -EBUSY; 761 } 762 } 763 764 if (num_gd) { 765 fst_gd = crypto4xx_get_n_gd(dev, num_gd); 766 if (fst_gd == ERING_WAS_FULL) { 767 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 768 return -EAGAIN; 769 } 770 } 771 if (num_sd) { 772 fst_sd = crypto4xx_get_n_sd(dev, num_sd); 773 if (fst_sd == ERING_WAS_FULL) { 774 if (num_gd) 775 dev->gdr_head = fst_gd; 776 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 777 return -EAGAIN; 778 } 779 } 780 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev); 781 if (pd_entry == ERING_WAS_FULL) { 782 if (num_gd) 783 dev->gdr_head = fst_gd; 784 if (num_sd) 785 dev->sdr_head = fst_sd; 786 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 787 return -EAGAIN; 788 } 789 spin_unlock_irqrestore(&dev->core_dev->lock, flags); 790 791 pd = &dev->pdr[pd_entry]; 792 pd->sa_len = sa_len; 793 794 pd_uinfo = &dev->pdr_uinfo[pd_entry]; 795 pd_uinfo->async_req = req; 796 pd_uinfo->num_gd = num_gd; 797 pd_uinfo->num_sd = num_sd; 798 799 if (iv_len) 800 memcpy(pd_uinfo->sr_va->save_iv, iv, iv_len); 801 802 sa = pd_uinfo->sa_va; 803 memcpy(sa, req_sa, sa_len * 4); 804 805 sa->sa_command_1.bf.hash_crypto_offset = (assoclen >> 2); 806 offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(sa); 807 *(u32 *)((unsigned long)sa + offset_to_sr_ptr) = pd_uinfo->sr_pa; 808 809 if (num_gd) { 810 dma_addr_t gd_dma; 811 struct scatterlist *sg; 812 813 /* get first gd we are going to use */ 814 gd_idx = fst_gd; 815 pd_uinfo->first_gd = fst_gd; 816 pd_uinfo->num_gd = num_gd; 817 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx); 818 pd->src = gd_dma; 819 /* enable gather */ 820 sa->sa_command_0.bf.gather = 1; 821 /* walk the sg, and setup gather array */ 822 823 sg = src; 824 while (nbytes) { 825 size_t len; 826 827 len = min(sg->length, nbytes); 828 gd->ptr = dma_map_page(dev->core_dev->device, 829 sg_page(sg), sg->offset, len, DMA_TO_DEVICE); 830 gd->ctl_len.len = len; 831 gd->ctl_len.done = 0; 832 gd->ctl_len.ready = 1; 833 if (len >= nbytes) 834 break; 835 836 nbytes -= sg->length; 837 gd_idx = get_next_gd(gd_idx); 838 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx); 839 sg = sg_next(sg); 840 } 841 } else { 842 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src), 843 src->offset, min(nbytes, src->length), 844 DMA_TO_DEVICE); 845 /* 846 * Disable gather in sa command 847 */ 848 sa->sa_command_0.bf.gather = 0; 849 /* 850 * Indicate gather array is not used 851 */ 852 pd_uinfo->first_gd = 0xffffffff; 853 pd_uinfo->num_gd = 0; 854 } 855 if (sg_is_last(dst)) { 856 /* 857 * we know application give us dst a whole piece of memory 858 * no need to use scatter ring. 859 */ 860 pd_uinfo->using_sd = 0; 861 pd_uinfo->first_sd = 0xffffffff; 862 pd_uinfo->num_sd = 0; 863 pd_uinfo->dest_va = dst; 864 sa->sa_command_0.bf.scatter = 0; 865 pd->dest = (u32)dma_map_page(dev->core_dev->device, 866 sg_page(dst), dst->offset, 867 min(datalen, dst->length), 868 DMA_TO_DEVICE); 869 } else { 870 dma_addr_t sd_dma; 871 struct ce_sd *sd = NULL; 872 873 u32 sd_idx = fst_sd; 874 nbytes = datalen; 875 sa->sa_command_0.bf.scatter = 1; 876 pd_uinfo->using_sd = 1; 877 pd_uinfo->dest_va = dst; 878 pd_uinfo->first_sd = fst_sd; 879 pd_uinfo->num_sd = num_sd; 880 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx); 881 pd->dest = sd_dma; 882 /* setup scatter descriptor */ 883 sd->ctl.done = 0; 884 sd->ctl.rdy = 1; 885 /* sd->ptr should be setup by sd_init routine*/ 886 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) 887 nbytes -= PPC4XX_SD_BUFFER_SIZE; 888 else 889 nbytes = 0; 890 while (nbytes) { 891 sd_idx = get_next_sd(sd_idx); 892 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx); 893 /* setup scatter descriptor */ 894 sd->ctl.done = 0; 895 sd->ctl.rdy = 1; 896 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) { 897 nbytes -= PPC4XX_SD_BUFFER_SIZE; 898 } else { 899 /* 900 * SD entry can hold PPC4XX_SD_BUFFER_SIZE, 901 * which is more than nbytes, so done. 902 */ 903 nbytes = 0; 904 } 905 } 906 } 907 908 pd->pd_ctl.w = PD_CTL_HOST_READY | 909 ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH) | 910 (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ? 911 PD_CTL_HASH_FINAL : 0); 912 pd->pd_ctl_len.w = 0x00400000 | (assoclen + datalen); 913 pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0); 914 915 wmb(); 916 /* write any value to push engine to read a pd */ 917 writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD); 918 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD); 919 return is_busy ? -EBUSY : -EINPROGRESS; 920 } 921 922 /** 923 * Algorithm Registration Functions 924 */ 925 static void crypto4xx_ctx_init(struct crypto4xx_alg *amcc_alg, 926 struct crypto4xx_ctx *ctx) 927 { 928 ctx->dev = amcc_alg->dev; 929 ctx->sa_in = NULL; 930 ctx->sa_out = NULL; 931 ctx->sa_len = 0; 932 } 933 934 static int crypto4xx_ablk_init(struct crypto_tfm *tfm) 935 { 936 struct crypto_alg *alg = tfm->__crt_alg; 937 struct crypto4xx_alg *amcc_alg; 938 struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm); 939 940 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.cipher); 941 crypto4xx_ctx_init(amcc_alg, ctx); 942 tfm->crt_ablkcipher.reqsize = sizeof(struct crypto4xx_ctx); 943 return 0; 944 } 945 946 static void crypto4xx_common_exit(struct crypto4xx_ctx *ctx) 947 { 948 crypto4xx_free_sa(ctx); 949 } 950 951 static void crypto4xx_ablk_exit(struct crypto_tfm *tfm) 952 { 953 crypto4xx_common_exit(crypto_tfm_ctx(tfm)); 954 } 955 956 static int crypto4xx_aead_init(struct crypto_aead *tfm) 957 { 958 struct aead_alg *alg = crypto_aead_alg(tfm); 959 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm); 960 struct crypto4xx_alg *amcc_alg; 961 962 ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0, 963 CRYPTO_ALG_NEED_FALLBACK | 964 CRYPTO_ALG_ASYNC); 965 if (IS_ERR(ctx->sw_cipher.aead)) 966 return PTR_ERR(ctx->sw_cipher.aead); 967 968 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.aead); 969 crypto4xx_ctx_init(amcc_alg, ctx); 970 crypto_aead_set_reqsize(tfm, sizeof(struct aead_request) + 971 max(sizeof(struct crypto4xx_ctx), 32 + 972 crypto_aead_reqsize(ctx->sw_cipher.aead))); 973 return 0; 974 } 975 976 static void crypto4xx_aead_exit(struct crypto_aead *tfm) 977 { 978 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm); 979 980 crypto4xx_common_exit(ctx); 981 crypto_free_aead(ctx->sw_cipher.aead); 982 } 983 984 static int crypto4xx_register_alg(struct crypto4xx_device *sec_dev, 985 struct crypto4xx_alg_common *crypto_alg, 986 int array_size) 987 { 988 struct crypto4xx_alg *alg; 989 int i; 990 int rc = 0; 991 992 for (i = 0; i < array_size; i++) { 993 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL); 994 if (!alg) 995 return -ENOMEM; 996 997 alg->alg = crypto_alg[i]; 998 alg->dev = sec_dev; 999 1000 switch (alg->alg.type) { 1001 case CRYPTO_ALG_TYPE_AEAD: 1002 rc = crypto_register_aead(&alg->alg.u.aead); 1003 break; 1004 1005 case CRYPTO_ALG_TYPE_AHASH: 1006 rc = crypto_register_ahash(&alg->alg.u.hash); 1007 break; 1008 1009 default: 1010 rc = crypto_register_alg(&alg->alg.u.cipher); 1011 break; 1012 } 1013 1014 if (rc) 1015 kfree(alg); 1016 else 1017 list_add_tail(&alg->entry, &sec_dev->alg_list); 1018 } 1019 1020 return 0; 1021 } 1022 1023 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev) 1024 { 1025 struct crypto4xx_alg *alg, *tmp; 1026 1027 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) { 1028 list_del(&alg->entry); 1029 switch (alg->alg.type) { 1030 case CRYPTO_ALG_TYPE_AHASH: 1031 crypto_unregister_ahash(&alg->alg.u.hash); 1032 break; 1033 1034 case CRYPTO_ALG_TYPE_AEAD: 1035 crypto_unregister_aead(&alg->alg.u.aead); 1036 break; 1037 1038 default: 1039 crypto_unregister_alg(&alg->alg.u.cipher); 1040 } 1041 kfree(alg); 1042 } 1043 } 1044 1045 static void crypto4xx_bh_tasklet_cb(unsigned long data) 1046 { 1047 struct device *dev = (struct device *)data; 1048 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev); 1049 struct pd_uinfo *pd_uinfo; 1050 struct ce_pd *pd; 1051 u32 tail = core_dev->dev->pdr_tail; 1052 u32 head = core_dev->dev->pdr_head; 1053 1054 do { 1055 pd_uinfo = &core_dev->dev->pdr_uinfo[tail]; 1056 pd = &core_dev->dev->pdr[tail]; 1057 if ((pd_uinfo->state & PD_ENTRY_INUSE) && 1058 ((READ_ONCE(pd->pd_ctl.w) & 1059 (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) == 1060 PD_CTL_PE_DONE)) { 1061 crypto4xx_pd_done(core_dev->dev, tail); 1062 tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail); 1063 } else { 1064 /* if tail not done, break */ 1065 break; 1066 } 1067 } while (head != tail); 1068 } 1069 1070 /** 1071 * Top Half of isr. 1072 */ 1073 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data) 1074 { 1075 struct device *dev = (struct device *)data; 1076 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev); 1077 1078 if (!core_dev->dev->ce_base) 1079 return 0; 1080 1081 writel(PPC4XX_INTERRUPT_CLR, 1082 core_dev->dev->ce_base + CRYPTO4XX_INT_CLR); 1083 tasklet_schedule(&core_dev->tasklet); 1084 1085 return IRQ_HANDLED; 1086 } 1087 1088 /** 1089 * Supported Crypto Algorithms 1090 */ 1091 static struct crypto4xx_alg_common crypto4xx_alg[] = { 1092 /* Crypto AES modes */ 1093 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = { 1094 .cra_name = "cbc(aes)", 1095 .cra_driver_name = "cbc-aes-ppc4xx", 1096 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1097 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 1098 CRYPTO_ALG_ASYNC | 1099 CRYPTO_ALG_KERN_DRIVER_ONLY, 1100 .cra_blocksize = AES_BLOCK_SIZE, 1101 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1102 .cra_type = &crypto_ablkcipher_type, 1103 .cra_init = crypto4xx_ablk_init, 1104 .cra_exit = crypto4xx_ablk_exit, 1105 .cra_module = THIS_MODULE, 1106 .cra_u = { 1107 .ablkcipher = { 1108 .min_keysize = AES_MIN_KEY_SIZE, 1109 .max_keysize = AES_MAX_KEY_SIZE, 1110 .ivsize = AES_IV_SIZE, 1111 .setkey = crypto4xx_setkey_aes_cbc, 1112 .encrypt = crypto4xx_encrypt, 1113 .decrypt = crypto4xx_decrypt, 1114 } 1115 } 1116 }}, 1117 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = { 1118 .cra_name = "cfb(aes)", 1119 .cra_driver_name = "cfb-aes-ppc4xx", 1120 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1121 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 1122 CRYPTO_ALG_ASYNC | 1123 CRYPTO_ALG_KERN_DRIVER_ONLY, 1124 .cra_blocksize = AES_BLOCK_SIZE, 1125 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1126 .cra_type = &crypto_ablkcipher_type, 1127 .cra_init = crypto4xx_ablk_init, 1128 .cra_exit = crypto4xx_ablk_exit, 1129 .cra_module = THIS_MODULE, 1130 .cra_u = { 1131 .ablkcipher = { 1132 .min_keysize = AES_MIN_KEY_SIZE, 1133 .max_keysize = AES_MAX_KEY_SIZE, 1134 .ivsize = AES_IV_SIZE, 1135 .setkey = crypto4xx_setkey_aes_cfb, 1136 .encrypt = crypto4xx_encrypt, 1137 .decrypt = crypto4xx_decrypt, 1138 } 1139 } 1140 } }, 1141 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = { 1142 .cra_name = "rfc3686(ctr(aes))", 1143 .cra_driver_name = "rfc3686-ctr-aes-ppc4xx", 1144 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1145 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 1146 CRYPTO_ALG_ASYNC | 1147 CRYPTO_ALG_KERN_DRIVER_ONLY, 1148 .cra_blocksize = AES_BLOCK_SIZE, 1149 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1150 .cra_type = &crypto_ablkcipher_type, 1151 .cra_init = crypto4xx_ablk_init, 1152 .cra_exit = crypto4xx_ablk_exit, 1153 .cra_module = THIS_MODULE, 1154 .cra_u = { 1155 .ablkcipher = { 1156 .min_keysize = AES_MIN_KEY_SIZE + 1157 CTR_RFC3686_NONCE_SIZE, 1158 .max_keysize = AES_MAX_KEY_SIZE + 1159 CTR_RFC3686_NONCE_SIZE, 1160 .ivsize = CTR_RFC3686_IV_SIZE, 1161 .setkey = crypto4xx_setkey_rfc3686, 1162 .encrypt = crypto4xx_rfc3686_encrypt, 1163 .decrypt = crypto4xx_rfc3686_decrypt, 1164 } 1165 } 1166 } }, 1167 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = { 1168 .cra_name = "ecb(aes)", 1169 .cra_driver_name = "ecb-aes-ppc4xx", 1170 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1171 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 1172 CRYPTO_ALG_ASYNC | 1173 CRYPTO_ALG_KERN_DRIVER_ONLY, 1174 .cra_blocksize = AES_BLOCK_SIZE, 1175 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1176 .cra_type = &crypto_ablkcipher_type, 1177 .cra_init = crypto4xx_ablk_init, 1178 .cra_exit = crypto4xx_ablk_exit, 1179 .cra_module = THIS_MODULE, 1180 .cra_u = { 1181 .ablkcipher = { 1182 .min_keysize = AES_MIN_KEY_SIZE, 1183 .max_keysize = AES_MAX_KEY_SIZE, 1184 .setkey = crypto4xx_setkey_aes_ecb, 1185 .encrypt = crypto4xx_encrypt, 1186 .decrypt = crypto4xx_decrypt, 1187 } 1188 } 1189 } }, 1190 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = { 1191 .cra_name = "ofb(aes)", 1192 .cra_driver_name = "ofb-aes-ppc4xx", 1193 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1194 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 1195 CRYPTO_ALG_ASYNC | 1196 CRYPTO_ALG_KERN_DRIVER_ONLY, 1197 .cra_blocksize = AES_BLOCK_SIZE, 1198 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1199 .cra_type = &crypto_ablkcipher_type, 1200 .cra_init = crypto4xx_ablk_init, 1201 .cra_exit = crypto4xx_ablk_exit, 1202 .cra_module = THIS_MODULE, 1203 .cra_u = { 1204 .ablkcipher = { 1205 .min_keysize = AES_MIN_KEY_SIZE, 1206 .max_keysize = AES_MAX_KEY_SIZE, 1207 .ivsize = AES_IV_SIZE, 1208 .setkey = crypto4xx_setkey_aes_ofb, 1209 .encrypt = crypto4xx_encrypt, 1210 .decrypt = crypto4xx_decrypt, 1211 } 1212 } 1213 } }, 1214 1215 /* AEAD */ 1216 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = { 1217 .setkey = crypto4xx_setkey_aes_ccm, 1218 .setauthsize = crypto4xx_setauthsize_aead, 1219 .encrypt = crypto4xx_encrypt_aes_ccm, 1220 .decrypt = crypto4xx_decrypt_aes_ccm, 1221 .init = crypto4xx_aead_init, 1222 .exit = crypto4xx_aead_exit, 1223 .ivsize = AES_BLOCK_SIZE, 1224 .maxauthsize = 16, 1225 .base = { 1226 .cra_name = "ccm(aes)", 1227 .cra_driver_name = "ccm-aes-ppc4xx", 1228 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1229 .cra_flags = CRYPTO_ALG_ASYNC | 1230 CRYPTO_ALG_NEED_FALLBACK | 1231 CRYPTO_ALG_KERN_DRIVER_ONLY, 1232 .cra_blocksize = 1, 1233 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1234 .cra_module = THIS_MODULE, 1235 }, 1236 } }, 1237 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = { 1238 .setkey = crypto4xx_setkey_aes_gcm, 1239 .setauthsize = crypto4xx_setauthsize_aead, 1240 .encrypt = crypto4xx_encrypt_aes_gcm, 1241 .decrypt = crypto4xx_decrypt_aes_gcm, 1242 .init = crypto4xx_aead_init, 1243 .exit = crypto4xx_aead_exit, 1244 .ivsize = GCM_AES_IV_SIZE, 1245 .maxauthsize = 16, 1246 .base = { 1247 .cra_name = "gcm(aes)", 1248 .cra_driver_name = "gcm-aes-ppc4xx", 1249 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY, 1250 .cra_flags = CRYPTO_ALG_ASYNC | 1251 CRYPTO_ALG_NEED_FALLBACK | 1252 CRYPTO_ALG_KERN_DRIVER_ONLY, 1253 .cra_blocksize = 1, 1254 .cra_ctxsize = sizeof(struct crypto4xx_ctx), 1255 .cra_module = THIS_MODULE, 1256 }, 1257 } }, 1258 }; 1259 1260 /** 1261 * Module Initialization Routine 1262 */ 1263 static int crypto4xx_probe(struct platform_device *ofdev) 1264 { 1265 int rc; 1266 struct resource res; 1267 struct device *dev = &ofdev->dev; 1268 struct crypto4xx_core_device *core_dev; 1269 1270 rc = of_address_to_resource(ofdev->dev.of_node, 0, &res); 1271 if (rc) 1272 return -ENODEV; 1273 1274 if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) { 1275 mtdcri(SDR0, PPC460EX_SDR0_SRST, 1276 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET); 1277 mtdcri(SDR0, PPC460EX_SDR0_SRST, 1278 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET); 1279 } else if (of_find_compatible_node(NULL, NULL, 1280 "amcc,ppc405ex-crypto")) { 1281 mtdcri(SDR0, PPC405EX_SDR0_SRST, 1282 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET); 1283 mtdcri(SDR0, PPC405EX_SDR0_SRST, 1284 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET); 1285 } else if (of_find_compatible_node(NULL, NULL, 1286 "amcc,ppc460sx-crypto")) { 1287 mtdcri(SDR0, PPC460SX_SDR0_SRST, 1288 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET); 1289 mtdcri(SDR0, PPC460SX_SDR0_SRST, 1290 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET); 1291 } else { 1292 printk(KERN_ERR "Crypto Function Not supported!\n"); 1293 return -EINVAL; 1294 } 1295 1296 core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL); 1297 if (!core_dev) 1298 return -ENOMEM; 1299 1300 dev_set_drvdata(dev, core_dev); 1301 core_dev->ofdev = ofdev; 1302 core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL); 1303 rc = -ENOMEM; 1304 if (!core_dev->dev) 1305 goto err_alloc_dev; 1306 1307 core_dev->dev->core_dev = core_dev; 1308 core_dev->device = dev; 1309 spin_lock_init(&core_dev->lock); 1310 INIT_LIST_HEAD(&core_dev->dev->alg_list); 1311 ratelimit_default_init(&core_dev->dev->aead_ratelimit); 1312 rc = crypto4xx_build_pdr(core_dev->dev); 1313 if (rc) 1314 goto err_build_pdr; 1315 1316 rc = crypto4xx_build_gdr(core_dev->dev); 1317 if (rc) 1318 goto err_build_pdr; 1319 1320 rc = crypto4xx_build_sdr(core_dev->dev); 1321 if (rc) 1322 goto err_build_sdr; 1323 1324 /* Init tasklet for bottom half processing */ 1325 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb, 1326 (unsigned long) dev); 1327 1328 /* Register for Crypto isr, Crypto Engine IRQ */ 1329 core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1330 rc = request_irq(core_dev->irq, crypto4xx_ce_interrupt_handler, 0, 1331 core_dev->dev->name, dev); 1332 if (rc) 1333 goto err_request_irq; 1334 1335 core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0); 1336 if (!core_dev->dev->ce_base) { 1337 dev_err(dev, "failed to of_iomap\n"); 1338 rc = -ENOMEM; 1339 goto err_iomap; 1340 } 1341 1342 /* need to setup pdr, rdr, gdr and sdr before this */ 1343 crypto4xx_hw_init(core_dev->dev); 1344 1345 /* Register security algorithms with Linux CryptoAPI */ 1346 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg, 1347 ARRAY_SIZE(crypto4xx_alg)); 1348 if (rc) 1349 goto err_start_dev; 1350 1351 ppc4xx_trng_probe(core_dev); 1352 return 0; 1353 1354 err_start_dev: 1355 iounmap(core_dev->dev->ce_base); 1356 err_iomap: 1357 free_irq(core_dev->irq, dev); 1358 err_request_irq: 1359 irq_dispose_mapping(core_dev->irq); 1360 tasklet_kill(&core_dev->tasklet); 1361 err_build_sdr: 1362 crypto4xx_destroy_sdr(core_dev->dev); 1363 crypto4xx_destroy_gdr(core_dev->dev); 1364 err_build_pdr: 1365 crypto4xx_destroy_pdr(core_dev->dev); 1366 kfree(core_dev->dev); 1367 err_alloc_dev: 1368 kfree(core_dev); 1369 1370 return rc; 1371 } 1372 1373 static int crypto4xx_remove(struct platform_device *ofdev) 1374 { 1375 struct device *dev = &ofdev->dev; 1376 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev); 1377 1378 ppc4xx_trng_remove(core_dev); 1379 1380 free_irq(core_dev->irq, dev); 1381 irq_dispose_mapping(core_dev->irq); 1382 1383 tasklet_kill(&core_dev->tasklet); 1384 /* Un-register with Linux CryptoAPI */ 1385 crypto4xx_unregister_alg(core_dev->dev); 1386 /* Free all allocated memory */ 1387 crypto4xx_stop_all(core_dev); 1388 1389 return 0; 1390 } 1391 1392 static const struct of_device_id crypto4xx_match[] = { 1393 { .compatible = "amcc,ppc4xx-crypto",}, 1394 { }, 1395 }; 1396 MODULE_DEVICE_TABLE(of, crypto4xx_match); 1397 1398 static struct platform_driver crypto4xx_driver = { 1399 .driver = { 1400 .name = MODULE_NAME, 1401 .of_match_table = crypto4xx_match, 1402 }, 1403 .probe = crypto4xx_probe, 1404 .remove = crypto4xx_remove, 1405 }; 1406 1407 module_platform_driver(crypto4xx_driver); 1408 1409 MODULE_LICENSE("GPL"); 1410 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>"); 1411 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator"); 1412