1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI CPUFreq/OPP hw-supported driver 4 * 5 * Copyright (C) 2016-2017 Texas Instruments, Inc. 6 * Dave Gerlach <d-gerlach@ti.com> 7 */ 8 9 #include <linux/cpu.h> 10 #include <linux/io.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 20 #define REVISION_MASK 0xF 21 #define REVISION_SHIFT 28 22 23 #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F 24 #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA 25 26 #define DRA7_EFUSE_HAS_OD_MPU_OPP 11 27 #define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15 28 #define DRA7_EFUSE_HAS_ALL_MPU_OPP 23 29 30 #define DRA7_EFUSE_NOM_MPU_OPP BIT(0) 31 #define DRA7_EFUSE_OD_MPU_OPP BIT(1) 32 #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) 33 34 #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C 35 #define OMAP3_CONTROL_IDCODE 0x4830A204 36 #define OMAP34xx_ProdID_SKUID 0x4830A20C 37 #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270) 38 39 #define VERSION_COUNT 2 40 41 struct ti_cpufreq_data; 42 43 struct ti_cpufreq_soc_data { 44 const char * const *reg_names; 45 unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data, 46 unsigned long efuse); 47 unsigned long efuse_fallback; 48 unsigned long efuse_offset; 49 unsigned long efuse_mask; 50 unsigned long efuse_shift; 51 unsigned long rev_offset; 52 bool multi_regulator; 53 }; 54 55 struct ti_cpufreq_data { 56 struct device *cpu_dev; 57 struct device_node *opp_node; 58 struct regmap *syscon; 59 const struct ti_cpufreq_soc_data *soc_data; 60 struct opp_table *opp_table; 61 }; 62 63 static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data, 64 unsigned long efuse) 65 { 66 if (!efuse) 67 efuse = opp_data->soc_data->efuse_fallback; 68 /* AM335x and AM437x use "OPP disable" bits, so invert */ 69 return ~efuse; 70 } 71 72 static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, 73 unsigned long efuse) 74 { 75 unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP; 76 77 /* 78 * The efuse on dra7 and am57 parts contains a specific 79 * value indicating the highest available OPP. 80 */ 81 82 switch (efuse) { 83 case DRA7_EFUSE_HAS_ALL_MPU_OPP: 84 case DRA7_EFUSE_HAS_HIGH_MPU_OPP: 85 calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP; 86 /* Fall through */ 87 case DRA7_EFUSE_HAS_OD_MPU_OPP: 88 calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP; 89 } 90 91 return calculated_efuse; 92 } 93 94 static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, 95 unsigned long efuse) 96 { 97 /* OPP enable bit ("Speed Binned") */ 98 return BIT(efuse); 99 } 100 101 static struct ti_cpufreq_soc_data am3x_soc_data = { 102 .efuse_xlate = amx3_efuse_xlate, 103 .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, 104 .efuse_offset = 0x07fc, 105 .efuse_mask = 0x1fff, 106 .rev_offset = 0x600, 107 .multi_regulator = false, 108 }; 109 110 static struct ti_cpufreq_soc_data am4x_soc_data = { 111 .efuse_xlate = amx3_efuse_xlate, 112 .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ, 113 .efuse_offset = 0x0610, 114 .efuse_mask = 0x3f, 115 .rev_offset = 0x600, 116 .multi_regulator = false, 117 }; 118 119 static struct ti_cpufreq_soc_data dra7_soc_data = { 120 .efuse_xlate = dra7_efuse_xlate, 121 .efuse_offset = 0x020c, 122 .efuse_mask = 0xf80000, 123 .efuse_shift = 19, 124 .rev_offset = 0x204, 125 .multi_regulator = true, 126 }; 127 128 /* 129 * OMAP35x TRM (SPRUF98K): 130 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. 131 * Control OMAP Status Register 15:0 (Address 0x4800 244C) 132 * to separate between omap3503, omap3515, omap3525, omap3530 133 * and feature presence. 134 * There are encodings for versions limited to 400/266MHz 135 * but we ignore. 136 * Not clear if this also holds for omap34xx. 137 * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1 138 * are stored in the SYSCON register range 139 * Register 0x4830A20C [ProdID.SKUID] [0:3] 140 * 0x0 for normal 600/430MHz device. 141 * 0x8 for 720/520MHz device. 142 * Not clear what omap34xx value is. 143 */ 144 145 static struct ti_cpufreq_soc_data omap34xx_soc_data = { 146 .efuse_xlate = omap3_efuse_xlate, 147 .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE, 148 .efuse_shift = 3, 149 .efuse_mask = BIT(3), 150 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, 151 .multi_regulator = false, 152 }; 153 154 /* 155 * AM/DM37x TRM (SPRUGN4M) 156 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. 157 * Control Device Status Register 15:0 (Address 0x4800 244C) 158 * to separate between am3703, am3715, dm3725, dm3730 159 * and feature presence. 160 * Speed Binned = Bit 9 161 * 0 800/600 MHz 162 * 1 1000/800 MHz 163 * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1 164 * are stored in the SYSCON register range. 165 * There is no 0x4830A20C [ProdID.SKUID] register (exists but 166 * seems to always read as 0). 167 */ 168 169 static const char * const omap3_reg_names[] = {"cpu0", "vbb"}; 170 171 static struct ti_cpufreq_soc_data omap36xx_soc_data = { 172 .reg_names = omap3_reg_names, 173 .efuse_xlate = omap3_efuse_xlate, 174 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, 175 .efuse_shift = 9, 176 .efuse_mask = BIT(9), 177 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, 178 .multi_regulator = true, 179 }; 180 181 /* 182 * AM3517 is quite similar to AM/DM37x except that it has no 183 * high speed grade eFuse and no abb ldo 184 */ 185 186 static struct ti_cpufreq_soc_data am3517_soc_data = { 187 .efuse_xlate = omap3_efuse_xlate, 188 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, 189 .efuse_shift = 0, 190 .efuse_mask = 0, 191 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, 192 .multi_regulator = false, 193 }; 194 195 196 /** 197 * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC 198 * @opp_data: pointer to ti_cpufreq_data context 199 * @efuse_value: Set to the value parsed from efuse 200 * 201 * Returns error code if efuse not read properly. 202 */ 203 static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, 204 u32 *efuse_value) 205 { 206 struct device *dev = opp_data->cpu_dev; 207 u32 efuse; 208 int ret; 209 210 ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, 211 &efuse); 212 if (ret == -EIO) { 213 /* not a syscon register! */ 214 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + 215 opp_data->soc_data->efuse_offset, 4); 216 217 if (!regs) 218 return -ENOMEM; 219 efuse = readl(regs); 220 iounmap(regs); 221 } 222 else if (ret) { 223 dev_err(dev, 224 "Failed to read the efuse value from syscon: %d\n", 225 ret); 226 return ret; 227 } 228 229 efuse = (efuse & opp_data->soc_data->efuse_mask); 230 efuse >>= opp_data->soc_data->efuse_shift; 231 232 *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); 233 234 return 0; 235 } 236 237 /** 238 * ti_cpufreq_get_rev() - Parse and return rev value present on SoC 239 * @opp_data: pointer to ti_cpufreq_data context 240 * @revision_value: Set to the value parsed from revision register 241 * 242 * Returns error code if revision not read properly. 243 */ 244 static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, 245 u32 *revision_value) 246 { 247 struct device *dev = opp_data->cpu_dev; 248 u32 revision; 249 int ret; 250 251 ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, 252 &revision); 253 if (ret == -EIO) { 254 /* not a syscon register! */ 255 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + 256 opp_data->soc_data->rev_offset, 4); 257 258 if (!regs) 259 return -ENOMEM; 260 revision = readl(regs); 261 iounmap(regs); 262 } 263 else if (ret) { 264 dev_err(dev, 265 "Failed to read the revision number from syscon: %d\n", 266 ret); 267 return ret; 268 } 269 270 *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); 271 272 return 0; 273 } 274 275 static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data) 276 { 277 struct device *dev = opp_data->cpu_dev; 278 struct device_node *np = opp_data->opp_node; 279 280 opp_data->syscon = syscon_regmap_lookup_by_phandle(np, 281 "syscon"); 282 if (IS_ERR(opp_data->syscon)) { 283 dev_err(dev, 284 "\"syscon\" is missing, cannot use OPPv2 table.\n"); 285 return PTR_ERR(opp_data->syscon); 286 } 287 288 return 0; 289 } 290 291 static const struct of_device_id ti_cpufreq_of_match[] = { 292 { .compatible = "ti,am33xx", .data = &am3x_soc_data, }, 293 { .compatible = "ti,am3517", .data = &am3517_soc_data, }, 294 { .compatible = "ti,am43", .data = &am4x_soc_data, }, 295 { .compatible = "ti,dra7", .data = &dra7_soc_data }, 296 { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, 297 { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, 298 /* legacy */ 299 { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, 300 { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, }, 301 {}, 302 }; 303 304 static const struct of_device_id *ti_cpufreq_match_node(void) 305 { 306 struct device_node *np; 307 const struct of_device_id *match; 308 309 np = of_find_node_by_path("/"); 310 match = of_match_node(ti_cpufreq_of_match, np); 311 of_node_put(np); 312 313 return match; 314 } 315 316 static int ti_cpufreq_probe(struct platform_device *pdev) 317 { 318 u32 version[VERSION_COUNT]; 319 const struct of_device_id *match; 320 struct opp_table *ti_opp_table; 321 struct ti_cpufreq_data *opp_data; 322 const char * const default_reg_names[] = {"vdd", "vbb"}; 323 int ret; 324 325 match = dev_get_platdata(&pdev->dev); 326 if (!match) 327 return -ENODEV; 328 329 opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL); 330 if (!opp_data) 331 return -ENOMEM; 332 333 opp_data->soc_data = match->data; 334 335 opp_data->cpu_dev = get_cpu_device(0); 336 if (!opp_data->cpu_dev) { 337 pr_err("%s: Failed to get device for CPU0\n", __func__); 338 return -ENODEV; 339 } 340 341 opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev); 342 if (!opp_data->opp_node) { 343 dev_info(opp_data->cpu_dev, 344 "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n"); 345 goto register_cpufreq_dt; 346 } 347 348 ret = ti_cpufreq_setup_syscon_register(opp_data); 349 if (ret) 350 goto fail_put_node; 351 352 /* 353 * OPPs determine whether or not they are supported based on 354 * two metrics: 355 * 0 - SoC Revision 356 * 1 - eFuse value 357 */ 358 ret = ti_cpufreq_get_rev(opp_data, &version[0]); 359 if (ret) 360 goto fail_put_node; 361 362 ret = ti_cpufreq_get_efuse(opp_data, &version[1]); 363 if (ret) 364 goto fail_put_node; 365 366 ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev, 367 version, VERSION_COUNT); 368 if (IS_ERR(ti_opp_table)) { 369 dev_err(opp_data->cpu_dev, 370 "Failed to set supported hardware\n"); 371 ret = PTR_ERR(ti_opp_table); 372 goto fail_put_node; 373 } 374 375 opp_data->opp_table = ti_opp_table; 376 377 if (opp_data->soc_data->multi_regulator) { 378 const char * const *reg_names = default_reg_names; 379 380 if (opp_data->soc_data->reg_names) 381 reg_names = opp_data->soc_data->reg_names; 382 ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev, 383 reg_names, 384 ARRAY_SIZE(default_reg_names)); 385 if (IS_ERR(ti_opp_table)) { 386 dev_pm_opp_put_supported_hw(opp_data->opp_table); 387 ret = PTR_ERR(ti_opp_table); 388 goto fail_put_node; 389 } 390 } 391 392 of_node_put(opp_data->opp_node); 393 register_cpufreq_dt: 394 platform_device_register_simple("cpufreq-dt", -1, NULL, 0); 395 396 return 0; 397 398 fail_put_node: 399 of_node_put(opp_data->opp_node); 400 401 return ret; 402 } 403 404 static int ti_cpufreq_init(void) 405 { 406 const struct of_device_id *match; 407 408 /* Check to ensure we are on a compatible platform */ 409 match = ti_cpufreq_match_node(); 410 if (match) 411 platform_device_register_data(NULL, "ti-cpufreq", -1, match, 412 sizeof(*match)); 413 414 return 0; 415 } 416 module_init(ti_cpufreq_init); 417 418 static struct platform_driver ti_cpufreq_driver = { 419 .probe = ti_cpufreq_probe, 420 .driver = { 421 .name = "ti-cpufreq", 422 }, 423 }; 424 builtin_platform_driver(ti_cpufreq_driver); 425 426 MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver"); 427 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>"); 428 MODULE_LICENSE("GPL v2"); 429