1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved 4 */ 5 6 #include <linux/cpu.h> 7 #include <linux/cpufreq.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include <asm/smp_plat.h> 17 18 #include <soc/tegra/bpmp.h> 19 #include <soc/tegra/bpmp-abi.h> 20 21 #define KHZ 1000 22 #define REF_CLK_MHZ 408 /* 408 MHz */ 23 #define US_DELAY 500 24 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ) 25 #define MAX_CNT ~0U 26 27 #define NDIV_MASK 0x1FF 28 29 #define CORE_OFFSET(cpu) (cpu * 8) 30 #define CMU_CLKS_BASE 0x2000 31 #define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu)) 32 33 #define MMCRAB_CLUSTER_BASE(cl) (0x30000 + (cl * 0x10000)) 34 #define CLUSTER_ACTMON_BASE(data, cl) \ 35 (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base)) 36 #define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu)) 37 38 /* cpufreq transisition latency */ 39 #define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */ 40 41 struct tegra_cpu_ctr { 42 u32 cpu; 43 u32 coreclk_cnt, last_coreclk_cnt; 44 u32 refclk_cnt, last_refclk_cnt; 45 }; 46 47 struct read_counters_work { 48 struct work_struct work; 49 struct tegra_cpu_ctr c; 50 }; 51 52 struct tegra_cpufreq_ops { 53 void (*read_counters)(struct tegra_cpu_ctr *c); 54 void (*set_cpu_ndiv)(struct cpufreq_policy *policy, u64 ndiv); 55 void (*get_cpu_cluster_id)(u32 cpu, u32 *cpuid, u32 *clusterid); 56 int (*get_cpu_ndiv)(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv); 57 }; 58 59 struct tegra_cpufreq_soc { 60 struct tegra_cpufreq_ops *ops; 61 int maxcpus_per_cluster; 62 unsigned int num_clusters; 63 phys_addr_t actmon_cntr_base; 64 }; 65 66 struct tegra194_cpufreq_data { 67 void __iomem *regs; 68 struct cpufreq_frequency_table **tables; 69 const struct tegra_cpufreq_soc *soc; 70 }; 71 72 static struct workqueue_struct *read_counters_wq; 73 74 static void tegra_get_cpu_mpidr(void *mpidr) 75 { 76 *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; 77 } 78 79 static void tegra234_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) 80 { 81 u64 mpidr; 82 83 smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); 84 85 if (cpuid) 86 *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1); 87 if (clusterid) 88 *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2); 89 } 90 91 static int tegra234_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) 92 { 93 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 94 void __iomem *freq_core_reg; 95 u64 mpidr_id; 96 97 /* use physical id to get address of per core frequency register */ 98 mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; 99 freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id); 100 101 *ndiv = readl(freq_core_reg) & NDIV_MASK; 102 103 return 0; 104 } 105 106 static void tegra234_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) 107 { 108 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 109 void __iomem *freq_core_reg; 110 u32 cpu, cpuid, clusterid; 111 u64 mpidr_id; 112 113 for_each_cpu_and(cpu, policy->cpus, cpu_online_mask) { 114 data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid); 115 116 /* use physical id to get address of per core frequency register */ 117 mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; 118 freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id); 119 120 writel(ndiv, freq_core_reg); 121 } 122 } 123 124 /* 125 * This register provides access to two counter values with a single 126 * 64-bit read. The counter values are used to determine the average 127 * actual frequency a core has run at over a period of time. 128 * [63:32] PLLP counter: Counts at fixed frequency (408 MHz) 129 * [31:0] Core clock counter: Counts on every core clock cycle 130 */ 131 static void tegra234_read_counters(struct tegra_cpu_ctr *c) 132 { 133 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 134 void __iomem *actmon_reg; 135 u32 cpuid, clusterid; 136 u64 val; 137 138 data->soc->ops->get_cpu_cluster_id(c->cpu, &cpuid, &clusterid); 139 actmon_reg = CORE_ACTMON_CNTR_REG(data, clusterid, cpuid); 140 141 val = readq(actmon_reg); 142 c->last_refclk_cnt = upper_32_bits(val); 143 c->last_coreclk_cnt = lower_32_bits(val); 144 udelay(US_DELAY); 145 val = readq(actmon_reg); 146 c->refclk_cnt = upper_32_bits(val); 147 c->coreclk_cnt = lower_32_bits(val); 148 } 149 150 static struct tegra_cpufreq_ops tegra234_cpufreq_ops = { 151 .read_counters = tegra234_read_counters, 152 .get_cpu_cluster_id = tegra234_get_cpu_cluster_id, 153 .get_cpu_ndiv = tegra234_get_cpu_ndiv, 154 .set_cpu_ndiv = tegra234_set_cpu_ndiv, 155 }; 156 157 static const struct tegra_cpufreq_soc tegra234_cpufreq_soc = { 158 .ops = &tegra234_cpufreq_ops, 159 .actmon_cntr_base = 0x9000, 160 .maxcpus_per_cluster = 4, 161 .num_clusters = 3, 162 }; 163 164 static const struct tegra_cpufreq_soc tegra239_cpufreq_soc = { 165 .ops = &tegra234_cpufreq_ops, 166 .actmon_cntr_base = 0x4000, 167 .maxcpus_per_cluster = 8, 168 .num_clusters = 1, 169 }; 170 171 static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) 172 { 173 u64 mpidr; 174 175 smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); 176 177 if (cpuid) 178 *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0); 179 if (clusterid) 180 *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); 181 } 182 183 /* 184 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1. 185 * The register provides frequency feedback information to 186 * determine the average actual frequency a core has run at over 187 * a period of time. 188 * [31:0] PLLP counter: Counts at fixed frequency (408 MHz) 189 * [63:32] Core clock counter: counts on every core clock cycle 190 * where the core is architecturally clocking 191 */ 192 static u64 read_freq_feedback(void) 193 { 194 u64 val = 0; 195 196 asm volatile("mrs %0, s3_0_c15_c0_5" : "=r" (val) : ); 197 198 return val; 199 } 200 201 static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response 202 *nltbl, u16 ndiv) 203 { 204 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); 205 } 206 207 static void tegra194_read_counters(struct tegra_cpu_ctr *c) 208 { 209 u64 val; 210 211 val = read_freq_feedback(); 212 c->last_refclk_cnt = lower_32_bits(val); 213 c->last_coreclk_cnt = upper_32_bits(val); 214 udelay(US_DELAY); 215 val = read_freq_feedback(); 216 c->refclk_cnt = lower_32_bits(val); 217 c->coreclk_cnt = upper_32_bits(val); 218 } 219 220 static void tegra_read_counters(struct work_struct *work) 221 { 222 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 223 struct read_counters_work *read_counters_work; 224 struct tegra_cpu_ctr *c; 225 226 /* 227 * ref_clk_counter(32 bit counter) runs on constant clk, 228 * pll_p(408MHz). 229 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter 230 * = 10526880 usec = 10.527 sec to overflow 231 * 232 * Like wise core_clk_counter(32 bit counter) runs on core clock. 233 * It's synchronized to crab_clk (cpu_crab_clk) which runs at 234 * freq of cluster. Assuming max cluster clock ~2000MHz, 235 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter 236 * = ~2.147 sec to overflow 237 */ 238 read_counters_work = container_of(work, struct read_counters_work, 239 work); 240 c = &read_counters_work->c; 241 242 data->soc->ops->read_counters(c); 243 } 244 245 /* 246 * Return instantaneous cpu speed 247 * Instantaneous freq is calculated as - 248 * -Takes sample on every query of getting the freq. 249 * - Read core and ref clock counters; 250 * - Delay for X us 251 * - Read above cycle counters again 252 * - Calculates freq by subtracting current and previous counters 253 * divided by the delay time or eqv. of ref_clk_counter in delta time 254 * - Return Kcycles/second, freq in KHz 255 * 256 * delta time period = x sec 257 * = delta ref_clk_counter / (408 * 10^6) sec 258 * freq in Hz = cycles/sec 259 * = (delta cycles / x sec 260 * = (delta cycles * 408 * 10^6) / delta ref_clk_counter 261 * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter 262 * 263 * @cpu - logical cpu whose freq to be updated 264 * Returns freq in KHz on success, 0 if cpu is offline 265 */ 266 static unsigned int tegra194_calculate_speed(u32 cpu) 267 { 268 struct read_counters_work read_counters_work; 269 struct tegra_cpu_ctr c; 270 u32 delta_refcnt; 271 u32 delta_ccnt; 272 u32 rate_mhz; 273 274 /* 275 * udelay() is required to reconstruct cpu frequency over an 276 * observation window. Using workqueue to call udelay() with 277 * interrupts enabled. 278 */ 279 read_counters_work.c.cpu = cpu; 280 INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters); 281 queue_work_on(cpu, read_counters_wq, &read_counters_work.work); 282 flush_work(&read_counters_work.work); 283 c = read_counters_work.c; 284 285 if (c.coreclk_cnt < c.last_coreclk_cnt) 286 delta_ccnt = c.coreclk_cnt + (MAX_CNT - c.last_coreclk_cnt); 287 else 288 delta_ccnt = c.coreclk_cnt - c.last_coreclk_cnt; 289 if (!delta_ccnt) 290 return 0; 291 292 /* ref clock is 32 bits */ 293 if (c.refclk_cnt < c.last_refclk_cnt) 294 delta_refcnt = c.refclk_cnt + (MAX_CNT - c.last_refclk_cnt); 295 else 296 delta_refcnt = c.refclk_cnt - c.last_refclk_cnt; 297 if (!delta_refcnt) { 298 pr_debug("cpufreq: %d is idle, delta_refcnt: 0\n", cpu); 299 return 0; 300 } 301 rate_mhz = ((unsigned long)(delta_ccnt * REF_CLK_MHZ)) / delta_refcnt; 302 303 return (rate_mhz * KHZ); /* in KHz */ 304 } 305 306 static void tegra194_get_cpu_ndiv_sysreg(void *ndiv) 307 { 308 u64 ndiv_val; 309 310 asm volatile("mrs %0, s3_0_c15_c0_4" : "=r" (ndiv_val) : ); 311 312 *(u64 *)ndiv = ndiv_val; 313 } 314 315 static int tegra194_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) 316 { 317 return smp_call_function_single(cpu, tegra194_get_cpu_ndiv_sysreg, &ndiv, true); 318 } 319 320 static void tegra194_set_cpu_ndiv_sysreg(void *data) 321 { 322 u64 ndiv_val = *(u64 *)data; 323 324 asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val)); 325 } 326 327 static void tegra194_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) 328 { 329 on_each_cpu_mask(policy->cpus, tegra194_set_cpu_ndiv_sysreg, &ndiv, true); 330 } 331 332 static unsigned int tegra194_get_speed(u32 cpu) 333 { 334 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 335 struct cpufreq_frequency_table *pos; 336 u32 cpuid, clusterid; 337 unsigned int rate; 338 u64 ndiv; 339 int ret; 340 341 data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid); 342 343 /* reconstruct actual cpu freq using counters */ 344 rate = tegra194_calculate_speed(cpu); 345 346 /* get last written ndiv value */ 347 ret = data->soc->ops->get_cpu_ndiv(cpu, cpuid, clusterid, &ndiv); 348 if (WARN_ON_ONCE(ret)) 349 return rate; 350 351 /* 352 * If the reconstructed frequency has acceptable delta from 353 * the last written value, then return freq corresponding 354 * to the last written ndiv value from freq_table. This is 355 * done to return consistent value. 356 */ 357 cpufreq_for_each_valid_entry(pos, data->tables[clusterid]) { 358 if (pos->driver_data != ndiv) 359 continue; 360 361 if (abs(pos->frequency - rate) > 115200) { 362 pr_warn("cpufreq: cpu%d,cur:%u,set:%u,set ndiv:%llu\n", 363 cpu, rate, pos->frequency, ndiv); 364 } else { 365 rate = pos->frequency; 366 } 367 break; 368 } 369 return rate; 370 } 371 372 static int tegra194_cpufreq_init(struct cpufreq_policy *policy) 373 { 374 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 375 int maxcpus_per_cluster = data->soc->maxcpus_per_cluster; 376 u32 start_cpu, cpu; 377 u32 clusterid; 378 379 data->soc->ops->get_cpu_cluster_id(policy->cpu, NULL, &clusterid); 380 381 if (clusterid >= data->soc->num_clusters || !data->tables[clusterid]) 382 return -EINVAL; 383 384 start_cpu = rounddown(policy->cpu, maxcpus_per_cluster); 385 /* set same policy for all cpus in a cluster */ 386 for (cpu = start_cpu; cpu < (start_cpu + maxcpus_per_cluster); cpu++) { 387 if (cpu_possible(cpu)) 388 cpumask_set_cpu(cpu, policy->cpus); 389 } 390 policy->freq_table = data->tables[clusterid]; 391 policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY; 392 393 return 0; 394 } 395 396 static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy, 397 unsigned int index) 398 { 399 struct cpufreq_frequency_table *tbl = policy->freq_table + index; 400 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); 401 402 /* 403 * Each core writes frequency in per core register. Then both cores 404 * in a cluster run at same frequency which is the maximum frequency 405 * request out of the values requested by both cores in that cluster. 406 */ 407 data->soc->ops->set_cpu_ndiv(policy, (u64)tbl->driver_data); 408 409 return 0; 410 } 411 412 static struct cpufreq_driver tegra194_cpufreq_driver = { 413 .name = "tegra194", 414 .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_INITIAL_FREQ_CHECK, 415 .verify = cpufreq_generic_frequency_table_verify, 416 .target_index = tegra194_cpufreq_set_target, 417 .get = tegra194_get_speed, 418 .init = tegra194_cpufreq_init, 419 .attr = cpufreq_generic_attr, 420 }; 421 422 static struct tegra_cpufreq_ops tegra194_cpufreq_ops = { 423 .read_counters = tegra194_read_counters, 424 .get_cpu_cluster_id = tegra194_get_cpu_cluster_id, 425 .get_cpu_ndiv = tegra194_get_cpu_ndiv, 426 .set_cpu_ndiv = tegra194_set_cpu_ndiv, 427 }; 428 429 static const struct tegra_cpufreq_soc tegra194_cpufreq_soc = { 430 .ops = &tegra194_cpufreq_ops, 431 .maxcpus_per_cluster = 2, 432 .num_clusters = 4, 433 }; 434 435 static void tegra194_cpufreq_free_resources(void) 436 { 437 destroy_workqueue(read_counters_wq); 438 } 439 440 static struct cpufreq_frequency_table * 441 init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp, 442 unsigned int cluster_id) 443 { 444 struct cpufreq_frequency_table *freq_table; 445 struct mrq_cpu_ndiv_limits_response resp; 446 unsigned int num_freqs, ndiv, delta_ndiv; 447 struct mrq_cpu_ndiv_limits_request req; 448 struct tegra_bpmp_message msg; 449 u16 freq_table_step_size; 450 int err, index; 451 452 memset(&req, 0, sizeof(req)); 453 req.cluster_id = cluster_id; 454 455 memset(&msg, 0, sizeof(msg)); 456 msg.mrq = MRQ_CPU_NDIV_LIMITS; 457 msg.tx.data = &req; 458 msg.tx.size = sizeof(req); 459 msg.rx.data = &resp; 460 msg.rx.size = sizeof(resp); 461 462 err = tegra_bpmp_transfer(bpmp, &msg); 463 if (err) 464 return ERR_PTR(err); 465 if (msg.rx.ret == -BPMP_EINVAL) { 466 /* Cluster not available */ 467 return NULL; 468 } 469 if (msg.rx.ret) 470 return ERR_PTR(-EINVAL); 471 472 /* 473 * Make sure frequency table step is a multiple of mdiv to match 474 * vhint table granularity. 475 */ 476 freq_table_step_size = resp.mdiv * 477 DIV_ROUND_UP(CPUFREQ_TBL_STEP_HZ, resp.ref_clk_hz); 478 479 dev_dbg(&pdev->dev, "cluster %d: frequency table step size: %d\n", 480 cluster_id, freq_table_step_size); 481 482 delta_ndiv = resp.ndiv_max - resp.ndiv_min; 483 484 if (unlikely(delta_ndiv == 0)) { 485 num_freqs = 1; 486 } else { 487 /* We store both ndiv_min and ndiv_max hence the +1 */ 488 num_freqs = delta_ndiv / freq_table_step_size + 1; 489 } 490 491 num_freqs += (delta_ndiv % freq_table_step_size) ? 1 : 0; 492 493 freq_table = devm_kcalloc(&pdev->dev, num_freqs + 1, 494 sizeof(*freq_table), GFP_KERNEL); 495 if (!freq_table) 496 return ERR_PTR(-ENOMEM); 497 498 for (index = 0, ndiv = resp.ndiv_min; 499 ndiv < resp.ndiv_max; 500 index++, ndiv += freq_table_step_size) { 501 freq_table[index].driver_data = ndiv; 502 freq_table[index].frequency = map_ndiv_to_freq(&resp, ndiv); 503 } 504 505 freq_table[index].driver_data = resp.ndiv_max; 506 freq_table[index++].frequency = map_ndiv_to_freq(&resp, resp.ndiv_max); 507 freq_table[index].frequency = CPUFREQ_TABLE_END; 508 509 return freq_table; 510 } 511 512 static int tegra194_cpufreq_probe(struct platform_device *pdev) 513 { 514 const struct tegra_cpufreq_soc *soc; 515 struct tegra194_cpufreq_data *data; 516 struct tegra_bpmp *bpmp; 517 int err, i; 518 519 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 520 if (!data) 521 return -ENOMEM; 522 523 soc = of_device_get_match_data(&pdev->dev); 524 525 if (soc->ops && soc->maxcpus_per_cluster && soc->num_clusters) { 526 data->soc = soc; 527 } else { 528 dev_err(&pdev->dev, "soc data missing\n"); 529 return -EINVAL; 530 } 531 532 data->tables = devm_kcalloc(&pdev->dev, data->soc->num_clusters, 533 sizeof(*data->tables), GFP_KERNEL); 534 if (!data->tables) 535 return -ENOMEM; 536 537 if (soc->actmon_cntr_base) { 538 /* mmio registers are used for frequency request and re-construction */ 539 data->regs = devm_platform_ioremap_resource(pdev, 0); 540 if (IS_ERR(data->regs)) 541 return PTR_ERR(data->regs); 542 } 543 544 platform_set_drvdata(pdev, data); 545 546 bpmp = tegra_bpmp_get(&pdev->dev); 547 if (IS_ERR(bpmp)) 548 return PTR_ERR(bpmp); 549 550 read_counters_wq = alloc_workqueue("read_counters_wq", __WQ_LEGACY, 1); 551 if (!read_counters_wq) { 552 dev_err(&pdev->dev, "fail to create_workqueue\n"); 553 err = -EINVAL; 554 goto put_bpmp; 555 } 556 557 for (i = 0; i < data->soc->num_clusters; i++) { 558 data->tables[i] = init_freq_table(pdev, bpmp, i); 559 if (IS_ERR(data->tables[i])) { 560 err = PTR_ERR(data->tables[i]); 561 goto err_free_res; 562 } 563 } 564 565 tegra194_cpufreq_driver.driver_data = data; 566 567 err = cpufreq_register_driver(&tegra194_cpufreq_driver); 568 if (!err) 569 goto put_bpmp; 570 571 err_free_res: 572 tegra194_cpufreq_free_resources(); 573 put_bpmp: 574 tegra_bpmp_put(bpmp); 575 return err; 576 } 577 578 static int tegra194_cpufreq_remove(struct platform_device *pdev) 579 { 580 cpufreq_unregister_driver(&tegra194_cpufreq_driver); 581 tegra194_cpufreq_free_resources(); 582 583 return 0; 584 } 585 586 static const struct of_device_id tegra194_cpufreq_of_match[] = { 587 { .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc }, 588 { .compatible = "nvidia,tegra234-ccplex-cluster", .data = &tegra234_cpufreq_soc }, 589 { .compatible = "nvidia,tegra239-ccplex-cluster", .data = &tegra239_cpufreq_soc }, 590 { /* sentinel */ } 591 }; 592 MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match); 593 594 static struct platform_driver tegra194_ccplex_driver = { 595 .driver = { 596 .name = "tegra194-cpufreq", 597 .of_match_table = tegra194_cpufreq_of_match, 598 }, 599 .probe = tegra194_cpufreq_probe, 600 .remove = tegra194_cpufreq_remove, 601 }; 602 module_platform_driver(tegra194_ccplex_driver); 603 604 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 605 MODULE_AUTHOR("Sumit Gupta <sumitg@nvidia.com>"); 606 MODULE_DESCRIPTION("NVIDIA Tegra194 cpufreq driver"); 607 MODULE_LICENSE("GPL v2"); 608