1 /* 2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 */ 13 14 #include <linux/cpufreq.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 20 #include <soc/tegra/bpmp.h> 21 #include <soc/tegra/bpmp-abi.h> 22 23 #define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4) 24 #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 25 #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 26 27 struct tegra186_cpufreq_cluster_info { 28 unsigned long offset; 29 int cpus[4]; 30 unsigned int bpmp_cluster_id; 31 }; 32 33 #define NO_CPU -1 34 static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = { 35 /* Denver cluster */ 36 { 37 .offset = SZ_64K * 7, 38 .cpus = { 1, 2, NO_CPU, NO_CPU }, 39 .bpmp_cluster_id = 0, 40 }, 41 /* A57 cluster */ 42 { 43 .offset = SZ_64K * 6, 44 .cpus = { 0, 3, 4, 5 }, 45 .bpmp_cluster_id = 1, 46 }, 47 }; 48 49 struct tegra186_cpufreq_cluster { 50 const struct tegra186_cpufreq_cluster_info *info; 51 struct cpufreq_frequency_table *table; 52 }; 53 54 struct tegra186_cpufreq_data { 55 void __iomem *regs; 56 57 size_t num_clusters; 58 struct tegra186_cpufreq_cluster *clusters; 59 }; 60 61 static int tegra186_cpufreq_init(struct cpufreq_policy *policy) 62 { 63 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 64 unsigned int i; 65 66 for (i = 0; i < data->num_clusters; i++) { 67 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; 68 const struct tegra186_cpufreq_cluster_info *info = 69 cluster->info; 70 int core; 71 72 for (core = 0; core < ARRAY_SIZE(info->cpus); core++) { 73 if (info->cpus[core] == policy->cpu) 74 break; 75 } 76 if (core == ARRAY_SIZE(info->cpus)) 77 continue; 78 79 policy->driver_data = 80 data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core); 81 policy->freq_table = cluster->table; 82 break; 83 } 84 85 policy->cpuinfo.transition_latency = 300 * 1000; 86 87 return 0; 88 } 89 90 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, 91 unsigned int index) 92 { 93 struct cpufreq_frequency_table *tbl = policy->freq_table + index; 94 void __iomem *edvd_reg = policy->driver_data; 95 u32 edvd_val = tbl->driver_data; 96 97 writel(edvd_val, edvd_reg); 98 99 return 0; 100 } 101 102 static struct cpufreq_driver tegra186_cpufreq_driver = { 103 .name = "tegra186", 104 .flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY, 105 .verify = cpufreq_generic_frequency_table_verify, 106 .target_index = tegra186_cpufreq_set_target, 107 .init = tegra186_cpufreq_init, 108 .attr = cpufreq_generic_attr, 109 }; 110 111 static struct cpufreq_frequency_table *init_vhint_table( 112 struct platform_device *pdev, struct tegra_bpmp *bpmp, 113 unsigned int cluster_id) 114 { 115 struct cpufreq_frequency_table *table; 116 struct mrq_cpu_vhint_request req; 117 struct tegra_bpmp_message msg; 118 struct cpu_vhint_data *data; 119 int err, i, j, num_rates = 0; 120 dma_addr_t phys; 121 void *virt; 122 123 virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys, 124 GFP_KERNEL | GFP_DMA32); 125 if (!virt) 126 return ERR_PTR(-ENOMEM); 127 128 data = (struct cpu_vhint_data *)virt; 129 130 memset(&req, 0, sizeof(req)); 131 req.addr = phys; 132 req.cluster_id = cluster_id; 133 134 memset(&msg, 0, sizeof(msg)); 135 msg.mrq = MRQ_CPU_VHINT; 136 msg.tx.data = &req; 137 msg.tx.size = sizeof(req); 138 139 err = tegra_bpmp_transfer(bpmp, &msg); 140 if (err) { 141 table = ERR_PTR(err); 142 goto free; 143 } 144 145 for (i = data->vfloor; i <= data->vceil; i++) { 146 u16 ndiv = data->ndiv[i]; 147 148 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) 149 continue; 150 151 /* Only store lowest voltage index for each rate */ 152 if (i > 0 && ndiv == data->ndiv[i - 1]) 153 continue; 154 155 num_rates++; 156 } 157 158 table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table), 159 GFP_KERNEL); 160 if (!table) { 161 table = ERR_PTR(-ENOMEM); 162 goto free; 163 } 164 165 for (i = data->vfloor, j = 0; i <= data->vceil; i++) { 166 struct cpufreq_frequency_table *point; 167 u16 ndiv = data->ndiv[i]; 168 u32 edvd_val = 0; 169 170 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) 171 continue; 172 173 /* Only store lowest voltage index for each rate */ 174 if (i > 0 && ndiv == data->ndiv[i - 1]) 175 continue; 176 177 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT; 178 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT; 179 180 point = &table[j++]; 181 point->driver_data = edvd_val; 182 point->frequency = data->ref_clk_hz * ndiv / data->pdiv / 183 data->mdiv / 1000; 184 } 185 186 table[j].frequency = CPUFREQ_TABLE_END; 187 188 free: 189 dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys); 190 191 return table; 192 } 193 194 static int tegra186_cpufreq_probe(struct platform_device *pdev) 195 { 196 struct tegra186_cpufreq_data *data; 197 struct tegra_bpmp *bpmp; 198 struct resource *res; 199 unsigned int i = 0, err; 200 201 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 202 if (!data) 203 return -ENOMEM; 204 205 data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters), 206 sizeof(*data->clusters), GFP_KERNEL); 207 if (!data->clusters) 208 return -ENOMEM; 209 210 data->num_clusters = ARRAY_SIZE(tegra186_clusters); 211 212 bpmp = tegra_bpmp_get(&pdev->dev); 213 if (IS_ERR(bpmp)) 214 return PTR_ERR(bpmp); 215 216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 217 data->regs = devm_ioremap_resource(&pdev->dev, res); 218 if (IS_ERR(data->regs)) { 219 err = PTR_ERR(data->regs); 220 goto put_bpmp; 221 } 222 223 for (i = 0; i < data->num_clusters; i++) { 224 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; 225 226 cluster->info = &tegra186_clusters[i]; 227 cluster->table = init_vhint_table( 228 pdev, bpmp, cluster->info->bpmp_cluster_id); 229 if (IS_ERR(cluster->table)) { 230 err = PTR_ERR(cluster->table); 231 goto put_bpmp; 232 } 233 } 234 235 tegra_bpmp_put(bpmp); 236 237 tegra186_cpufreq_driver.driver_data = data; 238 239 err = cpufreq_register_driver(&tegra186_cpufreq_driver); 240 if (err) 241 return err; 242 243 return 0; 244 245 put_bpmp: 246 tegra_bpmp_put(bpmp); 247 248 return err; 249 } 250 251 static int tegra186_cpufreq_remove(struct platform_device *pdev) 252 { 253 cpufreq_unregister_driver(&tegra186_cpufreq_driver); 254 255 return 0; 256 } 257 258 static const struct of_device_id tegra186_cpufreq_of_match[] = { 259 { .compatible = "nvidia,tegra186-ccplex-cluster", }, 260 { } 261 }; 262 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match); 263 264 static struct platform_driver tegra186_cpufreq_platform_driver = { 265 .driver = { 266 .name = "tegra186-cpufreq", 267 .of_match_table = tegra186_cpufreq_of_match, 268 }, 269 .probe = tegra186_cpufreq_probe, 270 .remove = tegra186_cpufreq_remove, 271 }; 272 module_platform_driver(tegra186_cpufreq_platform_driver); 273 274 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 275 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver"); 276 MODULE_LICENSE("GPL v2"); 277