1 /* 2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> 3 * 4 * Licensed under the terms of the GNU GPL License version 2. 5 * 6 * Library for common functions for Intel SpeedStep v.1 and v.2 support 7 * 8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/cpufreq.h> 18 19 #include <asm/msr.h> 20 #include <asm/tsc.h> 21 #include "speedstep-lib.h" 22 23 #define PFX "speedstep-lib: " 24 25 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK 26 static int relaxed_check; 27 #else 28 #define relaxed_check 0 29 #endif 30 31 /********************************************************************* 32 * GET PROCESSOR CORE SPEED IN KHZ * 33 *********************************************************************/ 34 35 static unsigned int pentium3_get_frequency(enum speedstep_processor processor) 36 { 37 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ 38 static const struct { 39 unsigned int ratio; /* Frequency Multiplier (x10) */ 40 u8 bitmap; /* power on configuration bits 41 [27, 25:22] (in MSR 0x2a) */ 42 } msr_decode_mult[] = { 43 { 30, 0x01 }, 44 { 35, 0x05 }, 45 { 40, 0x02 }, 46 { 45, 0x06 }, 47 { 50, 0x00 }, 48 { 55, 0x04 }, 49 { 60, 0x0b }, 50 { 65, 0x0f }, 51 { 70, 0x09 }, 52 { 75, 0x0d }, 53 { 80, 0x0a }, 54 { 85, 0x26 }, 55 { 90, 0x20 }, 56 { 100, 0x2b }, 57 { 0, 0xff } /* error or unknown value */ 58 }; 59 60 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ 61 static const struct { 62 unsigned int value; /* Front Side Bus speed in MHz */ 63 u8 bitmap; /* power on configuration bits [18: 19] 64 (in MSR 0x2a) */ 65 } msr_decode_fsb[] = { 66 { 66, 0x0 }, 67 { 100, 0x2 }, 68 { 133, 0x1 }, 69 { 0, 0xff} 70 }; 71 72 u32 msr_lo, msr_tmp; 73 int i = 0, j = 0; 74 75 /* read MSR 0x2a - we only need the low 32 bits */ 76 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); 77 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); 78 msr_tmp = msr_lo; 79 80 /* decode the FSB */ 81 msr_tmp &= 0x00c0000; 82 msr_tmp >>= 18; 83 while (msr_tmp != msr_decode_fsb[i].bitmap) { 84 if (msr_decode_fsb[i].bitmap == 0xff) 85 return 0; 86 i++; 87 } 88 89 /* decode the multiplier */ 90 if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) { 91 pr_debug("workaround for early PIIIs\n"); 92 msr_lo &= 0x03c00000; 93 } else 94 msr_lo &= 0x0bc00000; 95 msr_lo >>= 22; 96 while (msr_lo != msr_decode_mult[j].bitmap) { 97 if (msr_decode_mult[j].bitmap == 0xff) 98 return 0; 99 j++; 100 } 101 102 pr_debug("speed is %u\n", 103 (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100)); 104 105 return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100; 106 } 107 108 109 static unsigned int pentiumM_get_frequency(void) 110 { 111 u32 msr_lo, msr_tmp; 112 113 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); 114 pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); 115 116 /* see table B-2 of 24547212.pdf */ 117 if (msr_lo & 0x00040000) { 118 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n", 119 msr_lo, msr_tmp); 120 return 0; 121 } 122 123 msr_tmp = (msr_lo >> 22) & 0x1f; 124 pr_debug("bits 22-26 are 0x%x, speed is %u\n", 125 msr_tmp, (msr_tmp * 100 * 1000)); 126 127 return msr_tmp * 100 * 1000; 128 } 129 130 static unsigned int pentium_core_get_frequency(void) 131 { 132 u32 fsb = 0; 133 u32 msr_lo, msr_tmp; 134 int ret; 135 136 rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp); 137 /* see table B-2 of 25366920.pdf */ 138 switch (msr_lo & 0x07) { 139 case 5: 140 fsb = 100000; 141 break; 142 case 1: 143 fsb = 133333; 144 break; 145 case 3: 146 fsb = 166667; 147 break; 148 case 2: 149 fsb = 200000; 150 break; 151 case 0: 152 fsb = 266667; 153 break; 154 case 4: 155 fsb = 333333; 156 break; 157 default: 158 pr_err("PCORE - MSR_FSB_FREQ undefined value\n"); 159 } 160 161 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); 162 pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", 163 msr_lo, msr_tmp); 164 165 msr_tmp = (msr_lo >> 22) & 0x1f; 166 pr_debug("bits 22-26 are 0x%x, speed is %u\n", 167 msr_tmp, (msr_tmp * fsb)); 168 169 ret = (msr_tmp * fsb); 170 return ret; 171 } 172 173 174 static unsigned int pentium4_get_frequency(void) 175 { 176 struct cpuinfo_x86 *c = &boot_cpu_data; 177 u32 msr_lo, msr_hi, mult; 178 unsigned int fsb = 0; 179 unsigned int ret; 180 u8 fsb_code; 181 182 /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency 183 * to System Bus Frequency Ratio Field in the Processor Frequency 184 * Configuration Register of the MSR. Therefore the current 185 * frequency cannot be calculated and has to be measured. 186 */ 187 if (c->x86_model < 2) 188 return cpu_khz; 189 190 rdmsr(0x2c, msr_lo, msr_hi); 191 192 pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); 193 194 /* decode the FSB: see IA-32 Intel (C) Architecture Software 195 * Developer's Manual, Volume 3: System Prgramming Guide, 196 * revision #12 in Table B-1: MSRs in the Pentium 4 and 197 * Intel Xeon Processors, on page B-4 and B-5. 198 */ 199 fsb_code = (msr_lo >> 16) & 0x7; 200 switch (fsb_code) { 201 case 0: 202 fsb = 100 * 1000; 203 break; 204 case 1: 205 fsb = 13333 * 10; 206 break; 207 case 2: 208 fsb = 200 * 1000; 209 break; 210 } 211 212 if (!fsb) 213 printk(KERN_DEBUG PFX "couldn't detect FSB speed. " 214 "Please send an e-mail to <linux@brodo.de>\n"); 215 216 /* Multiplier. */ 217 mult = msr_lo >> 24; 218 219 pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", 220 fsb, mult, (fsb * mult)); 221 222 ret = (fsb * mult); 223 return ret; 224 } 225 226 227 /* Warning: may get called from smp_call_function_single. */ 228 unsigned int speedstep_get_frequency(enum speedstep_processor processor) 229 { 230 switch (processor) { 231 case SPEEDSTEP_CPU_PCORE: 232 return pentium_core_get_frequency(); 233 case SPEEDSTEP_CPU_PM: 234 return pentiumM_get_frequency(); 235 case SPEEDSTEP_CPU_P4D: 236 case SPEEDSTEP_CPU_P4M: 237 return pentium4_get_frequency(); 238 case SPEEDSTEP_CPU_PIII_T: 239 case SPEEDSTEP_CPU_PIII_C: 240 case SPEEDSTEP_CPU_PIII_C_EARLY: 241 return pentium3_get_frequency(processor); 242 default: 243 return 0; 244 }; 245 return 0; 246 } 247 EXPORT_SYMBOL_GPL(speedstep_get_frequency); 248 249 250 /********************************************************************* 251 * DETECT SPEEDSTEP-CAPABLE PROCESSOR * 252 *********************************************************************/ 253 254 /* Keep in sync with the x86_cpu_id tables in the different modules */ 255 enum speedstep_processor speedstep_detect_processor(void) 256 { 257 struct cpuinfo_x86 *c = &cpu_data(0); 258 u32 ebx, msr_lo, msr_hi; 259 260 pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model); 261 262 if ((c->x86_vendor != X86_VENDOR_INTEL) || 263 ((c->x86 != 6) && (c->x86 != 0xF))) 264 return 0; 265 266 if (c->x86 == 0xF) { 267 /* Intel Mobile Pentium 4-M 268 * or Intel Mobile Pentium 4 with 533 MHz FSB */ 269 if (c->x86_model != 2) 270 return 0; 271 272 ebx = cpuid_ebx(0x00000001); 273 ebx &= 0x000000FF; 274 275 pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping); 276 277 switch (c->x86_stepping) { 278 case 4: 279 /* 280 * B-stepping [M-P4-M] 281 * sample has ebx = 0x0f, production has 0x0e. 282 */ 283 if ((ebx == 0x0e) || (ebx == 0x0f)) 284 return SPEEDSTEP_CPU_P4M; 285 break; 286 case 7: 287 /* 288 * C-stepping [M-P4-M] 289 * needs to have ebx=0x0e, else it's a celeron: 290 * cf. 25130917.pdf / page 7, footnote 5 even 291 * though 25072120.pdf / page 7 doesn't say 292 * samples are only of B-stepping... 293 */ 294 if (ebx == 0x0e) 295 return SPEEDSTEP_CPU_P4M; 296 break; 297 case 9: 298 /* 299 * D-stepping [M-P4-M or M-P4/533] 300 * 301 * this is totally strange: CPUID 0x0F29 is 302 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs. 303 * The latter need to be sorted out as they don't 304 * support speedstep. 305 * Celerons with CPUID 0x0F29 may have either 306 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything 307 * specific. 308 * M-P4-Ms may have either ebx=0xe or 0xf [see above] 309 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf] 310 * also, M-P4M HTs have ebx=0x8, too 311 * For now, they are distinguished by the model_id 312 * string 313 */ 314 if ((ebx == 0x0e) || 315 (strstr(c->x86_model_id, 316 "Mobile Intel(R) Pentium(R) 4") != NULL)) 317 return SPEEDSTEP_CPU_P4M; 318 break; 319 default: 320 break; 321 } 322 return 0; 323 } 324 325 switch (c->x86_model) { 326 case 0x0B: /* Intel PIII [Tualatin] */ 327 /* cpuid_ebx(1) is 0x04 for desktop PIII, 328 * 0x06 for mobile PIII-M */ 329 ebx = cpuid_ebx(0x00000001); 330 pr_debug("ebx is %x\n", ebx); 331 332 ebx &= 0x000000FF; 333 334 if (ebx != 0x06) 335 return 0; 336 337 /* So far all PIII-M processors support SpeedStep. See 338 * Intel's 24540640.pdf of June 2003 339 */ 340 return SPEEDSTEP_CPU_PIII_T; 341 342 case 0x08: /* Intel PIII [Coppermine] */ 343 344 /* all mobile PIII Coppermines have FSB 100 MHz 345 * ==> sort out a few desktop PIIIs. */ 346 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); 347 pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", 348 msr_lo, msr_hi); 349 msr_lo &= 0x00c0000; 350 if (msr_lo != 0x0080000) 351 return 0; 352 353 /* 354 * If the processor is a mobile version, 355 * platform ID has bit 50 set 356 * it has SpeedStep technology if either 357 * bit 56 or 57 is set 358 */ 359 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); 360 pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", 361 msr_lo, msr_hi); 362 if ((msr_hi & (1<<18)) && 363 (relaxed_check ? 1 : (msr_hi & (3<<24)))) { 364 if (c->x86_stepping == 0x01) { 365 pr_debug("early PIII version\n"); 366 return SPEEDSTEP_CPU_PIII_C_EARLY; 367 } else 368 return SPEEDSTEP_CPU_PIII_C; 369 } 370 /* fall through */ 371 default: 372 return 0; 373 } 374 } 375 EXPORT_SYMBOL_GPL(speedstep_detect_processor); 376 377 378 /********************************************************************* 379 * DETECT SPEEDSTEP SPEEDS * 380 *********************************************************************/ 381 382 unsigned int speedstep_get_freqs(enum speedstep_processor processor, 383 unsigned int *low_speed, 384 unsigned int *high_speed, 385 unsigned int *transition_latency, 386 void (*set_state) (unsigned int state)) 387 { 388 unsigned int prev_speed; 389 unsigned int ret = 0; 390 unsigned long flags; 391 ktime_t tv1, tv2; 392 393 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) 394 return -EINVAL; 395 396 pr_debug("trying to determine both speeds\n"); 397 398 /* get current speed */ 399 prev_speed = speedstep_get_frequency(processor); 400 if (!prev_speed) 401 return -EIO; 402 403 pr_debug("previous speed is %u\n", prev_speed); 404 405 preempt_disable(); 406 local_irq_save(flags); 407 408 /* switch to low state */ 409 set_state(SPEEDSTEP_LOW); 410 *low_speed = speedstep_get_frequency(processor); 411 if (!*low_speed) { 412 ret = -EIO; 413 goto out; 414 } 415 416 pr_debug("low speed is %u\n", *low_speed); 417 418 /* start latency measurement */ 419 if (transition_latency) 420 tv1 = ktime_get(); 421 422 /* switch to high state */ 423 set_state(SPEEDSTEP_HIGH); 424 425 /* end latency measurement */ 426 if (transition_latency) 427 tv2 = ktime_get(); 428 429 *high_speed = speedstep_get_frequency(processor); 430 if (!*high_speed) { 431 ret = -EIO; 432 goto out; 433 } 434 435 pr_debug("high speed is %u\n", *high_speed); 436 437 if (*low_speed == *high_speed) { 438 ret = -ENODEV; 439 goto out; 440 } 441 442 /* switch to previous state, if necessary */ 443 if (*high_speed != prev_speed) 444 set_state(SPEEDSTEP_LOW); 445 446 if (transition_latency) { 447 *transition_latency = ktime_to_us(ktime_sub(tv2, tv1)); 448 pr_debug("transition latency is %u uSec\n", *transition_latency); 449 450 /* convert uSec to nSec and add 20% for safety reasons */ 451 *transition_latency *= 1200; 452 453 /* check if the latency measurement is too high or too low 454 * and set it to a safe value (500uSec) in that case 455 */ 456 if (*transition_latency > 10000000 || 457 *transition_latency < 50000) { 458 pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n", 459 *transition_latency, 500000); 460 *transition_latency = 500000; 461 } 462 } 463 464 out: 465 local_irq_restore(flags); 466 preempt_enable(); 467 468 return ret; 469 } 470 EXPORT_SYMBOL_GPL(speedstep_get_freqs); 471 472 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK 473 module_param(relaxed_check, int, 0444); 474 MODULE_PARM_DESC(relaxed_check, 475 "Don't do all checks for speedstep capability."); 476 #endif 477 478 MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>"); 479 MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers."); 480 MODULE_LICENSE("GPL"); 481