1 /* 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * CPU frequency scaling for S5PC110/S5PV210 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/types.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/io.h> 18 #include <linux/cpufreq.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/platform_device.h> 22 #include <linux/reboot.h> 23 #include <linux/regulator/consumer.h> 24 25 static void __iomem *clk_base; 26 static void __iomem *dmc_base[2]; 27 28 #define S5P_CLKREG(x) (clk_base + (x)) 29 30 #define S5P_APLL_LOCK S5P_CLKREG(0x00) 31 #define S5P_APLL_CON S5P_CLKREG(0x100) 32 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) 33 #define S5P_CLK_SRC2 S5P_CLKREG(0x208) 34 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) 35 #define S5P_CLK_DIV2 S5P_CLKREG(0x308) 36 #define S5P_CLK_DIV6 S5P_CLKREG(0x318) 37 #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) 38 #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) 39 #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) 40 #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) 41 42 #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) 43 44 /* CLKSRC0 */ 45 #define S5P_CLKSRC0_MUX200_SHIFT (16) 46 #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) 47 #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) 48 #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) 49 50 /* CLKSRC2 */ 51 #define S5P_CLKSRC2_G3D_SHIFT (0) 52 #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) 53 #define S5P_CLKSRC2_MFC_SHIFT (4) 54 #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) 55 56 /* CLKDIV0 */ 57 #define S5P_CLKDIV0_APLL_SHIFT (0) 58 #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) 59 #define S5P_CLKDIV0_A2M_SHIFT (4) 60 #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) 61 #define S5P_CLKDIV0_HCLK200_SHIFT (8) 62 #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) 63 #define S5P_CLKDIV0_PCLK100_SHIFT (12) 64 #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) 65 #define S5P_CLKDIV0_HCLK166_SHIFT (16) 66 #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) 67 #define S5P_CLKDIV0_PCLK83_SHIFT (20) 68 #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) 69 #define S5P_CLKDIV0_HCLK133_SHIFT (24) 70 #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) 71 #define S5P_CLKDIV0_PCLK66_SHIFT (28) 72 #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) 73 74 /* CLKDIV2 */ 75 #define S5P_CLKDIV2_G3D_SHIFT (0) 76 #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) 77 #define S5P_CLKDIV2_MFC_SHIFT (4) 78 #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) 79 80 /* CLKDIV6 */ 81 #define S5P_CLKDIV6_ONEDRAM_SHIFT (28) 82 #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) 83 84 static struct clk *dmc0_clk; 85 static struct clk *dmc1_clk; 86 static DEFINE_MUTEX(set_freq_lock); 87 88 /* APLL M,P,S values for 1G/800Mhz */ 89 #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1) 90 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1) 91 92 /* Use 800MHz when entering sleep mode */ 93 #define SLEEP_FREQ (800 * 1000) 94 95 /* Tracks if cpu freqency can be updated anymore */ 96 static bool no_cpufreq_access; 97 98 /* 99 * DRAM configurations to calculate refresh counter for changing 100 * frequency of memory. 101 */ 102 struct dram_conf { 103 unsigned long freq; /* HZ */ 104 unsigned long refresh; /* DRAM refresh counter * 1000 */ 105 }; 106 107 /* DRAM configuration (DMC0 and DMC1) */ 108 static struct dram_conf s5pv210_dram_conf[2]; 109 110 enum perf_level { 111 L0, L1, L2, L3, L4, 112 }; 113 114 enum s5pv210_mem_type { 115 LPDDR = 0x1, 116 LPDDR2 = 0x2, 117 DDR2 = 0x4, 118 }; 119 120 enum s5pv210_dmc_port { 121 DMC0 = 0, 122 DMC1, 123 }; 124 125 static struct cpufreq_frequency_table s5pv210_freq_table[] = { 126 {0, L0, 1000*1000}, 127 {0, L1, 800*1000}, 128 {0, L2, 400*1000}, 129 {0, L3, 200*1000}, 130 {0, L4, 100*1000}, 131 {0, 0, CPUFREQ_TABLE_END}, 132 }; 133 134 static struct regulator *arm_regulator; 135 static struct regulator *int_regulator; 136 137 struct s5pv210_dvs_conf { 138 int arm_volt; /* uV */ 139 int int_volt; /* uV */ 140 }; 141 142 static const int arm_volt_max = 1350000; 143 static const int int_volt_max = 1250000; 144 145 static struct s5pv210_dvs_conf dvs_conf[] = { 146 [L0] = { 147 .arm_volt = 1250000, 148 .int_volt = 1100000, 149 }, 150 [L1] = { 151 .arm_volt = 1200000, 152 .int_volt = 1100000, 153 }, 154 [L2] = { 155 .arm_volt = 1050000, 156 .int_volt = 1100000, 157 }, 158 [L3] = { 159 .arm_volt = 950000, 160 .int_volt = 1100000, 161 }, 162 [L4] = { 163 .arm_volt = 950000, 164 .int_volt = 1000000, 165 }, 166 }; 167 168 static u32 clkdiv_val[5][11] = { 169 /* 170 * Clock divider value for following 171 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS, 172 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, 173 * ONEDRAM, MFC, G3D } 174 */ 175 176 /* L0 : [1000/200/100][166/83][133/66][200/200] */ 177 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0}, 178 179 /* L1 : [800/200/100][166/83][133/66][200/200] */ 180 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0}, 181 182 /* L2 : [400/200/100][166/83][133/66][200/200] */ 183 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, 184 185 /* L3 : [200/200/100][166/83][133/66][200/200] */ 186 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, 187 188 /* L4 : [100/100/100][83/83][66/66][100/100] */ 189 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0}, 190 }; 191 192 /* 193 * This function set DRAM refresh counter 194 * accoriding to operating frequency of DRAM 195 * ch: DMC port number 0 or 1 196 * freq: Operating frequency of DRAM(KHz) 197 */ 198 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq) 199 { 200 unsigned long tmp, tmp1; 201 void __iomem *reg = NULL; 202 203 if (ch == DMC0) { 204 reg = (dmc_base[0] + 0x30); 205 } else if (ch == DMC1) { 206 reg = (dmc_base[1] + 0x30); 207 } else { 208 printk(KERN_ERR "Cannot find DMC port\n"); 209 return; 210 } 211 212 /* Find current DRAM frequency */ 213 tmp = s5pv210_dram_conf[ch].freq; 214 215 tmp /= freq; 216 217 tmp1 = s5pv210_dram_conf[ch].refresh; 218 219 tmp1 /= tmp; 220 221 __raw_writel(tmp1, reg); 222 } 223 224 static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) 225 { 226 unsigned long reg; 227 unsigned int priv_index; 228 unsigned int pll_changing = 0; 229 unsigned int bus_speed_changing = 0; 230 unsigned int old_freq, new_freq; 231 int arm_volt, int_volt; 232 int ret = 0; 233 234 mutex_lock(&set_freq_lock); 235 236 if (no_cpufreq_access) { 237 pr_err("Denied access to %s as it is disabled temporarily\n", 238 __func__); 239 ret = -EINVAL; 240 goto exit; 241 } 242 243 old_freq = policy->cur; 244 new_freq = s5pv210_freq_table[index].frequency; 245 246 /* Finding current running level index */ 247 if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, 248 old_freq, CPUFREQ_RELATION_H, 249 &priv_index)) { 250 ret = -EINVAL; 251 goto exit; 252 } 253 254 arm_volt = dvs_conf[index].arm_volt; 255 int_volt = dvs_conf[index].int_volt; 256 257 if (new_freq > old_freq) { 258 ret = regulator_set_voltage(arm_regulator, 259 arm_volt, arm_volt_max); 260 if (ret) 261 goto exit; 262 263 ret = regulator_set_voltage(int_regulator, 264 int_volt, int_volt_max); 265 if (ret) 266 goto exit; 267 } 268 269 /* Check if there need to change PLL */ 270 if ((index == L0) || (priv_index == L0)) 271 pll_changing = 1; 272 273 /* Check if there need to change System bus clock */ 274 if ((index == L4) || (priv_index == L4)) 275 bus_speed_changing = 1; 276 277 if (bus_speed_changing) { 278 /* 279 * Reconfigure DRAM refresh counter value for minimum 280 * temporary clock while changing divider. 281 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 282 */ 283 if (pll_changing) 284 s5pv210_set_refresh(DMC1, 83000); 285 else 286 s5pv210_set_refresh(DMC1, 100000); 287 288 s5pv210_set_refresh(DMC0, 83000); 289 } 290 291 /* 292 * APLL should be changed in this level 293 * APLL -> MPLL(for stable transition) -> APLL 294 * Some clock source's clock API are not prepared. 295 * Do not use clock API in below code. 296 */ 297 if (pll_changing) { 298 /* 299 * 1. Temporary Change divider for MFC and G3D 300 * SCLKA2M(200/1=200)->(200/4=50)Mhz 301 */ 302 reg = __raw_readl(S5P_CLK_DIV2); 303 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); 304 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) | 305 (3 << S5P_CLKDIV2_MFC_SHIFT); 306 __raw_writel(reg, S5P_CLK_DIV2); 307 308 /* For MFC, G3D dividing */ 309 do { 310 reg = __raw_readl(S5P_CLKDIV_STAT0); 311 } while (reg & ((1 << 16) | (1 << 17))); 312 313 /* 314 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX 315 * (200/4=50)->(667/4=166)Mhz 316 */ 317 reg = __raw_readl(S5P_CLK_SRC2); 318 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); 319 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) | 320 (1 << S5P_CLKSRC2_MFC_SHIFT); 321 __raw_writel(reg, S5P_CLK_SRC2); 322 323 do { 324 reg = __raw_readl(S5P_CLKMUX_STAT1); 325 } while (reg & ((1 << 7) | (1 << 3))); 326 327 /* 328 * 3. DMC1 refresh count for 133Mhz if (index == L4) is 329 * true refresh counter is already programed in upper 330 * code. 0x287@83Mhz 331 */ 332 if (!bus_speed_changing) 333 s5pv210_set_refresh(DMC1, 133000); 334 335 /* 4. SCLKAPLL -> SCLKMPLL */ 336 reg = __raw_readl(S5P_CLK_SRC0); 337 reg &= ~(S5P_CLKSRC0_MUX200_MASK); 338 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT); 339 __raw_writel(reg, S5P_CLK_SRC0); 340 341 do { 342 reg = __raw_readl(S5P_CLKMUX_STAT0); 343 } while (reg & (0x1 << 18)); 344 345 } 346 347 /* Change divider */ 348 reg = __raw_readl(S5P_CLK_DIV0); 349 350 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK | 351 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK | 352 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK | 353 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK); 354 355 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) | 356 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) | 357 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) | 358 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) | 359 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) | 360 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) | 361 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) | 362 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT)); 363 364 __raw_writel(reg, S5P_CLK_DIV0); 365 366 do { 367 reg = __raw_readl(S5P_CLKDIV_STAT0); 368 } while (reg & 0xff); 369 370 /* ARM MCS value changed */ 371 reg = __raw_readl(S5P_ARM_MCS_CON); 372 reg &= ~0x3; 373 if (index >= L3) 374 reg |= 0x3; 375 else 376 reg |= 0x1; 377 378 __raw_writel(reg, S5P_ARM_MCS_CON); 379 380 if (pll_changing) { 381 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ 382 __raw_writel(0x2cf, S5P_APLL_LOCK); 383 384 /* 385 * 6. Turn on APLL 386 * 6-1. Set PMS values 387 * 6-2. Wait untile the PLL is locked 388 */ 389 if (index == L0) 390 __raw_writel(APLL_VAL_1000, S5P_APLL_CON); 391 else 392 __raw_writel(APLL_VAL_800, S5P_APLL_CON); 393 394 do { 395 reg = __raw_readl(S5P_APLL_CON); 396 } while (!(reg & (0x1 << 29))); 397 398 /* 399 * 7. Change souce clock from SCLKMPLL(667Mhz) 400 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX 401 * (667/4=166)->(200/4=50)Mhz 402 */ 403 reg = __raw_readl(S5P_CLK_SRC2); 404 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); 405 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | 406 (0 << S5P_CLKSRC2_MFC_SHIFT); 407 __raw_writel(reg, S5P_CLK_SRC2); 408 409 do { 410 reg = __raw_readl(S5P_CLKMUX_STAT1); 411 } while (reg & ((1 << 7) | (1 << 3))); 412 413 /* 414 * 8. Change divider for MFC and G3D 415 * (200/4=50)->(200/1=200)Mhz 416 */ 417 reg = __raw_readl(S5P_CLK_DIV2); 418 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); 419 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) | 420 (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT); 421 __raw_writel(reg, S5P_CLK_DIV2); 422 423 /* For MFC, G3D dividing */ 424 do { 425 reg = __raw_readl(S5P_CLKDIV_STAT0); 426 } while (reg & ((1 << 16) | (1 << 17))); 427 428 /* 9. Change MPLL to APLL in MSYS_MUX */ 429 reg = __raw_readl(S5P_CLK_SRC0); 430 reg &= ~(S5P_CLKSRC0_MUX200_MASK); 431 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); 432 __raw_writel(reg, S5P_CLK_SRC0); 433 434 do { 435 reg = __raw_readl(S5P_CLKMUX_STAT0); 436 } while (reg & (0x1 << 18)); 437 438 /* 439 * 10. DMC1 refresh counter 440 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c 441 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618 442 */ 443 if (!bus_speed_changing) 444 s5pv210_set_refresh(DMC1, 200000); 445 } 446 447 /* 448 * L4 level need to change memory bus speed, hence onedram clock divier 449 * and memory refresh parameter should be changed 450 */ 451 if (bus_speed_changing) { 452 reg = __raw_readl(S5P_CLK_DIV6); 453 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK; 454 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT); 455 __raw_writel(reg, S5P_CLK_DIV6); 456 457 do { 458 reg = __raw_readl(S5P_CLKDIV_STAT1); 459 } while (reg & (1 << 15)); 460 461 /* Reconfigure DRAM refresh counter value */ 462 if (index != L4) { 463 /* 464 * DMC0 : 166Mhz 465 * DMC1 : 200Mhz 466 */ 467 s5pv210_set_refresh(DMC0, 166000); 468 s5pv210_set_refresh(DMC1, 200000); 469 } else { 470 /* 471 * DMC0 : 83Mhz 472 * DMC1 : 100Mhz 473 */ 474 s5pv210_set_refresh(DMC0, 83000); 475 s5pv210_set_refresh(DMC1, 100000); 476 } 477 } 478 479 if (new_freq < old_freq) { 480 regulator_set_voltage(int_regulator, 481 int_volt, int_volt_max); 482 483 regulator_set_voltage(arm_regulator, 484 arm_volt, arm_volt_max); 485 } 486 487 printk(KERN_DEBUG "Perf changed[L%d]\n", index); 488 489 exit: 490 mutex_unlock(&set_freq_lock); 491 return ret; 492 } 493 494 static int check_mem_type(void __iomem *dmc_reg) 495 { 496 unsigned long val; 497 498 val = __raw_readl(dmc_reg + 0x4); 499 val = (val & (0xf << 8)); 500 501 return val >> 8; 502 } 503 504 static int s5pv210_cpu_init(struct cpufreq_policy *policy) 505 { 506 unsigned long mem_type; 507 int ret; 508 509 policy->clk = clk_get(NULL, "armclk"); 510 if (IS_ERR(policy->clk)) 511 return PTR_ERR(policy->clk); 512 513 dmc0_clk = clk_get(NULL, "sclk_dmc0"); 514 if (IS_ERR(dmc0_clk)) { 515 ret = PTR_ERR(dmc0_clk); 516 goto out_dmc0; 517 } 518 519 dmc1_clk = clk_get(NULL, "hclk_msys"); 520 if (IS_ERR(dmc1_clk)) { 521 ret = PTR_ERR(dmc1_clk); 522 goto out_dmc1; 523 } 524 525 if (policy->cpu != 0) { 526 ret = -EINVAL; 527 goto out_dmc1; 528 } 529 530 /* 531 * check_mem_type : This driver only support LPDDR & LPDDR2. 532 * other memory type is not supported. 533 */ 534 mem_type = check_mem_type(dmc_base[0]); 535 536 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) { 537 printk(KERN_ERR "CPUFreq doesn't support this memory type\n"); 538 ret = -EINVAL; 539 goto out_dmc1; 540 } 541 542 /* Find current refresh counter and frequency each DMC */ 543 s5pv210_dram_conf[0].refresh = (__raw_readl(dmc_base[0] + 0x30) * 1000); 544 s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk); 545 546 s5pv210_dram_conf[1].refresh = (__raw_readl(dmc_base[1] + 0x30) * 1000); 547 s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk); 548 549 policy->suspend_freq = SLEEP_FREQ; 550 return cpufreq_generic_init(policy, s5pv210_freq_table, 40000); 551 552 out_dmc1: 553 clk_put(dmc0_clk); 554 out_dmc0: 555 clk_put(policy->clk); 556 return ret; 557 } 558 559 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this, 560 unsigned long event, void *ptr) 561 { 562 int ret; 563 564 ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0); 565 if (ret < 0) 566 return NOTIFY_BAD; 567 568 no_cpufreq_access = true; 569 return NOTIFY_DONE; 570 } 571 572 static struct cpufreq_driver s5pv210_driver = { 573 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, 574 .verify = cpufreq_generic_frequency_table_verify, 575 .target_index = s5pv210_target, 576 .get = cpufreq_generic_get, 577 .init = s5pv210_cpu_init, 578 .name = "s5pv210", 579 .suspend = cpufreq_generic_suspend, 580 .resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */ 581 }; 582 583 static struct notifier_block s5pv210_cpufreq_reboot_notifier = { 584 .notifier_call = s5pv210_cpufreq_reboot_notifier_event, 585 }; 586 587 static int s5pv210_cpufreq_probe(struct platform_device *pdev) 588 { 589 struct device_node *np; 590 int id; 591 592 /* 593 * HACK: This is a temporary workaround to get access to clock 594 * and DMC controller registers directly and remove static mappings 595 * and dependencies on platform headers. It is necessary to enable 596 * S5PV210 multi-platform support and will be removed together with 597 * this whole driver as soon as S5PV210 gets migrated to use 598 * cpufreq-dt driver. 599 */ 600 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); 601 if (!np) { 602 pr_err("%s: failed to find clock controller DT node\n", 603 __func__); 604 return -ENODEV; 605 } 606 607 clk_base = of_iomap(np, 0); 608 if (!clk_base) { 609 pr_err("%s: failed to map clock registers\n", __func__); 610 return -EFAULT; 611 } 612 613 for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") { 614 id = of_alias_get_id(np, "dmc"); 615 if (id < 0 || id >= ARRAY_SIZE(dmc_base)) { 616 pr_err("%s: failed to get alias of dmc node '%s'\n", 617 __func__, np->name); 618 return id; 619 } 620 621 dmc_base[id] = of_iomap(np, 0); 622 if (!dmc_base[id]) { 623 pr_err("%s: failed to map dmc%d registers\n", 624 __func__, id); 625 return -EFAULT; 626 } 627 } 628 629 for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) { 630 if (!dmc_base[id]) { 631 pr_err("%s: failed to find dmc%d node\n", __func__, id); 632 return -ENODEV; 633 } 634 } 635 636 arm_regulator = regulator_get(NULL, "vddarm"); 637 if (IS_ERR(arm_regulator)) { 638 pr_err("failed to get regulator vddarm"); 639 return PTR_ERR(arm_regulator); 640 } 641 642 int_regulator = regulator_get(NULL, "vddint"); 643 if (IS_ERR(int_regulator)) { 644 pr_err("failed to get regulator vddint"); 645 regulator_put(arm_regulator); 646 return PTR_ERR(int_regulator); 647 } 648 649 register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier); 650 651 return cpufreq_register_driver(&s5pv210_driver); 652 } 653 654 static struct platform_driver s5pv210_cpufreq_platdrv = { 655 .driver = { 656 .name = "s5pv210-cpufreq", 657 }, 658 .probe = s5pv210_cpufreq_probe, 659 }; 660 builtin_platform_driver(s5pv210_cpufreq_platdrv); 661