1 /* 2 * Copyright 2009 Wolfson Microelectronics plc 3 * 4 * S3C64xx CPUfreq Support 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) "cpufreq: " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/init.h> 16 #include <linux/cpufreq.h> 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/module.h> 21 22 static struct clk *armclk; 23 static struct regulator *vddarm; 24 static unsigned long regulator_latency; 25 26 #ifdef CONFIG_CPU_S3C6410 27 struct s3c64xx_dvfs { 28 unsigned int vddarm_min; 29 unsigned int vddarm_max; 30 }; 31 32 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { 33 [0] = { 1000000, 1150000 }, 34 [1] = { 1050000, 1150000 }, 35 [2] = { 1100000, 1150000 }, 36 [3] = { 1200000, 1350000 }, 37 [4] = { 1300000, 1350000 }, 38 }; 39 40 static struct cpufreq_frequency_table s3c64xx_freq_table[] = { 41 { 0, 66000 }, 42 { 0, 100000 }, 43 { 0, 133000 }, 44 { 1, 200000 }, 45 { 1, 222000 }, 46 { 1, 266000 }, 47 { 2, 333000 }, 48 { 2, 400000 }, 49 { 2, 532000 }, 50 { 2, 533000 }, 51 { 3, 667000 }, 52 { 4, 800000 }, 53 { 0, CPUFREQ_TABLE_END }, 54 }; 55 #endif 56 57 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu) 58 { 59 if (cpu != 0) 60 return 0; 61 62 return clk_get_rate(armclk) / 1000; 63 } 64 65 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, 66 unsigned int index) 67 { 68 struct s3c64xx_dvfs *dvfs; 69 unsigned int old_freq, new_freq; 70 int ret; 71 72 old_freq = clk_get_rate(armclk) / 1000; 73 new_freq = s3c64xx_freq_table[index].frequency; 74 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; 75 76 #ifdef CONFIG_REGULATOR 77 if (vddarm && new_freq > old_freq) { 78 ret = regulator_set_voltage(vddarm, 79 dvfs->vddarm_min, 80 dvfs->vddarm_max); 81 if (ret != 0) { 82 pr_err("Failed to set VDDARM for %dkHz: %d\n", 83 new_freq, ret); 84 return ret; 85 } 86 } 87 #endif 88 89 ret = clk_set_rate(armclk, new_freq * 1000); 90 if (ret < 0) { 91 pr_err("Failed to set rate %dkHz: %d\n", 92 new_freq, ret); 93 return ret; 94 } 95 96 #ifdef CONFIG_REGULATOR 97 if (vddarm && new_freq < old_freq) { 98 ret = regulator_set_voltage(vddarm, 99 dvfs->vddarm_min, 100 dvfs->vddarm_max); 101 if (ret != 0) { 102 pr_err("Failed to set VDDARM for %dkHz: %d\n", 103 new_freq, ret); 104 if (clk_set_rate(armclk, old_freq * 1000) < 0) 105 pr_err("Failed to restore original clock rate\n"); 106 107 return ret; 108 } 109 } 110 #endif 111 112 pr_debug("Set actual frequency %lukHz\n", 113 clk_get_rate(armclk) / 1000); 114 115 return 0; 116 } 117 118 #ifdef CONFIG_REGULATOR 119 static void __init s3c64xx_cpufreq_config_regulator(void) 120 { 121 int count, v, i, found; 122 struct cpufreq_frequency_table *freq; 123 struct s3c64xx_dvfs *dvfs; 124 125 count = regulator_count_voltages(vddarm); 126 if (count < 0) { 127 pr_err("Unable to check supported voltages\n"); 128 } 129 130 freq = s3c64xx_freq_table; 131 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { 132 if (freq->frequency == CPUFREQ_ENTRY_INVALID) 133 continue; 134 135 dvfs = &s3c64xx_dvfs_table[freq->driver_data]; 136 found = 0; 137 138 for (i = 0; i < count; i++) { 139 v = regulator_list_voltage(vddarm, i); 140 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) 141 found = 1; 142 } 143 144 if (!found) { 145 pr_debug("%dkHz unsupported by regulator\n", 146 freq->frequency); 147 freq->frequency = CPUFREQ_ENTRY_INVALID; 148 } 149 150 freq++; 151 } 152 153 /* Guess based on having to do an I2C/SPI write; in future we 154 * will be able to query the regulator performance here. */ 155 regulator_latency = 1 * 1000 * 1000; 156 } 157 #endif 158 159 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) 160 { 161 int ret; 162 struct cpufreq_frequency_table *freq; 163 164 if (policy->cpu != 0) 165 return -EINVAL; 166 167 if (s3c64xx_freq_table == NULL) { 168 pr_err("No frequency information for this CPU\n"); 169 return -ENODEV; 170 } 171 172 armclk = clk_get(NULL, "armclk"); 173 if (IS_ERR(armclk)) { 174 pr_err("Unable to obtain ARMCLK: %ld\n", 175 PTR_ERR(armclk)); 176 return PTR_ERR(armclk); 177 } 178 179 #ifdef CONFIG_REGULATOR 180 vddarm = regulator_get(NULL, "vddarm"); 181 if (IS_ERR(vddarm)) { 182 ret = PTR_ERR(vddarm); 183 pr_err("Failed to obtain VDDARM: %d\n", ret); 184 pr_err("Only frequency scaling available\n"); 185 vddarm = NULL; 186 } else { 187 s3c64xx_cpufreq_config_regulator(); 188 } 189 #endif 190 191 freq = s3c64xx_freq_table; 192 while (freq->frequency != CPUFREQ_TABLE_END) { 193 unsigned long r; 194 195 /* Check for frequencies we can generate */ 196 r = clk_round_rate(armclk, freq->frequency * 1000); 197 r /= 1000; 198 if (r != freq->frequency) { 199 pr_debug("%dkHz unsupported by clock\n", 200 freq->frequency); 201 freq->frequency = CPUFREQ_ENTRY_INVALID; 202 } 203 204 /* If we have no regulator then assume startup 205 * frequency is the maximum we can support. */ 206 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0)) 207 freq->frequency = CPUFREQ_ENTRY_INVALID; 208 209 freq++; 210 } 211 212 /* Datasheet says PLL stabalisation time (if we were to use 213 * the PLLs, which we don't currently) is ~300us worst case, 214 * but add some fudge. 215 */ 216 ret = cpufreq_generic_init(policy, s3c64xx_freq_table, 217 (500 * 1000) + regulator_latency); 218 if (ret != 0) { 219 pr_err("Failed to configure frequency table: %d\n", 220 ret); 221 regulator_put(vddarm); 222 clk_put(armclk); 223 } 224 225 return ret; 226 } 227 228 static struct cpufreq_driver s3c64xx_cpufreq_driver = { 229 .flags = 0, 230 .verify = cpufreq_generic_frequency_table_verify, 231 .target_index = s3c64xx_cpufreq_set_target, 232 .get = s3c64xx_cpufreq_get_speed, 233 .init = s3c64xx_cpufreq_driver_init, 234 .name = "s3c", 235 }; 236 237 static int __init s3c64xx_cpufreq_init(void) 238 { 239 return cpufreq_register_driver(&s3c64xx_cpufreq_driver); 240 } 241 module_init(s3c64xx_cpufreq_init); 242