1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2009 Wolfson Microelectronics plc 4 * 5 * S3C64xx CPUfreq Support 6 */ 7 8 #define pr_fmt(fmt) "cpufreq: " fmt 9 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/cpufreq.h> 14 #include <linux/clk.h> 15 #include <linux/err.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/module.h> 18 19 static struct regulator *vddarm; 20 static unsigned long regulator_latency; 21 22 #ifdef CONFIG_CPU_S3C6410 23 struct s3c64xx_dvfs { 24 unsigned int vddarm_min; 25 unsigned int vddarm_max; 26 }; 27 28 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { 29 [0] = { 1000000, 1150000 }, 30 [1] = { 1050000, 1150000 }, 31 [2] = { 1100000, 1150000 }, 32 [3] = { 1200000, 1350000 }, 33 [4] = { 1300000, 1350000 }, 34 }; 35 36 static struct cpufreq_frequency_table s3c64xx_freq_table[] = { 37 { 0, 0, 66000 }, 38 { 0, 0, 100000 }, 39 { 0, 0, 133000 }, 40 { 0, 1, 200000 }, 41 { 0, 1, 222000 }, 42 { 0, 1, 266000 }, 43 { 0, 2, 333000 }, 44 { 0, 2, 400000 }, 45 { 0, 2, 532000 }, 46 { 0, 2, 533000 }, 47 { 0, 3, 667000 }, 48 { 0, 4, 800000 }, 49 { 0, 0, CPUFREQ_TABLE_END }, 50 }; 51 #endif 52 53 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, 54 unsigned int index) 55 { 56 struct s3c64xx_dvfs *dvfs; 57 unsigned int old_freq, new_freq; 58 int ret; 59 60 old_freq = clk_get_rate(policy->clk) / 1000; 61 new_freq = s3c64xx_freq_table[index].frequency; 62 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; 63 64 #ifdef CONFIG_REGULATOR 65 if (vddarm && new_freq > old_freq) { 66 ret = regulator_set_voltage(vddarm, 67 dvfs->vddarm_min, 68 dvfs->vddarm_max); 69 if (ret != 0) { 70 pr_err("Failed to set VDDARM for %dkHz: %d\n", 71 new_freq, ret); 72 return ret; 73 } 74 } 75 #endif 76 77 ret = clk_set_rate(policy->clk, new_freq * 1000); 78 if (ret < 0) { 79 pr_err("Failed to set rate %dkHz: %d\n", 80 new_freq, ret); 81 return ret; 82 } 83 84 #ifdef CONFIG_REGULATOR 85 if (vddarm && new_freq < old_freq) { 86 ret = regulator_set_voltage(vddarm, 87 dvfs->vddarm_min, 88 dvfs->vddarm_max); 89 if (ret != 0) { 90 pr_err("Failed to set VDDARM for %dkHz: %d\n", 91 new_freq, ret); 92 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) 93 pr_err("Failed to restore original clock rate\n"); 94 95 return ret; 96 } 97 } 98 #endif 99 100 pr_debug("Set actual frequency %lukHz\n", 101 clk_get_rate(policy->clk) / 1000); 102 103 return 0; 104 } 105 106 #ifdef CONFIG_REGULATOR 107 static void s3c64xx_cpufreq_config_regulator(void) 108 { 109 int count, v, i, found; 110 struct cpufreq_frequency_table *freq; 111 struct s3c64xx_dvfs *dvfs; 112 113 count = regulator_count_voltages(vddarm); 114 if (count < 0) { 115 pr_err("Unable to check supported voltages\n"); 116 } 117 118 if (!count) 119 goto out; 120 121 cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) { 122 dvfs = &s3c64xx_dvfs_table[freq->driver_data]; 123 found = 0; 124 125 for (i = 0; i < count; i++) { 126 v = regulator_list_voltage(vddarm, i); 127 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) 128 found = 1; 129 } 130 131 if (!found) { 132 pr_debug("%dkHz unsupported by regulator\n", 133 freq->frequency); 134 freq->frequency = CPUFREQ_ENTRY_INVALID; 135 } 136 } 137 138 out: 139 /* Guess based on having to do an I2C/SPI write; in future we 140 * will be able to query the regulator performance here. */ 141 regulator_latency = 1 * 1000 * 1000; 142 } 143 #endif 144 145 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) 146 { 147 int ret; 148 struct cpufreq_frequency_table *freq; 149 150 if (policy->cpu != 0) 151 return -EINVAL; 152 153 if (s3c64xx_freq_table == NULL) { 154 pr_err("No frequency information for this CPU\n"); 155 return -ENODEV; 156 } 157 158 policy->clk = clk_get(NULL, "armclk"); 159 if (IS_ERR(policy->clk)) { 160 pr_err("Unable to obtain ARMCLK: %ld\n", 161 PTR_ERR(policy->clk)); 162 return PTR_ERR(policy->clk); 163 } 164 165 #ifdef CONFIG_REGULATOR 166 vddarm = regulator_get(NULL, "vddarm"); 167 if (IS_ERR(vddarm)) { 168 ret = PTR_ERR(vddarm); 169 pr_err("Failed to obtain VDDARM: %d\n", ret); 170 pr_err("Only frequency scaling available\n"); 171 vddarm = NULL; 172 } else { 173 s3c64xx_cpufreq_config_regulator(); 174 } 175 #endif 176 177 cpufreq_for_each_entry(freq, s3c64xx_freq_table) { 178 unsigned long r; 179 180 /* Check for frequencies we can generate */ 181 r = clk_round_rate(policy->clk, freq->frequency * 1000); 182 r /= 1000; 183 if (r != freq->frequency) { 184 pr_debug("%dkHz unsupported by clock\n", 185 freq->frequency); 186 freq->frequency = CPUFREQ_ENTRY_INVALID; 187 } 188 189 /* If we have no regulator then assume startup 190 * frequency is the maximum we can support. */ 191 if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000) 192 freq->frequency = CPUFREQ_ENTRY_INVALID; 193 } 194 195 /* Datasheet says PLL stabalisation time (if we were to use 196 * the PLLs, which we don't currently) is ~300us worst case, 197 * but add some fudge. 198 */ 199 ret = cpufreq_generic_init(policy, s3c64xx_freq_table, 200 (500 * 1000) + regulator_latency); 201 if (ret != 0) { 202 pr_err("Failed to configure frequency table: %d\n", 203 ret); 204 regulator_put(vddarm); 205 clk_put(policy->clk); 206 } 207 208 return ret; 209 } 210 211 static struct cpufreq_driver s3c64xx_cpufreq_driver = { 212 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 213 .verify = cpufreq_generic_frequency_table_verify, 214 .target_index = s3c64xx_cpufreq_set_target, 215 .get = cpufreq_generic_get, 216 .init = s3c64xx_cpufreq_driver_init, 217 .name = "s3c", 218 }; 219 220 static int __init s3c64xx_cpufreq_init(void) 221 { 222 return cpufreq_register_driver(&s3c64xx_cpufreq_driver); 223 } 224 module_init(s3c64xx_cpufreq_init); 225