1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * CPU Frequency Scaling driver for Freescale QorIQ SoCs. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/cpufreq.h> 16 #include <linux/errno.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mutex.h> 21 #include <linux/of.h> 22 #include <linux/slab.h> 23 #include <linux/smp.h> 24 25 /** 26 * struct cpu_data 27 * @pclk: the parent clock of cpu 28 * @table: frequency table 29 */ 30 struct cpu_data { 31 struct clk **pclk; 32 struct cpufreq_frequency_table *table; 33 }; 34 35 /* 36 * Don't use cpufreq on this SoC -- used when the SoC would have otherwise 37 * matched a more generic compatible. 38 */ 39 #define SOC_BLACKLIST 1 40 41 /** 42 * struct soc_data - SoC specific data 43 * @flags: SOC_xxx 44 */ 45 struct soc_data { 46 u32 flags; 47 }; 48 49 static u32 get_bus_freq(void) 50 { 51 struct device_node *soc; 52 u32 sysfreq; 53 struct clk *pltclk; 54 int ret; 55 56 /* get platform freq by searching bus-frequency property */ 57 soc = of_find_node_by_type(NULL, "soc"); 58 if (soc) { 59 ret = of_property_read_u32(soc, "bus-frequency", &sysfreq); 60 of_node_put(soc); 61 if (!ret) 62 return sysfreq; 63 } 64 65 /* get platform freq by its clock name */ 66 pltclk = clk_get(NULL, "cg-pll0-div1"); 67 if (IS_ERR(pltclk)) { 68 pr_err("%s: can't get bus frequency %ld\n", 69 __func__, PTR_ERR(pltclk)); 70 return PTR_ERR(pltclk); 71 } 72 73 return clk_get_rate(pltclk); 74 } 75 76 static struct clk *cpu_to_clk(int cpu) 77 { 78 struct device_node *np; 79 struct clk *clk; 80 81 if (!cpu_present(cpu)) 82 return NULL; 83 84 np = of_get_cpu_node(cpu, NULL); 85 if (!np) 86 return NULL; 87 88 clk = of_clk_get(np, 0); 89 of_node_put(np); 90 return clk; 91 } 92 93 /* traverse cpu nodes to get cpu mask of sharing clock wire */ 94 static void set_affected_cpus(struct cpufreq_policy *policy) 95 { 96 struct cpumask *dstp = policy->cpus; 97 struct clk *clk; 98 int i; 99 100 for_each_present_cpu(i) { 101 clk = cpu_to_clk(i); 102 if (IS_ERR(clk)) { 103 pr_err("%s: no clock for cpu %d\n", __func__, i); 104 continue; 105 } 106 107 if (clk_is_match(policy->clk, clk)) 108 cpumask_set_cpu(i, dstp); 109 } 110 } 111 112 /* reduce the duplicated frequencies in frequency table */ 113 static void freq_table_redup(struct cpufreq_frequency_table *freq_table, 114 int count) 115 { 116 int i, j; 117 118 for (i = 1; i < count; i++) { 119 for (j = 0; j < i; j++) { 120 if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID || 121 freq_table[j].frequency != 122 freq_table[i].frequency) 123 continue; 124 125 freq_table[i].frequency = CPUFREQ_ENTRY_INVALID; 126 break; 127 } 128 } 129 } 130 131 /* sort the frequencies in frequency table in descenting order */ 132 static void freq_table_sort(struct cpufreq_frequency_table *freq_table, 133 int count) 134 { 135 int i, j, ind; 136 unsigned int freq, max_freq; 137 struct cpufreq_frequency_table table; 138 139 for (i = 0; i < count - 1; i++) { 140 max_freq = freq_table[i].frequency; 141 ind = i; 142 for (j = i + 1; j < count; j++) { 143 freq = freq_table[j].frequency; 144 if (freq == CPUFREQ_ENTRY_INVALID || 145 freq <= max_freq) 146 continue; 147 ind = j; 148 max_freq = freq; 149 } 150 151 if (ind != i) { 152 /* exchange the frequencies */ 153 table.driver_data = freq_table[i].driver_data; 154 table.frequency = freq_table[i].frequency; 155 freq_table[i].driver_data = freq_table[ind].driver_data; 156 freq_table[i].frequency = freq_table[ind].frequency; 157 freq_table[ind].driver_data = table.driver_data; 158 freq_table[ind].frequency = table.frequency; 159 } 160 } 161 } 162 163 static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy) 164 { 165 struct device_node *np; 166 int i, count; 167 u32 freq; 168 struct clk *clk; 169 const struct clk_hw *hwclk; 170 struct cpufreq_frequency_table *table; 171 struct cpu_data *data; 172 unsigned int cpu = policy->cpu; 173 u64 u64temp; 174 175 np = of_get_cpu_node(cpu, NULL); 176 if (!np) 177 return -ENODEV; 178 179 data = kzalloc(sizeof(*data), GFP_KERNEL); 180 if (!data) 181 goto err_np; 182 183 policy->clk = of_clk_get(np, 0); 184 if (IS_ERR(policy->clk)) { 185 pr_err("%s: no clock information\n", __func__); 186 goto err_nomem2; 187 } 188 189 hwclk = __clk_get_hw(policy->clk); 190 count = clk_hw_get_num_parents(hwclk); 191 192 data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL); 193 if (!data->pclk) 194 goto err_nomem2; 195 196 table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL); 197 if (!table) 198 goto err_pclk; 199 200 for (i = 0; i < count; i++) { 201 clk = clk_hw_get_parent_by_index(hwclk, i)->clk; 202 data->pclk[i] = clk; 203 freq = clk_get_rate(clk); 204 table[i].frequency = freq / 1000; 205 table[i].driver_data = i; 206 } 207 freq_table_redup(table, count); 208 freq_table_sort(table, count); 209 table[i].frequency = CPUFREQ_TABLE_END; 210 policy->freq_table = table; 211 data->table = table; 212 213 /* update ->cpus if we have cluster, no harm if not */ 214 set_affected_cpus(policy); 215 policy->driver_data = data; 216 217 /* Minimum transition latency is 12 platform clocks */ 218 u64temp = 12ULL * NSEC_PER_SEC; 219 do_div(u64temp, get_bus_freq()); 220 policy->cpuinfo.transition_latency = u64temp + 1; 221 222 of_node_put(np); 223 224 return 0; 225 226 err_pclk: 227 kfree(data->pclk); 228 err_nomem2: 229 kfree(data); 230 err_np: 231 of_node_put(np); 232 233 return -ENODEV; 234 } 235 236 static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy) 237 { 238 struct cpu_data *data = policy->driver_data; 239 240 kfree(data->pclk); 241 kfree(data->table); 242 kfree(data); 243 policy->driver_data = NULL; 244 245 return 0; 246 } 247 248 static int qoriq_cpufreq_target(struct cpufreq_policy *policy, 249 unsigned int index) 250 { 251 struct clk *parent; 252 struct cpu_data *data = policy->driver_data; 253 254 parent = data->pclk[data->table[index].driver_data]; 255 return clk_set_parent(policy->clk, parent); 256 } 257 258 static struct cpufreq_driver qoriq_cpufreq_driver = { 259 .name = "qoriq_cpufreq", 260 .flags = CPUFREQ_CONST_LOOPS | 261 CPUFREQ_IS_COOLING_DEV, 262 .init = qoriq_cpufreq_cpu_init, 263 .exit = qoriq_cpufreq_cpu_exit, 264 .verify = cpufreq_generic_frequency_table_verify, 265 .target_index = qoriq_cpufreq_target, 266 .get = cpufreq_generic_get, 267 .attr = cpufreq_generic_attr, 268 }; 269 270 static const struct soc_data blacklist = { 271 .flags = SOC_BLACKLIST, 272 }; 273 274 static const struct of_device_id node_matches[] __initconst = { 275 /* e6500 cannot use cpufreq due to erratum A-008083 */ 276 { .compatible = "fsl,b4420-clockgen", &blacklist }, 277 { .compatible = "fsl,b4860-clockgen", &blacklist }, 278 { .compatible = "fsl,t2080-clockgen", &blacklist }, 279 { .compatible = "fsl,t4240-clockgen", &blacklist }, 280 281 { .compatible = "fsl,ls1012a-clockgen", }, 282 { .compatible = "fsl,ls1021a-clockgen", }, 283 { .compatible = "fsl,ls1028a-clockgen", }, 284 { .compatible = "fsl,ls1043a-clockgen", }, 285 { .compatible = "fsl,ls1046a-clockgen", }, 286 { .compatible = "fsl,ls1088a-clockgen", }, 287 { .compatible = "fsl,ls2080a-clockgen", }, 288 { .compatible = "fsl,lx2160a-clockgen", }, 289 { .compatible = "fsl,p4080-clockgen", }, 290 { .compatible = "fsl,qoriq-clockgen-1.0", }, 291 { .compatible = "fsl,qoriq-clockgen-2.0", }, 292 {} 293 }; 294 295 static int __init qoriq_cpufreq_init(void) 296 { 297 int ret; 298 struct device_node *np; 299 const struct of_device_id *match; 300 const struct soc_data *data; 301 302 np = of_find_matching_node(NULL, node_matches); 303 if (!np) 304 return -ENODEV; 305 306 match = of_match_node(node_matches, np); 307 data = match->data; 308 309 of_node_put(np); 310 311 if (data && data->flags & SOC_BLACKLIST) 312 return -ENODEV; 313 314 ret = cpufreq_register_driver(&qoriq_cpufreq_driver); 315 if (!ret) 316 pr_info("Freescale QorIQ CPU frequency scaling driver\n"); 317 318 return ret; 319 } 320 module_init(qoriq_cpufreq_init); 321 322 static void __exit qoriq_cpufreq_exit(void) 323 { 324 cpufreq_unregister_driver(&qoriq_cpufreq_driver); 325 } 326 module_exit(qoriq_cpufreq_exit); 327 328 MODULE_LICENSE("GPL"); 329 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>"); 330 MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs"); 331