17d127095SSricharan R // SPDX-License-Identifier: GPL-2.0 27d127095SSricharan R /* 37d127095SSricharan R * Copyright (c) 2018, The Linux Foundation. All rights reserved. 47d127095SSricharan R */ 57d127095SSricharan R 67d127095SSricharan R /* 77d127095SSricharan R * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, 87d127095SSricharan R * the CPU frequency subset and voltage value of each OPP varies 97d127095SSricharan R * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables 107d127095SSricharan R * defines the voltage and frequency value based on the msm-id in SMEM 117d127095SSricharan R * and speedbin blown in the efuse combination. 127d127095SSricharan R * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC 137d127095SSricharan R * to provide the OPP framework with required information. 147d127095SSricharan R * This is used to determine the voltage and frequency value for each OPP of 157d127095SSricharan R * operating-points-v2 table when it is parsed by the OPP framework. 167d127095SSricharan R */ 177d127095SSricharan R 187d127095SSricharan R #include <linux/cpu.h> 197d127095SSricharan R #include <linux/err.h> 207d127095SSricharan R #include <linux/init.h> 217d127095SSricharan R #include <linux/kernel.h> 227d127095SSricharan R #include <linux/module.h> 237d127095SSricharan R #include <linux/nvmem-consumer.h> 247d127095SSricharan R #include <linux/of.h> 257d127095SSricharan R #include <linux/of_device.h> 267d127095SSricharan R #include <linux/platform_device.h> 271cb8339cSNiklas Cassel #include <linux/pm_domain.h> 287d127095SSricharan R #include <linux/pm_opp.h> 297d127095SSricharan R #include <linux/slab.h> 307d127095SSricharan R #include <linux/soc/qcom/smem.h> 317d127095SSricharan R 327d127095SSricharan R #define MSM_ID_SMEM 137 337d127095SSricharan R 347d127095SSricharan R enum _msm_id { 357d127095SSricharan R MSM8996V3 = 0xF6ul, 367d127095SSricharan R APQ8096V3 = 0x123ul, 377d127095SSricharan R MSM8996SG = 0x131ul, 387d127095SSricharan R APQ8096SG = 0x138ul, 397d127095SSricharan R }; 407d127095SSricharan R 417d127095SSricharan R enum _msm8996_version { 427d127095SSricharan R MSM8996_V3, 437d127095SSricharan R MSM8996_SG, 447d127095SSricharan R NUM_OF_MSM8996_VERSIONS, 457d127095SSricharan R }; 467d127095SSricharan R 4757f2f8b4SNiklas Cassel struct qcom_cpufreq_drv; 4857f2f8b4SNiklas Cassel 4957f2f8b4SNiklas Cassel struct qcom_cpufreq_match_data { 5057f2f8b4SNiklas Cassel int (*get_version)(struct device *cpu_dev, 5157f2f8b4SNiklas Cassel struct nvmem_cell *speedbin_nvmem, 52a8811ec7SAnsuel Smith char **pvs_name, 5357f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv); 541cb8339cSNiklas Cassel const char **genpd_names; 5557f2f8b4SNiklas Cassel }; 5657f2f8b4SNiklas Cassel 5757f2f8b4SNiklas Cassel struct qcom_cpufreq_drv { 58a8811ec7SAnsuel Smith struct opp_table **names_opp_tables; 59a8811ec7SAnsuel Smith struct opp_table **hw_opp_tables; 601cb8339cSNiklas Cassel struct opp_table **genpd_opp_tables; 6157f2f8b4SNiklas Cassel u32 versions; 6257f2f8b4SNiklas Cassel const struct qcom_cpufreq_match_data *data; 6357f2f8b4SNiklas Cassel }; 6457f2f8b4SNiklas Cassel 657d127095SSricharan R static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; 667d127095SSricharan R 67a8811ec7SAnsuel Smith static void get_krait_bin_format_a(struct device *cpu_dev, 68a8811ec7SAnsuel Smith int *speed, int *pvs, int *pvs_ver, 69a8811ec7SAnsuel Smith struct nvmem_cell *pvs_nvmem, u8 *buf) 70a8811ec7SAnsuel Smith { 71a8811ec7SAnsuel Smith u32 pte_efuse; 72a8811ec7SAnsuel Smith 73a8811ec7SAnsuel Smith pte_efuse = *((u32 *)buf); 74a8811ec7SAnsuel Smith 75a8811ec7SAnsuel Smith *speed = pte_efuse & 0xf; 76a8811ec7SAnsuel Smith if (*speed == 0xf) 77a8811ec7SAnsuel Smith *speed = (pte_efuse >> 4) & 0xf; 78a8811ec7SAnsuel Smith 79a8811ec7SAnsuel Smith if (*speed == 0xf) { 80a8811ec7SAnsuel Smith *speed = 0; 81a8811ec7SAnsuel Smith dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed); 82a8811ec7SAnsuel Smith } else { 83a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 84a8811ec7SAnsuel Smith } 85a8811ec7SAnsuel Smith 86a8811ec7SAnsuel Smith *pvs = (pte_efuse >> 10) & 0x7; 87a8811ec7SAnsuel Smith if (*pvs == 0x7) 88a8811ec7SAnsuel Smith *pvs = (pte_efuse >> 13) & 0x7; 89a8811ec7SAnsuel Smith 90a8811ec7SAnsuel Smith if (*pvs == 0x7) { 91a8811ec7SAnsuel Smith *pvs = 0; 92a8811ec7SAnsuel Smith dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs); 93a8811ec7SAnsuel Smith } else { 94a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 95a8811ec7SAnsuel Smith } 96a8811ec7SAnsuel Smith } 97a8811ec7SAnsuel Smith 98a8811ec7SAnsuel Smith static void get_krait_bin_format_b(struct device *cpu_dev, 99a8811ec7SAnsuel Smith int *speed, int *pvs, int *pvs_ver, 100a8811ec7SAnsuel Smith struct nvmem_cell *pvs_nvmem, u8 *buf) 101a8811ec7SAnsuel Smith { 102a8811ec7SAnsuel Smith u32 pte_efuse, redundant_sel; 103a8811ec7SAnsuel Smith 104a8811ec7SAnsuel Smith pte_efuse = *((u32 *)buf); 105a8811ec7SAnsuel Smith redundant_sel = (pte_efuse >> 24) & 0x7; 106a8811ec7SAnsuel Smith 107a8811ec7SAnsuel Smith *pvs_ver = (pte_efuse >> 4) & 0x3; 108a8811ec7SAnsuel Smith 109a8811ec7SAnsuel Smith switch (redundant_sel) { 110a8811ec7SAnsuel Smith case 1: 111a8811ec7SAnsuel Smith *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 112a8811ec7SAnsuel Smith *speed = (pte_efuse >> 27) & 0xf; 113a8811ec7SAnsuel Smith break; 114a8811ec7SAnsuel Smith case 2: 115a8811ec7SAnsuel Smith *pvs = (pte_efuse >> 27) & 0xf; 116a8811ec7SAnsuel Smith *speed = pte_efuse & 0x7; 117a8811ec7SAnsuel Smith break; 118a8811ec7SAnsuel Smith default: 119a8811ec7SAnsuel Smith /* 4 bits of PVS are in efuse register bits 31, 8-6. */ 120a8811ec7SAnsuel Smith *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); 121a8811ec7SAnsuel Smith *speed = pte_efuse & 0x7; 122a8811ec7SAnsuel Smith } 123a8811ec7SAnsuel Smith 124a8811ec7SAnsuel Smith /* Check SPEED_BIN_BLOW_STATUS */ 125a8811ec7SAnsuel Smith if (pte_efuse & BIT(3)) { 126a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "Speed bin: %d\n", *speed); 127a8811ec7SAnsuel Smith } else { 128a8811ec7SAnsuel Smith dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n"); 129a8811ec7SAnsuel Smith *speed = 0; 130a8811ec7SAnsuel Smith } 131a8811ec7SAnsuel Smith 132a8811ec7SAnsuel Smith /* Check PVS_BLOW_STATUS */ 133a8811ec7SAnsuel Smith pte_efuse = *(((u32 *)buf) + 4); 134a8811ec7SAnsuel Smith pte_efuse &= BIT(21); 135a8811ec7SAnsuel Smith if (pte_efuse) { 136a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); 137a8811ec7SAnsuel Smith } else { 138a8811ec7SAnsuel Smith dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n"); 139a8811ec7SAnsuel Smith *pvs = 0; 140a8811ec7SAnsuel Smith } 141a8811ec7SAnsuel Smith 142a8811ec7SAnsuel Smith dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); 143a8811ec7SAnsuel Smith } 144a8811ec7SAnsuel Smith 1457d127095SSricharan R static enum _msm8996_version qcom_cpufreq_get_msm_id(void) 1467d127095SSricharan R { 1477d127095SSricharan R size_t len; 1487d127095SSricharan R u32 *msm_id; 1497d127095SSricharan R enum _msm8996_version version; 1507d127095SSricharan R 1517d127095SSricharan R msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); 1527d127095SSricharan R if (IS_ERR(msm_id)) 1537d127095SSricharan R return NUM_OF_MSM8996_VERSIONS; 1547d127095SSricharan R 1557d127095SSricharan R /* The first 4 bytes are format, next to them is the actual msm-id */ 1567d127095SSricharan R msm_id++; 1577d127095SSricharan R 1587d127095SSricharan R switch ((enum _msm_id)*msm_id) { 1597d127095SSricharan R case MSM8996V3: 1607d127095SSricharan R case APQ8096V3: 1617d127095SSricharan R version = MSM8996_V3; 1627d127095SSricharan R break; 1637d127095SSricharan R case MSM8996SG: 1647d127095SSricharan R case APQ8096SG: 1657d127095SSricharan R version = MSM8996_SG; 1667d127095SSricharan R break; 1677d127095SSricharan R default: 1687d127095SSricharan R version = NUM_OF_MSM8996_VERSIONS; 1697d127095SSricharan R } 1707d127095SSricharan R 1717d127095SSricharan R return version; 1727d127095SSricharan R } 1737d127095SSricharan R 1747d127095SSricharan R static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, 1757d127095SSricharan R struct nvmem_cell *speedbin_nvmem, 176a8811ec7SAnsuel Smith char **pvs_name, 17757f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv) 1787d127095SSricharan R { 1797d127095SSricharan R size_t len; 1807d127095SSricharan R u8 *speedbin; 1817d127095SSricharan R enum _msm8996_version msm8996_version; 182a8811ec7SAnsuel Smith *pvs_name = NULL; 1837d127095SSricharan R 1847d127095SSricharan R msm8996_version = qcom_cpufreq_get_msm_id(); 1857d127095SSricharan R if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { 1867d127095SSricharan R dev_err(cpu_dev, "Not Snapdragon 820/821!"); 1877d127095SSricharan R return -ENODEV; 1887d127095SSricharan R } 1897d127095SSricharan R 1907d127095SSricharan R speedbin = nvmem_cell_read(speedbin_nvmem, &len); 1917d127095SSricharan R if (IS_ERR(speedbin)) 1927d127095SSricharan R return PTR_ERR(speedbin); 1937d127095SSricharan R 1947d127095SSricharan R switch (msm8996_version) { 1957d127095SSricharan R case MSM8996_V3: 19657f2f8b4SNiklas Cassel drv->versions = 1 << (unsigned int)(*speedbin); 1977d127095SSricharan R break; 1987d127095SSricharan R case MSM8996_SG: 19957f2f8b4SNiklas Cassel drv->versions = 1 << ((unsigned int)(*speedbin) + 4); 2007d127095SSricharan R break; 2017d127095SSricharan R default: 2027d127095SSricharan R BUG(); 2037d127095SSricharan R break; 2047d127095SSricharan R } 2057d127095SSricharan R 2067d127095SSricharan R kfree(speedbin); 2077d127095SSricharan R return 0; 2087d127095SSricharan R } 2097d127095SSricharan R 210a8811ec7SAnsuel Smith static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, 211a8811ec7SAnsuel Smith struct nvmem_cell *speedbin_nvmem, 212a8811ec7SAnsuel Smith char **pvs_name, 213a8811ec7SAnsuel Smith struct qcom_cpufreq_drv *drv) 214a8811ec7SAnsuel Smith { 215a8811ec7SAnsuel Smith int speed = 0, pvs = 0, pvs_ver = 0; 216a8811ec7SAnsuel Smith u8 *speedbin; 217a8811ec7SAnsuel Smith size_t len; 218a8811ec7SAnsuel Smith 219a8811ec7SAnsuel Smith speedbin = nvmem_cell_read(speedbin_nvmem, &len); 220a8811ec7SAnsuel Smith 221a8811ec7SAnsuel Smith if (IS_ERR(speedbin)) 222a8811ec7SAnsuel Smith return PTR_ERR(speedbin); 223a8811ec7SAnsuel Smith 224a8811ec7SAnsuel Smith switch (len) { 225a8811ec7SAnsuel Smith case 4: 226a8811ec7SAnsuel Smith get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, 227a8811ec7SAnsuel Smith speedbin_nvmem, speedbin); 228a8811ec7SAnsuel Smith break; 229a8811ec7SAnsuel Smith case 8: 230a8811ec7SAnsuel Smith get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver, 231a8811ec7SAnsuel Smith speedbin_nvmem, speedbin); 232a8811ec7SAnsuel Smith break; 233a8811ec7SAnsuel Smith default: 234a8811ec7SAnsuel Smith dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); 235a8811ec7SAnsuel Smith return -ENODEV; 236a8811ec7SAnsuel Smith } 237a8811ec7SAnsuel Smith 238a8811ec7SAnsuel Smith snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d", 239a8811ec7SAnsuel Smith speed, pvs, pvs_ver); 240a8811ec7SAnsuel Smith 241a8811ec7SAnsuel Smith drv->versions = (1 << speed); 242a8811ec7SAnsuel Smith 243a8811ec7SAnsuel Smith kfree(speedbin); 244a8811ec7SAnsuel Smith return 0; 245a8811ec7SAnsuel Smith } 246a8811ec7SAnsuel Smith 24757f2f8b4SNiklas Cassel static const struct qcom_cpufreq_match_data match_data_kryo = { 24857f2f8b4SNiklas Cassel .get_version = qcom_cpufreq_kryo_name_version, 24957f2f8b4SNiklas Cassel }; 25057f2f8b4SNiklas Cassel 251a8811ec7SAnsuel Smith static const struct qcom_cpufreq_match_data match_data_krait = { 252a8811ec7SAnsuel Smith .get_version = qcom_cpufreq_krait_name_version, 253a8811ec7SAnsuel Smith }; 254a8811ec7SAnsuel Smith 2551cb8339cSNiklas Cassel static const char *qcs404_genpd_names[] = { "cpr", NULL }; 2561cb8339cSNiklas Cassel 2571cb8339cSNiklas Cassel static const struct qcom_cpufreq_match_data match_data_qcs404 = { 2581cb8339cSNiklas Cassel .genpd_names = qcs404_genpd_names, 2591cb8339cSNiklas Cassel }; 2601cb8339cSNiklas Cassel 2617d127095SSricharan R static int qcom_cpufreq_probe(struct platform_device *pdev) 2627d127095SSricharan R { 26357f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv; 2647d127095SSricharan R struct nvmem_cell *speedbin_nvmem; 2657d127095SSricharan R struct device_node *np; 2667d127095SSricharan R struct device *cpu_dev; 267a8811ec7SAnsuel Smith char *pvs_name = "speedXX-pvsXX-vXX"; 2687d127095SSricharan R unsigned cpu; 2697d127095SSricharan R const struct of_device_id *match; 2707d127095SSricharan R int ret; 2717d127095SSricharan R 2727d127095SSricharan R cpu_dev = get_cpu_device(0); 2737d127095SSricharan R if (!cpu_dev) 2747d127095SSricharan R return -ENODEV; 2757d127095SSricharan R 2767d127095SSricharan R np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); 2777d127095SSricharan R if (!np) 2787d127095SSricharan R return -ENOENT; 2797d127095SSricharan R 2802dea6516SAnsuel Smith ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); 2817d127095SSricharan R if (!ret) { 2827d127095SSricharan R of_node_put(np); 2837d127095SSricharan R return -ENOENT; 2847d127095SSricharan R } 2857d127095SSricharan R 28657f2f8b4SNiklas Cassel drv = kzalloc(sizeof(*drv), GFP_KERNEL); 28757f2f8b4SNiklas Cassel if (!drv) 28857f2f8b4SNiklas Cassel return -ENOMEM; 28957f2f8b4SNiklas Cassel 29057f2f8b4SNiklas Cassel match = pdev->dev.platform_data; 29157f2f8b4SNiklas Cassel drv->data = match->data; 29257f2f8b4SNiklas Cassel if (!drv->data) { 29357f2f8b4SNiklas Cassel ret = -ENODEV; 29457f2f8b4SNiklas Cassel goto free_drv; 2957d127095SSricharan R } 2967d127095SSricharan R 29757f2f8b4SNiklas Cassel if (drv->data->get_version) { 29857f2f8b4SNiklas Cassel speedbin_nvmem = of_nvmem_cell_get(np, NULL); 29957f2f8b4SNiklas Cassel if (IS_ERR(speedbin_nvmem)) { 30057f2f8b4SNiklas Cassel if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER) 30157f2f8b4SNiklas Cassel dev_err(cpu_dev, 30257f2f8b4SNiklas Cassel "Could not get nvmem cell: %ld\n", 30357f2f8b4SNiklas Cassel PTR_ERR(speedbin_nvmem)); 30457f2f8b4SNiklas Cassel ret = PTR_ERR(speedbin_nvmem); 30557f2f8b4SNiklas Cassel goto free_drv; 30657f2f8b4SNiklas Cassel } 3077d127095SSricharan R 308a8811ec7SAnsuel Smith ret = drv->data->get_version(cpu_dev, 309a8811ec7SAnsuel Smith speedbin_nvmem, &pvs_name, drv); 31057f2f8b4SNiklas Cassel if (ret) { 31157f2f8b4SNiklas Cassel nvmem_cell_put(speedbin_nvmem); 31257f2f8b4SNiklas Cassel goto free_drv; 31357f2f8b4SNiklas Cassel } 31457f2f8b4SNiklas Cassel nvmem_cell_put(speedbin_nvmem); 31557f2f8b4SNiklas Cassel } 31657f2f8b4SNiklas Cassel of_node_put(np); 31757f2f8b4SNiklas Cassel 318a8811ec7SAnsuel Smith drv->names_opp_tables = kcalloc(num_possible_cpus(), 319a8811ec7SAnsuel Smith sizeof(*drv->names_opp_tables), 32057f2f8b4SNiklas Cassel GFP_KERNEL); 321a8811ec7SAnsuel Smith if (!drv->names_opp_tables) { 32257f2f8b4SNiklas Cassel ret = -ENOMEM; 32357f2f8b4SNiklas Cassel goto free_drv; 32457f2f8b4SNiklas Cassel } 325a8811ec7SAnsuel Smith drv->hw_opp_tables = kcalloc(num_possible_cpus(), 326a8811ec7SAnsuel Smith sizeof(*drv->hw_opp_tables), 327a8811ec7SAnsuel Smith GFP_KERNEL); 328a8811ec7SAnsuel Smith if (!drv->hw_opp_tables) { 329a8811ec7SAnsuel Smith ret = -ENOMEM; 330a8811ec7SAnsuel Smith goto free_opp_names; 331a8811ec7SAnsuel Smith } 3327d127095SSricharan R 3331cb8339cSNiklas Cassel drv->genpd_opp_tables = kcalloc(num_possible_cpus(), 3341cb8339cSNiklas Cassel sizeof(*drv->genpd_opp_tables), 3351cb8339cSNiklas Cassel GFP_KERNEL); 3361cb8339cSNiklas Cassel if (!drv->genpd_opp_tables) { 3371cb8339cSNiklas Cassel ret = -ENOMEM; 3381cb8339cSNiklas Cassel goto free_opp; 3391cb8339cSNiklas Cassel } 3401cb8339cSNiklas Cassel 3417d127095SSricharan R for_each_possible_cpu(cpu) { 3427d127095SSricharan R cpu_dev = get_cpu_device(cpu); 3437d127095SSricharan R if (NULL == cpu_dev) { 3447d127095SSricharan R ret = -ENODEV; 3451cb8339cSNiklas Cassel goto free_genpd_opp; 3467d127095SSricharan R } 3477d127095SSricharan R 34857f2f8b4SNiklas Cassel if (drv->data->get_version) { 349a8811ec7SAnsuel Smith 350a8811ec7SAnsuel Smith if (pvs_name) { 351a8811ec7SAnsuel Smith drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name( 352a8811ec7SAnsuel Smith cpu_dev, 353a8811ec7SAnsuel Smith pvs_name); 354a8811ec7SAnsuel Smith if (IS_ERR(drv->names_opp_tables[cpu])) { 355a8811ec7SAnsuel Smith ret = PTR_ERR(drv->names_opp_tables[cpu]); 356a8811ec7SAnsuel Smith dev_err(cpu_dev, "Failed to add OPP name %s\n", 357a8811ec7SAnsuel Smith pvs_name); 358a8811ec7SAnsuel Smith goto free_opp; 359a8811ec7SAnsuel Smith } 360a8811ec7SAnsuel Smith } 361a8811ec7SAnsuel Smith 362a8811ec7SAnsuel Smith drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw( 363a8811ec7SAnsuel Smith cpu_dev, &drv->versions, 1); 364a8811ec7SAnsuel Smith if (IS_ERR(drv->hw_opp_tables[cpu])) { 365a8811ec7SAnsuel Smith ret = PTR_ERR(drv->hw_opp_tables[cpu]); 36657f2f8b4SNiklas Cassel dev_err(cpu_dev, 36757f2f8b4SNiklas Cassel "Failed to set supported hardware\n"); 3681cb8339cSNiklas Cassel goto free_genpd_opp; 3691cb8339cSNiklas Cassel } 3701cb8339cSNiklas Cassel } 3711cb8339cSNiklas Cassel 3721cb8339cSNiklas Cassel if (drv->data->genpd_names) { 3731cb8339cSNiklas Cassel drv->genpd_opp_tables[cpu] = 3741cb8339cSNiklas Cassel dev_pm_opp_attach_genpd(cpu_dev, 3751cb8339cSNiklas Cassel drv->data->genpd_names, 3761cb8339cSNiklas Cassel NULL); 3771cb8339cSNiklas Cassel if (IS_ERR(drv->genpd_opp_tables[cpu])) { 3781cb8339cSNiklas Cassel ret = PTR_ERR(drv->genpd_opp_tables[cpu]); 3791cb8339cSNiklas Cassel if (ret != -EPROBE_DEFER) 3801cb8339cSNiklas Cassel dev_err(cpu_dev, 3811cb8339cSNiklas Cassel "Could not attach to pm_domain: %d\n", 3821cb8339cSNiklas Cassel ret); 3831cb8339cSNiklas Cassel goto free_genpd_opp; 3847d127095SSricharan R } 3857d127095SSricharan R } 38657f2f8b4SNiklas Cassel } 3877d127095SSricharan R 3887d127095SSricharan R cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, 3897d127095SSricharan R NULL, 0); 3907d127095SSricharan R if (!IS_ERR(cpufreq_dt_pdev)) { 39157f2f8b4SNiklas Cassel platform_set_drvdata(pdev, drv); 3927d127095SSricharan R return 0; 3937d127095SSricharan R } 3947d127095SSricharan R 3957d127095SSricharan R ret = PTR_ERR(cpufreq_dt_pdev); 3967d127095SSricharan R dev_err(cpu_dev, "Failed to register platform device\n"); 3977d127095SSricharan R 3981cb8339cSNiklas Cassel free_genpd_opp: 3991cb8339cSNiklas Cassel for_each_possible_cpu(cpu) { 4001cb8339cSNiklas Cassel if (IS_ERR_OR_NULL(drv->genpd_opp_tables[cpu])) 4011cb8339cSNiklas Cassel break; 4021cb8339cSNiklas Cassel dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); 4031cb8339cSNiklas Cassel } 4041cb8339cSNiklas Cassel kfree(drv->genpd_opp_tables); 4057d127095SSricharan R free_opp: 4067d127095SSricharan R for_each_possible_cpu(cpu) { 407a8811ec7SAnsuel Smith if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu])) 4087d127095SSricharan R break; 409a8811ec7SAnsuel Smith dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]); 4107d127095SSricharan R } 411a8811ec7SAnsuel Smith for_each_possible_cpu(cpu) { 412a8811ec7SAnsuel Smith if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu])) 413a8811ec7SAnsuel Smith break; 414a8811ec7SAnsuel Smith dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]); 415a8811ec7SAnsuel Smith } 416a8811ec7SAnsuel Smith kfree(drv->hw_opp_tables); 417a8811ec7SAnsuel Smith free_opp_names: 418a8811ec7SAnsuel Smith kfree(drv->names_opp_tables); 41957f2f8b4SNiklas Cassel free_drv: 42057f2f8b4SNiklas Cassel kfree(drv); 4217d127095SSricharan R 4227d127095SSricharan R return ret; 4237d127095SSricharan R } 4247d127095SSricharan R 4257d127095SSricharan R static int qcom_cpufreq_remove(struct platform_device *pdev) 4267d127095SSricharan R { 42757f2f8b4SNiklas Cassel struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev); 4287d127095SSricharan R unsigned int cpu; 4297d127095SSricharan R 4307d127095SSricharan R platform_device_unregister(cpufreq_dt_pdev); 4317d127095SSricharan R 4321cb8339cSNiklas Cassel for_each_possible_cpu(cpu) { 433a8811ec7SAnsuel Smith if (drv->names_opp_tables[cpu]) 434a8811ec7SAnsuel Smith dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]); 435a8811ec7SAnsuel Smith if (drv->hw_opp_tables[cpu]) 436a8811ec7SAnsuel Smith dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]); 4371cb8339cSNiklas Cassel if (drv->genpd_opp_tables[cpu]) 4381cb8339cSNiklas Cassel dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]); 4391cb8339cSNiklas Cassel } 4407d127095SSricharan R 441a8811ec7SAnsuel Smith kfree(drv->names_opp_tables); 442a8811ec7SAnsuel Smith kfree(drv->hw_opp_tables); 4431cb8339cSNiklas Cassel kfree(drv->genpd_opp_tables); 44457f2f8b4SNiklas Cassel kfree(drv); 4457d127095SSricharan R 4467d127095SSricharan R return 0; 4477d127095SSricharan R } 4487d127095SSricharan R 4497d127095SSricharan R static struct platform_driver qcom_cpufreq_driver = { 4507d127095SSricharan R .probe = qcom_cpufreq_probe, 4517d127095SSricharan R .remove = qcom_cpufreq_remove, 4527d127095SSricharan R .driver = { 4537d127095SSricharan R .name = "qcom-cpufreq-nvmem", 4547d127095SSricharan R }, 4557d127095SSricharan R }; 4567d127095SSricharan R 4577d127095SSricharan R static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { 45857f2f8b4SNiklas Cassel { .compatible = "qcom,apq8096", .data = &match_data_kryo }, 45957f2f8b4SNiklas Cassel { .compatible = "qcom,msm8996", .data = &match_data_kryo }, 4601cb8339cSNiklas Cassel { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, 461a8811ec7SAnsuel Smith { .compatible = "qcom,ipq8064", .data = &match_data_krait }, 462a8811ec7SAnsuel Smith { .compatible = "qcom,apq8064", .data = &match_data_krait }, 463a8811ec7SAnsuel Smith { .compatible = "qcom,msm8974", .data = &match_data_krait }, 464a8811ec7SAnsuel Smith { .compatible = "qcom,msm8960", .data = &match_data_krait }, 4657d127095SSricharan R {}, 4667d127095SSricharan R }; 467*a5a60316SPali Rohár MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); 4687d127095SSricharan R 4697d127095SSricharan R /* 4707d127095SSricharan R * Since the driver depends on smem and nvmem drivers, which may 4717d127095SSricharan R * return EPROBE_DEFER, all the real activity is done in the probe, 4727d127095SSricharan R * which may be defered as well. The init here is only registering 4737d127095SSricharan R * the driver and the platform device. 4747d127095SSricharan R */ 4757d127095SSricharan R static int __init qcom_cpufreq_init(void) 4767d127095SSricharan R { 4777d127095SSricharan R struct device_node *np = of_find_node_by_path("/"); 4787d127095SSricharan R const struct of_device_id *match; 4797d127095SSricharan R int ret; 4807d127095SSricharan R 4817d127095SSricharan R if (!np) 4827d127095SSricharan R return -ENODEV; 4837d127095SSricharan R 4847d127095SSricharan R match = of_match_node(qcom_cpufreq_match_list, np); 4857d127095SSricharan R of_node_put(np); 4867d127095SSricharan R if (!match) 4877d127095SSricharan R return -ENODEV; 4887d127095SSricharan R 4897d127095SSricharan R ret = platform_driver_register(&qcom_cpufreq_driver); 4907d127095SSricharan R if (unlikely(ret < 0)) 4917d127095SSricharan R return ret; 4927d127095SSricharan R 4937d127095SSricharan R cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", 4947d127095SSricharan R -1, match, sizeof(*match)); 4957d127095SSricharan R ret = PTR_ERR_OR_ZERO(cpufreq_pdev); 4967d127095SSricharan R if (0 == ret) 4977d127095SSricharan R return 0; 4987d127095SSricharan R 4997d127095SSricharan R platform_driver_unregister(&qcom_cpufreq_driver); 5007d127095SSricharan R return ret; 5017d127095SSricharan R } 5027d127095SSricharan R module_init(qcom_cpufreq_init); 5037d127095SSricharan R 5047d127095SSricharan R static void __exit qcom_cpufreq_exit(void) 5057d127095SSricharan R { 5067d127095SSricharan R platform_device_unregister(cpufreq_pdev); 5077d127095SSricharan R platform_driver_unregister(&qcom_cpufreq_driver); 5087d127095SSricharan R } 5097d127095SSricharan R module_exit(qcom_cpufreq_exit); 5107d127095SSricharan R 5117d127095SSricharan R MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); 5127d127095SSricharan R MODULE_LICENSE("GPL v2"); 513