1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk-provider.h> 8 #include <linux/cpufreq.h> 9 #include <linux/init.h> 10 #include <linux/interconnect.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_opp.h> 17 #include <linux/pm_qos.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/units.h> 21 22 #define LUT_MAX_ENTRIES 40U 23 #define LUT_SRC GENMASK(31, 30) 24 #define LUT_L_VAL GENMASK(7, 0) 25 #define LUT_CORE_COUNT GENMASK(18, 16) 26 #define LUT_VOLT GENMASK(11, 0) 27 #define CLK_HW_DIV 2 28 #define LUT_TURBO_IND 1 29 30 #define GT_IRQ_STATUS BIT(2) 31 32 struct qcom_cpufreq_soc_data { 33 u32 reg_enable; 34 u32 reg_domain_state; 35 u32 reg_dcvs_ctrl; 36 u32 reg_freq_lut; 37 u32 reg_volt_lut; 38 u32 reg_intr_clr; 39 u32 reg_current_vote; 40 u32 reg_perf_state; 41 u8 lut_row_size; 42 }; 43 44 struct qcom_cpufreq_data { 45 void __iomem *base; 46 struct resource *res; 47 48 /* 49 * Mutex to synchronize between de-init sequence and re-starting LMh 50 * polling/interrupts 51 */ 52 struct mutex throttle_lock; 53 int throttle_irq; 54 char irq_name[15]; 55 bool cancel_throttle; 56 struct delayed_work throttle_work; 57 struct cpufreq_policy *policy; 58 struct clk_hw cpu_clk; 59 60 bool per_core_dcvs; 61 62 struct freq_qos_request throttle_freq_req; 63 }; 64 65 static struct { 66 struct qcom_cpufreq_data *data; 67 const struct qcom_cpufreq_soc_data *soc_data; 68 } qcom_cpufreq; 69 70 static unsigned long cpu_hw_rate, xo_rate; 71 static bool icc_scaling_enabled; 72 73 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, 74 unsigned long freq_khz) 75 { 76 unsigned long freq_hz = freq_khz * 1000; 77 struct dev_pm_opp *opp; 78 struct device *dev; 79 int ret; 80 81 dev = get_cpu_device(policy->cpu); 82 if (!dev) 83 return -ENODEV; 84 85 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); 86 if (IS_ERR(opp)) 87 return PTR_ERR(opp); 88 89 ret = dev_pm_opp_set_opp(dev, opp); 90 dev_pm_opp_put(opp); 91 return ret; 92 } 93 94 static int qcom_cpufreq_update_opp(struct device *cpu_dev, 95 unsigned long freq_khz, 96 unsigned long volt) 97 { 98 unsigned long freq_hz = freq_khz * 1000; 99 int ret; 100 101 /* Skip voltage update if the opp table is not available */ 102 if (!icc_scaling_enabled) 103 return dev_pm_opp_add(cpu_dev, freq_hz, volt); 104 105 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt); 106 if (ret) { 107 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz); 108 return ret; 109 } 110 111 return dev_pm_opp_enable(cpu_dev, freq_hz); 112 } 113 114 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, 115 unsigned int index) 116 { 117 struct qcom_cpufreq_data *data = policy->driver_data; 118 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; 119 unsigned long freq = policy->freq_table[index].frequency; 120 unsigned int i; 121 122 writel_relaxed(index, data->base + soc_data->reg_perf_state); 123 124 if (data->per_core_dcvs) 125 for (i = 1; i < cpumask_weight(policy->related_cpus); i++) 126 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4); 127 128 if (icc_scaling_enabled) 129 qcom_cpufreq_set_bw(policy, freq); 130 131 return 0; 132 } 133 134 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) 135 { 136 unsigned int lval; 137 138 if (qcom_cpufreq.soc_data->reg_current_vote) 139 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_vote) & 0x3ff; 140 else 141 lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_state) & 0xff; 142 143 return lval * xo_rate; 144 } 145 146 /* Get the frequency requested by the cpufreq core for the CPU */ 147 static unsigned int qcom_cpufreq_get_freq(unsigned int cpu) 148 { 149 struct qcom_cpufreq_data *data; 150 const struct qcom_cpufreq_soc_data *soc_data; 151 struct cpufreq_policy *policy; 152 unsigned int index; 153 154 policy = cpufreq_cpu_get_raw(cpu); 155 if (!policy) 156 return 0; 157 158 data = policy->driver_data; 159 soc_data = qcom_cpufreq.soc_data; 160 161 index = readl_relaxed(data->base + soc_data->reg_perf_state); 162 index = min(index, LUT_MAX_ENTRIES - 1); 163 164 return policy->freq_table[index].frequency; 165 } 166 167 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) 168 { 169 struct qcom_cpufreq_data *data; 170 struct cpufreq_policy *policy; 171 172 policy = cpufreq_cpu_get_raw(cpu); 173 if (!policy) 174 return 0; 175 176 data = policy->driver_data; 177 178 if (data->throttle_irq >= 0) 179 return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; 180 181 return qcom_cpufreq_get_freq(cpu); 182 } 183 184 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, 185 unsigned int target_freq) 186 { 187 struct qcom_cpufreq_data *data = policy->driver_data; 188 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; 189 unsigned int index; 190 unsigned int i; 191 192 index = policy->cached_resolved_idx; 193 writel_relaxed(index, data->base + soc_data->reg_perf_state); 194 195 if (data->per_core_dcvs) 196 for (i = 1; i < cpumask_weight(policy->related_cpus); i++) 197 writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4); 198 199 return policy->freq_table[index].frequency; 200 } 201 202 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, 203 struct cpufreq_policy *policy) 204 { 205 u32 data, src, lval, i, core_count, prev_freq = 0, freq; 206 u32 volt; 207 struct cpufreq_frequency_table *table; 208 struct dev_pm_opp *opp; 209 unsigned long rate; 210 int ret; 211 struct qcom_cpufreq_data *drv_data = policy->driver_data; 212 const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; 213 214 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); 215 if (!table) 216 return -ENOMEM; 217 218 ret = dev_pm_opp_of_add_table(cpu_dev); 219 if (!ret) { 220 /* Disable all opps and cross-validate against LUT later */ 221 icc_scaling_enabled = true; 222 for (rate = 0; ; rate++) { 223 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); 224 if (IS_ERR(opp)) 225 break; 226 227 dev_pm_opp_put(opp); 228 dev_pm_opp_disable(cpu_dev, rate); 229 } 230 } else if (ret != -ENODEV) { 231 dev_err(cpu_dev, "Invalid opp table in device tree\n"); 232 kfree(table); 233 return ret; 234 } else { 235 policy->fast_switch_possible = true; 236 icc_scaling_enabled = false; 237 } 238 239 for (i = 0; i < LUT_MAX_ENTRIES; i++) { 240 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + 241 i * soc_data->lut_row_size); 242 src = FIELD_GET(LUT_SRC, data); 243 lval = FIELD_GET(LUT_L_VAL, data); 244 core_count = FIELD_GET(LUT_CORE_COUNT, data); 245 246 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + 247 i * soc_data->lut_row_size); 248 volt = FIELD_GET(LUT_VOLT, data) * 1000; 249 250 if (src) 251 freq = xo_rate * lval / 1000; 252 else 253 freq = cpu_hw_rate / 1000; 254 255 if (freq != prev_freq && core_count != LUT_TURBO_IND) { 256 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) { 257 table[i].frequency = freq; 258 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, 259 freq, core_count); 260 } else { 261 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq); 262 table[i].frequency = CPUFREQ_ENTRY_INVALID; 263 } 264 265 } else if (core_count == LUT_TURBO_IND) { 266 table[i].frequency = CPUFREQ_ENTRY_INVALID; 267 } 268 269 /* 270 * Two of the same frequencies with the same core counts means 271 * end of table 272 */ 273 if (i > 0 && prev_freq == freq) { 274 struct cpufreq_frequency_table *prev = &table[i - 1]; 275 276 /* 277 * Only treat the last frequency that might be a boost 278 * as the boost frequency 279 */ 280 if (prev->frequency == CPUFREQ_ENTRY_INVALID) { 281 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) { 282 prev->frequency = prev_freq; 283 prev->flags = CPUFREQ_BOOST_FREQ; 284 } else { 285 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", 286 freq); 287 } 288 } 289 290 break; 291 } 292 293 prev_freq = freq; 294 } 295 296 table[i].frequency = CPUFREQ_TABLE_END; 297 policy->freq_table = table; 298 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); 299 300 return 0; 301 } 302 303 static void qcom_get_related_cpus(int index, struct cpumask *m) 304 { 305 struct device_node *cpu_np; 306 struct of_phandle_args args; 307 int cpu, ret; 308 309 for_each_possible_cpu(cpu) { 310 cpu_np = of_cpu_device_node_get(cpu); 311 if (!cpu_np) 312 continue; 313 314 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 315 "#freq-domain-cells", 0, 316 &args); 317 of_node_put(cpu_np); 318 if (ret < 0) 319 continue; 320 321 if (index == args.args[0]) 322 cpumask_set_cpu(cpu, m); 323 } 324 } 325 326 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) 327 { 328 struct cpufreq_policy *policy = data->policy; 329 int cpu = cpumask_first(policy->related_cpus); 330 struct device *dev = get_cpu_device(cpu); 331 unsigned long freq_hz, throttled_freq; 332 struct dev_pm_opp *opp; 333 334 /* 335 * Get the h/w throttled frequency, normalize it using the 336 * registered opp table and use it to calculate thermal pressure. 337 */ 338 freq_hz = qcom_lmh_get_throttle_freq(data); 339 340 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz); 341 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE) 342 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz); 343 344 if (IS_ERR(opp)) { 345 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp); 346 } else { 347 dev_pm_opp_put(opp); 348 } 349 350 throttled_freq = freq_hz / HZ_PER_KHZ; 351 352 freq_qos_update_request(&data->throttle_freq_req, throttled_freq); 353 354 /* Update thermal pressure (the boost frequencies are accepted) */ 355 arch_update_thermal_pressure(policy->related_cpus, throttled_freq); 356 357 /* 358 * In the unlikely case policy is unregistered do not enable 359 * polling or h/w interrupt 360 */ 361 mutex_lock(&data->throttle_lock); 362 if (data->cancel_throttle) 363 goto out; 364 365 /* 366 * If h/w throttled frequency is higher than what cpufreq has requested 367 * for, then stop polling and switch back to interrupt mechanism. 368 */ 369 if (throttled_freq >= qcom_cpufreq_get_freq(cpu)) 370 enable_irq(data->throttle_irq); 371 else 372 mod_delayed_work(system_highpri_wq, &data->throttle_work, 373 msecs_to_jiffies(10)); 374 375 out: 376 mutex_unlock(&data->throttle_lock); 377 } 378 379 static void qcom_lmh_dcvs_poll(struct work_struct *work) 380 { 381 struct qcom_cpufreq_data *data; 382 383 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work); 384 qcom_lmh_dcvs_notify(data); 385 } 386 387 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) 388 { 389 struct qcom_cpufreq_data *c_data = data; 390 391 /* Disable interrupt and enable polling */ 392 disable_irq_nosync(c_data->throttle_irq); 393 schedule_delayed_work(&c_data->throttle_work, 0); 394 395 if (qcom_cpufreq.soc_data->reg_intr_clr) 396 writel_relaxed(GT_IRQ_STATUS, 397 c_data->base + qcom_cpufreq.soc_data->reg_intr_clr); 398 399 return IRQ_HANDLED; 400 } 401 402 static const struct qcom_cpufreq_soc_data qcom_soc_data = { 403 .reg_enable = 0x0, 404 .reg_dcvs_ctrl = 0xbc, 405 .reg_freq_lut = 0x110, 406 .reg_volt_lut = 0x114, 407 .reg_current_vote = 0x704, 408 .reg_perf_state = 0x920, 409 .lut_row_size = 32, 410 }; 411 412 static const struct qcom_cpufreq_soc_data epss_soc_data = { 413 .reg_enable = 0x0, 414 .reg_domain_state = 0x20, 415 .reg_dcvs_ctrl = 0xb0, 416 .reg_freq_lut = 0x100, 417 .reg_volt_lut = 0x200, 418 .reg_intr_clr = 0x308, 419 .reg_perf_state = 0x320, 420 .lut_row_size = 4, 421 }; 422 423 static const struct of_device_id qcom_cpufreq_hw_match[] = { 424 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, 425 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, 426 {} 427 }; 428 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); 429 430 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index) 431 { 432 struct qcom_cpufreq_data *data = policy->driver_data; 433 struct platform_device *pdev = cpufreq_get_driver_data(); 434 int ret; 435 436 /* 437 * Look for LMh interrupt. If no interrupt line is specified / 438 * if there is an error, allow cpufreq to be enabled as usual. 439 */ 440 data->throttle_irq = platform_get_irq_optional(pdev, index); 441 if (data->throttle_irq == -ENXIO) 442 return 0; 443 if (data->throttle_irq < 0) 444 return data->throttle_irq; 445 446 ret = freq_qos_add_request(&policy->constraints, 447 &data->throttle_freq_req, FREQ_QOS_MAX, 448 FREQ_QOS_MAX_DEFAULT_VALUE); 449 if (ret < 0) { 450 dev_err(&pdev->dev, "Failed to add freq constraint (%d)\n", ret); 451 return ret; 452 } 453 454 data->cancel_throttle = false; 455 data->policy = policy; 456 457 mutex_init(&data->throttle_lock); 458 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll); 459 460 snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu); 461 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq, 462 IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data); 463 if (ret) { 464 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret); 465 return 0; 466 } 467 468 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus); 469 if (ret) 470 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n", 471 data->irq_name, data->throttle_irq); 472 473 return 0; 474 } 475 476 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy) 477 { 478 struct qcom_cpufreq_data *data = policy->driver_data; 479 struct platform_device *pdev = cpufreq_get_driver_data(); 480 int ret; 481 482 if (data->throttle_irq <= 0) 483 return 0; 484 485 mutex_lock(&data->throttle_lock); 486 data->cancel_throttle = false; 487 mutex_unlock(&data->throttle_lock); 488 489 ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus); 490 if (ret) 491 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n", 492 data->irq_name, data->throttle_irq); 493 494 return ret; 495 } 496 497 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy) 498 { 499 struct qcom_cpufreq_data *data = policy->driver_data; 500 501 if (data->throttle_irq <= 0) 502 return 0; 503 504 mutex_lock(&data->throttle_lock); 505 data->cancel_throttle = true; 506 mutex_unlock(&data->throttle_lock); 507 508 cancel_delayed_work_sync(&data->throttle_work); 509 irq_set_affinity_and_hint(data->throttle_irq, NULL); 510 disable_irq_nosync(data->throttle_irq); 511 512 return 0; 513 } 514 515 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data) 516 { 517 if (data->throttle_irq <= 0) 518 return; 519 520 freq_qos_remove_request(&data->throttle_freq_req); 521 free_irq(data->throttle_irq, data); 522 } 523 524 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) 525 { 526 struct platform_device *pdev = cpufreq_get_driver_data(); 527 struct device *dev = &pdev->dev; 528 struct of_phandle_args args; 529 struct device_node *cpu_np; 530 struct device *cpu_dev; 531 struct qcom_cpufreq_data *data; 532 int ret, index; 533 534 cpu_dev = get_cpu_device(policy->cpu); 535 if (!cpu_dev) { 536 pr_err("%s: failed to get cpu%d device\n", __func__, 537 policy->cpu); 538 return -ENODEV; 539 } 540 541 cpu_np = of_cpu_device_node_get(policy->cpu); 542 if (!cpu_np) 543 return -EINVAL; 544 545 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 546 "#freq-domain-cells", 0, &args); 547 of_node_put(cpu_np); 548 if (ret) 549 return ret; 550 551 index = args.args[0]; 552 data = &qcom_cpufreq.data[index]; 553 554 /* HW should be in enabled state to proceed */ 555 if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) { 556 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); 557 return -ENODEV; 558 } 559 560 if (readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_dcvs_ctrl) & 0x1) 561 data->per_core_dcvs = true; 562 563 qcom_get_related_cpus(index, policy->cpus); 564 565 policy->driver_data = data; 566 policy->dvfs_possible_from_any_cpu = true; 567 568 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); 569 if (ret) { 570 dev_err(dev, "Domain-%d failed to read LUT\n", index); 571 return ret; 572 } 573 574 ret = dev_pm_opp_get_opp_count(cpu_dev); 575 if (ret <= 0) { 576 dev_err(cpu_dev, "Failed to add OPPs\n"); 577 return -ENODEV; 578 } 579 580 if (policy_has_boost_freq(policy)) { 581 ret = cpufreq_enable_boost_support(); 582 if (ret) 583 dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); 584 } 585 586 return qcom_cpufreq_hw_lmh_init(policy, index); 587 } 588 589 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) 590 { 591 struct device *cpu_dev = get_cpu_device(policy->cpu); 592 struct qcom_cpufreq_data *data = policy->driver_data; 593 struct resource *res = data->res; 594 void __iomem *base = data->base; 595 596 dev_pm_opp_remove_all_dynamic(cpu_dev); 597 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); 598 qcom_cpufreq_hw_lmh_exit(data); 599 kfree(policy->freq_table); 600 kfree(data); 601 iounmap(base); 602 release_mem_region(res->start, resource_size(res)); 603 604 return 0; 605 } 606 607 static void qcom_cpufreq_ready(struct cpufreq_policy *policy) 608 { 609 struct qcom_cpufreq_data *data = policy->driver_data; 610 611 if (data->throttle_irq >= 0) 612 enable_irq(data->throttle_irq); 613 } 614 615 static struct freq_attr *qcom_cpufreq_hw_attr[] = { 616 &cpufreq_freq_attr_scaling_available_freqs, 617 &cpufreq_freq_attr_scaling_boost_freqs, 618 NULL 619 }; 620 621 static struct cpufreq_driver cpufreq_qcom_hw_driver = { 622 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 623 CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 624 CPUFREQ_IS_COOLING_DEV, 625 .verify = cpufreq_generic_frequency_table_verify, 626 .target_index = qcom_cpufreq_hw_target_index, 627 .get = qcom_cpufreq_hw_get, 628 .init = qcom_cpufreq_hw_cpu_init, 629 .exit = qcom_cpufreq_hw_cpu_exit, 630 .online = qcom_cpufreq_hw_cpu_online, 631 .offline = qcom_cpufreq_hw_cpu_offline, 632 .register_em = cpufreq_register_em_with_opp, 633 .fast_switch = qcom_cpufreq_hw_fast_switch, 634 .name = "qcom-cpufreq-hw", 635 .attr = qcom_cpufreq_hw_attr, 636 .ready = qcom_cpufreq_ready, 637 }; 638 639 static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 640 { 641 struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk); 642 643 return qcom_lmh_get_throttle_freq(data); 644 } 645 646 static const struct clk_ops qcom_cpufreq_hw_clk_ops = { 647 .recalc_rate = qcom_cpufreq_hw_recalc_rate, 648 }; 649 650 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) 651 { 652 struct clk_hw_onecell_data *clk_data; 653 struct device *dev = &pdev->dev; 654 struct device_node *soc_node; 655 struct device *cpu_dev; 656 struct clk *clk; 657 int ret, i, num_domains, reg_sz; 658 659 clk = clk_get(dev, "xo"); 660 if (IS_ERR(clk)) 661 return PTR_ERR(clk); 662 663 xo_rate = clk_get_rate(clk); 664 clk_put(clk); 665 666 clk = clk_get(dev, "alternate"); 667 if (IS_ERR(clk)) 668 return PTR_ERR(clk); 669 670 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; 671 clk_put(clk); 672 673 cpufreq_qcom_hw_driver.driver_data = pdev; 674 675 /* Check for optional interconnect paths on CPU0 */ 676 cpu_dev = get_cpu_device(0); 677 if (!cpu_dev) 678 return -EPROBE_DEFER; 679 680 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); 681 if (ret) 682 return ret; 683 684 /* Allocate qcom_cpufreq_data based on the available frequency domains in DT */ 685 soc_node = of_get_parent(dev->of_node); 686 if (!soc_node) 687 return -EINVAL; 688 689 ret = of_property_read_u32(soc_node, "#address-cells", ®_sz); 690 if (ret) 691 goto of_exit; 692 693 ret = of_property_read_u32(soc_node, "#size-cells", &i); 694 if (ret) 695 goto of_exit; 696 697 reg_sz += i; 698 699 num_domains = of_property_count_elems_of_size(dev->of_node, "reg", sizeof(u32) * reg_sz); 700 if (num_domains <= 0) 701 return num_domains; 702 703 qcom_cpufreq.data = devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) * num_domains, 704 GFP_KERNEL); 705 if (!qcom_cpufreq.data) 706 return -ENOMEM; 707 708 qcom_cpufreq.soc_data = of_device_get_match_data(dev); 709 if (!qcom_cpufreq.soc_data) 710 return -ENODEV; 711 712 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), GFP_KERNEL); 713 if (!clk_data) 714 return -ENOMEM; 715 716 clk_data->num = num_domains; 717 718 for (i = 0; i < num_domains; i++) { 719 struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i]; 720 struct clk_init_data clk_init = {}; 721 struct resource *res; 722 void __iomem *base; 723 724 base = devm_platform_get_and_ioremap_resource(pdev, i, &res); 725 if (IS_ERR(base)) { 726 dev_err(dev, "Failed to map resource %pR\n", res); 727 return PTR_ERR(base); 728 } 729 730 data->base = base; 731 data->res = res; 732 733 /* Register CPU clock for each frequency domain */ 734 clk_init.name = kasprintf(GFP_KERNEL, "qcom_cpufreq%d", i); 735 if (!clk_init.name) 736 return -ENOMEM; 737 738 clk_init.flags = CLK_GET_RATE_NOCACHE; 739 clk_init.ops = &qcom_cpufreq_hw_clk_ops; 740 data->cpu_clk.init = &clk_init; 741 742 ret = devm_clk_hw_register(dev, &data->cpu_clk); 743 if (ret < 0) { 744 dev_err(dev, "Failed to register clock %d: %d\n", i, ret); 745 kfree(clk_init.name); 746 return ret; 747 } 748 749 clk_data->hws[i] = &data->cpu_clk; 750 kfree(clk_init.name); 751 } 752 753 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 754 if (ret < 0) { 755 dev_err(dev, "Failed to add clock provider\n"); 756 return ret; 757 } 758 759 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); 760 if (ret) 761 dev_err(dev, "CPUFreq HW driver failed to register\n"); 762 else 763 dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n"); 764 765 of_exit: 766 of_node_put(soc_node); 767 768 return ret; 769 } 770 771 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) 772 { 773 cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); 774 775 return 0; 776 } 777 778 static struct platform_driver qcom_cpufreq_hw_driver = { 779 .probe = qcom_cpufreq_hw_driver_probe, 780 .remove = qcom_cpufreq_hw_driver_remove, 781 .driver = { 782 .name = "qcom-cpufreq-hw", 783 .of_match_table = qcom_cpufreq_hw_match, 784 }, 785 }; 786 787 static int __init qcom_cpufreq_hw_init(void) 788 { 789 return platform_driver_register(&qcom_cpufreq_hw_driver); 790 } 791 postcore_initcall(qcom_cpufreq_hw_init); 792 793 static void __exit qcom_cpufreq_hw_exit(void) 794 { 795 platform_driver_unregister(&qcom_cpufreq_hw_driver); 796 } 797 module_exit(qcom_cpufreq_hw_exit); 798 799 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver"); 800 MODULE_LICENSE("GPL v2"); 801