12849dd8bSTaniya Das // SPDX-License-Identifier: GPL-2.0 22849dd8bSTaniya Das /* 32849dd8bSTaniya Das * Copyright (c) 2018, The Linux Foundation. All rights reserved. 42849dd8bSTaniya Das */ 52849dd8bSTaniya Das 62849dd8bSTaniya Das #include <linux/bitfield.h> 72849dd8bSTaniya Das #include <linux/cpufreq.h> 82849dd8bSTaniya Das #include <linux/init.h> 951c843cfSSibi Sankar #include <linux/interconnect.h> 102849dd8bSTaniya Das #include <linux/kernel.h> 112849dd8bSTaniya Das #include <linux/module.h> 122849dd8bSTaniya Das #include <linux/of_address.h> 132849dd8bSTaniya Das #include <linux/of_platform.h> 1455538fbcSTaniya Das #include <linux/pm_opp.h> 152849dd8bSTaniya Das #include <linux/slab.h> 162849dd8bSTaniya Das 172849dd8bSTaniya Das #define LUT_MAX_ENTRIES 40U 182849dd8bSTaniya Das #define LUT_SRC GENMASK(31, 30) 192849dd8bSTaniya Das #define LUT_L_VAL GENMASK(7, 0) 202849dd8bSTaniya Das #define LUT_CORE_COUNT GENMASK(18, 16) 2155538fbcSTaniya Das #define LUT_VOLT GENMASK(11, 0) 222849dd8bSTaniya Das #define CLK_HW_DIV 2 230eae1e37SSibi Sankar #define LUT_TURBO_IND 1 242849dd8bSTaniya Das 25dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_soc_data { 26dcd1fd72SManivannan Sadhasivam u32 reg_enable; 27dcd1fd72SManivannan Sadhasivam u32 reg_freq_lut; 28dcd1fd72SManivannan Sadhasivam u32 reg_volt_lut; 29dcd1fd72SManivannan Sadhasivam u32 reg_perf_state; 30dcd1fd72SManivannan Sadhasivam u8 lut_row_size; 31dcd1fd72SManivannan Sadhasivam }; 32dcd1fd72SManivannan Sadhasivam 33dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data { 34dcd1fd72SManivannan Sadhasivam void __iomem *base; 35dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data; 36dcd1fd72SManivannan Sadhasivam }; 372849dd8bSTaniya Das 382849dd8bSTaniya Das static unsigned long cpu_hw_rate, xo_rate; 3951c843cfSSibi Sankar static bool icc_scaling_enabled; 4051c843cfSSibi Sankar 4151c843cfSSibi Sankar static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, 4251c843cfSSibi Sankar unsigned long freq_khz) 4351c843cfSSibi Sankar { 4451c843cfSSibi Sankar unsigned long freq_hz = freq_khz * 1000; 4551c843cfSSibi Sankar struct dev_pm_opp *opp; 4651c843cfSSibi Sankar struct device *dev; 4751c843cfSSibi Sankar int ret; 4851c843cfSSibi Sankar 4951c843cfSSibi Sankar dev = get_cpu_device(policy->cpu); 5051c843cfSSibi Sankar if (!dev) 5151c843cfSSibi Sankar return -ENODEV; 5251c843cfSSibi Sankar 5351c843cfSSibi Sankar opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); 5451c843cfSSibi Sankar if (IS_ERR(opp)) 5551c843cfSSibi Sankar return PTR_ERR(opp); 5651c843cfSSibi Sankar 5751c843cfSSibi Sankar ret = dev_pm_opp_set_bw(dev, opp); 5851c843cfSSibi Sankar dev_pm_opp_put(opp); 5951c843cfSSibi Sankar return ret; 6051c843cfSSibi Sankar } 6151c843cfSSibi Sankar 6251c843cfSSibi Sankar static int qcom_cpufreq_update_opp(struct device *cpu_dev, 6351c843cfSSibi Sankar unsigned long freq_khz, 6451c843cfSSibi Sankar unsigned long volt) 6551c843cfSSibi Sankar { 6651c843cfSSibi Sankar unsigned long freq_hz = freq_khz * 1000; 6751c843cfSSibi Sankar int ret; 6851c843cfSSibi Sankar 6951c843cfSSibi Sankar /* Skip voltage update if the opp table is not available */ 7051c843cfSSibi Sankar if (!icc_scaling_enabled) 7151c843cfSSibi Sankar return dev_pm_opp_add(cpu_dev, freq_hz, volt); 7251c843cfSSibi Sankar 7351c843cfSSibi Sankar ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt); 7451c843cfSSibi Sankar if (ret) { 7551c843cfSSibi Sankar dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz); 7651c843cfSSibi Sankar return ret; 7751c843cfSSibi Sankar } 7851c843cfSSibi Sankar 7951c843cfSSibi Sankar return dev_pm_opp_enable(cpu_dev, freq_hz); 8051c843cfSSibi Sankar } 812849dd8bSTaniya Das 822849dd8bSTaniya Das static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, 832849dd8bSTaniya Das unsigned int index) 842849dd8bSTaniya Das { 85dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data = policy->driver_data; 86dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; 87ada54f35SDouglas RAILLARD unsigned long freq = policy->freq_table[index].frequency; 882849dd8bSTaniya Das 89dcd1fd72SManivannan Sadhasivam writel_relaxed(index, data->base + soc_data->reg_perf_state); 902849dd8bSTaniya Das 9151c843cfSSibi Sankar if (icc_scaling_enabled) 9251c843cfSSibi Sankar qcom_cpufreq_set_bw(policy, freq); 9351c843cfSSibi Sankar 94ada54f35SDouglas RAILLARD arch_set_freq_scale(policy->related_cpus, freq, 95ada54f35SDouglas RAILLARD policy->cpuinfo.max_freq); 962849dd8bSTaniya Das return 0; 972849dd8bSTaniya Das } 982849dd8bSTaniya Das 992849dd8bSTaniya Das static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) 1002849dd8bSTaniya Das { 101dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data; 102dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data; 1032849dd8bSTaniya Das struct cpufreq_policy *policy; 1042849dd8bSTaniya Das unsigned int index; 1052849dd8bSTaniya Das 1062849dd8bSTaniya Das policy = cpufreq_cpu_get_raw(cpu); 1072849dd8bSTaniya Das if (!policy) 1082849dd8bSTaniya Das return 0; 1092849dd8bSTaniya Das 110dcd1fd72SManivannan Sadhasivam data = policy->driver_data; 111dcd1fd72SManivannan Sadhasivam soc_data = data->soc_data; 1122849dd8bSTaniya Das 113dcd1fd72SManivannan Sadhasivam index = readl_relaxed(data->base + soc_data->reg_perf_state); 1142849dd8bSTaniya Das index = min(index, LUT_MAX_ENTRIES - 1); 1152849dd8bSTaniya Das 1162849dd8bSTaniya Das return policy->freq_table[index].frequency; 1172849dd8bSTaniya Das } 1182849dd8bSTaniya Das 1192849dd8bSTaniya Das static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, 1202849dd8bSTaniya Das unsigned int target_freq) 1212849dd8bSTaniya Das { 122dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data = policy->driver_data; 123dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; 124292072c3SViresh Kumar unsigned int index; 125ada54f35SDouglas RAILLARD unsigned long freq; 1262849dd8bSTaniya Das 1272849dd8bSTaniya Das index = policy->cached_resolved_idx; 128dcd1fd72SManivannan Sadhasivam writel_relaxed(index, data->base + soc_data->reg_perf_state); 1292849dd8bSTaniya Das 130ada54f35SDouglas RAILLARD freq = policy->freq_table[index].frequency; 131ada54f35SDouglas RAILLARD arch_set_freq_scale(policy->related_cpus, freq, 132ada54f35SDouglas RAILLARD policy->cpuinfo.max_freq); 133ada54f35SDouglas RAILLARD 134ada54f35SDouglas RAILLARD return freq; 1352849dd8bSTaniya Das } 1362849dd8bSTaniya Das 13755538fbcSTaniya Das static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, 138dcd1fd72SManivannan Sadhasivam struct cpufreq_policy *policy) 1392849dd8bSTaniya Das { 1400eae1e37SSibi Sankar u32 data, src, lval, i, core_count, prev_freq = 0, freq; 14155538fbcSTaniya Das u32 volt; 1422849dd8bSTaniya Das struct cpufreq_frequency_table *table; 14351c843cfSSibi Sankar struct dev_pm_opp *opp; 14451c843cfSSibi Sankar unsigned long rate; 14551c843cfSSibi Sankar int ret; 146dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *drv_data = policy->driver_data; 147dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data; 1482849dd8bSTaniya Das 1492849dd8bSTaniya Das table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); 1502849dd8bSTaniya Das if (!table) 1512849dd8bSTaniya Das return -ENOMEM; 1522849dd8bSTaniya Das 15351c843cfSSibi Sankar ret = dev_pm_opp_of_add_table(cpu_dev); 15451c843cfSSibi Sankar if (!ret) { 15551c843cfSSibi Sankar /* Disable all opps and cross-validate against LUT later */ 15651c843cfSSibi Sankar icc_scaling_enabled = true; 15751c843cfSSibi Sankar for (rate = 0; ; rate++) { 15851c843cfSSibi Sankar opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); 15951c843cfSSibi Sankar if (IS_ERR(opp)) 16051c843cfSSibi Sankar break; 16151c843cfSSibi Sankar 16251c843cfSSibi Sankar dev_pm_opp_put(opp); 16351c843cfSSibi Sankar dev_pm_opp_disable(cpu_dev, rate); 16451c843cfSSibi Sankar } 16551c843cfSSibi Sankar } else if (ret != -ENODEV) { 16651c843cfSSibi Sankar dev_err(cpu_dev, "Invalid opp table in device tree\n"); 16751c843cfSSibi Sankar return ret; 16851c843cfSSibi Sankar } else { 169afdb219bSSibi Sankar policy->fast_switch_possible = true; 17051c843cfSSibi Sankar icc_scaling_enabled = false; 17151c843cfSSibi Sankar } 17251c843cfSSibi Sankar 1732849dd8bSTaniya Das for (i = 0; i < LUT_MAX_ENTRIES; i++) { 174dcd1fd72SManivannan Sadhasivam data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + 175dcd1fd72SManivannan Sadhasivam i * soc_data->lut_row_size); 1762849dd8bSTaniya Das src = FIELD_GET(LUT_SRC, data); 1772849dd8bSTaniya Das lval = FIELD_GET(LUT_L_VAL, data); 1782849dd8bSTaniya Das core_count = FIELD_GET(LUT_CORE_COUNT, data); 1792849dd8bSTaniya Das 180dcd1fd72SManivannan Sadhasivam data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + 181dcd1fd72SManivannan Sadhasivam i * soc_data->lut_row_size); 18255538fbcSTaniya Das volt = FIELD_GET(LUT_VOLT, data) * 1000; 18355538fbcSTaniya Das 1842849dd8bSTaniya Das if (src) 1852849dd8bSTaniya Das freq = xo_rate * lval / 1000; 1862849dd8bSTaniya Das else 1872849dd8bSTaniya Das freq = cpu_hw_rate / 1000; 1882849dd8bSTaniya Das 1890eae1e37SSibi Sankar if (freq != prev_freq && core_count != LUT_TURBO_IND) { 1902849dd8bSTaniya Das table[i].frequency = freq; 19151c843cfSSibi Sankar qcom_cpufreq_update_opp(cpu_dev, freq, volt); 19255538fbcSTaniya Das dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, 1932849dd8bSTaniya Das freq, core_count); 1940eae1e37SSibi Sankar } else if (core_count == LUT_TURBO_IND) { 19555538fbcSTaniya Das table[i].frequency = CPUFREQ_ENTRY_INVALID; 1962849dd8bSTaniya Das } 1972849dd8bSTaniya Das 1982849dd8bSTaniya Das /* 1992849dd8bSTaniya Das * Two of the same frequencies with the same core counts means 2002849dd8bSTaniya Das * end of table 2012849dd8bSTaniya Das */ 2020eae1e37SSibi Sankar if (i > 0 && prev_freq == freq) { 2032849dd8bSTaniya Das struct cpufreq_frequency_table *prev = &table[i - 1]; 2042849dd8bSTaniya Das 2052849dd8bSTaniya Das /* 2062849dd8bSTaniya Das * Only treat the last frequency that might be a boost 2072849dd8bSTaniya Das * as the boost frequency 2082849dd8bSTaniya Das */ 2090eae1e37SSibi Sankar if (prev->frequency == CPUFREQ_ENTRY_INVALID) { 2102849dd8bSTaniya Das prev->frequency = prev_freq; 2112849dd8bSTaniya Das prev->flags = CPUFREQ_BOOST_FREQ; 21251c843cfSSibi Sankar qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt); 2132849dd8bSTaniya Das } 2142849dd8bSTaniya Das 2152849dd8bSTaniya Das break; 2162849dd8bSTaniya Das } 2172849dd8bSTaniya Das 2182849dd8bSTaniya Das prev_freq = freq; 2192849dd8bSTaniya Das } 2202849dd8bSTaniya Das 2212849dd8bSTaniya Das table[i].frequency = CPUFREQ_TABLE_END; 2222849dd8bSTaniya Das policy->freq_table = table; 22355538fbcSTaniya Das dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); 2242849dd8bSTaniya Das 2252849dd8bSTaniya Das return 0; 2262849dd8bSTaniya Das } 2272849dd8bSTaniya Das 2282849dd8bSTaniya Das static void qcom_get_related_cpus(int index, struct cpumask *m) 2292849dd8bSTaniya Das { 2302849dd8bSTaniya Das struct device_node *cpu_np; 2312849dd8bSTaniya Das struct of_phandle_args args; 2322849dd8bSTaniya Das int cpu, ret; 2332849dd8bSTaniya Das 2342849dd8bSTaniya Das for_each_possible_cpu(cpu) { 2352849dd8bSTaniya Das cpu_np = of_cpu_device_node_get(cpu); 2362849dd8bSTaniya Das if (!cpu_np) 2372849dd8bSTaniya Das continue; 2382849dd8bSTaniya Das 2392849dd8bSTaniya Das ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 2402849dd8bSTaniya Das "#freq-domain-cells", 0, 2412849dd8bSTaniya Das &args); 2422849dd8bSTaniya Das of_node_put(cpu_np); 2432849dd8bSTaniya Das if (ret < 0) 2442849dd8bSTaniya Das continue; 2452849dd8bSTaniya Das 2462849dd8bSTaniya Das if (index == args.args[0]) 2472849dd8bSTaniya Das cpumask_set_cpu(cpu, m); 2482849dd8bSTaniya Das } 2492849dd8bSTaniya Das } 2502849dd8bSTaniya Das 251dcd1fd72SManivannan Sadhasivam static const struct qcom_cpufreq_soc_data qcom_soc_data = { 252dcd1fd72SManivannan Sadhasivam .reg_enable = 0x0, 253dcd1fd72SManivannan Sadhasivam .reg_freq_lut = 0x110, 254dcd1fd72SManivannan Sadhasivam .reg_volt_lut = 0x114, 255dcd1fd72SManivannan Sadhasivam .reg_perf_state = 0x920, 256dcd1fd72SManivannan Sadhasivam .lut_row_size = 32, 257dcd1fd72SManivannan Sadhasivam }; 258dcd1fd72SManivannan Sadhasivam 259dcd1fd72SManivannan Sadhasivam static const struct of_device_id qcom_cpufreq_hw_match[] = { 260dcd1fd72SManivannan Sadhasivam { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, 261dcd1fd72SManivannan Sadhasivam {} 262dcd1fd72SManivannan Sadhasivam }; 263dcd1fd72SManivannan Sadhasivam MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); 264dcd1fd72SManivannan Sadhasivam 2652849dd8bSTaniya Das static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) 2662849dd8bSTaniya Das { 267bd74e286SManivannan Sadhasivam struct platform_device *pdev = cpufreq_get_driver_data(); 268bd74e286SManivannan Sadhasivam struct device *dev = &pdev->dev; 2692849dd8bSTaniya Das struct of_phandle_args args; 2702849dd8bSTaniya Das struct device_node *cpu_np; 27155538fbcSTaniya Das struct device *cpu_dev; 2722849dd8bSTaniya Das void __iomem *base; 273dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data; 2742849dd8bSTaniya Das int ret, index; 2752849dd8bSTaniya Das 27655538fbcSTaniya Das cpu_dev = get_cpu_device(policy->cpu); 27755538fbcSTaniya Das if (!cpu_dev) { 27855538fbcSTaniya Das pr_err("%s: failed to get cpu%d device\n", __func__, 27955538fbcSTaniya Das policy->cpu); 28055538fbcSTaniya Das return -ENODEV; 28155538fbcSTaniya Das } 28255538fbcSTaniya Das 2832849dd8bSTaniya Das cpu_np = of_cpu_device_node_get(policy->cpu); 2842849dd8bSTaniya Das if (!cpu_np) 2852849dd8bSTaniya Das return -EINVAL; 2862849dd8bSTaniya Das 2872849dd8bSTaniya Das ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 2882849dd8bSTaniya Das "#freq-domain-cells", 0, &args); 2892849dd8bSTaniya Das of_node_put(cpu_np); 2902849dd8bSTaniya Das if (ret) 2912849dd8bSTaniya Das return ret; 2922849dd8bSTaniya Das 2932849dd8bSTaniya Das index = args.args[0]; 2942849dd8bSTaniya Das 295f17b3e44SManivannan Sadhasivam base = devm_platform_ioremap_resource(pdev, index); 296f17b3e44SManivannan Sadhasivam if (IS_ERR(base)) 297f17b3e44SManivannan Sadhasivam return PTR_ERR(base); 2982849dd8bSTaniya Das 299dcd1fd72SManivannan Sadhasivam data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 300dcd1fd72SManivannan Sadhasivam if (!data) { 301dcd1fd72SManivannan Sadhasivam ret = -ENOMEM; 302dcd1fd72SManivannan Sadhasivam goto error; 303dcd1fd72SManivannan Sadhasivam } 304dcd1fd72SManivannan Sadhasivam 305dcd1fd72SManivannan Sadhasivam data->soc_data = of_device_get_match_data(&pdev->dev); 306dcd1fd72SManivannan Sadhasivam data->base = base; 307dcd1fd72SManivannan Sadhasivam 3082849dd8bSTaniya Das /* HW should be in enabled state to proceed */ 309dcd1fd72SManivannan Sadhasivam if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { 3102849dd8bSTaniya Das dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); 3112849dd8bSTaniya Das ret = -ENODEV; 3122849dd8bSTaniya Das goto error; 3132849dd8bSTaniya Das } 3142849dd8bSTaniya Das 3152849dd8bSTaniya Das qcom_get_related_cpus(index, policy->cpus); 3162849dd8bSTaniya Das if (!cpumask_weight(policy->cpus)) { 3172849dd8bSTaniya Das dev_err(dev, "Domain-%d failed to get related CPUs\n", index); 3182849dd8bSTaniya Das ret = -ENOENT; 3192849dd8bSTaniya Das goto error; 3202849dd8bSTaniya Das } 3212849dd8bSTaniya Das 322dcd1fd72SManivannan Sadhasivam policy->driver_data = data; 3232849dd8bSTaniya Das 324dcd1fd72SManivannan Sadhasivam ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); 3252849dd8bSTaniya Das if (ret) { 3262849dd8bSTaniya Das dev_err(dev, "Domain-%d failed to read LUT\n", index); 3272849dd8bSTaniya Das goto error; 3282849dd8bSTaniya Das } 3292849dd8bSTaniya Das 33055538fbcSTaniya Das ret = dev_pm_opp_get_opp_count(cpu_dev); 33155538fbcSTaniya Das if (ret <= 0) { 33255538fbcSTaniya Das dev_err(cpu_dev, "Failed to add OPPs\n"); 33355538fbcSTaniya Das ret = -ENODEV; 33455538fbcSTaniya Das goto error; 33555538fbcSTaniya Das } 33655538fbcSTaniya Das 3370e0ffa85SLukasz Luba dev_pm_opp_of_register_em(cpu_dev, policy->cpus); 338dab53505SMatthias Kaehlcke 3392849dd8bSTaniya Das return 0; 3402849dd8bSTaniya Das error: 3412849dd8bSTaniya Das devm_iounmap(dev, base); 3422849dd8bSTaniya Das return ret; 3432849dd8bSTaniya Das } 3442849dd8bSTaniya Das 3452849dd8bSTaniya Das static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) 3462849dd8bSTaniya Das { 34755538fbcSTaniya Das struct device *cpu_dev = get_cpu_device(policy->cpu); 348dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data = policy->driver_data; 349bd74e286SManivannan Sadhasivam struct platform_device *pdev = cpufreq_get_driver_data(); 3502849dd8bSTaniya Das 35155538fbcSTaniya Das dev_pm_opp_remove_all_dynamic(cpu_dev); 35251c843cfSSibi Sankar dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); 3532849dd8bSTaniya Das kfree(policy->freq_table); 354dcd1fd72SManivannan Sadhasivam devm_iounmap(&pdev->dev, data->base); 3552849dd8bSTaniya Das 3562849dd8bSTaniya Das return 0; 3572849dd8bSTaniya Das } 3582849dd8bSTaniya Das 3592849dd8bSTaniya Das static struct freq_attr *qcom_cpufreq_hw_attr[] = { 3602849dd8bSTaniya Das &cpufreq_freq_attr_scaling_available_freqs, 3612849dd8bSTaniya Das &cpufreq_freq_attr_scaling_boost_freqs, 3622849dd8bSTaniya Das NULL 3632849dd8bSTaniya Das }; 3642849dd8bSTaniya Das 3652849dd8bSTaniya Das static struct cpufreq_driver cpufreq_qcom_hw_driver = { 3662849dd8bSTaniya Das .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | 3674c5ff1c8SAmit Kucheria CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 3684c5ff1c8SAmit Kucheria CPUFREQ_IS_COOLING_DEV, 3692849dd8bSTaniya Das .verify = cpufreq_generic_frequency_table_verify, 3702849dd8bSTaniya Das .target_index = qcom_cpufreq_hw_target_index, 3712849dd8bSTaniya Das .get = qcom_cpufreq_hw_get, 3722849dd8bSTaniya Das .init = qcom_cpufreq_hw_cpu_init, 3732849dd8bSTaniya Das .exit = qcom_cpufreq_hw_cpu_exit, 3742849dd8bSTaniya Das .fast_switch = qcom_cpufreq_hw_fast_switch, 3752849dd8bSTaniya Das .name = "qcom-cpufreq-hw", 3762849dd8bSTaniya Das .attr = qcom_cpufreq_hw_attr, 3772849dd8bSTaniya Das }; 3782849dd8bSTaniya Das 3792849dd8bSTaniya Das static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) 3802849dd8bSTaniya Das { 38151c843cfSSibi Sankar struct device *cpu_dev; 3822849dd8bSTaniya Das struct clk *clk; 3832849dd8bSTaniya Das int ret; 3842849dd8bSTaniya Das 3852849dd8bSTaniya Das clk = clk_get(&pdev->dev, "xo"); 3862849dd8bSTaniya Das if (IS_ERR(clk)) 3872849dd8bSTaniya Das return PTR_ERR(clk); 3882849dd8bSTaniya Das 3892849dd8bSTaniya Das xo_rate = clk_get_rate(clk); 3902849dd8bSTaniya Das clk_put(clk); 3912849dd8bSTaniya Das 3922849dd8bSTaniya Das clk = clk_get(&pdev->dev, "alternate"); 3932849dd8bSTaniya Das if (IS_ERR(clk)) 3942849dd8bSTaniya Das return PTR_ERR(clk); 3952849dd8bSTaniya Das 3962849dd8bSTaniya Das cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; 3972849dd8bSTaniya Das clk_put(clk); 3982849dd8bSTaniya Das 399bd74e286SManivannan Sadhasivam cpufreq_qcom_hw_driver.driver_data = pdev; 4002849dd8bSTaniya Das 40151c843cfSSibi Sankar /* Check for optional interconnect paths on CPU0 */ 40251c843cfSSibi Sankar cpu_dev = get_cpu_device(0); 40351c843cfSSibi Sankar if (!cpu_dev) 40451c843cfSSibi Sankar return -EPROBE_DEFER; 40551c843cfSSibi Sankar 40651c843cfSSibi Sankar ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); 40751c843cfSSibi Sankar if (ret) 40851c843cfSSibi Sankar return ret; 40951c843cfSSibi Sankar 4102849dd8bSTaniya Das ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); 4112849dd8bSTaniya Das if (ret) 4122849dd8bSTaniya Das dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); 4132849dd8bSTaniya Das else 4142849dd8bSTaniya Das dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); 4152849dd8bSTaniya Das 4162849dd8bSTaniya Das return ret; 4172849dd8bSTaniya Das } 4182849dd8bSTaniya Das 4192849dd8bSTaniya Das static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) 4202849dd8bSTaniya Das { 4212849dd8bSTaniya Das return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); 4222849dd8bSTaniya Das } 4232849dd8bSTaniya Das 4242849dd8bSTaniya Das static struct platform_driver qcom_cpufreq_hw_driver = { 4252849dd8bSTaniya Das .probe = qcom_cpufreq_hw_driver_probe, 4262849dd8bSTaniya Das .remove = qcom_cpufreq_hw_driver_remove, 4272849dd8bSTaniya Das .driver = { 4282849dd8bSTaniya Das .name = "qcom-cpufreq-hw", 4292849dd8bSTaniya Das .of_match_table = qcom_cpufreq_hw_match, 4302849dd8bSTaniya Das }, 4312849dd8bSTaniya Das }; 4322849dd8bSTaniya Das 4332849dd8bSTaniya Das static int __init qcom_cpufreq_hw_init(void) 4342849dd8bSTaniya Das { 4352849dd8bSTaniya Das return platform_driver_register(&qcom_cpufreq_hw_driver); 4362849dd8bSTaniya Das } 43711ff4bddSAmit Kucheria postcore_initcall(qcom_cpufreq_hw_init); 4382849dd8bSTaniya Das 4392849dd8bSTaniya Das static void __exit qcom_cpufreq_hw_exit(void) 4402849dd8bSTaniya Das { 4412849dd8bSTaniya Das platform_driver_unregister(&qcom_cpufreq_hw_driver); 4422849dd8bSTaniya Das } 4432849dd8bSTaniya Das module_exit(qcom_cpufreq_hw_exit); 4442849dd8bSTaniya Das 4452849dd8bSTaniya Das MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver"); 4462849dd8bSTaniya Das MODULE_LICENSE("GPL v2"); 447