12849dd8bSTaniya Das // SPDX-License-Identifier: GPL-2.0 22849dd8bSTaniya Das /* 32849dd8bSTaniya Das * Copyright (c) 2018, The Linux Foundation. All rights reserved. 42849dd8bSTaniya Das */ 52849dd8bSTaniya Das 62849dd8bSTaniya Das #include <linux/bitfield.h> 72849dd8bSTaniya Das #include <linux/cpufreq.h> 82849dd8bSTaniya Das #include <linux/init.h> 951c843cfSSibi Sankar #include <linux/interconnect.h> 102849dd8bSTaniya Das #include <linux/kernel.h> 112849dd8bSTaniya Das #include <linux/module.h> 122849dd8bSTaniya Das #include <linux/of_address.h> 132849dd8bSTaniya Das #include <linux/of_platform.h> 1455538fbcSTaniya Das #include <linux/pm_opp.h> 152849dd8bSTaniya Das #include <linux/slab.h> 162849dd8bSTaniya Das 172849dd8bSTaniya Das #define LUT_MAX_ENTRIES 40U 182849dd8bSTaniya Das #define LUT_SRC GENMASK(31, 30) 192849dd8bSTaniya Das #define LUT_L_VAL GENMASK(7, 0) 202849dd8bSTaniya Das #define LUT_CORE_COUNT GENMASK(18, 16) 2155538fbcSTaniya Das #define LUT_VOLT GENMASK(11, 0) 222849dd8bSTaniya Das #define CLK_HW_DIV 2 230eae1e37SSibi Sankar #define LUT_TURBO_IND 1 242849dd8bSTaniya Das 25dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_soc_data { 26dcd1fd72SManivannan Sadhasivam u32 reg_enable; 27dcd1fd72SManivannan Sadhasivam u32 reg_freq_lut; 28dcd1fd72SManivannan Sadhasivam u32 reg_volt_lut; 29dcd1fd72SManivannan Sadhasivam u32 reg_perf_state; 30dcd1fd72SManivannan Sadhasivam u8 lut_row_size; 31dcd1fd72SManivannan Sadhasivam }; 32dcd1fd72SManivannan Sadhasivam 33dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data { 34dcd1fd72SManivannan Sadhasivam void __iomem *base; 3567fc209bSShawn Guo struct resource *res; 36dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data; 37dcd1fd72SManivannan Sadhasivam }; 382849dd8bSTaniya Das 392849dd8bSTaniya Das static unsigned long cpu_hw_rate, xo_rate; 4051c843cfSSibi Sankar static bool icc_scaling_enabled; 4151c843cfSSibi Sankar 4251c843cfSSibi Sankar static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, 4351c843cfSSibi Sankar unsigned long freq_khz) 4451c843cfSSibi Sankar { 4551c843cfSSibi Sankar unsigned long freq_hz = freq_khz * 1000; 4651c843cfSSibi Sankar struct dev_pm_opp *opp; 4751c843cfSSibi Sankar struct device *dev; 4851c843cfSSibi Sankar int ret; 4951c843cfSSibi Sankar 5051c843cfSSibi Sankar dev = get_cpu_device(policy->cpu); 5151c843cfSSibi Sankar if (!dev) 5251c843cfSSibi Sankar return -ENODEV; 5351c843cfSSibi Sankar 5451c843cfSSibi Sankar opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); 5551c843cfSSibi Sankar if (IS_ERR(opp)) 5651c843cfSSibi Sankar return PTR_ERR(opp); 5751c843cfSSibi Sankar 588d25157fSViresh Kumar ret = dev_pm_opp_set_opp(dev, opp); 5951c843cfSSibi Sankar dev_pm_opp_put(opp); 6051c843cfSSibi Sankar return ret; 6151c843cfSSibi Sankar } 6251c843cfSSibi Sankar 6351c843cfSSibi Sankar static int qcom_cpufreq_update_opp(struct device *cpu_dev, 6451c843cfSSibi Sankar unsigned long freq_khz, 6551c843cfSSibi Sankar unsigned long volt) 6651c843cfSSibi Sankar { 6751c843cfSSibi Sankar unsigned long freq_hz = freq_khz * 1000; 6851c843cfSSibi Sankar int ret; 6951c843cfSSibi Sankar 7051c843cfSSibi Sankar /* Skip voltage update if the opp table is not available */ 7151c843cfSSibi Sankar if (!icc_scaling_enabled) 7251c843cfSSibi Sankar return dev_pm_opp_add(cpu_dev, freq_hz, volt); 7351c843cfSSibi Sankar 7451c843cfSSibi Sankar ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt); 7551c843cfSSibi Sankar if (ret) { 7651c843cfSSibi Sankar dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz); 7751c843cfSSibi Sankar return ret; 7851c843cfSSibi Sankar } 7951c843cfSSibi Sankar 8051c843cfSSibi Sankar return dev_pm_opp_enable(cpu_dev, freq_hz); 8151c843cfSSibi Sankar } 822849dd8bSTaniya Das 832849dd8bSTaniya Das static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, 842849dd8bSTaniya Das unsigned int index) 852849dd8bSTaniya Das { 86dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data = policy->driver_data; 87dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; 88ada54f35SDouglas RAILLARD unsigned long freq = policy->freq_table[index].frequency; 892849dd8bSTaniya Das 90dcd1fd72SManivannan Sadhasivam writel_relaxed(index, data->base + soc_data->reg_perf_state); 912849dd8bSTaniya Das 9251c843cfSSibi Sankar if (icc_scaling_enabled) 9351c843cfSSibi Sankar qcom_cpufreq_set_bw(policy, freq); 9451c843cfSSibi Sankar 952849dd8bSTaniya Das return 0; 962849dd8bSTaniya Das } 972849dd8bSTaniya Das 982849dd8bSTaniya Das static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) 992849dd8bSTaniya Das { 100dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data; 101dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data; 1022849dd8bSTaniya Das struct cpufreq_policy *policy; 1032849dd8bSTaniya Das unsigned int index; 1042849dd8bSTaniya Das 1052849dd8bSTaniya Das policy = cpufreq_cpu_get_raw(cpu); 1062849dd8bSTaniya Das if (!policy) 1072849dd8bSTaniya Das return 0; 1082849dd8bSTaniya Das 109dcd1fd72SManivannan Sadhasivam data = policy->driver_data; 110dcd1fd72SManivannan Sadhasivam soc_data = data->soc_data; 1112849dd8bSTaniya Das 112dcd1fd72SManivannan Sadhasivam index = readl_relaxed(data->base + soc_data->reg_perf_state); 1132849dd8bSTaniya Das index = min(index, LUT_MAX_ENTRIES - 1); 1142849dd8bSTaniya Das 1152849dd8bSTaniya Das return policy->freq_table[index].frequency; 1162849dd8bSTaniya Das } 1172849dd8bSTaniya Das 1182849dd8bSTaniya Das static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, 1192849dd8bSTaniya Das unsigned int target_freq) 1202849dd8bSTaniya Das { 121dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data = policy->driver_data; 122dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; 123292072c3SViresh Kumar unsigned int index; 1242849dd8bSTaniya Das 1252849dd8bSTaniya Das index = policy->cached_resolved_idx; 126dcd1fd72SManivannan Sadhasivam writel_relaxed(index, data->base + soc_data->reg_perf_state); 1272849dd8bSTaniya Das 1281a0419b0SIonela Voinescu return policy->freq_table[index].frequency; 1292849dd8bSTaniya Das } 1302849dd8bSTaniya Das 13155538fbcSTaniya Das static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, 132dcd1fd72SManivannan Sadhasivam struct cpufreq_policy *policy) 1332849dd8bSTaniya Das { 1340eae1e37SSibi Sankar u32 data, src, lval, i, core_count, prev_freq = 0, freq; 13555538fbcSTaniya Das u32 volt; 1362849dd8bSTaniya Das struct cpufreq_frequency_table *table; 13751c843cfSSibi Sankar struct dev_pm_opp *opp; 13851c843cfSSibi Sankar unsigned long rate; 13951c843cfSSibi Sankar int ret; 140dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *drv_data = policy->driver_data; 141dcd1fd72SManivannan Sadhasivam const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data; 1422849dd8bSTaniya Das 1432849dd8bSTaniya Das table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); 1442849dd8bSTaniya Das if (!table) 1452849dd8bSTaniya Das return -ENOMEM; 1462849dd8bSTaniya Das 14751c843cfSSibi Sankar ret = dev_pm_opp_of_add_table(cpu_dev); 14851c843cfSSibi Sankar if (!ret) { 14951c843cfSSibi Sankar /* Disable all opps and cross-validate against LUT later */ 15051c843cfSSibi Sankar icc_scaling_enabled = true; 15151c843cfSSibi Sankar for (rate = 0; ; rate++) { 15251c843cfSSibi Sankar opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); 15351c843cfSSibi Sankar if (IS_ERR(opp)) 15451c843cfSSibi Sankar break; 15551c843cfSSibi Sankar 15651c843cfSSibi Sankar dev_pm_opp_put(opp); 15751c843cfSSibi Sankar dev_pm_opp_disable(cpu_dev, rate); 15851c843cfSSibi Sankar } 15951c843cfSSibi Sankar } else if (ret != -ENODEV) { 16051c843cfSSibi Sankar dev_err(cpu_dev, "Invalid opp table in device tree\n"); 16151c843cfSSibi Sankar return ret; 16251c843cfSSibi Sankar } else { 163afdb219bSSibi Sankar policy->fast_switch_possible = true; 16451c843cfSSibi Sankar icc_scaling_enabled = false; 16551c843cfSSibi Sankar } 16651c843cfSSibi Sankar 1672849dd8bSTaniya Das for (i = 0; i < LUT_MAX_ENTRIES; i++) { 168dcd1fd72SManivannan Sadhasivam data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + 169dcd1fd72SManivannan Sadhasivam i * soc_data->lut_row_size); 1702849dd8bSTaniya Das src = FIELD_GET(LUT_SRC, data); 1712849dd8bSTaniya Das lval = FIELD_GET(LUT_L_VAL, data); 1722849dd8bSTaniya Das core_count = FIELD_GET(LUT_CORE_COUNT, data); 1732849dd8bSTaniya Das 174dcd1fd72SManivannan Sadhasivam data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + 175dcd1fd72SManivannan Sadhasivam i * soc_data->lut_row_size); 17655538fbcSTaniya Das volt = FIELD_GET(LUT_VOLT, data) * 1000; 17755538fbcSTaniya Das 1782849dd8bSTaniya Das if (src) 1792849dd8bSTaniya Das freq = xo_rate * lval / 1000; 1802849dd8bSTaniya Das else 1812849dd8bSTaniya Das freq = cpu_hw_rate / 1000; 1822849dd8bSTaniya Das 1830eae1e37SSibi Sankar if (freq != prev_freq && core_count != LUT_TURBO_IND) { 184bc9b9c5aSMatthias Kaehlcke if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) { 1852849dd8bSTaniya Das table[i].frequency = freq; 18655538fbcSTaniya Das dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, 1872849dd8bSTaniya Das freq, core_count); 188bc9b9c5aSMatthias Kaehlcke } else { 189bc9b9c5aSMatthias Kaehlcke dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq); 190bc9b9c5aSMatthias Kaehlcke table[i].frequency = CPUFREQ_ENTRY_INVALID; 191bc9b9c5aSMatthias Kaehlcke } 192bc9b9c5aSMatthias Kaehlcke 1930eae1e37SSibi Sankar } else if (core_count == LUT_TURBO_IND) { 19455538fbcSTaniya Das table[i].frequency = CPUFREQ_ENTRY_INVALID; 1952849dd8bSTaniya Das } 1962849dd8bSTaniya Das 1972849dd8bSTaniya Das /* 1982849dd8bSTaniya Das * Two of the same frequencies with the same core counts means 1992849dd8bSTaniya Das * end of table 2002849dd8bSTaniya Das */ 2010eae1e37SSibi Sankar if (i > 0 && prev_freq == freq) { 2022849dd8bSTaniya Das struct cpufreq_frequency_table *prev = &table[i - 1]; 2032849dd8bSTaniya Das 2042849dd8bSTaniya Das /* 2052849dd8bSTaniya Das * Only treat the last frequency that might be a boost 2062849dd8bSTaniya Das * as the boost frequency 2072849dd8bSTaniya Das */ 2080eae1e37SSibi Sankar if (prev->frequency == CPUFREQ_ENTRY_INVALID) { 209bc9b9c5aSMatthias Kaehlcke if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) { 2102849dd8bSTaniya Das prev->frequency = prev_freq; 2112849dd8bSTaniya Das prev->flags = CPUFREQ_BOOST_FREQ; 212bc9b9c5aSMatthias Kaehlcke } else { 213bc9b9c5aSMatthias Kaehlcke dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", 214bc9b9c5aSMatthias Kaehlcke freq); 215bc9b9c5aSMatthias Kaehlcke } 2162849dd8bSTaniya Das } 2172849dd8bSTaniya Das 2182849dd8bSTaniya Das break; 2192849dd8bSTaniya Das } 2202849dd8bSTaniya Das 2212849dd8bSTaniya Das prev_freq = freq; 2222849dd8bSTaniya Das } 2232849dd8bSTaniya Das 2242849dd8bSTaniya Das table[i].frequency = CPUFREQ_TABLE_END; 2252849dd8bSTaniya Das policy->freq_table = table; 22655538fbcSTaniya Das dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); 2272849dd8bSTaniya Das 2282849dd8bSTaniya Das return 0; 2292849dd8bSTaniya Das } 2302849dd8bSTaniya Das 2312849dd8bSTaniya Das static void qcom_get_related_cpus(int index, struct cpumask *m) 2322849dd8bSTaniya Das { 2332849dd8bSTaniya Das struct device_node *cpu_np; 2342849dd8bSTaniya Das struct of_phandle_args args; 2352849dd8bSTaniya Das int cpu, ret; 2362849dd8bSTaniya Das 2372849dd8bSTaniya Das for_each_possible_cpu(cpu) { 2382849dd8bSTaniya Das cpu_np = of_cpu_device_node_get(cpu); 2392849dd8bSTaniya Das if (!cpu_np) 2402849dd8bSTaniya Das continue; 2412849dd8bSTaniya Das 2422849dd8bSTaniya Das ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 2432849dd8bSTaniya Das "#freq-domain-cells", 0, 2442849dd8bSTaniya Das &args); 2452849dd8bSTaniya Das of_node_put(cpu_np); 2462849dd8bSTaniya Das if (ret < 0) 2472849dd8bSTaniya Das continue; 2482849dd8bSTaniya Das 2492849dd8bSTaniya Das if (index == args.args[0]) 2502849dd8bSTaniya Das cpumask_set_cpu(cpu, m); 2512849dd8bSTaniya Das } 2522849dd8bSTaniya Das } 2532849dd8bSTaniya Das 254dcd1fd72SManivannan Sadhasivam static const struct qcom_cpufreq_soc_data qcom_soc_data = { 255dcd1fd72SManivannan Sadhasivam .reg_enable = 0x0, 256dcd1fd72SManivannan Sadhasivam .reg_freq_lut = 0x110, 257dcd1fd72SManivannan Sadhasivam .reg_volt_lut = 0x114, 258dcd1fd72SManivannan Sadhasivam .reg_perf_state = 0x920, 259dcd1fd72SManivannan Sadhasivam .lut_row_size = 32, 260dcd1fd72SManivannan Sadhasivam }; 261dcd1fd72SManivannan Sadhasivam 26249b59f4cSManivannan Sadhasivam static const struct qcom_cpufreq_soc_data epss_soc_data = { 26349b59f4cSManivannan Sadhasivam .reg_enable = 0x0, 26449b59f4cSManivannan Sadhasivam .reg_freq_lut = 0x100, 26549b59f4cSManivannan Sadhasivam .reg_volt_lut = 0x200, 26649b59f4cSManivannan Sadhasivam .reg_perf_state = 0x320, 26749b59f4cSManivannan Sadhasivam .lut_row_size = 4, 26849b59f4cSManivannan Sadhasivam }; 26949b59f4cSManivannan Sadhasivam 270dcd1fd72SManivannan Sadhasivam static const struct of_device_id qcom_cpufreq_hw_match[] = { 271dcd1fd72SManivannan Sadhasivam { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, 27249b59f4cSManivannan Sadhasivam { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, 273dcd1fd72SManivannan Sadhasivam {} 274dcd1fd72SManivannan Sadhasivam }; 275dcd1fd72SManivannan Sadhasivam MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); 276dcd1fd72SManivannan Sadhasivam 2772849dd8bSTaniya Das static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) 2782849dd8bSTaniya Das { 279bd74e286SManivannan Sadhasivam struct platform_device *pdev = cpufreq_get_driver_data(); 280bd74e286SManivannan Sadhasivam struct device *dev = &pdev->dev; 2812849dd8bSTaniya Das struct of_phandle_args args; 2822849dd8bSTaniya Das struct device_node *cpu_np; 28355538fbcSTaniya Das struct device *cpu_dev; 28467fc209bSShawn Guo struct resource *res; 2852849dd8bSTaniya Das void __iomem *base; 286dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data; 2872849dd8bSTaniya Das int ret, index; 2882849dd8bSTaniya Das 28955538fbcSTaniya Das cpu_dev = get_cpu_device(policy->cpu); 29055538fbcSTaniya Das if (!cpu_dev) { 29155538fbcSTaniya Das pr_err("%s: failed to get cpu%d device\n", __func__, 29255538fbcSTaniya Das policy->cpu); 29355538fbcSTaniya Das return -ENODEV; 29455538fbcSTaniya Das } 29555538fbcSTaniya Das 2962849dd8bSTaniya Das cpu_np = of_cpu_device_node_get(policy->cpu); 2972849dd8bSTaniya Das if (!cpu_np) 2982849dd8bSTaniya Das return -EINVAL; 2992849dd8bSTaniya Das 3002849dd8bSTaniya Das ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain", 3012849dd8bSTaniya Das "#freq-domain-cells", 0, &args); 3022849dd8bSTaniya Das of_node_put(cpu_np); 3032849dd8bSTaniya Das if (ret) 3042849dd8bSTaniya Das return ret; 3052849dd8bSTaniya Das 3062849dd8bSTaniya Das index = args.args[0]; 3072849dd8bSTaniya Das 30867fc209bSShawn Guo res = platform_get_resource(pdev, IORESOURCE_MEM, index); 30967fc209bSShawn Guo if (!res) { 31067fc209bSShawn Guo dev_err(dev, "failed to get mem resource %d\n", index); 31167fc209bSShawn Guo return -ENODEV; 31267fc209bSShawn Guo } 3132849dd8bSTaniya Das 31467fc209bSShawn Guo if (!request_mem_region(res->start, resource_size(res), res->name)) { 31567fc209bSShawn Guo dev_err(dev, "failed to request resource %pR\n", res); 31667fc209bSShawn Guo return -EBUSY; 31767fc209bSShawn Guo } 31867fc209bSShawn Guo 31967fc209bSShawn Guo base = ioremap(res->start, resource_size(res)); 32067fc209bSShawn Guo if (IS_ERR(base)) { 32167fc209bSShawn Guo dev_err(dev, "failed to map resource %pR\n", res); 32267fc209bSShawn Guo ret = PTR_ERR(base); 32367fc209bSShawn Guo goto release_region; 32467fc209bSShawn Guo } 32567fc209bSShawn Guo 32667fc209bSShawn Guo data = kzalloc(sizeof(*data), GFP_KERNEL); 327dcd1fd72SManivannan Sadhasivam if (!data) { 328dcd1fd72SManivannan Sadhasivam ret = -ENOMEM; 32967fc209bSShawn Guo goto unmap_base; 330dcd1fd72SManivannan Sadhasivam } 331dcd1fd72SManivannan Sadhasivam 332dcd1fd72SManivannan Sadhasivam data->soc_data = of_device_get_match_data(&pdev->dev); 333dcd1fd72SManivannan Sadhasivam data->base = base; 33467fc209bSShawn Guo data->res = res; 3352849dd8bSTaniya Das 3362849dd8bSTaniya Das /* HW should be in enabled state to proceed */ 337dcd1fd72SManivannan Sadhasivam if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { 3382849dd8bSTaniya Das dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); 3392849dd8bSTaniya Das ret = -ENODEV; 3402849dd8bSTaniya Das goto error; 3412849dd8bSTaniya Das } 3422849dd8bSTaniya Das 3432849dd8bSTaniya Das qcom_get_related_cpus(index, policy->cpus); 3442849dd8bSTaniya Das if (!cpumask_weight(policy->cpus)) { 3452849dd8bSTaniya Das dev_err(dev, "Domain-%d failed to get related CPUs\n", index); 3462849dd8bSTaniya Das ret = -ENOENT; 3472849dd8bSTaniya Das goto error; 3482849dd8bSTaniya Das } 3492849dd8bSTaniya Das 350dcd1fd72SManivannan Sadhasivam policy->driver_data = data; 3512849dd8bSTaniya Das 352dcd1fd72SManivannan Sadhasivam ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); 3532849dd8bSTaniya Das if (ret) { 3542849dd8bSTaniya Das dev_err(dev, "Domain-%d failed to read LUT\n", index); 3552849dd8bSTaniya Das goto error; 3562849dd8bSTaniya Das } 3572849dd8bSTaniya Das 35855538fbcSTaniya Das ret = dev_pm_opp_get_opp_count(cpu_dev); 35955538fbcSTaniya Das if (ret <= 0) { 36055538fbcSTaniya Das dev_err(cpu_dev, "Failed to add OPPs\n"); 36155538fbcSTaniya Das ret = -ENODEV; 36255538fbcSTaniya Das goto error; 36355538fbcSTaniya Das } 36455538fbcSTaniya Das 3650e0ffa85SLukasz Luba dev_pm_opp_of_register_em(cpu_dev, policy->cpus); 366dab53505SMatthias Kaehlcke 36726699172SShawn Guo if (policy_has_boost_freq(policy)) { 36826699172SShawn Guo ret = cpufreq_enable_boost_support(); 36926699172SShawn Guo if (ret) 37026699172SShawn Guo dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); 37126699172SShawn Guo } 37226699172SShawn Guo 3732849dd8bSTaniya Das return 0; 3742849dd8bSTaniya Das error: 37567fc209bSShawn Guo kfree(data); 37667fc209bSShawn Guo unmap_base: 377*02fc4095SShawn Guo iounmap(base); 37867fc209bSShawn Guo release_region: 37967fc209bSShawn Guo release_mem_region(res->start, resource_size(res)); 3802849dd8bSTaniya Das return ret; 3812849dd8bSTaniya Das } 3822849dd8bSTaniya Das 3832849dd8bSTaniya Das static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) 3842849dd8bSTaniya Das { 38555538fbcSTaniya Das struct device *cpu_dev = get_cpu_device(policy->cpu); 386dcd1fd72SManivannan Sadhasivam struct qcom_cpufreq_data *data = policy->driver_data; 38767fc209bSShawn Guo struct resource *res = data->res; 38867fc209bSShawn Guo void __iomem *base = data->base; 3892849dd8bSTaniya Das 39055538fbcSTaniya Das dev_pm_opp_remove_all_dynamic(cpu_dev); 39151c843cfSSibi Sankar dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); 3922849dd8bSTaniya Das kfree(policy->freq_table); 39367fc209bSShawn Guo kfree(data); 39467fc209bSShawn Guo iounmap(base); 39567fc209bSShawn Guo release_mem_region(res->start, resource_size(res)); 3962849dd8bSTaniya Das 3972849dd8bSTaniya Das return 0; 3982849dd8bSTaniya Das } 3992849dd8bSTaniya Das 4002849dd8bSTaniya Das static struct freq_attr *qcom_cpufreq_hw_attr[] = { 4012849dd8bSTaniya Das &cpufreq_freq_attr_scaling_available_freqs, 4022849dd8bSTaniya Das &cpufreq_freq_attr_scaling_boost_freqs, 4032849dd8bSTaniya Das NULL 4042849dd8bSTaniya Das }; 4052849dd8bSTaniya Das 4062849dd8bSTaniya Das static struct cpufreq_driver cpufreq_qcom_hw_driver = { 4075ae4a4b4SViresh Kumar .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 4084c5ff1c8SAmit Kucheria CPUFREQ_HAVE_GOVERNOR_PER_POLICY | 4094c5ff1c8SAmit Kucheria CPUFREQ_IS_COOLING_DEV, 4102849dd8bSTaniya Das .verify = cpufreq_generic_frequency_table_verify, 4112849dd8bSTaniya Das .target_index = qcom_cpufreq_hw_target_index, 4122849dd8bSTaniya Das .get = qcom_cpufreq_hw_get, 4132849dd8bSTaniya Das .init = qcom_cpufreq_hw_cpu_init, 4142849dd8bSTaniya Das .exit = qcom_cpufreq_hw_cpu_exit, 4152849dd8bSTaniya Das .fast_switch = qcom_cpufreq_hw_fast_switch, 4162849dd8bSTaniya Das .name = "qcom-cpufreq-hw", 4172849dd8bSTaniya Das .attr = qcom_cpufreq_hw_attr, 4182849dd8bSTaniya Das }; 4192849dd8bSTaniya Das 4202849dd8bSTaniya Das static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) 4212849dd8bSTaniya Das { 42251c843cfSSibi Sankar struct device *cpu_dev; 4232849dd8bSTaniya Das struct clk *clk; 4242849dd8bSTaniya Das int ret; 4252849dd8bSTaniya Das 4262849dd8bSTaniya Das clk = clk_get(&pdev->dev, "xo"); 4272849dd8bSTaniya Das if (IS_ERR(clk)) 4282849dd8bSTaniya Das return PTR_ERR(clk); 4292849dd8bSTaniya Das 4302849dd8bSTaniya Das xo_rate = clk_get_rate(clk); 4312849dd8bSTaniya Das clk_put(clk); 4322849dd8bSTaniya Das 4332849dd8bSTaniya Das clk = clk_get(&pdev->dev, "alternate"); 4342849dd8bSTaniya Das if (IS_ERR(clk)) 4352849dd8bSTaniya Das return PTR_ERR(clk); 4362849dd8bSTaniya Das 4372849dd8bSTaniya Das cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; 4382849dd8bSTaniya Das clk_put(clk); 4392849dd8bSTaniya Das 440bd74e286SManivannan Sadhasivam cpufreq_qcom_hw_driver.driver_data = pdev; 4412849dd8bSTaniya Das 44251c843cfSSibi Sankar /* Check for optional interconnect paths on CPU0 */ 44351c843cfSSibi Sankar cpu_dev = get_cpu_device(0); 44451c843cfSSibi Sankar if (!cpu_dev) 44551c843cfSSibi Sankar return -EPROBE_DEFER; 44651c843cfSSibi Sankar 44751c843cfSSibi Sankar ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); 44851c843cfSSibi Sankar if (ret) 44951c843cfSSibi Sankar return ret; 45051c843cfSSibi Sankar 4512849dd8bSTaniya Das ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); 4522849dd8bSTaniya Das if (ret) 4532849dd8bSTaniya Das dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); 4542849dd8bSTaniya Das else 4552849dd8bSTaniya Das dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); 4562849dd8bSTaniya Das 4572849dd8bSTaniya Das return ret; 4582849dd8bSTaniya Das } 4592849dd8bSTaniya Das 4602849dd8bSTaniya Das static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) 4612849dd8bSTaniya Das { 4622849dd8bSTaniya Das return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); 4632849dd8bSTaniya Das } 4642849dd8bSTaniya Das 4652849dd8bSTaniya Das static struct platform_driver qcom_cpufreq_hw_driver = { 4662849dd8bSTaniya Das .probe = qcom_cpufreq_hw_driver_probe, 4672849dd8bSTaniya Das .remove = qcom_cpufreq_hw_driver_remove, 4682849dd8bSTaniya Das .driver = { 4692849dd8bSTaniya Das .name = "qcom-cpufreq-hw", 4702849dd8bSTaniya Das .of_match_table = qcom_cpufreq_hw_match, 4712849dd8bSTaniya Das }, 4722849dd8bSTaniya Das }; 4732849dd8bSTaniya Das 4742849dd8bSTaniya Das static int __init qcom_cpufreq_hw_init(void) 4752849dd8bSTaniya Das { 4762849dd8bSTaniya Das return platform_driver_register(&qcom_cpufreq_hw_driver); 4772849dd8bSTaniya Das } 47811ff4bddSAmit Kucheria postcore_initcall(qcom_cpufreq_hw_init); 4792849dd8bSTaniya Das 4802849dd8bSTaniya Das static void __exit qcom_cpufreq_hw_exit(void) 4812849dd8bSTaniya Das { 4822849dd8bSTaniya Das platform_driver_unregister(&qcom_cpufreq_hw_driver); 4832849dd8bSTaniya Das } 4842849dd8bSTaniya Das module_exit(qcom_cpufreq_hw_exit); 4852849dd8bSTaniya Das 4862849dd8bSTaniya Das MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver"); 4872849dd8bSTaniya Das MODULE_LICENSE("GPL v2"); 488