1adde904bSViresh Kumar /* 2adde904bSViresh Kumar * Copyright (C) 2008 Marvell International Ltd. 3adde904bSViresh Kumar * 4adde904bSViresh Kumar * This program is free software; you can redistribute it and/or modify 5adde904bSViresh Kumar * it under the terms of the GNU General Public License as published by 6adde904bSViresh Kumar * the Free Software Foundation; either version 2 of the License, or 7adde904bSViresh Kumar * (at your option) any later version. 8adde904bSViresh Kumar */ 9adde904bSViresh Kumar 10adde904bSViresh Kumar #include <linux/kernel.h> 11adde904bSViresh Kumar #include <linux/module.h> 12adde904bSViresh Kumar #include <linux/sched.h> 13adde904bSViresh Kumar #include <linux/init.h> 14adde904bSViresh Kumar #include <linux/cpufreq.h> 15adde904bSViresh Kumar #include <linux/slab.h> 16adde904bSViresh Kumar #include <linux/io.h> 17adde904bSViresh Kumar 18adde904bSViresh Kumar #include <mach/generic.h> 19adde904bSViresh Kumar #include <mach/pxa3xx-regs.h> 20adde904bSViresh Kumar 21adde904bSViresh Kumar #define HSS_104M (0) 22adde904bSViresh Kumar #define HSS_156M (1) 23adde904bSViresh Kumar #define HSS_208M (2) 24adde904bSViresh Kumar #define HSS_312M (3) 25adde904bSViresh Kumar 26adde904bSViresh Kumar #define SMCFS_78M (0) 27adde904bSViresh Kumar #define SMCFS_104M (2) 28adde904bSViresh Kumar #define SMCFS_208M (5) 29adde904bSViresh Kumar 30adde904bSViresh Kumar #define SFLFS_104M (0) 31adde904bSViresh Kumar #define SFLFS_156M (1) 32adde904bSViresh Kumar #define SFLFS_208M (2) 33adde904bSViresh Kumar #define SFLFS_312M (3) 34adde904bSViresh Kumar 35adde904bSViresh Kumar #define XSPCLK_156M (0) 36adde904bSViresh Kumar #define XSPCLK_NONE (3) 37adde904bSViresh Kumar 38adde904bSViresh Kumar #define DMCFS_26M (0) 39adde904bSViresh Kumar #define DMCFS_260M (3) 40adde904bSViresh Kumar 41adde904bSViresh Kumar struct pxa3xx_freq_info { 42adde904bSViresh Kumar unsigned int cpufreq_mhz; 43adde904bSViresh Kumar unsigned int core_xl : 5; 44adde904bSViresh Kumar unsigned int core_xn : 3; 45adde904bSViresh Kumar unsigned int hss : 2; 46adde904bSViresh Kumar unsigned int dmcfs : 2; 47adde904bSViresh Kumar unsigned int smcfs : 3; 48adde904bSViresh Kumar unsigned int sflfs : 2; 49adde904bSViresh Kumar unsigned int df_clkdiv : 3; 50adde904bSViresh Kumar 51adde904bSViresh Kumar int vcc_core; /* in mV */ 52adde904bSViresh Kumar int vcc_sram; /* in mV */ 53adde904bSViresh Kumar }; 54adde904bSViresh Kumar 55adde904bSViresh Kumar #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \ 56adde904bSViresh Kumar { \ 57adde904bSViresh Kumar .cpufreq_mhz = cpufreq, \ 58adde904bSViresh Kumar .core_xl = _xl, \ 59adde904bSViresh Kumar .core_xn = _xn, \ 60adde904bSViresh Kumar .hss = HSS_##_hss##M, \ 61adde904bSViresh Kumar .dmcfs = DMCFS_##_dmc##M, \ 62adde904bSViresh Kumar .smcfs = SMCFS_##_smc##M, \ 63adde904bSViresh Kumar .sflfs = SFLFS_##_sfl##M, \ 64adde904bSViresh Kumar .df_clkdiv = _dfi, \ 65adde904bSViresh Kumar .vcc_core = vcore, \ 66adde904bSViresh Kumar .vcc_sram = vsram, \ 67adde904bSViresh Kumar } 68adde904bSViresh Kumar 69adde904bSViresh Kumar static struct pxa3xx_freq_info pxa300_freqs[] = { 70adde904bSViresh Kumar /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */ 71adde904bSViresh Kumar OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ 72adde904bSViresh Kumar OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ 73adde904bSViresh Kumar OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ 74adde904bSViresh Kumar OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ 75adde904bSViresh Kumar }; 76adde904bSViresh Kumar 77adde904bSViresh Kumar static struct pxa3xx_freq_info pxa320_freqs[] = { 78adde904bSViresh Kumar /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */ 79adde904bSViresh Kumar OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ 80adde904bSViresh Kumar OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ 81adde904bSViresh Kumar OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ 82adde904bSViresh Kumar OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ 83adde904bSViresh Kumar OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */ 84adde904bSViresh Kumar }; 85adde904bSViresh Kumar 86adde904bSViresh Kumar static unsigned int pxa3xx_freqs_num; 87adde904bSViresh Kumar static struct pxa3xx_freq_info *pxa3xx_freqs; 88adde904bSViresh Kumar static struct cpufreq_frequency_table *pxa3xx_freqs_table; 89adde904bSViresh Kumar 90adde904bSViresh Kumar static int setup_freqs_table(struct cpufreq_policy *policy, 91adde904bSViresh Kumar struct pxa3xx_freq_info *freqs, int num) 92adde904bSViresh Kumar { 93adde904bSViresh Kumar struct cpufreq_frequency_table *table; 9415cc921bSViresh Kumar int i; 95adde904bSViresh Kumar 96adde904bSViresh Kumar table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL); 97adde904bSViresh Kumar if (table == NULL) 98adde904bSViresh Kumar return -ENOMEM; 99adde904bSViresh Kumar 100adde904bSViresh Kumar for (i = 0; i < num; i++) { 10150701588SViresh Kumar table[i].driver_data = i; 102adde904bSViresh Kumar table[i].frequency = freqs[i].cpufreq_mhz * 1000; 103adde904bSViresh Kumar } 10450701588SViresh Kumar table[num].driver_data = i; 105adde904bSViresh Kumar table[num].frequency = CPUFREQ_TABLE_END; 106adde904bSViresh Kumar 107adde904bSViresh Kumar pxa3xx_freqs = freqs; 108adde904bSViresh Kumar pxa3xx_freqs_num = num; 109adde904bSViresh Kumar pxa3xx_freqs_table = table; 110adde904bSViresh Kumar 1118ed5a219SViresh Kumar policy->freq_table = table; 1128ed5a219SViresh Kumar 1138ed5a219SViresh Kumar return 0; 114adde904bSViresh Kumar } 115adde904bSViresh Kumar 116adde904bSViresh Kumar static void __update_core_freq(struct pxa3xx_freq_info *info) 117adde904bSViresh Kumar { 118adde904bSViresh Kumar uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK; 119adde904bSViresh Kumar uint32_t accr = ACCR; 120adde904bSViresh Kumar uint32_t xclkcfg; 121adde904bSViresh Kumar 122adde904bSViresh Kumar accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK); 123adde904bSViresh Kumar accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl); 124adde904bSViresh Kumar 125adde904bSViresh Kumar /* No clock until core PLL is re-locked */ 126adde904bSViresh Kumar accr |= ACCR_XSPCLK(XSPCLK_NONE); 127adde904bSViresh Kumar 128adde904bSViresh Kumar xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */ 129adde904bSViresh Kumar 130adde904bSViresh Kumar ACCR = accr; 131adde904bSViresh Kumar __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg)); 132adde904bSViresh Kumar 133adde904bSViresh Kumar while ((ACSR & mask) != (accr & mask)) 134adde904bSViresh Kumar cpu_relax(); 135adde904bSViresh Kumar } 136adde904bSViresh Kumar 137adde904bSViresh Kumar static void __update_bus_freq(struct pxa3xx_freq_info *info) 138adde904bSViresh Kumar { 139adde904bSViresh Kumar uint32_t mask; 140adde904bSViresh Kumar uint32_t accr = ACCR; 141adde904bSViresh Kumar 142adde904bSViresh Kumar mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK | 143adde904bSViresh Kumar ACCR_DMCFS_MASK; 144adde904bSViresh Kumar 145adde904bSViresh Kumar accr &= ~mask; 146adde904bSViresh Kumar accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) | 147adde904bSViresh Kumar ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs); 148adde904bSViresh Kumar 149adde904bSViresh Kumar ACCR = accr; 150adde904bSViresh Kumar 151adde904bSViresh Kumar while ((ACSR & mask) != (accr & mask)) 152adde904bSViresh Kumar cpu_relax(); 153adde904bSViresh Kumar } 154adde904bSViresh Kumar 155adde904bSViresh Kumar static unsigned int pxa3xx_cpufreq_get(unsigned int cpu) 156adde904bSViresh Kumar { 157adde904bSViresh Kumar return pxa3xx_get_clk_frequency_khz(0); 158adde904bSViresh Kumar } 159adde904bSViresh Kumar 1609c0ebcf7SViresh Kumar static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy, unsigned int index) 161adde904bSViresh Kumar { 162adde904bSViresh Kumar struct pxa3xx_freq_info *next; 163adde904bSViresh Kumar unsigned long flags; 164adde904bSViresh Kumar 165adde904bSViresh Kumar if (policy->cpu != 0) 166adde904bSViresh Kumar return -EINVAL; 167adde904bSViresh Kumar 1689c0ebcf7SViresh Kumar next = &pxa3xx_freqs[index]; 169adde904bSViresh Kumar 170adde904bSViresh Kumar local_irq_save(flags); 171adde904bSViresh Kumar __update_core_freq(next); 172adde904bSViresh Kumar __update_bus_freq(next); 173adde904bSViresh Kumar local_irq_restore(flags); 174adde904bSViresh Kumar 175adde904bSViresh Kumar return 0; 176adde904bSViresh Kumar } 177adde904bSViresh Kumar 178adde904bSViresh Kumar static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy) 179adde904bSViresh Kumar { 180adde904bSViresh Kumar int ret = -EINVAL; 181adde904bSViresh Kumar 182adde904bSViresh Kumar /* set default policy and cpuinfo */ 183200ea8e2SViresh Kumar policy->min = policy->cpuinfo.min_freq = 104000; 184200ea8e2SViresh Kumar policy->max = policy->cpuinfo.max_freq = 185200ea8e2SViresh Kumar (cpu_is_pxa320()) ? 806000 : 624000; 186adde904bSViresh Kumar policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ 187adde904bSViresh Kumar 188adde904bSViresh Kumar if (cpu_is_pxa300() || cpu_is_pxa310()) 1898ee3f8e0SJulia Lawall ret = setup_freqs_table(policy, pxa300_freqs, 1908ee3f8e0SJulia Lawall ARRAY_SIZE(pxa300_freqs)); 191adde904bSViresh Kumar 192adde904bSViresh Kumar if (cpu_is_pxa320()) 1938ee3f8e0SJulia Lawall ret = setup_freqs_table(policy, pxa320_freqs, 1948ee3f8e0SJulia Lawall ARRAY_SIZE(pxa320_freqs)); 195adde904bSViresh Kumar 196adde904bSViresh Kumar if (ret) { 197adde904bSViresh Kumar pr_err("failed to setup frequency table\n"); 198adde904bSViresh Kumar return ret; 199adde904bSViresh Kumar } 200adde904bSViresh Kumar 201adde904bSViresh Kumar pr_info("CPUFREQ support for PXA3xx initialized\n"); 202adde904bSViresh Kumar return 0; 203adde904bSViresh Kumar } 204adde904bSViresh Kumar 205adde904bSViresh Kumar static struct cpufreq_driver pxa3xx_cpufreq_driver = { 206ae6b4271SViresh Kumar .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 207bf36e48dSViresh Kumar .verify = cpufreq_generic_frequency_table_verify, 2089c0ebcf7SViresh Kumar .target_index = pxa3xx_cpufreq_set, 209adde904bSViresh Kumar .init = pxa3xx_cpufreq_init, 210adde904bSViresh Kumar .get = pxa3xx_cpufreq_get, 211adde904bSViresh Kumar .name = "pxa3xx-cpufreq", 212adde904bSViresh Kumar }; 213adde904bSViresh Kumar 214adde904bSViresh Kumar static int __init cpufreq_init(void) 215adde904bSViresh Kumar { 216adde904bSViresh Kumar if (cpu_is_pxa3xx()) 217adde904bSViresh Kumar return cpufreq_register_driver(&pxa3xx_cpufreq_driver); 218adde904bSViresh Kumar 219adde904bSViresh Kumar return 0; 220adde904bSViresh Kumar } 221adde904bSViresh Kumar module_init(cpufreq_init); 222adde904bSViresh Kumar 223adde904bSViresh Kumar static void __exit cpufreq_exit(void) 224adde904bSViresh Kumar { 225adde904bSViresh Kumar cpufreq_unregister_driver(&pxa3xx_cpufreq_driver); 226adde904bSViresh Kumar } 227adde904bSViresh Kumar module_exit(cpufreq_exit); 228adde904bSViresh Kumar 229adde904bSViresh Kumar MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx"); 230adde904bSViresh Kumar MODULE_LICENSE("GPL"); 231