1 /* 2 * Copyright (C) 2002,2003 Intrinsyc Software 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 * History: 19 * 31-Jul-2002 : Initial version [FB] 20 * 29-Jan-2003 : added PXA255 support [FB] 21 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.) 22 * 23 * Note: 24 * This driver may change the memory bus clock rate, but will not do any 25 * platform specific access timing changes... for example if you have flash 26 * memory connected to CS0, you will need to register a platform specific 27 * notifier which will adjust the memory access strobes to maintain a 28 * minimum strobe width. 29 * 30 */ 31 32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/sched.h> 37 #include <linux/init.h> 38 #include <linux/cpufreq.h> 39 #include <linux/err.h> 40 #include <linux/regulator/consumer.h> 41 #include <linux/io.h> 42 43 #include <mach/pxa2xx-regs.h> 44 #include <mach/smemc.h> 45 46 #ifdef DEBUG 47 static unsigned int freq_debug; 48 module_param(freq_debug, uint, 0); 49 MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0"); 50 #else 51 #define freq_debug 0 52 #endif 53 54 static struct regulator *vcc_core; 55 56 static unsigned int pxa27x_maxfreq; 57 module_param(pxa27x_maxfreq, uint, 0); 58 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz" 59 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)"); 60 61 struct pxa_freqs { 62 unsigned int khz; 63 unsigned int membus; 64 unsigned int cccr; 65 unsigned int div2; 66 unsigned int cclkcfg; 67 int vmin; 68 int vmax; 69 }; 70 71 /* Define the refresh period in mSec for the SDRAM and the number of rows */ 72 #define SDRAM_TREF 64 /* standard 64ms SDRAM */ 73 static unsigned int sdram_rows; 74 75 #define CCLKCFG_TURBO 0x1 76 #define CCLKCFG_FCS 0x2 77 #define CCLKCFG_HALFTURBO 0x4 78 #define CCLKCFG_FASTBUS 0x8 79 #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) 80 #define MDREFR_DRI_MASK 0xFFF 81 82 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) 83 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) 84 85 /* 86 * PXA255 definitions 87 */ 88 /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ 89 #define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS 90 91 static const struct pxa_freqs pxa255_run_freqs[] = 92 { 93 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ 94 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */ 95 {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */ 96 {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */ 97 {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */ 98 {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */ 99 {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */ 100 }; 101 102 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ 103 static const struct pxa_freqs pxa255_turbo_freqs[] = 104 { 105 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */ 106 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */ 107 {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */ 108 {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */ 109 {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */ 110 {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */ 111 }; 112 113 #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs) 114 #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs) 115 116 static struct cpufreq_frequency_table 117 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1]; 118 static struct cpufreq_frequency_table 119 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; 120 121 static unsigned int pxa255_turbo_table; 122 module_param(pxa255_turbo_table, uint, 0); 123 MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); 124 125 /* 126 * PXA270 definitions 127 * 128 * For the PXA27x: 129 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG. 130 * 131 * A = 0 => memory controller clock from table 3-7, 132 * A = 1 => memory controller clock = system bus clock 133 * Run mode frequency = 13 MHz * L 134 * Turbo mode frequency = 13 MHz * L * N 135 * System bus frequency = 13 MHz * L / (B + 1) 136 * 137 * In CCCR: 138 * A = 1 139 * L = 16 oscillator to run mode ratio 140 * 2N = 6 2 * (turbo mode to run mode ratio) 141 * 142 * In CCLKCFG: 143 * B = 1 Fast bus mode 144 * HT = 0 Half-Turbo mode 145 * T = 1 Turbo mode 146 * 147 * For now, just support some of the combinations in table 3-7 of 148 * PXA27x Processor Family Developer's Manual to simplify frequency 149 * change sequences. 150 */ 151 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L) 152 #define CCLKCFG2(B, HT, T) \ 153 (CCLKCFG_FCS | \ 154 ((B) ? CCLKCFG_FASTBUS : 0) | \ 155 ((HT) ? CCLKCFG_HALFTURBO : 0) | \ 156 ((T) ? CCLKCFG_TURBO : 0)) 157 158 static struct pxa_freqs pxa27x_freqs[] = { 159 {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 }, 160 {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 }, 161 {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 }, 162 {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 }, 163 {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 }, 164 {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 }, 165 {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 } 166 }; 167 168 #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs) 169 static struct cpufreq_frequency_table 170 pxa27x_freq_table[NUM_PXA27x_FREQS+1]; 171 172 extern unsigned get_clk_frequency_khz(int info); 173 174 #ifdef CONFIG_REGULATOR 175 176 static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq) 177 { 178 int ret = 0; 179 int vmin, vmax; 180 181 if (!cpu_is_pxa27x()) 182 return 0; 183 184 vmin = pxa_freq->vmin; 185 vmax = pxa_freq->vmax; 186 if ((vmin == -1) || (vmax == -1)) 187 return 0; 188 189 ret = regulator_set_voltage(vcc_core, vmin, vmax); 190 if (ret) 191 pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax); 192 return ret; 193 } 194 195 static void __init pxa_cpufreq_init_voltages(void) 196 { 197 vcc_core = regulator_get(NULL, "vcc_core"); 198 if (IS_ERR(vcc_core)) { 199 pr_info("Didn't find vcc_core regulator\n"); 200 vcc_core = NULL; 201 } else { 202 pr_info("Found vcc_core regulator\n"); 203 } 204 } 205 #else 206 static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq) 207 { 208 return 0; 209 } 210 211 static void __init pxa_cpufreq_init_voltages(void) { } 212 #endif 213 214 static void find_freq_tables(struct cpufreq_frequency_table **freq_table, 215 const struct pxa_freqs **pxa_freqs) 216 { 217 if (cpu_is_pxa25x()) { 218 if (!pxa255_turbo_table) { 219 *pxa_freqs = pxa255_run_freqs; 220 *freq_table = pxa255_run_freq_table; 221 } else { 222 *pxa_freqs = pxa255_turbo_freqs; 223 *freq_table = pxa255_turbo_freq_table; 224 } 225 } else if (cpu_is_pxa27x()) { 226 *pxa_freqs = pxa27x_freqs; 227 *freq_table = pxa27x_freq_table; 228 } else { 229 BUG(); 230 } 231 } 232 233 static void pxa27x_guess_max_freq(void) 234 { 235 if (!pxa27x_maxfreq) { 236 pxa27x_maxfreq = 416000; 237 pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n", 238 pxa27x_maxfreq); 239 } else { 240 pxa27x_maxfreq *= 1000; 241 } 242 } 243 244 static void init_sdram_rows(void) 245 { 246 uint32_t mdcnfg = __raw_readl(MDCNFG); 247 unsigned int drac2 = 0, drac0 = 0; 248 249 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) 250 drac2 = MDCNFG_DRAC2(mdcnfg); 251 252 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) 253 drac0 = MDCNFG_DRAC0(mdcnfg); 254 255 sdram_rows = 1 << (11 + max(drac0, drac2)); 256 } 257 258 static u32 mdrefr_dri(unsigned int freq) 259 { 260 u32 interval = freq * SDRAM_TREF / sdram_rows; 261 262 return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32; 263 } 264 265 static unsigned int pxa_cpufreq_get(unsigned int cpu) 266 { 267 return get_clk_frequency_khz(0); 268 } 269 270 static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx) 271 { 272 struct cpufreq_frequency_table *pxa_freqs_table; 273 const struct pxa_freqs *pxa_freq_settings; 274 unsigned long flags; 275 unsigned int new_freq_cpu, new_freq_mem; 276 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; 277 int ret = 0; 278 279 /* Get the current policy */ 280 find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); 281 282 new_freq_cpu = pxa_freq_settings[idx].khz; 283 new_freq_mem = pxa_freq_settings[idx].membus; 284 285 if (freq_debug) 286 pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", 287 new_freq_cpu / 1000, (pxa_freq_settings[idx].div2) ? 288 (new_freq_mem / 2000) : (new_freq_mem / 1000)); 289 290 if (vcc_core && new_freq_cpu > policy->cur) { 291 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]); 292 if (ret) 293 return ret; 294 } 295 296 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock 297 * we need to preset the smaller DRI before the change. If we're 298 * speeding up we need to set the larger DRI value after the change. 299 */ 300 preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR); 301 if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { 302 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); 303 preset_mdrefr |= mdrefr_dri(new_freq_mem); 304 } 305 postset_mdrefr = 306 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem); 307 308 /* If we're dividing the memory clock by two for the SDRAM clock, this 309 * must be set prior to the change. Clearing the divide must be done 310 * after the change. 311 */ 312 if (pxa_freq_settings[idx].div2) { 313 preset_mdrefr |= MDREFR_DB2_MASK; 314 postset_mdrefr |= MDREFR_DB2_MASK; 315 } else { 316 postset_mdrefr &= ~MDREFR_DB2_MASK; 317 } 318 319 local_irq_save(flags); 320 321 /* Set new the CCCR and prepare CCLKCFG */ 322 writel(pxa_freq_settings[idx].cccr, CCCR); 323 cclkcfg = pxa_freq_settings[idx].cclkcfg; 324 325 asm volatile(" \n\ 326 ldr r4, [%1] /* load MDREFR */ \n\ 327 b 2f \n\ 328 .align 5 \n\ 329 1: \n\ 330 str %3, [%1] /* preset the MDREFR */ \n\ 331 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ 332 str %4, [%1] /* postset the MDREFR */ \n\ 333 \n\ 334 b 3f \n\ 335 2: b 1b \n\ 336 3: nop \n\ 337 " 338 : "=&r" (unused) 339 : "r" (MDREFR), "r" (cclkcfg), 340 "r" (preset_mdrefr), "r" (postset_mdrefr) 341 : "r4", "r5"); 342 local_irq_restore(flags); 343 344 /* 345 * Even if voltage setting fails, we don't report it, as the frequency 346 * change succeeded. The voltage reduction is not a critical failure, 347 * only power savings will suffer from this. 348 * 349 * Note: if the voltage change fails, and a return value is returned, a 350 * bug is triggered (seems a deadlock). Should anybody find out where, 351 * the "return 0" should become a "return ret". 352 */ 353 if (vcc_core && new_freq_cpu < policy->cur) 354 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]); 355 356 return 0; 357 } 358 359 static int pxa_cpufreq_init(struct cpufreq_policy *policy) 360 { 361 int i; 362 unsigned int freq; 363 struct cpufreq_frequency_table *pxa255_freq_table; 364 const struct pxa_freqs *pxa255_freqs; 365 366 /* try to guess pxa27x cpu */ 367 if (cpu_is_pxa27x()) 368 pxa27x_guess_max_freq(); 369 370 pxa_cpufreq_init_voltages(); 371 372 init_sdram_rows(); 373 374 /* set default policy and cpuinfo */ 375 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ 376 377 /* Generate pxa25x the run cpufreq_frequency_table struct */ 378 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) { 379 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; 380 pxa255_run_freq_table[i].driver_data = i; 381 } 382 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; 383 384 /* Generate pxa25x the turbo cpufreq_frequency_table struct */ 385 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) { 386 pxa255_turbo_freq_table[i].frequency = 387 pxa255_turbo_freqs[i].khz; 388 pxa255_turbo_freq_table[i].driver_data = i; 389 } 390 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; 391 392 pxa255_turbo_table = !!pxa255_turbo_table; 393 394 /* Generate the pxa27x cpufreq_frequency_table struct */ 395 for (i = 0; i < NUM_PXA27x_FREQS; i++) { 396 freq = pxa27x_freqs[i].khz; 397 if (freq > pxa27x_maxfreq) 398 break; 399 pxa27x_freq_table[i].frequency = freq; 400 pxa27x_freq_table[i].driver_data = i; 401 } 402 pxa27x_freq_table[i].driver_data = i; 403 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END; 404 405 /* 406 * Set the policy's minimum and maximum frequencies from the tables 407 * just constructed. This sets cpuinfo.mxx_freq, min and max. 408 */ 409 if (cpu_is_pxa25x()) { 410 find_freq_tables(&pxa255_freq_table, &pxa255_freqs); 411 pr_info("using %s frequency table\n", 412 pxa255_turbo_table ? "turbo" : "run"); 413 414 cpufreq_table_validate_and_show(policy, pxa255_freq_table); 415 } 416 else if (cpu_is_pxa27x()) { 417 cpufreq_table_validate_and_show(policy, pxa27x_freq_table); 418 } 419 420 pr_info("frequency change support initialized\n"); 421 422 return 0; 423 } 424 425 static struct cpufreq_driver pxa_cpufreq_driver = { 426 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 427 .verify = cpufreq_generic_frequency_table_verify, 428 .target_index = pxa_set_target, 429 .init = pxa_cpufreq_init, 430 .get = pxa_cpufreq_get, 431 .name = "PXA2xx", 432 }; 433 434 static int __init pxa_cpu_init(void) 435 { 436 int ret = -ENODEV; 437 if (cpu_is_pxa25x() || cpu_is_pxa27x()) 438 ret = cpufreq_register_driver(&pxa_cpufreq_driver); 439 return ret; 440 } 441 442 static void __exit pxa_cpu_exit(void) 443 { 444 cpufreq_unregister_driver(&pxa_cpufreq_driver); 445 } 446 447 448 MODULE_AUTHOR("Intrinsyc Software Inc."); 449 MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture"); 450 MODULE_LICENSE("GPL"); 451 module_init(pxa_cpu_init); 452 module_exit(pxa_cpu_exit); 453