1 /* 2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org> 3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs, 10 * that is iMac G5 and latest single CPU desktop. 11 */ 12 13 #undef DEBUG 14 15 #include <linux/module.h> 16 #include <linux/types.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/sched.h> 21 #include <linux/cpufreq.h> 22 #include <linux/init.h> 23 #include <linux/completion.h> 24 #include <linux/mutex.h> 25 #include <linux/of_device.h> 26 #include <asm/prom.h> 27 #include <asm/machdep.h> 28 #include <asm/irq.h> 29 #include <asm/sections.h> 30 #include <asm/cputable.h> 31 #include <asm/time.h> 32 #include <asm/smu.h> 33 #include <asm/pmac_pfunc.h> 34 35 #define DBG(fmt...) pr_debug(fmt) 36 37 /* see 970FX user manual */ 38 39 #define SCOM_PCR 0x0aa001 /* PCR scom addr */ 40 41 #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */ 42 #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */ 43 #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */ 44 #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */ 45 #define PCR_SPEED_MASK 0x000e0000U /* speed mask */ 46 #define PCR_SPEED_SHIFT 17 47 #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */ 48 #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */ 49 #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */ 50 #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */ 51 #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */ 52 #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */ 53 54 #define SCOM_PSR 0x408001 /* PSR scom addr */ 55 /* warning: PSR is a 64 bits register */ 56 #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */ 57 #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */ 58 #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */ 59 #define PSR_CUR_SPEED_SHIFT (56) 60 61 /* 62 * The G5 only supports two frequencies (Quarter speed is not supported) 63 */ 64 #define CPUFREQ_HIGH 0 65 #define CPUFREQ_LOW 1 66 67 static struct cpufreq_frequency_table g5_cpu_freqs[] = { 68 {CPUFREQ_HIGH, 0}, 69 {CPUFREQ_LOW, 0}, 70 {0, CPUFREQ_TABLE_END}, 71 }; 72 73 /* Power mode data is an array of the 32 bits PCR values to use for 74 * the various frequencies, retrieved from the device-tree 75 */ 76 static int g5_pmode_cur; 77 78 static void (*g5_switch_volt)(int speed_mode); 79 static int (*g5_switch_freq)(int speed_mode); 80 static int (*g5_query_freq)(void); 81 82 static DEFINE_MUTEX(g5_switch_mutex); 83 84 static unsigned long transition_latency; 85 86 #ifdef CONFIG_PMAC_SMU 87 88 static const u32 *g5_pmode_data; 89 static int g5_pmode_max; 90 91 static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */ 92 static int g5_fvt_count; /* number of op. points */ 93 static int g5_fvt_cur; /* current op. point */ 94 95 /* 96 * SMU based voltage switching for Neo2 platforms 97 */ 98 99 static void g5_smu_switch_volt(int speed_mode) 100 { 101 struct smu_simple_cmd cmd; 102 103 DECLARE_COMPLETION_ONSTACK(comp); 104 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete, 105 &comp, 'V', 'S', 'L', 'E', 'W', 106 0xff, g5_fvt_cur+1, speed_mode); 107 wait_for_completion(&comp); 108 } 109 110 /* 111 * Platform function based voltage/vdnap switching for Neo2 112 */ 113 114 static struct pmf_function *pfunc_set_vdnap0; 115 static struct pmf_function *pfunc_vdnap0_complete; 116 117 static void g5_vdnap_switch_volt(int speed_mode) 118 { 119 struct pmf_args args; 120 u32 slew, done = 0; 121 unsigned long timeout; 122 123 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0; 124 args.count = 1; 125 args.u[0].p = &slew; 126 127 pmf_call_one(pfunc_set_vdnap0, &args); 128 129 /* It's an irq GPIO so we should be able to just block here, 130 * I'll do that later after I've properly tested the IRQ code for 131 * platform functions 132 */ 133 timeout = jiffies + HZ/10; 134 while(!time_after(jiffies, timeout)) { 135 args.count = 1; 136 args.u[0].p = &done; 137 pmf_call_one(pfunc_vdnap0_complete, &args); 138 if (done) 139 break; 140 usleep_range(1000, 1000); 141 } 142 if (done == 0) 143 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n"); 144 } 145 146 147 /* 148 * SCOM based frequency switching for 970FX rev3 149 */ 150 static int g5_scom_switch_freq(int speed_mode) 151 { 152 unsigned long flags; 153 int to; 154 155 /* If frequency is going up, first ramp up the voltage */ 156 if (speed_mode < g5_pmode_cur) 157 g5_switch_volt(speed_mode); 158 159 local_irq_save(flags); 160 161 /* Clear PCR high */ 162 scom970_write(SCOM_PCR, 0); 163 /* Clear PCR low */ 164 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0); 165 /* Set PCR low */ 166 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 167 g5_pmode_data[speed_mode]); 168 169 /* Wait for completion */ 170 for (to = 0; to < 10; to++) { 171 unsigned long psr = scom970_read(SCOM_PSR); 172 173 if ((psr & PSR_CMD_RECEIVED) == 0 && 174 (((psr >> PSR_CUR_SPEED_SHIFT) ^ 175 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3) 176 == 0) 177 break; 178 if (psr & PSR_CMD_COMPLETED) 179 break; 180 udelay(100); 181 } 182 183 local_irq_restore(flags); 184 185 /* If frequency is going down, last ramp the voltage */ 186 if (speed_mode > g5_pmode_cur) 187 g5_switch_volt(speed_mode); 188 189 g5_pmode_cur = speed_mode; 190 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; 191 192 return 0; 193 } 194 195 static int g5_scom_query_freq(void) 196 { 197 unsigned long psr = scom970_read(SCOM_PSR); 198 int i; 199 200 for (i = 0; i <= g5_pmode_max; i++) 201 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ 202 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0) 203 break; 204 return i; 205 } 206 207 /* 208 * Fake voltage switching for platforms with missing support 209 */ 210 211 static void g5_dummy_switch_volt(int speed_mode) 212 { 213 } 214 215 #endif /* CONFIG_PMAC_SMU */ 216 217 /* 218 * Platform function based voltage switching for PowerMac7,2 & 7,3 219 */ 220 221 static struct pmf_function *pfunc_cpu0_volt_high; 222 static struct pmf_function *pfunc_cpu0_volt_low; 223 static struct pmf_function *pfunc_cpu1_volt_high; 224 static struct pmf_function *pfunc_cpu1_volt_low; 225 226 static void g5_pfunc_switch_volt(int speed_mode) 227 { 228 if (speed_mode == CPUFREQ_HIGH) { 229 if (pfunc_cpu0_volt_high) 230 pmf_call_one(pfunc_cpu0_volt_high, NULL); 231 if (pfunc_cpu1_volt_high) 232 pmf_call_one(pfunc_cpu1_volt_high, NULL); 233 } else { 234 if (pfunc_cpu0_volt_low) 235 pmf_call_one(pfunc_cpu0_volt_low, NULL); 236 if (pfunc_cpu1_volt_low) 237 pmf_call_one(pfunc_cpu1_volt_low, NULL); 238 } 239 usleep_range(10000, 10000); /* should be faster , to fix */ 240 } 241 242 /* 243 * Platform function based frequency switching for PowerMac7,2 & 7,3 244 */ 245 246 static struct pmf_function *pfunc_cpu_setfreq_high; 247 static struct pmf_function *pfunc_cpu_setfreq_low; 248 static struct pmf_function *pfunc_cpu_getfreq; 249 static struct pmf_function *pfunc_slewing_done; 250 251 static int g5_pfunc_switch_freq(int speed_mode) 252 { 253 struct pmf_args args; 254 u32 done = 0; 255 unsigned long timeout; 256 int rc; 257 258 DBG("g5_pfunc_switch_freq(%d)\n", speed_mode); 259 260 /* If frequency is going up, first ramp up the voltage */ 261 if (speed_mode < g5_pmode_cur) 262 g5_switch_volt(speed_mode); 263 264 /* Do it */ 265 if (speed_mode == CPUFREQ_HIGH) 266 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL); 267 else 268 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL); 269 270 if (rc) 271 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc); 272 273 /* It's an irq GPIO so we should be able to just block here, 274 * I'll do that later after I've properly tested the IRQ code for 275 * platform functions 276 */ 277 timeout = jiffies + HZ/10; 278 while(!time_after(jiffies, timeout)) { 279 args.count = 1; 280 args.u[0].p = &done; 281 pmf_call_one(pfunc_slewing_done, &args); 282 if (done) 283 break; 284 usleep_range(500, 500); 285 } 286 if (done == 0) 287 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n"); 288 289 /* If frequency is going down, last ramp the voltage */ 290 if (speed_mode > g5_pmode_cur) 291 g5_switch_volt(speed_mode); 292 293 g5_pmode_cur = speed_mode; 294 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; 295 296 return 0; 297 } 298 299 static int g5_pfunc_query_freq(void) 300 { 301 struct pmf_args args; 302 u32 val = 0; 303 304 args.count = 1; 305 args.u[0].p = &val; 306 pmf_call_one(pfunc_cpu_getfreq, &args); 307 return val ? CPUFREQ_HIGH : CPUFREQ_LOW; 308 } 309 310 311 /* 312 * Common interface to the cpufreq core 313 */ 314 315 static int g5_cpufreq_target(struct cpufreq_policy *policy, 316 unsigned int target_freq, unsigned int relation) 317 { 318 unsigned int newstate = 0; 319 struct cpufreq_freqs freqs; 320 int rc; 321 322 if (cpufreq_frequency_table_target(policy, g5_cpu_freqs, 323 target_freq, relation, &newstate)) 324 return -EINVAL; 325 326 if (g5_pmode_cur == newstate) 327 return 0; 328 329 mutex_lock(&g5_switch_mutex); 330 331 freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency; 332 freqs.new = g5_cpu_freqs[newstate].frequency; 333 334 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); 335 rc = g5_switch_freq(newstate); 336 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); 337 338 mutex_unlock(&g5_switch_mutex); 339 340 return rc; 341 } 342 343 static unsigned int g5_cpufreq_get_speed(unsigned int cpu) 344 { 345 return g5_cpu_freqs[g5_pmode_cur].frequency; 346 } 347 348 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy) 349 { 350 return cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency); 351 } 352 353 static struct cpufreq_driver g5_cpufreq_driver = { 354 .name = "powermac", 355 .flags = CPUFREQ_CONST_LOOPS, 356 .init = g5_cpufreq_cpu_init, 357 .verify = cpufreq_generic_frequency_table_verify, 358 .target = g5_cpufreq_target, 359 .get = g5_cpufreq_get_speed, 360 .attr = cpufreq_generic_attr, 361 }; 362 363 364 #ifdef CONFIG_PMAC_SMU 365 366 static int __init g5_neo2_cpufreq_init(struct device_node *cpunode) 367 { 368 unsigned int psize, ssize; 369 unsigned long max_freq; 370 char *freq_method, *volt_method; 371 const u32 *valp; 372 u32 pvr_hi; 373 int use_volts_vdnap = 0; 374 int use_volts_smu = 0; 375 int rc = -ENODEV; 376 377 /* Check supported platforms */ 378 if (of_machine_is_compatible("PowerMac8,1") || 379 of_machine_is_compatible("PowerMac8,2") || 380 of_machine_is_compatible("PowerMac9,1")) 381 use_volts_smu = 1; 382 else if (of_machine_is_compatible("PowerMac11,2")) 383 use_volts_vdnap = 1; 384 else 385 return -ENODEV; 386 387 /* Check 970FX for now */ 388 valp = of_get_property(cpunode, "cpu-version", NULL); 389 if (!valp) { 390 DBG("No cpu-version property !\n"); 391 goto bail_noprops; 392 } 393 pvr_hi = (*valp) >> 16; 394 if (pvr_hi != 0x3c && pvr_hi != 0x44) { 395 printk(KERN_ERR "cpufreq: Unsupported CPU version\n"); 396 goto bail_noprops; 397 } 398 399 /* Look for the powertune data in the device-tree */ 400 g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize); 401 if (!g5_pmode_data) { 402 DBG("No power-mode-data !\n"); 403 goto bail_noprops; 404 } 405 g5_pmode_max = psize / sizeof(u32) - 1; 406 407 if (use_volts_smu) { 408 const struct smu_sdbp_header *shdr; 409 410 /* Look for the FVT table */ 411 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL); 412 if (!shdr) 413 goto bail_noprops; 414 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1]; 415 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr); 416 g5_fvt_count = ssize / sizeof(*g5_fvt_table); 417 g5_fvt_cur = 0; 418 419 /* Sanity checking */ 420 if (g5_fvt_count < 1 || g5_pmode_max < 1) 421 goto bail_noprops; 422 423 g5_switch_volt = g5_smu_switch_volt; 424 volt_method = "SMU"; 425 } else if (use_volts_vdnap) { 426 struct device_node *root; 427 428 root = of_find_node_by_path("/"); 429 if (root == NULL) { 430 printk(KERN_ERR "cpufreq: Can't find root of " 431 "device tree\n"); 432 goto bail_noprops; 433 } 434 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0"); 435 pfunc_vdnap0_complete = 436 pmf_find_function(root, "slewing-done"); 437 if (pfunc_set_vdnap0 == NULL || 438 pfunc_vdnap0_complete == NULL) { 439 printk(KERN_ERR "cpufreq: Can't find required " 440 "platform function\n"); 441 goto bail_noprops; 442 } 443 444 g5_switch_volt = g5_vdnap_switch_volt; 445 volt_method = "GPIO"; 446 } else { 447 g5_switch_volt = g5_dummy_switch_volt; 448 volt_method = "none"; 449 } 450 451 /* 452 * From what I see, clock-frequency is always the maximal frequency. 453 * The current driver can not slew sysclk yet, so we really only deal 454 * with powertune steps for now. We also only implement full freq and 455 * half freq in this version. So far, I haven't yet seen a machine 456 * supporting anything else. 457 */ 458 valp = of_get_property(cpunode, "clock-frequency", NULL); 459 if (!valp) 460 return -ENODEV; 461 max_freq = (*valp)/1000; 462 g5_cpu_freqs[0].frequency = max_freq; 463 g5_cpu_freqs[1].frequency = max_freq/2; 464 465 /* Set callbacks */ 466 transition_latency = 12000; 467 g5_switch_freq = g5_scom_switch_freq; 468 g5_query_freq = g5_scom_query_freq; 469 freq_method = "SCOM"; 470 471 /* Force apply current frequency to make sure everything is in 472 * sync (voltage is right for example). Firmware may leave us with 473 * a strange setting ... 474 */ 475 g5_switch_volt(CPUFREQ_HIGH); 476 msleep(10); 477 g5_pmode_cur = -1; 478 g5_switch_freq(g5_query_freq()); 479 480 printk(KERN_INFO "Registering G5 CPU frequency driver\n"); 481 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n", 482 freq_method, volt_method); 483 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n", 484 g5_cpu_freqs[1].frequency/1000, 485 g5_cpu_freqs[0].frequency/1000, 486 g5_cpu_freqs[g5_pmode_cur].frequency/1000); 487 488 rc = cpufreq_register_driver(&g5_cpufreq_driver); 489 490 /* We keep the CPU node on hold... hopefully, Apple G5 don't have 491 * hotplug CPU with a dynamic device-tree ... 492 */ 493 return rc; 494 495 bail_noprops: 496 of_node_put(cpunode); 497 498 return rc; 499 } 500 501 #endif /* CONFIG_PMAC_SMU */ 502 503 504 static int __init g5_pm72_cpufreq_init(struct device_node *cpunode) 505 { 506 struct device_node *cpuid = NULL, *hwclock = NULL; 507 const u8 *eeprom = NULL; 508 const u32 *valp; 509 u64 max_freq, min_freq, ih, il; 510 int has_volt = 1, rc = 0; 511 512 DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and" 513 " RackMac3,1...\n"); 514 515 /* Lookup the cpuid eeprom node */ 516 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0"); 517 if (cpuid != NULL) 518 eeprom = of_get_property(cpuid, "cpuid", NULL); 519 if (eeprom == NULL) { 520 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n"); 521 rc = -ENODEV; 522 goto bail; 523 } 524 525 /* Lookup the i2c hwclock */ 526 for (hwclock = NULL; 527 (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){ 528 const char *loc = of_get_property(hwclock, 529 "hwctrl-location", NULL); 530 if (loc == NULL) 531 continue; 532 if (strcmp(loc, "CPU CLOCK")) 533 continue; 534 if (!of_get_property(hwclock, "platform-get-frequency", NULL)) 535 continue; 536 break; 537 } 538 if (hwclock == NULL) { 539 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n"); 540 rc = -ENODEV; 541 goto bail; 542 } 543 544 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name); 545 546 /* Now get all the platform functions */ 547 pfunc_cpu_getfreq = 548 pmf_find_function(hwclock, "get-frequency"); 549 pfunc_cpu_setfreq_high = 550 pmf_find_function(hwclock, "set-frequency-high"); 551 pfunc_cpu_setfreq_low = 552 pmf_find_function(hwclock, "set-frequency-low"); 553 pfunc_slewing_done = 554 pmf_find_function(hwclock, "slewing-done"); 555 pfunc_cpu0_volt_high = 556 pmf_find_function(hwclock, "set-voltage-high-0"); 557 pfunc_cpu0_volt_low = 558 pmf_find_function(hwclock, "set-voltage-low-0"); 559 pfunc_cpu1_volt_high = 560 pmf_find_function(hwclock, "set-voltage-high-1"); 561 pfunc_cpu1_volt_low = 562 pmf_find_function(hwclock, "set-voltage-low-1"); 563 564 /* Check we have minimum requirements */ 565 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL || 566 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) { 567 printk(KERN_ERR "cpufreq: Can't find platform functions !\n"); 568 rc = -ENODEV; 569 goto bail; 570 } 571 572 /* Check that we have complete sets */ 573 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) { 574 pmf_put_function(pfunc_cpu0_volt_high); 575 pmf_put_function(pfunc_cpu0_volt_low); 576 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL; 577 has_volt = 0; 578 } 579 if (!has_volt || 580 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) { 581 pmf_put_function(pfunc_cpu1_volt_high); 582 pmf_put_function(pfunc_cpu1_volt_low); 583 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL; 584 } 585 586 /* Note: The device tree also contains a "platform-set-values" 587 * function for which I haven't quite figured out the usage. It 588 * might have to be called on init and/or wakeup, I'm not too sure 589 * but things seem to work fine without it so far ... 590 */ 591 592 /* Get max frequency from device-tree */ 593 valp = of_get_property(cpunode, "clock-frequency", NULL); 594 if (!valp) { 595 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n"); 596 rc = -ENODEV; 597 goto bail; 598 } 599 600 max_freq = (*valp)/1000; 601 602 /* Now calculate reduced frequency by using the cpuid input freq 603 * ratio. This requires 64 bits math unless we are willing to lose 604 * some precision 605 */ 606 ih = *((u32 *)(eeprom + 0x10)); 607 il = *((u32 *)(eeprom + 0x20)); 608 609 /* Check for machines with no useful settings */ 610 if (il == ih) { 611 printk(KERN_WARNING "cpufreq: No low frequency mode available" 612 " on this model !\n"); 613 rc = -ENODEV; 614 goto bail; 615 } 616 617 min_freq = 0; 618 if (ih != 0 && il != 0) 619 min_freq = (max_freq * il) / ih; 620 621 /* Sanity check */ 622 if (min_freq >= max_freq || min_freq < 1000) { 623 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n"); 624 rc = -ENXIO; 625 goto bail; 626 } 627 g5_cpu_freqs[0].frequency = max_freq; 628 g5_cpu_freqs[1].frequency = min_freq; 629 630 /* Based on a measurement on Xserve G5, rounded up. */ 631 transition_latency = 10 * NSEC_PER_MSEC; 632 633 /* Set callbacks */ 634 g5_switch_volt = g5_pfunc_switch_volt; 635 g5_switch_freq = g5_pfunc_switch_freq; 636 g5_query_freq = g5_pfunc_query_freq; 637 638 /* Force apply current frequency to make sure everything is in 639 * sync (voltage is right for example). Firmware may leave us with 640 * a strange setting ... 641 */ 642 g5_switch_volt(CPUFREQ_HIGH); 643 msleep(10); 644 g5_pmode_cur = -1; 645 g5_switch_freq(g5_query_freq()); 646 647 printk(KERN_INFO "Registering G5 CPU frequency driver\n"); 648 printk(KERN_INFO "Frequency method: i2c/pfunc, " 649 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none"); 650 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n", 651 g5_cpu_freqs[1].frequency/1000, 652 g5_cpu_freqs[0].frequency/1000, 653 g5_cpu_freqs[g5_pmode_cur].frequency/1000); 654 655 rc = cpufreq_register_driver(&g5_cpufreq_driver); 656 bail: 657 if (rc != 0) { 658 pmf_put_function(pfunc_cpu_getfreq); 659 pmf_put_function(pfunc_cpu_setfreq_high); 660 pmf_put_function(pfunc_cpu_setfreq_low); 661 pmf_put_function(pfunc_slewing_done); 662 pmf_put_function(pfunc_cpu0_volt_high); 663 pmf_put_function(pfunc_cpu0_volt_low); 664 pmf_put_function(pfunc_cpu1_volt_high); 665 pmf_put_function(pfunc_cpu1_volt_low); 666 } 667 of_node_put(hwclock); 668 of_node_put(cpuid); 669 of_node_put(cpunode); 670 671 return rc; 672 } 673 674 static int __init g5_cpufreq_init(void) 675 { 676 struct device_node *cpunode; 677 int rc = 0; 678 679 /* Get first CPU node */ 680 cpunode = of_cpu_device_node_get(0); 681 if (cpunode == NULL) { 682 pr_err("cpufreq: Can't find any CPU node\n"); 683 return -ENODEV; 684 } 685 686 if (of_machine_is_compatible("PowerMac7,2") || 687 of_machine_is_compatible("PowerMac7,3") || 688 of_machine_is_compatible("RackMac3,1")) 689 rc = g5_pm72_cpufreq_init(cpunode); 690 #ifdef CONFIG_PMAC_SMU 691 else 692 rc = g5_neo2_cpufreq_init(cpunode); 693 #endif /* CONFIG_PMAC_SMU */ 694 695 return rc; 696 } 697 698 module_init(g5_cpufreq_init); 699 700 701 MODULE_LICENSE("GPL"); 702