1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 39 #define ATOM_RATIOS 0x66a 40 #define ATOM_VIDS 0x66b 41 #define ATOM_TURBO_RATIOS 0x66c 42 #define ATOM_TURBO_VIDS 0x66d 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #endif 47 48 #define FRAC_BITS 8 49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 50 #define fp_toint(X) ((X) >> FRAC_BITS) 51 52 static inline int32_t mul_fp(int32_t x, int32_t y) 53 { 54 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 55 } 56 57 static inline int32_t div_fp(s64 x, s64 y) 58 { 59 return div64_s64((int64_t)x << FRAC_BITS, y); 60 } 61 62 static inline int ceiling_fp(int32_t x) 63 { 64 int mask, ret; 65 66 ret = fp_toint(x); 67 mask = (1 << FRAC_BITS) - 1; 68 if (x & mask) 69 ret += 1; 70 return ret; 71 } 72 73 /** 74 * struct sample - Store performance sample 75 * @core_pct_busy: Ratio of APERF/MPERF in percent, which is actual 76 * performance during last sample period 77 * @busy_scaled: Scaled busy value which is used to calculate next 78 * P state. This can be different than core_pct_busy 79 * to account for cpu idle period 80 * @aperf: Difference of actual performance frequency clock count 81 * read from APERF MSR between last and current sample 82 * @mperf: Difference of maximum performance frequency clock count 83 * read from MPERF MSR between last and current sample 84 * @tsc: Difference of time stamp counter between last and 85 * current sample 86 * @freq: Effective frequency calculated from APERF/MPERF 87 * @time: Current time from scheduler 88 * 89 * This structure is used in the cpudata structure to store performance sample 90 * data for choosing next P State. 91 */ 92 struct sample { 93 int32_t core_pct_busy; 94 int32_t busy_scaled; 95 u64 aperf; 96 u64 mperf; 97 u64 tsc; 98 int freq; 99 u64 time; 100 }; 101 102 /** 103 * struct pstate_data - Store P state data 104 * @current_pstate: Current requested P state 105 * @min_pstate: Min P state possible for this platform 106 * @max_pstate: Max P state possible for this platform 107 * @max_pstate_physical:This is physical Max P state for a processor 108 * This can be higher than the max_pstate which can 109 * be limited by platform thermal design power limits 110 * @scaling: Scaling factor to convert frequency to cpufreq 111 * frequency units 112 * @turbo_pstate: Max Turbo P state possible for this platform 113 * 114 * Stores the per cpu model P state limits and current P state. 115 */ 116 struct pstate_data { 117 int current_pstate; 118 int min_pstate; 119 int max_pstate; 120 int max_pstate_physical; 121 int scaling; 122 int turbo_pstate; 123 }; 124 125 /** 126 * struct vid_data - Stores voltage information data 127 * @min: VID data for this platform corresponding to 128 * the lowest P state 129 * @max: VID data corresponding to the highest P State. 130 * @turbo: VID data for turbo P state 131 * @ratio: Ratio of (vid max - vid min) / 132 * (max P state - Min P State) 133 * 134 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 135 * This data is used in Atom platforms, where in addition to target P state, 136 * the voltage data needs to be specified to select next P State. 137 */ 138 struct vid_data { 139 int min; 140 int max; 141 int turbo; 142 int32_t ratio; 143 }; 144 145 /** 146 * struct _pid - Stores PID data 147 * @setpoint: Target set point for busyness or performance 148 * @integral: Storage for accumulated error values 149 * @p_gain: PID proportional gain 150 * @i_gain: PID integral gain 151 * @d_gain: PID derivative gain 152 * @deadband: PID deadband 153 * @last_err: Last error storage for integral part of PID calculation 154 * 155 * Stores PID coefficients and last error for PID controller. 156 */ 157 struct _pid { 158 int setpoint; 159 int32_t integral; 160 int32_t p_gain; 161 int32_t i_gain; 162 int32_t d_gain; 163 int deadband; 164 int32_t last_err; 165 }; 166 167 /** 168 * struct cpudata - Per CPU instance data storage 169 * @cpu: CPU number for this instance data 170 * @update_util: CPUFreq utility callback information 171 * @pstate: Stores P state limits for this CPU 172 * @vid: Stores VID limits for this CPU 173 * @pid: Stores PID parameters for this CPU 174 * @last_sample_time: Last Sample time 175 * @prev_aperf: Last APERF value read from APERF MSR 176 * @prev_mperf: Last MPERF value read from MPERF MSR 177 * @prev_tsc: Last timestamp counter (TSC) value 178 * @prev_cummulative_iowait: IO Wait time difference from last and 179 * current sample 180 * @sample: Storage for storing last Sample data 181 * @acpi_perf_data: Stores ACPI perf information read from _PSS 182 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 183 * 184 * This structure stores per CPU instance data for all CPUs. 185 */ 186 struct cpudata { 187 int cpu; 188 189 struct update_util_data update_util; 190 191 struct pstate_data pstate; 192 struct vid_data vid; 193 struct _pid pid; 194 195 u64 last_sample_time; 196 u64 prev_aperf; 197 u64 prev_mperf; 198 u64 prev_tsc; 199 u64 prev_cummulative_iowait; 200 struct sample sample; 201 #ifdef CONFIG_ACPI 202 struct acpi_processor_performance acpi_perf_data; 203 bool valid_pss_table; 204 #endif 205 }; 206 207 static struct cpudata **all_cpu_data; 208 209 /** 210 * struct pid_adjust_policy - Stores static PID configuration data 211 * @sample_rate_ms: PID calculation sample rate in ms 212 * @sample_rate_ns: Sample rate calculation in ns 213 * @deadband: PID deadband 214 * @setpoint: PID Setpoint 215 * @p_gain_pct: PID proportional gain 216 * @i_gain_pct: PID integral gain 217 * @d_gain_pct: PID derivative gain 218 * 219 * Stores per CPU model static PID configuration data. 220 */ 221 struct pstate_adjust_policy { 222 int sample_rate_ms; 223 s64 sample_rate_ns; 224 int deadband; 225 int setpoint; 226 int p_gain_pct; 227 int d_gain_pct; 228 int i_gain_pct; 229 }; 230 231 /** 232 * struct pstate_funcs - Per CPU model specific callbacks 233 * @get_max: Callback to get maximum non turbo effective P state 234 * @get_max_physical: Callback to get maximum non turbo physical P state 235 * @get_min: Callback to get minimum P state 236 * @get_turbo: Callback to get turbo P state 237 * @get_scaling: Callback to get frequency scaling factor 238 * @get_val: Callback to convert P state to actual MSR write value 239 * @get_vid: Callback to get VID data for Atom platforms 240 * @get_target_pstate: Callback to a function to calculate next P state to use 241 * 242 * Core and Atom CPU models have different way to get P State limits. This 243 * structure is used to store those callbacks. 244 */ 245 struct pstate_funcs { 246 int (*get_max)(void); 247 int (*get_max_physical)(void); 248 int (*get_min)(void); 249 int (*get_turbo)(void); 250 int (*get_scaling)(void); 251 u64 (*get_val)(struct cpudata*, int pstate); 252 void (*get_vid)(struct cpudata *); 253 int32_t (*get_target_pstate)(struct cpudata *); 254 }; 255 256 /** 257 * struct cpu_defaults- Per CPU model default config data 258 * @pid_policy: PID config data 259 * @funcs: Callback function data 260 */ 261 struct cpu_defaults { 262 struct pstate_adjust_policy pid_policy; 263 struct pstate_funcs funcs; 264 }; 265 266 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 267 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 268 269 static struct pstate_adjust_policy pid_params; 270 static struct pstate_funcs pstate_funcs; 271 static int hwp_active; 272 273 #ifdef CONFIG_ACPI 274 static bool acpi_ppc; 275 #endif 276 277 /** 278 * struct perf_limits - Store user and policy limits 279 * @no_turbo: User requested turbo state from intel_pstate sysfs 280 * @turbo_disabled: Platform turbo status either from msr 281 * MSR_IA32_MISC_ENABLE or when maximum available pstate 282 * matches the maximum turbo pstate 283 * @max_perf_pct: Effective maximum performance limit in percentage, this 284 * is minimum of either limits enforced by cpufreq policy 285 * or limits from user set limits via intel_pstate sysfs 286 * @min_perf_pct: Effective minimum performance limit in percentage, this 287 * is maximum of either limits enforced by cpufreq policy 288 * or limits from user set limits via intel_pstate sysfs 289 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 290 * This value is used to limit max pstate 291 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 292 * This value is used to limit min pstate 293 * @max_policy_pct: The maximum performance in percentage enforced by 294 * cpufreq setpolicy interface 295 * @max_sysfs_pct: The maximum performance in percentage enforced by 296 * intel pstate sysfs interface 297 * @min_policy_pct: The minimum performance in percentage enforced by 298 * cpufreq setpolicy interface 299 * @min_sysfs_pct: The minimum performance in percentage enforced by 300 * intel pstate sysfs interface 301 * 302 * Storage for user and policy defined limits. 303 */ 304 struct perf_limits { 305 int no_turbo; 306 int turbo_disabled; 307 int max_perf_pct; 308 int min_perf_pct; 309 int32_t max_perf; 310 int32_t min_perf; 311 int max_policy_pct; 312 int max_sysfs_pct; 313 int min_policy_pct; 314 int min_sysfs_pct; 315 }; 316 317 static struct perf_limits performance_limits = { 318 .no_turbo = 0, 319 .turbo_disabled = 0, 320 .max_perf_pct = 100, 321 .max_perf = int_tofp(1), 322 .min_perf_pct = 100, 323 .min_perf = int_tofp(1), 324 .max_policy_pct = 100, 325 .max_sysfs_pct = 100, 326 .min_policy_pct = 0, 327 .min_sysfs_pct = 0, 328 }; 329 330 static struct perf_limits powersave_limits = { 331 .no_turbo = 0, 332 .turbo_disabled = 0, 333 .max_perf_pct = 100, 334 .max_perf = int_tofp(1), 335 .min_perf_pct = 0, 336 .min_perf = 0, 337 .max_policy_pct = 100, 338 .max_sysfs_pct = 100, 339 .min_policy_pct = 0, 340 .min_sysfs_pct = 0, 341 }; 342 343 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 344 static struct perf_limits *limits = &performance_limits; 345 #else 346 static struct perf_limits *limits = &powersave_limits; 347 #endif 348 349 #ifdef CONFIG_ACPI 350 351 static bool intel_pstate_get_ppc_enable_status(void) 352 { 353 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 354 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 355 return true; 356 357 return acpi_ppc; 358 } 359 360 /* 361 * The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and 362 * in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and 363 * max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state 364 * ratio, out of it only high 8 bits are used. For example 0x1700 is setting 365 * target ratio 0x17. The _PSS control value stores in a format which can be 366 * directly written to PERF_CTL MSR. But in intel_pstate driver this shift 367 * occurs during write to PERF_CTL (E.g. for cores core_set_pstate()). 368 * This function converts the _PSS control value to intel pstate driver format 369 * for comparison and assignment. 370 */ 371 static int convert_to_native_pstate_format(struct cpudata *cpu, int index) 372 { 373 return cpu->acpi_perf_data.states[index].control >> 8; 374 } 375 376 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 377 { 378 struct cpudata *cpu; 379 int turbo_pss_ctl; 380 int ret; 381 int i; 382 383 if (hwp_active) 384 return; 385 386 if (!intel_pstate_get_ppc_enable_status()) 387 return; 388 389 cpu = all_cpu_data[policy->cpu]; 390 391 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 392 policy->cpu); 393 if (ret) 394 return; 395 396 /* 397 * Check if the control value in _PSS is for PERF_CTL MSR, which should 398 * guarantee that the states returned by it map to the states in our 399 * list directly. 400 */ 401 if (cpu->acpi_perf_data.control_register.space_id != 402 ACPI_ADR_SPACE_FIXED_HARDWARE) 403 goto err; 404 405 /* 406 * If there is only one entry _PSS, simply ignore _PSS and continue as 407 * usual without taking _PSS into account 408 */ 409 if (cpu->acpi_perf_data.state_count < 2) 410 goto err; 411 412 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 413 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 414 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 415 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 416 (u32) cpu->acpi_perf_data.states[i].core_frequency, 417 (u32) cpu->acpi_perf_data.states[i].power, 418 (u32) cpu->acpi_perf_data.states[i].control); 419 } 420 421 /* 422 * The _PSS table doesn't contain whole turbo frequency range. 423 * This just contains +1 MHZ above the max non turbo frequency, 424 * with control value corresponding to max turbo ratio. But 425 * when cpufreq set policy is called, it will call with this 426 * max frequency, which will cause a reduced performance as 427 * this driver uses real max turbo frequency as the max 428 * frequency. So correct this frequency in _PSS table to 429 * correct max turbo frequency based on the turbo ratio. 430 * Also need to convert to MHz as _PSS freq is in MHz. 431 */ 432 turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0); 433 if (turbo_pss_ctl > cpu->pstate.max_pstate) 434 cpu->acpi_perf_data.states[0].core_frequency = 435 policy->cpuinfo.max_freq / 1000; 436 cpu->valid_pss_table = true; 437 pr_info("_PPC limits will be enforced\n"); 438 439 return; 440 441 err: 442 cpu->valid_pss_table = false; 443 acpi_processor_unregister_performance(policy->cpu); 444 } 445 446 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 447 { 448 struct cpudata *cpu; 449 450 cpu = all_cpu_data[policy->cpu]; 451 if (!cpu->valid_pss_table) 452 return; 453 454 acpi_processor_unregister_performance(policy->cpu); 455 } 456 457 #else 458 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 459 { 460 } 461 462 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 463 { 464 } 465 #endif 466 467 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 468 int deadband, int integral) { 469 pid->setpoint = int_tofp(setpoint); 470 pid->deadband = int_tofp(deadband); 471 pid->integral = int_tofp(integral); 472 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 473 } 474 475 static inline void pid_p_gain_set(struct _pid *pid, int percent) 476 { 477 pid->p_gain = div_fp(percent, 100); 478 } 479 480 static inline void pid_i_gain_set(struct _pid *pid, int percent) 481 { 482 pid->i_gain = div_fp(percent, 100); 483 } 484 485 static inline void pid_d_gain_set(struct _pid *pid, int percent) 486 { 487 pid->d_gain = div_fp(percent, 100); 488 } 489 490 static signed int pid_calc(struct _pid *pid, int32_t busy) 491 { 492 signed int result; 493 int32_t pterm, dterm, fp_error; 494 int32_t integral_limit; 495 496 fp_error = pid->setpoint - busy; 497 498 if (abs(fp_error) <= pid->deadband) 499 return 0; 500 501 pterm = mul_fp(pid->p_gain, fp_error); 502 503 pid->integral += fp_error; 504 505 /* 506 * We limit the integral here so that it will never 507 * get higher than 30. This prevents it from becoming 508 * too large an input over long periods of time and allows 509 * it to get factored out sooner. 510 * 511 * The value of 30 was chosen through experimentation. 512 */ 513 integral_limit = int_tofp(30); 514 if (pid->integral > integral_limit) 515 pid->integral = integral_limit; 516 if (pid->integral < -integral_limit) 517 pid->integral = -integral_limit; 518 519 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 520 pid->last_err = fp_error; 521 522 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 523 result = result + (1 << (FRAC_BITS-1)); 524 return (signed int)fp_toint(result); 525 } 526 527 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 528 { 529 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 530 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 531 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 532 533 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 534 } 535 536 static inline void intel_pstate_reset_all_pid(void) 537 { 538 unsigned int cpu; 539 540 for_each_online_cpu(cpu) { 541 if (all_cpu_data[cpu]) 542 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 543 } 544 } 545 546 static inline void update_turbo_state(void) 547 { 548 u64 misc_en; 549 struct cpudata *cpu; 550 551 cpu = all_cpu_data[0]; 552 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 553 limits->turbo_disabled = 554 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 555 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 556 } 557 558 static void intel_pstate_hwp_set(const struct cpumask *cpumask) 559 { 560 int min, hw_min, max, hw_max, cpu, range, adj_range; 561 u64 value, cap; 562 563 rdmsrl(MSR_HWP_CAPABILITIES, cap); 564 hw_min = HWP_LOWEST_PERF(cap); 565 hw_max = HWP_HIGHEST_PERF(cap); 566 range = hw_max - hw_min; 567 568 for_each_cpu(cpu, cpumask) { 569 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 570 adj_range = limits->min_perf_pct * range / 100; 571 min = hw_min + adj_range; 572 value &= ~HWP_MIN_PERF(~0L); 573 value |= HWP_MIN_PERF(min); 574 575 adj_range = limits->max_perf_pct * range / 100; 576 max = hw_min + adj_range; 577 if (limits->no_turbo) { 578 hw_max = HWP_GUARANTEED_PERF(cap); 579 if (hw_max < max) 580 max = hw_max; 581 } 582 583 value &= ~HWP_MAX_PERF(~0L); 584 value |= HWP_MAX_PERF(max); 585 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 586 } 587 } 588 589 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) 590 { 591 if (hwp_active) 592 intel_pstate_hwp_set(policy->cpus); 593 594 return 0; 595 } 596 597 static void intel_pstate_hwp_set_online_cpus(void) 598 { 599 get_online_cpus(); 600 intel_pstate_hwp_set(cpu_online_mask); 601 put_online_cpus(); 602 } 603 604 /************************** debugfs begin ************************/ 605 static int pid_param_set(void *data, u64 val) 606 { 607 *(u32 *)data = val; 608 intel_pstate_reset_all_pid(); 609 return 0; 610 } 611 612 static int pid_param_get(void *data, u64 *val) 613 { 614 *val = *(u32 *)data; 615 return 0; 616 } 617 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 618 619 struct pid_param { 620 char *name; 621 void *value; 622 }; 623 624 static struct pid_param pid_files[] = { 625 {"sample_rate_ms", &pid_params.sample_rate_ms}, 626 {"d_gain_pct", &pid_params.d_gain_pct}, 627 {"i_gain_pct", &pid_params.i_gain_pct}, 628 {"deadband", &pid_params.deadband}, 629 {"setpoint", &pid_params.setpoint}, 630 {"p_gain_pct", &pid_params.p_gain_pct}, 631 {NULL, NULL} 632 }; 633 634 static void __init intel_pstate_debug_expose_params(void) 635 { 636 struct dentry *debugfs_parent; 637 int i = 0; 638 639 if (hwp_active) 640 return; 641 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 642 if (IS_ERR_OR_NULL(debugfs_parent)) 643 return; 644 while (pid_files[i].name) { 645 debugfs_create_file(pid_files[i].name, 0660, 646 debugfs_parent, pid_files[i].value, 647 &fops_pid_param); 648 i++; 649 } 650 } 651 652 /************************** debugfs end ************************/ 653 654 /************************** sysfs begin ************************/ 655 #define show_one(file_name, object) \ 656 static ssize_t show_##file_name \ 657 (struct kobject *kobj, struct attribute *attr, char *buf) \ 658 { \ 659 return sprintf(buf, "%u\n", limits->object); \ 660 } 661 662 static ssize_t show_turbo_pct(struct kobject *kobj, 663 struct attribute *attr, char *buf) 664 { 665 struct cpudata *cpu; 666 int total, no_turbo, turbo_pct; 667 uint32_t turbo_fp; 668 669 cpu = all_cpu_data[0]; 670 671 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 672 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 673 turbo_fp = div_fp(no_turbo, total); 674 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 675 return sprintf(buf, "%u\n", turbo_pct); 676 } 677 678 static ssize_t show_num_pstates(struct kobject *kobj, 679 struct attribute *attr, char *buf) 680 { 681 struct cpudata *cpu; 682 int total; 683 684 cpu = all_cpu_data[0]; 685 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 686 return sprintf(buf, "%u\n", total); 687 } 688 689 static ssize_t show_no_turbo(struct kobject *kobj, 690 struct attribute *attr, char *buf) 691 { 692 ssize_t ret; 693 694 update_turbo_state(); 695 if (limits->turbo_disabled) 696 ret = sprintf(buf, "%u\n", limits->turbo_disabled); 697 else 698 ret = sprintf(buf, "%u\n", limits->no_turbo); 699 700 return ret; 701 } 702 703 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 704 const char *buf, size_t count) 705 { 706 unsigned int input; 707 int ret; 708 709 ret = sscanf(buf, "%u", &input); 710 if (ret != 1) 711 return -EINVAL; 712 713 update_turbo_state(); 714 if (limits->turbo_disabled) { 715 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 716 return -EPERM; 717 } 718 719 limits->no_turbo = clamp_t(int, input, 0, 1); 720 721 if (hwp_active) 722 intel_pstate_hwp_set_online_cpus(); 723 724 return count; 725 } 726 727 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 728 const char *buf, size_t count) 729 { 730 unsigned int input; 731 int ret; 732 733 ret = sscanf(buf, "%u", &input); 734 if (ret != 1) 735 return -EINVAL; 736 737 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); 738 limits->max_perf_pct = min(limits->max_policy_pct, 739 limits->max_sysfs_pct); 740 limits->max_perf_pct = max(limits->min_policy_pct, 741 limits->max_perf_pct); 742 limits->max_perf_pct = max(limits->min_perf_pct, 743 limits->max_perf_pct); 744 limits->max_perf = div_fp(limits->max_perf_pct, 100); 745 746 if (hwp_active) 747 intel_pstate_hwp_set_online_cpus(); 748 return count; 749 } 750 751 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 752 const char *buf, size_t count) 753 { 754 unsigned int input; 755 int ret; 756 757 ret = sscanf(buf, "%u", &input); 758 if (ret != 1) 759 return -EINVAL; 760 761 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); 762 limits->min_perf_pct = max(limits->min_policy_pct, 763 limits->min_sysfs_pct); 764 limits->min_perf_pct = min(limits->max_policy_pct, 765 limits->min_perf_pct); 766 limits->min_perf_pct = min(limits->max_perf_pct, 767 limits->min_perf_pct); 768 limits->min_perf = div_fp(limits->min_perf_pct, 100); 769 770 if (hwp_active) 771 intel_pstate_hwp_set_online_cpus(); 772 return count; 773 } 774 775 show_one(max_perf_pct, max_perf_pct); 776 show_one(min_perf_pct, min_perf_pct); 777 778 define_one_global_rw(no_turbo); 779 define_one_global_rw(max_perf_pct); 780 define_one_global_rw(min_perf_pct); 781 define_one_global_ro(turbo_pct); 782 define_one_global_ro(num_pstates); 783 784 static struct attribute *intel_pstate_attributes[] = { 785 &no_turbo.attr, 786 &max_perf_pct.attr, 787 &min_perf_pct.attr, 788 &turbo_pct.attr, 789 &num_pstates.attr, 790 NULL 791 }; 792 793 static struct attribute_group intel_pstate_attr_group = { 794 .attrs = intel_pstate_attributes, 795 }; 796 797 static void __init intel_pstate_sysfs_expose_params(void) 798 { 799 struct kobject *intel_pstate_kobject; 800 int rc; 801 802 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 803 &cpu_subsys.dev_root->kobj); 804 BUG_ON(!intel_pstate_kobject); 805 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 806 BUG_ON(rc); 807 } 808 /************************** sysfs end ************************/ 809 810 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 811 { 812 /* First disable HWP notification interrupt as we don't process them */ 813 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 814 815 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 816 } 817 818 static int atom_get_min_pstate(void) 819 { 820 u64 value; 821 822 rdmsrl(ATOM_RATIOS, value); 823 return (value >> 8) & 0x7F; 824 } 825 826 static int atom_get_max_pstate(void) 827 { 828 u64 value; 829 830 rdmsrl(ATOM_RATIOS, value); 831 return (value >> 16) & 0x7F; 832 } 833 834 static int atom_get_turbo_pstate(void) 835 { 836 u64 value; 837 838 rdmsrl(ATOM_TURBO_RATIOS, value); 839 return value & 0x7F; 840 } 841 842 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 843 { 844 u64 val; 845 int32_t vid_fp; 846 u32 vid; 847 848 val = (u64)pstate << 8; 849 if (limits->no_turbo && !limits->turbo_disabled) 850 val |= (u64)1 << 32; 851 852 vid_fp = cpudata->vid.min + mul_fp( 853 int_tofp(pstate - cpudata->pstate.min_pstate), 854 cpudata->vid.ratio); 855 856 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 857 vid = ceiling_fp(vid_fp); 858 859 if (pstate > cpudata->pstate.max_pstate) 860 vid = cpudata->vid.turbo; 861 862 return val | vid; 863 } 864 865 static int silvermont_get_scaling(void) 866 { 867 u64 value; 868 int i; 869 /* Defined in Table 35-6 from SDM (Sept 2015) */ 870 static int silvermont_freq_table[] = { 871 83300, 100000, 133300, 116700, 80000}; 872 873 rdmsrl(MSR_FSB_FREQ, value); 874 i = value & 0x7; 875 WARN_ON(i > 4); 876 877 return silvermont_freq_table[i]; 878 } 879 880 static int airmont_get_scaling(void) 881 { 882 u64 value; 883 int i; 884 /* Defined in Table 35-10 from SDM (Sept 2015) */ 885 static int airmont_freq_table[] = { 886 83300, 100000, 133300, 116700, 80000, 887 93300, 90000, 88900, 87500}; 888 889 rdmsrl(MSR_FSB_FREQ, value); 890 i = value & 0xF; 891 WARN_ON(i > 8); 892 893 return airmont_freq_table[i]; 894 } 895 896 static void atom_get_vid(struct cpudata *cpudata) 897 { 898 u64 value; 899 900 rdmsrl(ATOM_VIDS, value); 901 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 902 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 903 cpudata->vid.ratio = div_fp( 904 cpudata->vid.max - cpudata->vid.min, 905 int_tofp(cpudata->pstate.max_pstate - 906 cpudata->pstate.min_pstate)); 907 908 rdmsrl(ATOM_TURBO_VIDS, value); 909 cpudata->vid.turbo = value & 0x7f; 910 } 911 912 static int core_get_min_pstate(void) 913 { 914 u64 value; 915 916 rdmsrl(MSR_PLATFORM_INFO, value); 917 return (value >> 40) & 0xFF; 918 } 919 920 static int core_get_max_pstate_physical(void) 921 { 922 u64 value; 923 924 rdmsrl(MSR_PLATFORM_INFO, value); 925 return (value >> 8) & 0xFF; 926 } 927 928 static int core_get_max_pstate(void) 929 { 930 u64 tar; 931 u64 plat_info; 932 int max_pstate; 933 int err; 934 935 rdmsrl(MSR_PLATFORM_INFO, plat_info); 936 max_pstate = (plat_info >> 8) & 0xFF; 937 938 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 939 if (!err) { 940 /* Do some sanity checking for safety */ 941 if (plat_info & 0x600000000) { 942 u64 tdp_ctrl; 943 u64 tdp_ratio; 944 int tdp_msr; 945 946 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 947 if (err) 948 goto skip_tar; 949 950 tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; 951 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 952 if (err) 953 goto skip_tar; 954 955 /* For level 1 and 2, bits[23:16] contain the ratio */ 956 if (tdp_ctrl) 957 tdp_ratio >>= 16; 958 959 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 960 if (tdp_ratio - 1 == tar) { 961 max_pstate = tar; 962 pr_debug("max_pstate=TAC %x\n", max_pstate); 963 } else { 964 goto skip_tar; 965 } 966 } 967 } 968 969 skip_tar: 970 return max_pstate; 971 } 972 973 static int core_get_turbo_pstate(void) 974 { 975 u64 value; 976 int nont, ret; 977 978 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 979 nont = core_get_max_pstate(); 980 ret = (value) & 255; 981 if (ret <= nont) 982 ret = nont; 983 return ret; 984 } 985 986 static inline int core_get_scaling(void) 987 { 988 return 100000; 989 } 990 991 static u64 core_get_val(struct cpudata *cpudata, int pstate) 992 { 993 u64 val; 994 995 val = (u64)pstate << 8; 996 if (limits->no_turbo && !limits->turbo_disabled) 997 val |= (u64)1 << 32; 998 999 return val; 1000 } 1001 1002 static int knl_get_turbo_pstate(void) 1003 { 1004 u64 value; 1005 int nont, ret; 1006 1007 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 1008 nont = core_get_max_pstate(); 1009 ret = (((value) >> 8) & 0xFF); 1010 if (ret <= nont) 1011 ret = nont; 1012 return ret; 1013 } 1014 1015 static struct cpu_defaults core_params = { 1016 .pid_policy = { 1017 .sample_rate_ms = 10, 1018 .deadband = 0, 1019 .setpoint = 97, 1020 .p_gain_pct = 20, 1021 .d_gain_pct = 0, 1022 .i_gain_pct = 0, 1023 }, 1024 .funcs = { 1025 .get_max = core_get_max_pstate, 1026 .get_max_physical = core_get_max_pstate_physical, 1027 .get_min = core_get_min_pstate, 1028 .get_turbo = core_get_turbo_pstate, 1029 .get_scaling = core_get_scaling, 1030 .get_val = core_get_val, 1031 .get_target_pstate = get_target_pstate_use_performance, 1032 }, 1033 }; 1034 1035 static struct cpu_defaults silvermont_params = { 1036 .pid_policy = { 1037 .sample_rate_ms = 10, 1038 .deadband = 0, 1039 .setpoint = 60, 1040 .p_gain_pct = 14, 1041 .d_gain_pct = 0, 1042 .i_gain_pct = 4, 1043 }, 1044 .funcs = { 1045 .get_max = atom_get_max_pstate, 1046 .get_max_physical = atom_get_max_pstate, 1047 .get_min = atom_get_min_pstate, 1048 .get_turbo = atom_get_turbo_pstate, 1049 .get_val = atom_get_val, 1050 .get_scaling = silvermont_get_scaling, 1051 .get_vid = atom_get_vid, 1052 .get_target_pstate = get_target_pstate_use_cpu_load, 1053 }, 1054 }; 1055 1056 static struct cpu_defaults airmont_params = { 1057 .pid_policy = { 1058 .sample_rate_ms = 10, 1059 .deadband = 0, 1060 .setpoint = 60, 1061 .p_gain_pct = 14, 1062 .d_gain_pct = 0, 1063 .i_gain_pct = 4, 1064 }, 1065 .funcs = { 1066 .get_max = atom_get_max_pstate, 1067 .get_max_physical = atom_get_max_pstate, 1068 .get_min = atom_get_min_pstate, 1069 .get_turbo = atom_get_turbo_pstate, 1070 .get_val = atom_get_val, 1071 .get_scaling = airmont_get_scaling, 1072 .get_vid = atom_get_vid, 1073 .get_target_pstate = get_target_pstate_use_cpu_load, 1074 }, 1075 }; 1076 1077 static struct cpu_defaults knl_params = { 1078 .pid_policy = { 1079 .sample_rate_ms = 10, 1080 .deadband = 0, 1081 .setpoint = 97, 1082 .p_gain_pct = 20, 1083 .d_gain_pct = 0, 1084 .i_gain_pct = 0, 1085 }, 1086 .funcs = { 1087 .get_max = core_get_max_pstate, 1088 .get_max_physical = core_get_max_pstate_physical, 1089 .get_min = core_get_min_pstate, 1090 .get_turbo = knl_get_turbo_pstate, 1091 .get_scaling = core_get_scaling, 1092 .get_val = core_get_val, 1093 .get_target_pstate = get_target_pstate_use_performance, 1094 }, 1095 }; 1096 1097 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1098 { 1099 int max_perf = cpu->pstate.turbo_pstate; 1100 int max_perf_adj; 1101 int min_perf; 1102 1103 if (limits->no_turbo || limits->turbo_disabled) 1104 max_perf = cpu->pstate.max_pstate; 1105 1106 /* 1107 * performance can be limited by user through sysfs, by cpufreq 1108 * policy, or by cpu specific default values determined through 1109 * experimentation. 1110 */ 1111 max_perf_adj = fp_toint(max_perf * limits->max_perf); 1112 *max = clamp_t(int, max_perf_adj, 1113 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1114 1115 min_perf = fp_toint(max_perf * limits->min_perf); 1116 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1117 } 1118 1119 static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate) 1120 { 1121 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1122 cpu->pstate.current_pstate = pstate; 1123 } 1124 1125 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1126 { 1127 int pstate = cpu->pstate.min_pstate; 1128 1129 intel_pstate_record_pstate(cpu, pstate); 1130 /* 1131 * Generally, there is no guarantee that this code will always run on 1132 * the CPU being updated, so force the register update to run on the 1133 * right CPU. 1134 */ 1135 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1136 pstate_funcs.get_val(cpu, pstate)); 1137 } 1138 1139 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1140 { 1141 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1142 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1143 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1144 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1145 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1146 1147 if (pstate_funcs.get_vid) 1148 pstate_funcs.get_vid(cpu); 1149 1150 intel_pstate_set_min_pstate(cpu); 1151 } 1152 1153 static inline void intel_pstate_calc_busy(struct cpudata *cpu) 1154 { 1155 struct sample *sample = &cpu->sample; 1156 int64_t core_pct; 1157 1158 core_pct = sample->aperf * int_tofp(100); 1159 core_pct = div64_u64(core_pct, sample->mperf); 1160 1161 sample->core_pct_busy = (int32_t)core_pct; 1162 } 1163 1164 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1165 { 1166 u64 aperf, mperf; 1167 unsigned long flags; 1168 u64 tsc; 1169 1170 local_irq_save(flags); 1171 rdmsrl(MSR_IA32_APERF, aperf); 1172 rdmsrl(MSR_IA32_MPERF, mperf); 1173 tsc = rdtsc(); 1174 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1175 local_irq_restore(flags); 1176 return false; 1177 } 1178 local_irq_restore(flags); 1179 1180 cpu->last_sample_time = cpu->sample.time; 1181 cpu->sample.time = time; 1182 cpu->sample.aperf = aperf; 1183 cpu->sample.mperf = mperf; 1184 cpu->sample.tsc = tsc; 1185 cpu->sample.aperf -= cpu->prev_aperf; 1186 cpu->sample.mperf -= cpu->prev_mperf; 1187 cpu->sample.tsc -= cpu->prev_tsc; 1188 1189 cpu->prev_aperf = aperf; 1190 cpu->prev_mperf = mperf; 1191 cpu->prev_tsc = tsc; 1192 /* 1193 * First time this function is invoked in a given cycle, all of the 1194 * previous sample data fields are equal to zero or stale and they must 1195 * be populated with meaningful numbers for things to work, so assume 1196 * that sample.time will always be reset before setting the utilization 1197 * update hook and make the caller skip the sample then. 1198 */ 1199 return !!cpu->last_sample_time; 1200 } 1201 1202 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1203 { 1204 return fp_toint(mul_fp(cpu->sample.core_pct_busy, 1205 int_tofp(cpu->pstate.max_pstate_physical * 1206 cpu->pstate.scaling / 100))); 1207 } 1208 1209 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1210 { 1211 return div64_u64(cpu->pstate.max_pstate_physical * cpu->sample.aperf, 1212 cpu->sample.mperf); 1213 } 1214 1215 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1216 { 1217 struct sample *sample = &cpu->sample; 1218 u64 cummulative_iowait, delta_iowait_us; 1219 u64 delta_iowait_mperf; 1220 u64 mperf, now; 1221 int32_t cpu_load; 1222 1223 cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now); 1224 1225 /* 1226 * Convert iowait time into number of IO cycles spent at max_freq. 1227 * IO is considered as busy only for the cpu_load algorithm. For 1228 * performance this is not needed since we always try to reach the 1229 * maximum P-State, so we are already boosting the IOs. 1230 */ 1231 delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait; 1232 delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling * 1233 cpu->pstate.max_pstate, MSEC_PER_SEC); 1234 1235 mperf = cpu->sample.mperf + delta_iowait_mperf; 1236 cpu->prev_cummulative_iowait = cummulative_iowait; 1237 1238 /* 1239 * The load can be estimated as the ratio of the mperf counter 1240 * running at a constant frequency during active periods 1241 * (C0) and the time stamp counter running at the same frequency 1242 * also during C-states. 1243 */ 1244 cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc); 1245 cpu->sample.busy_scaled = cpu_load; 1246 1247 return get_avg_pstate(cpu) - pid_calc(&cpu->pid, cpu_load); 1248 } 1249 1250 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1251 { 1252 int32_t core_busy, max_pstate, current_pstate, sample_ratio; 1253 u64 duration_ns; 1254 1255 /* 1256 * core_busy is the ratio of actual performance to max 1257 * max_pstate is the max non turbo pstate available 1258 * current_pstate was the pstate that was requested during 1259 * the last sample period. 1260 * 1261 * We normalize core_busy, which was our actual percent 1262 * performance to what we requested during the last sample 1263 * period. The result will be a percentage of busy at a 1264 * specified pstate. 1265 */ 1266 core_busy = cpu->sample.core_pct_busy; 1267 max_pstate = cpu->pstate.max_pstate_physical; 1268 current_pstate = cpu->pstate.current_pstate; 1269 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); 1270 1271 /* 1272 * Since our utilization update callback will not run unless we are 1273 * in C0, check if the actual elapsed time is significantly greater (3x) 1274 * than our sample interval. If it is, then we were idle for a long 1275 * enough period of time to adjust our busyness. 1276 */ 1277 duration_ns = cpu->sample.time - cpu->last_sample_time; 1278 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1279 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1280 core_busy = mul_fp(core_busy, sample_ratio); 1281 } else { 1282 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1283 if (sample_ratio < int_tofp(1)) 1284 core_busy = 0; 1285 } 1286 1287 cpu->sample.busy_scaled = core_busy; 1288 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, core_busy); 1289 } 1290 1291 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1292 { 1293 int max_perf, min_perf; 1294 1295 update_turbo_state(); 1296 1297 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1298 pstate = clamp_t(int, pstate, min_perf, max_perf); 1299 if (pstate == cpu->pstate.current_pstate) 1300 return; 1301 1302 intel_pstate_record_pstate(cpu, pstate); 1303 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1304 } 1305 1306 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1307 { 1308 int from, target_pstate; 1309 struct sample *sample; 1310 1311 from = cpu->pstate.current_pstate; 1312 1313 target_pstate = pstate_funcs.get_target_pstate(cpu); 1314 1315 intel_pstate_update_pstate(cpu, target_pstate); 1316 1317 sample = &cpu->sample; 1318 trace_pstate_sample(fp_toint(sample->core_pct_busy), 1319 fp_toint(sample->busy_scaled), 1320 from, 1321 cpu->pstate.current_pstate, 1322 sample->mperf, 1323 sample->aperf, 1324 sample->tsc, 1325 get_avg_frequency(cpu)); 1326 } 1327 1328 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1329 unsigned long util, unsigned long max) 1330 { 1331 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1332 u64 delta_ns = time - cpu->sample.time; 1333 1334 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1335 bool sample_taken = intel_pstate_sample(cpu, time); 1336 1337 if (sample_taken) { 1338 intel_pstate_calc_busy(cpu); 1339 if (!hwp_active) 1340 intel_pstate_adjust_busy_pstate(cpu); 1341 } 1342 } 1343 } 1344 1345 #define ICPU(model, policy) \ 1346 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1347 (unsigned long)&policy } 1348 1349 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1350 ICPU(0x2a, core_params), 1351 ICPU(0x2d, core_params), 1352 ICPU(0x37, silvermont_params), 1353 ICPU(0x3a, core_params), 1354 ICPU(0x3c, core_params), 1355 ICPU(0x3d, core_params), 1356 ICPU(0x3e, core_params), 1357 ICPU(0x3f, core_params), 1358 ICPU(0x45, core_params), 1359 ICPU(0x46, core_params), 1360 ICPU(0x47, core_params), 1361 ICPU(0x4c, airmont_params), 1362 ICPU(0x4e, core_params), 1363 ICPU(0x4f, core_params), 1364 ICPU(0x5e, core_params), 1365 ICPU(0x56, core_params), 1366 ICPU(0x57, knl_params), 1367 {} 1368 }; 1369 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1370 1371 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { 1372 ICPU(0x56, core_params), 1373 {} 1374 }; 1375 1376 static int intel_pstate_init_cpu(unsigned int cpunum) 1377 { 1378 struct cpudata *cpu; 1379 1380 if (!all_cpu_data[cpunum]) 1381 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), 1382 GFP_KERNEL); 1383 if (!all_cpu_data[cpunum]) 1384 return -ENOMEM; 1385 1386 cpu = all_cpu_data[cpunum]; 1387 1388 cpu->cpu = cpunum; 1389 1390 if (hwp_active) { 1391 intel_pstate_hwp_enable(cpu); 1392 pid_params.sample_rate_ms = 50; 1393 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1394 } 1395 1396 intel_pstate_get_cpu_pstates(cpu); 1397 1398 intel_pstate_busy_pid_reset(cpu); 1399 1400 pr_debug("controlling: cpu %d\n", cpunum); 1401 1402 return 0; 1403 } 1404 1405 static unsigned int intel_pstate_get(unsigned int cpu_num) 1406 { 1407 struct cpudata *cpu = all_cpu_data[cpu_num]; 1408 1409 return cpu ? get_avg_frequency(cpu) : 0; 1410 } 1411 1412 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1413 { 1414 struct cpudata *cpu = all_cpu_data[cpu_num]; 1415 1416 /* Prevent intel_pstate_update_util() from using stale data. */ 1417 cpu->sample.time = 0; 1418 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1419 intel_pstate_update_util); 1420 } 1421 1422 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1423 { 1424 cpufreq_remove_update_util_hook(cpu); 1425 synchronize_sched(); 1426 } 1427 1428 static void intel_pstate_set_performance_limits(struct perf_limits *limits) 1429 { 1430 limits->no_turbo = 0; 1431 limits->turbo_disabled = 0; 1432 limits->max_perf_pct = 100; 1433 limits->max_perf = int_tofp(1); 1434 limits->min_perf_pct = 100; 1435 limits->min_perf = int_tofp(1); 1436 limits->max_policy_pct = 100; 1437 limits->max_sysfs_pct = 100; 1438 limits->min_policy_pct = 0; 1439 limits->min_sysfs_pct = 0; 1440 } 1441 1442 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1443 { 1444 struct cpudata *cpu; 1445 1446 if (!policy->cpuinfo.max_freq) 1447 return -ENODEV; 1448 1449 intel_pstate_clear_update_util_hook(policy->cpu); 1450 1451 cpu = all_cpu_data[0]; 1452 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate) { 1453 if (policy->max < policy->cpuinfo.max_freq && 1454 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 1455 pr_debug("policy->max > max non turbo frequency\n"); 1456 policy->max = policy->cpuinfo.max_freq; 1457 } 1458 } 1459 1460 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 1461 limits = &performance_limits; 1462 if (policy->max >= policy->cpuinfo.max_freq) { 1463 pr_debug("set performance\n"); 1464 intel_pstate_set_performance_limits(limits); 1465 goto out; 1466 } 1467 } else { 1468 pr_debug("set powersave\n"); 1469 limits = &powersave_limits; 1470 } 1471 1472 limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 1473 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); 1474 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, 1475 policy->cpuinfo.max_freq); 1476 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); 1477 1478 /* Normalize user input to [min_policy_pct, max_policy_pct] */ 1479 limits->min_perf_pct = max(limits->min_policy_pct, 1480 limits->min_sysfs_pct); 1481 limits->min_perf_pct = min(limits->max_policy_pct, 1482 limits->min_perf_pct); 1483 limits->max_perf_pct = min(limits->max_policy_pct, 1484 limits->max_sysfs_pct); 1485 limits->max_perf_pct = max(limits->min_policy_pct, 1486 limits->max_perf_pct); 1487 limits->max_perf = round_up(limits->max_perf, FRAC_BITS); 1488 1489 /* Make sure min_perf_pct <= max_perf_pct */ 1490 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); 1491 1492 limits->min_perf = div_fp(limits->min_perf_pct, 100); 1493 limits->max_perf = div_fp(limits->max_perf_pct, 100); 1494 1495 out: 1496 intel_pstate_set_update_util_hook(policy->cpu); 1497 1498 intel_pstate_hwp_set_policy(policy); 1499 1500 return 0; 1501 } 1502 1503 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 1504 { 1505 cpufreq_verify_within_cpu_limits(policy); 1506 1507 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 1508 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 1509 return -EINVAL; 1510 1511 return 0; 1512 } 1513 1514 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 1515 { 1516 int cpu_num = policy->cpu; 1517 struct cpudata *cpu = all_cpu_data[cpu_num]; 1518 1519 pr_debug("CPU %d exiting\n", cpu_num); 1520 1521 intel_pstate_clear_update_util_hook(cpu_num); 1522 1523 if (hwp_active) 1524 return; 1525 1526 intel_pstate_set_min_pstate(cpu); 1527 } 1528 1529 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 1530 { 1531 struct cpudata *cpu; 1532 int rc; 1533 1534 rc = intel_pstate_init_cpu(policy->cpu); 1535 if (rc) 1536 return rc; 1537 1538 cpu = all_cpu_data[policy->cpu]; 1539 1540 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) 1541 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1542 else 1543 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1544 1545 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 1546 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1547 1548 /* cpuinfo and default policy values */ 1549 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1550 policy->cpuinfo.max_freq = 1551 cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1552 intel_pstate_init_acpi_perf_limits(policy); 1553 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1554 cpumask_set_cpu(policy->cpu, policy->cpus); 1555 1556 return 0; 1557 } 1558 1559 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 1560 { 1561 intel_pstate_exit_perf_limits(policy); 1562 1563 return 0; 1564 } 1565 1566 static struct cpufreq_driver intel_pstate_driver = { 1567 .flags = CPUFREQ_CONST_LOOPS, 1568 .verify = intel_pstate_verify_policy, 1569 .setpolicy = intel_pstate_set_policy, 1570 .resume = intel_pstate_hwp_set_policy, 1571 .get = intel_pstate_get, 1572 .init = intel_pstate_cpu_init, 1573 .exit = intel_pstate_cpu_exit, 1574 .stop_cpu = intel_pstate_stop_cpu, 1575 .name = "intel_pstate", 1576 }; 1577 1578 static int __initdata no_load; 1579 static int __initdata no_hwp; 1580 static int __initdata hwp_only; 1581 static unsigned int force_load; 1582 1583 static int intel_pstate_msrs_not_valid(void) 1584 { 1585 if (!pstate_funcs.get_max() || 1586 !pstate_funcs.get_min() || 1587 !pstate_funcs.get_turbo()) 1588 return -ENODEV; 1589 1590 return 0; 1591 } 1592 1593 static void copy_pid_params(struct pstate_adjust_policy *policy) 1594 { 1595 pid_params.sample_rate_ms = policy->sample_rate_ms; 1596 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 1597 pid_params.p_gain_pct = policy->p_gain_pct; 1598 pid_params.i_gain_pct = policy->i_gain_pct; 1599 pid_params.d_gain_pct = policy->d_gain_pct; 1600 pid_params.deadband = policy->deadband; 1601 pid_params.setpoint = policy->setpoint; 1602 } 1603 1604 static void copy_cpu_funcs(struct pstate_funcs *funcs) 1605 { 1606 pstate_funcs.get_max = funcs->get_max; 1607 pstate_funcs.get_max_physical = funcs->get_max_physical; 1608 pstate_funcs.get_min = funcs->get_min; 1609 pstate_funcs.get_turbo = funcs->get_turbo; 1610 pstate_funcs.get_scaling = funcs->get_scaling; 1611 pstate_funcs.get_val = funcs->get_val; 1612 pstate_funcs.get_vid = funcs->get_vid; 1613 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 1614 1615 } 1616 1617 #ifdef CONFIG_ACPI 1618 1619 static bool intel_pstate_no_acpi_pss(void) 1620 { 1621 int i; 1622 1623 for_each_possible_cpu(i) { 1624 acpi_status status; 1625 union acpi_object *pss; 1626 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1627 struct acpi_processor *pr = per_cpu(processors, i); 1628 1629 if (!pr) 1630 continue; 1631 1632 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1633 if (ACPI_FAILURE(status)) 1634 continue; 1635 1636 pss = buffer.pointer; 1637 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1638 kfree(pss); 1639 return false; 1640 } 1641 1642 kfree(pss); 1643 } 1644 1645 return true; 1646 } 1647 1648 static bool intel_pstate_has_acpi_ppc(void) 1649 { 1650 int i; 1651 1652 for_each_possible_cpu(i) { 1653 struct acpi_processor *pr = per_cpu(processors, i); 1654 1655 if (!pr) 1656 continue; 1657 if (acpi_has_method(pr->handle, "_PPC")) 1658 return true; 1659 } 1660 return false; 1661 } 1662 1663 enum { 1664 PSS, 1665 PPC, 1666 }; 1667 1668 struct hw_vendor_info { 1669 u16 valid; 1670 char oem_id[ACPI_OEM_ID_SIZE]; 1671 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1672 int oem_pwr_table; 1673 }; 1674 1675 /* Hardware vendor-specific info that has its own power management modes */ 1676 static struct hw_vendor_info vendor_info[] = { 1677 {1, "HP ", "ProLiant", PSS}, 1678 {1, "ORACLE", "X4-2 ", PPC}, 1679 {1, "ORACLE", "X4-2L ", PPC}, 1680 {1, "ORACLE", "X4-2B ", PPC}, 1681 {1, "ORACLE", "X3-2 ", PPC}, 1682 {1, "ORACLE", "X3-2L ", PPC}, 1683 {1, "ORACLE", "X3-2B ", PPC}, 1684 {1, "ORACLE", "X4470M2 ", PPC}, 1685 {1, "ORACLE", "X4270M3 ", PPC}, 1686 {1, "ORACLE", "X4270M2 ", PPC}, 1687 {1, "ORACLE", "X4170M2 ", PPC}, 1688 {1, "ORACLE", "X4170 M3", PPC}, 1689 {1, "ORACLE", "X4275 M3", PPC}, 1690 {1, "ORACLE", "X6-2 ", PPC}, 1691 {1, "ORACLE", "Sudbury ", PPC}, 1692 {0, "", ""}, 1693 }; 1694 1695 static bool intel_pstate_platform_pwr_mgmt_exists(void) 1696 { 1697 struct acpi_table_header hdr; 1698 struct hw_vendor_info *v_info; 1699 const struct x86_cpu_id *id; 1700 u64 misc_pwr; 1701 1702 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1703 if (id) { 1704 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1705 if ( misc_pwr & (1 << 8)) 1706 return true; 1707 } 1708 1709 if (acpi_disabled || 1710 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1711 return false; 1712 1713 for (v_info = vendor_info; v_info->valid; v_info++) { 1714 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1715 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1716 ACPI_OEM_TABLE_ID_SIZE)) 1717 switch (v_info->oem_pwr_table) { 1718 case PSS: 1719 return intel_pstate_no_acpi_pss(); 1720 case PPC: 1721 return intel_pstate_has_acpi_ppc() && 1722 (!force_load); 1723 } 1724 } 1725 1726 return false; 1727 } 1728 #else /* CONFIG_ACPI not enabled */ 1729 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1730 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1731 #endif /* CONFIG_ACPI */ 1732 1733 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 1734 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 1735 {} 1736 }; 1737 1738 static int __init intel_pstate_init(void) 1739 { 1740 int cpu, rc = 0; 1741 const struct x86_cpu_id *id; 1742 struct cpu_defaults *cpu_def; 1743 1744 if (no_load) 1745 return -ENODEV; 1746 1747 if (x86_match_cpu(hwp_support_ids) && !no_hwp) { 1748 copy_cpu_funcs(&core_params.funcs); 1749 hwp_active++; 1750 goto hwp_cpu_matched; 1751 } 1752 1753 id = x86_match_cpu(intel_pstate_cpu_ids); 1754 if (!id) 1755 return -ENODEV; 1756 1757 cpu_def = (struct cpu_defaults *)id->driver_data; 1758 1759 copy_pid_params(&cpu_def->pid_policy); 1760 copy_cpu_funcs(&cpu_def->funcs); 1761 1762 if (intel_pstate_msrs_not_valid()) 1763 return -ENODEV; 1764 1765 hwp_cpu_matched: 1766 /* 1767 * The Intel pstate driver will be ignored if the platform 1768 * firmware has its own power management modes. 1769 */ 1770 if (intel_pstate_platform_pwr_mgmt_exists()) 1771 return -ENODEV; 1772 1773 pr_info("Intel P-state driver initializing\n"); 1774 1775 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1776 if (!all_cpu_data) 1777 return -ENOMEM; 1778 1779 if (!hwp_active && hwp_only) 1780 goto out; 1781 1782 rc = cpufreq_register_driver(&intel_pstate_driver); 1783 if (rc) 1784 goto out; 1785 1786 intel_pstate_debug_expose_params(); 1787 intel_pstate_sysfs_expose_params(); 1788 1789 if (hwp_active) 1790 pr_info("HWP enabled\n"); 1791 1792 return rc; 1793 out: 1794 get_online_cpus(); 1795 for_each_online_cpu(cpu) { 1796 if (all_cpu_data[cpu]) { 1797 intel_pstate_clear_update_util_hook(cpu); 1798 kfree(all_cpu_data[cpu]); 1799 } 1800 } 1801 1802 put_online_cpus(); 1803 vfree(all_cpu_data); 1804 return -ENODEV; 1805 } 1806 device_initcall(intel_pstate_init); 1807 1808 static int __init intel_pstate_setup(char *str) 1809 { 1810 if (!str) 1811 return -EINVAL; 1812 1813 if (!strcmp(str, "disable")) 1814 no_load = 1; 1815 if (!strcmp(str, "no_hwp")) { 1816 pr_info("HWP disabled\n"); 1817 no_hwp = 1; 1818 } 1819 if (!strcmp(str, "force")) 1820 force_load = 1; 1821 if (!strcmp(str, "hwp_only")) 1822 hwp_only = 1; 1823 1824 #ifdef CONFIG_ACPI 1825 if (!strcmp(str, "support_acpi_ppc")) 1826 acpi_ppc = true; 1827 #endif 1828 1829 return 0; 1830 } 1831 early_param("intel_pstate", intel_pstate_setup); 1832 1833 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1834 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1835 MODULE_LICENSE("GPL"); 1836