1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 40 #define ATOM_RATIOS 0x66a 41 #define ATOM_VIDS 0x66b 42 #define ATOM_TURBO_RATIOS 0x66c 43 #define ATOM_TURBO_VIDS 0x66d 44 45 #ifdef CONFIG_ACPI 46 #include <acpi/processor.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define EXT_BITS 6 54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 55 56 static inline int32_t mul_fp(int32_t x, int32_t y) 57 { 58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 59 } 60 61 static inline int32_t div_fp(s64 x, s64 y) 62 { 63 return div64_s64((int64_t)x << FRAC_BITS, y); 64 } 65 66 static inline int ceiling_fp(int32_t x) 67 { 68 int mask, ret; 69 70 ret = fp_toint(x); 71 mask = (1 << FRAC_BITS) - 1; 72 if (x & mask) 73 ret += 1; 74 return ret; 75 } 76 77 static inline u64 mul_ext_fp(u64 x, u64 y) 78 { 79 return (x * y) >> EXT_FRAC_BITS; 80 } 81 82 static inline u64 div_ext_fp(u64 x, u64 y) 83 { 84 return div64_u64(x << EXT_FRAC_BITS, y); 85 } 86 87 /** 88 * struct sample - Store performance sample 89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 90 * performance during last sample period 91 * @busy_scaled: Scaled busy value which is used to calculate next 92 * P state. This can be different than core_avg_perf 93 * to account for cpu idle period 94 * @aperf: Difference of actual performance frequency clock count 95 * read from APERF MSR between last and current sample 96 * @mperf: Difference of maximum performance frequency clock count 97 * read from MPERF MSR between last and current sample 98 * @tsc: Difference of time stamp counter between last and 99 * current sample 100 * @freq: Effective frequency calculated from APERF/MPERF 101 * @time: Current time from scheduler 102 * 103 * This structure is used in the cpudata structure to store performance sample 104 * data for choosing next P State. 105 */ 106 struct sample { 107 int32_t core_avg_perf; 108 int32_t busy_scaled; 109 u64 aperf; 110 u64 mperf; 111 u64 tsc; 112 int freq; 113 u64 time; 114 }; 115 116 /** 117 * struct pstate_data - Store P state data 118 * @current_pstate: Current requested P state 119 * @min_pstate: Min P state possible for this platform 120 * @max_pstate: Max P state possible for this platform 121 * @max_pstate_physical:This is physical Max P state for a processor 122 * This can be higher than the max_pstate which can 123 * be limited by platform thermal design power limits 124 * @scaling: Scaling factor to convert frequency to cpufreq 125 * frequency units 126 * @turbo_pstate: Max Turbo P state possible for this platform 127 * 128 * Stores the per cpu model P state limits and current P state. 129 */ 130 struct pstate_data { 131 int current_pstate; 132 int min_pstate; 133 int max_pstate; 134 int max_pstate_physical; 135 int scaling; 136 int turbo_pstate; 137 }; 138 139 /** 140 * struct vid_data - Stores voltage information data 141 * @min: VID data for this platform corresponding to 142 * the lowest P state 143 * @max: VID data corresponding to the highest P State. 144 * @turbo: VID data for turbo P state 145 * @ratio: Ratio of (vid max - vid min) / 146 * (max P state - Min P State) 147 * 148 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 149 * This data is used in Atom platforms, where in addition to target P state, 150 * the voltage data needs to be specified to select next P State. 151 */ 152 struct vid_data { 153 int min; 154 int max; 155 int turbo; 156 int32_t ratio; 157 }; 158 159 /** 160 * struct _pid - Stores PID data 161 * @setpoint: Target set point for busyness or performance 162 * @integral: Storage for accumulated error values 163 * @p_gain: PID proportional gain 164 * @i_gain: PID integral gain 165 * @d_gain: PID derivative gain 166 * @deadband: PID deadband 167 * @last_err: Last error storage for integral part of PID calculation 168 * 169 * Stores PID coefficients and last error for PID controller. 170 */ 171 struct _pid { 172 int setpoint; 173 int32_t integral; 174 int32_t p_gain; 175 int32_t i_gain; 176 int32_t d_gain; 177 int deadband; 178 int32_t last_err; 179 }; 180 181 /** 182 * struct cpudata - Per CPU instance data storage 183 * @cpu: CPU number for this instance data 184 * @update_util: CPUFreq utility callback information 185 * @update_util_set: CPUFreq utility callback is set 186 * @pstate: Stores P state limits for this CPU 187 * @vid: Stores VID limits for this CPU 188 * @pid: Stores PID parameters for this CPU 189 * @last_sample_time: Last Sample time 190 * @prev_aperf: Last APERF value read from APERF MSR 191 * @prev_mperf: Last MPERF value read from MPERF MSR 192 * @prev_tsc: Last timestamp counter (TSC) value 193 * @prev_cummulative_iowait: IO Wait time difference from last and 194 * current sample 195 * @sample: Storage for storing last Sample data 196 * @acpi_perf_data: Stores ACPI perf information read from _PSS 197 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 198 * 199 * This structure stores per CPU instance data for all CPUs. 200 */ 201 struct cpudata { 202 int cpu; 203 204 struct update_util_data update_util; 205 bool update_util_set; 206 207 struct pstate_data pstate; 208 struct vid_data vid; 209 struct _pid pid; 210 211 u64 last_sample_time; 212 u64 prev_aperf; 213 u64 prev_mperf; 214 u64 prev_tsc; 215 u64 prev_cummulative_iowait; 216 struct sample sample; 217 #ifdef CONFIG_ACPI 218 struct acpi_processor_performance acpi_perf_data; 219 bool valid_pss_table; 220 #endif 221 }; 222 223 static struct cpudata **all_cpu_data; 224 225 /** 226 * struct pid_adjust_policy - Stores static PID configuration data 227 * @sample_rate_ms: PID calculation sample rate in ms 228 * @sample_rate_ns: Sample rate calculation in ns 229 * @deadband: PID deadband 230 * @setpoint: PID Setpoint 231 * @p_gain_pct: PID proportional gain 232 * @i_gain_pct: PID integral gain 233 * @d_gain_pct: PID derivative gain 234 * 235 * Stores per CPU model static PID configuration data. 236 */ 237 struct pstate_adjust_policy { 238 int sample_rate_ms; 239 s64 sample_rate_ns; 240 int deadband; 241 int setpoint; 242 int p_gain_pct; 243 int d_gain_pct; 244 int i_gain_pct; 245 }; 246 247 /** 248 * struct pstate_funcs - Per CPU model specific callbacks 249 * @get_max: Callback to get maximum non turbo effective P state 250 * @get_max_physical: Callback to get maximum non turbo physical P state 251 * @get_min: Callback to get minimum P state 252 * @get_turbo: Callback to get turbo P state 253 * @get_scaling: Callback to get frequency scaling factor 254 * @get_val: Callback to convert P state to actual MSR write value 255 * @get_vid: Callback to get VID data for Atom platforms 256 * @get_target_pstate: Callback to a function to calculate next P state to use 257 * 258 * Core and Atom CPU models have different way to get P State limits. This 259 * structure is used to store those callbacks. 260 */ 261 struct pstate_funcs { 262 int (*get_max)(void); 263 int (*get_max_physical)(void); 264 int (*get_min)(void); 265 int (*get_turbo)(void); 266 int (*get_scaling)(void); 267 u64 (*get_val)(struct cpudata*, int pstate); 268 void (*get_vid)(struct cpudata *); 269 int32_t (*get_target_pstate)(struct cpudata *); 270 }; 271 272 /** 273 * struct cpu_defaults- Per CPU model default config data 274 * @pid_policy: PID config data 275 * @funcs: Callback function data 276 */ 277 struct cpu_defaults { 278 struct pstate_adjust_policy pid_policy; 279 struct pstate_funcs funcs; 280 }; 281 282 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 283 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 284 285 static struct pstate_adjust_policy pid_params; 286 static struct pstate_funcs pstate_funcs; 287 static int hwp_active; 288 289 #ifdef CONFIG_ACPI 290 static bool acpi_ppc; 291 #endif 292 293 /** 294 * struct perf_limits - Store user and policy limits 295 * @no_turbo: User requested turbo state from intel_pstate sysfs 296 * @turbo_disabled: Platform turbo status either from msr 297 * MSR_IA32_MISC_ENABLE or when maximum available pstate 298 * matches the maximum turbo pstate 299 * @max_perf_pct: Effective maximum performance limit in percentage, this 300 * is minimum of either limits enforced by cpufreq policy 301 * or limits from user set limits via intel_pstate sysfs 302 * @min_perf_pct: Effective minimum performance limit in percentage, this 303 * is maximum of either limits enforced by cpufreq policy 304 * or limits from user set limits via intel_pstate sysfs 305 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 306 * This value is used to limit max pstate 307 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 308 * This value is used to limit min pstate 309 * @max_policy_pct: The maximum performance in percentage enforced by 310 * cpufreq setpolicy interface 311 * @max_sysfs_pct: The maximum performance in percentage enforced by 312 * intel pstate sysfs interface 313 * @min_policy_pct: The minimum performance in percentage enforced by 314 * cpufreq setpolicy interface 315 * @min_sysfs_pct: The minimum performance in percentage enforced by 316 * intel pstate sysfs interface 317 * 318 * Storage for user and policy defined limits. 319 */ 320 struct perf_limits { 321 int no_turbo; 322 int turbo_disabled; 323 int max_perf_pct; 324 int min_perf_pct; 325 int32_t max_perf; 326 int32_t min_perf; 327 int max_policy_pct; 328 int max_sysfs_pct; 329 int min_policy_pct; 330 int min_sysfs_pct; 331 }; 332 333 static struct perf_limits performance_limits = { 334 .no_turbo = 0, 335 .turbo_disabled = 0, 336 .max_perf_pct = 100, 337 .max_perf = int_tofp(1), 338 .min_perf_pct = 100, 339 .min_perf = int_tofp(1), 340 .max_policy_pct = 100, 341 .max_sysfs_pct = 100, 342 .min_policy_pct = 0, 343 .min_sysfs_pct = 0, 344 }; 345 346 static struct perf_limits powersave_limits = { 347 .no_turbo = 0, 348 .turbo_disabled = 0, 349 .max_perf_pct = 100, 350 .max_perf = int_tofp(1), 351 .min_perf_pct = 0, 352 .min_perf = 0, 353 .max_policy_pct = 100, 354 .max_sysfs_pct = 100, 355 .min_policy_pct = 0, 356 .min_sysfs_pct = 0, 357 }; 358 359 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 360 static struct perf_limits *limits = &performance_limits; 361 #else 362 static struct perf_limits *limits = &powersave_limits; 363 #endif 364 365 #ifdef CONFIG_ACPI 366 367 static bool intel_pstate_get_ppc_enable_status(void) 368 { 369 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 370 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 371 return true; 372 373 return acpi_ppc; 374 } 375 376 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 377 { 378 struct cpudata *cpu; 379 int ret; 380 int i; 381 382 if (hwp_active) 383 return; 384 385 if (!intel_pstate_get_ppc_enable_status()) 386 return; 387 388 cpu = all_cpu_data[policy->cpu]; 389 390 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 391 policy->cpu); 392 if (ret) 393 return; 394 395 /* 396 * Check if the control value in _PSS is for PERF_CTL MSR, which should 397 * guarantee that the states returned by it map to the states in our 398 * list directly. 399 */ 400 if (cpu->acpi_perf_data.control_register.space_id != 401 ACPI_ADR_SPACE_FIXED_HARDWARE) 402 goto err; 403 404 /* 405 * If there is only one entry _PSS, simply ignore _PSS and continue as 406 * usual without taking _PSS into account 407 */ 408 if (cpu->acpi_perf_data.state_count < 2) 409 goto err; 410 411 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 412 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 413 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 414 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 415 (u32) cpu->acpi_perf_data.states[i].core_frequency, 416 (u32) cpu->acpi_perf_data.states[i].power, 417 (u32) cpu->acpi_perf_data.states[i].control); 418 } 419 420 /* 421 * The _PSS table doesn't contain whole turbo frequency range. 422 * This just contains +1 MHZ above the max non turbo frequency, 423 * with control value corresponding to max turbo ratio. But 424 * when cpufreq set policy is called, it will call with this 425 * max frequency, which will cause a reduced performance as 426 * this driver uses real max turbo frequency as the max 427 * frequency. So correct this frequency in _PSS table to 428 * correct max turbo frequency based on the turbo state. 429 * Also need to convert to MHz as _PSS freq is in MHz. 430 */ 431 if (!limits->turbo_disabled) 432 cpu->acpi_perf_data.states[0].core_frequency = 433 policy->cpuinfo.max_freq / 1000; 434 cpu->valid_pss_table = true; 435 pr_debug("_PPC limits will be enforced\n"); 436 437 return; 438 439 err: 440 cpu->valid_pss_table = false; 441 acpi_processor_unregister_performance(policy->cpu); 442 } 443 444 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 445 { 446 struct cpudata *cpu; 447 448 cpu = all_cpu_data[policy->cpu]; 449 if (!cpu->valid_pss_table) 450 return; 451 452 acpi_processor_unregister_performance(policy->cpu); 453 } 454 455 #else 456 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 457 { 458 } 459 460 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 461 { 462 } 463 #endif 464 465 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 466 int deadband, int integral) { 467 pid->setpoint = int_tofp(setpoint); 468 pid->deadband = int_tofp(deadband); 469 pid->integral = int_tofp(integral); 470 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 471 } 472 473 static inline void pid_p_gain_set(struct _pid *pid, int percent) 474 { 475 pid->p_gain = div_fp(percent, 100); 476 } 477 478 static inline void pid_i_gain_set(struct _pid *pid, int percent) 479 { 480 pid->i_gain = div_fp(percent, 100); 481 } 482 483 static inline void pid_d_gain_set(struct _pid *pid, int percent) 484 { 485 pid->d_gain = div_fp(percent, 100); 486 } 487 488 static signed int pid_calc(struct _pid *pid, int32_t busy) 489 { 490 signed int result; 491 int32_t pterm, dterm, fp_error; 492 int32_t integral_limit; 493 494 fp_error = pid->setpoint - busy; 495 496 if (abs(fp_error) <= pid->deadband) 497 return 0; 498 499 pterm = mul_fp(pid->p_gain, fp_error); 500 501 pid->integral += fp_error; 502 503 /* 504 * We limit the integral here so that it will never 505 * get higher than 30. This prevents it from becoming 506 * too large an input over long periods of time and allows 507 * it to get factored out sooner. 508 * 509 * The value of 30 was chosen through experimentation. 510 */ 511 integral_limit = int_tofp(30); 512 if (pid->integral > integral_limit) 513 pid->integral = integral_limit; 514 if (pid->integral < -integral_limit) 515 pid->integral = -integral_limit; 516 517 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 518 pid->last_err = fp_error; 519 520 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 521 result = result + (1 << (FRAC_BITS-1)); 522 return (signed int)fp_toint(result); 523 } 524 525 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 526 { 527 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 528 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 529 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 530 531 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 532 } 533 534 static inline void intel_pstate_reset_all_pid(void) 535 { 536 unsigned int cpu; 537 538 for_each_online_cpu(cpu) { 539 if (all_cpu_data[cpu]) 540 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 541 } 542 } 543 544 static inline void update_turbo_state(void) 545 { 546 u64 misc_en; 547 struct cpudata *cpu; 548 549 cpu = all_cpu_data[0]; 550 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 551 limits->turbo_disabled = 552 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 553 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 554 } 555 556 static void intel_pstate_hwp_set(const struct cpumask *cpumask) 557 { 558 int min, hw_min, max, hw_max, cpu, range, adj_range; 559 u64 value, cap; 560 561 rdmsrl(MSR_HWP_CAPABILITIES, cap); 562 hw_min = HWP_LOWEST_PERF(cap); 563 hw_max = HWP_HIGHEST_PERF(cap); 564 range = hw_max - hw_min; 565 566 for_each_cpu(cpu, cpumask) { 567 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 568 adj_range = limits->min_perf_pct * range / 100; 569 min = hw_min + adj_range; 570 value &= ~HWP_MIN_PERF(~0L); 571 value |= HWP_MIN_PERF(min); 572 573 adj_range = limits->max_perf_pct * range / 100; 574 max = hw_min + adj_range; 575 if (limits->no_turbo) { 576 hw_max = HWP_GUARANTEED_PERF(cap); 577 if (hw_max < max) 578 max = hw_max; 579 } 580 581 value &= ~HWP_MAX_PERF(~0L); 582 value |= HWP_MAX_PERF(max); 583 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 584 } 585 } 586 587 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) 588 { 589 if (hwp_active) 590 intel_pstate_hwp_set(policy->cpus); 591 592 return 0; 593 } 594 595 static void intel_pstate_hwp_set_online_cpus(void) 596 { 597 get_online_cpus(); 598 intel_pstate_hwp_set(cpu_online_mask); 599 put_online_cpus(); 600 } 601 602 /************************** debugfs begin ************************/ 603 static int pid_param_set(void *data, u64 val) 604 { 605 *(u32 *)data = val; 606 intel_pstate_reset_all_pid(); 607 return 0; 608 } 609 610 static int pid_param_get(void *data, u64 *val) 611 { 612 *val = *(u32 *)data; 613 return 0; 614 } 615 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 616 617 struct pid_param { 618 char *name; 619 void *value; 620 }; 621 622 static struct pid_param pid_files[] = { 623 {"sample_rate_ms", &pid_params.sample_rate_ms}, 624 {"d_gain_pct", &pid_params.d_gain_pct}, 625 {"i_gain_pct", &pid_params.i_gain_pct}, 626 {"deadband", &pid_params.deadband}, 627 {"setpoint", &pid_params.setpoint}, 628 {"p_gain_pct", &pid_params.p_gain_pct}, 629 {NULL, NULL} 630 }; 631 632 static void __init intel_pstate_debug_expose_params(void) 633 { 634 struct dentry *debugfs_parent; 635 int i = 0; 636 637 if (hwp_active) 638 return; 639 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 640 if (IS_ERR_OR_NULL(debugfs_parent)) 641 return; 642 while (pid_files[i].name) { 643 debugfs_create_file(pid_files[i].name, 0660, 644 debugfs_parent, pid_files[i].value, 645 &fops_pid_param); 646 i++; 647 } 648 } 649 650 /************************** debugfs end ************************/ 651 652 /************************** sysfs begin ************************/ 653 #define show_one(file_name, object) \ 654 static ssize_t show_##file_name \ 655 (struct kobject *kobj, struct attribute *attr, char *buf) \ 656 { \ 657 return sprintf(buf, "%u\n", limits->object); \ 658 } 659 660 static ssize_t show_turbo_pct(struct kobject *kobj, 661 struct attribute *attr, char *buf) 662 { 663 struct cpudata *cpu; 664 int total, no_turbo, turbo_pct; 665 uint32_t turbo_fp; 666 667 cpu = all_cpu_data[0]; 668 669 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 670 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 671 turbo_fp = div_fp(no_turbo, total); 672 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 673 return sprintf(buf, "%u\n", turbo_pct); 674 } 675 676 static ssize_t show_num_pstates(struct kobject *kobj, 677 struct attribute *attr, char *buf) 678 { 679 struct cpudata *cpu; 680 int total; 681 682 cpu = all_cpu_data[0]; 683 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 684 return sprintf(buf, "%u\n", total); 685 } 686 687 static ssize_t show_no_turbo(struct kobject *kobj, 688 struct attribute *attr, char *buf) 689 { 690 ssize_t ret; 691 692 update_turbo_state(); 693 if (limits->turbo_disabled) 694 ret = sprintf(buf, "%u\n", limits->turbo_disabled); 695 else 696 ret = sprintf(buf, "%u\n", limits->no_turbo); 697 698 return ret; 699 } 700 701 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 702 const char *buf, size_t count) 703 { 704 unsigned int input; 705 int ret; 706 707 ret = sscanf(buf, "%u", &input); 708 if (ret != 1) 709 return -EINVAL; 710 711 update_turbo_state(); 712 if (limits->turbo_disabled) { 713 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 714 return -EPERM; 715 } 716 717 limits->no_turbo = clamp_t(int, input, 0, 1); 718 719 if (hwp_active) 720 intel_pstate_hwp_set_online_cpus(); 721 722 return count; 723 } 724 725 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 726 const char *buf, size_t count) 727 { 728 unsigned int input; 729 int ret; 730 731 ret = sscanf(buf, "%u", &input); 732 if (ret != 1) 733 return -EINVAL; 734 735 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); 736 limits->max_perf_pct = min(limits->max_policy_pct, 737 limits->max_sysfs_pct); 738 limits->max_perf_pct = max(limits->min_policy_pct, 739 limits->max_perf_pct); 740 limits->max_perf_pct = max(limits->min_perf_pct, 741 limits->max_perf_pct); 742 limits->max_perf = div_fp(limits->max_perf_pct, 100); 743 744 if (hwp_active) 745 intel_pstate_hwp_set_online_cpus(); 746 return count; 747 } 748 749 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 750 const char *buf, size_t count) 751 { 752 unsigned int input; 753 int ret; 754 755 ret = sscanf(buf, "%u", &input); 756 if (ret != 1) 757 return -EINVAL; 758 759 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); 760 limits->min_perf_pct = max(limits->min_policy_pct, 761 limits->min_sysfs_pct); 762 limits->min_perf_pct = min(limits->max_policy_pct, 763 limits->min_perf_pct); 764 limits->min_perf_pct = min(limits->max_perf_pct, 765 limits->min_perf_pct); 766 limits->min_perf = div_fp(limits->min_perf_pct, 100); 767 768 if (hwp_active) 769 intel_pstate_hwp_set_online_cpus(); 770 return count; 771 } 772 773 show_one(max_perf_pct, max_perf_pct); 774 show_one(min_perf_pct, min_perf_pct); 775 776 define_one_global_rw(no_turbo); 777 define_one_global_rw(max_perf_pct); 778 define_one_global_rw(min_perf_pct); 779 define_one_global_ro(turbo_pct); 780 define_one_global_ro(num_pstates); 781 782 static struct attribute *intel_pstate_attributes[] = { 783 &no_turbo.attr, 784 &max_perf_pct.attr, 785 &min_perf_pct.attr, 786 &turbo_pct.attr, 787 &num_pstates.attr, 788 NULL 789 }; 790 791 static struct attribute_group intel_pstate_attr_group = { 792 .attrs = intel_pstate_attributes, 793 }; 794 795 static void __init intel_pstate_sysfs_expose_params(void) 796 { 797 struct kobject *intel_pstate_kobject; 798 int rc; 799 800 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 801 &cpu_subsys.dev_root->kobj); 802 BUG_ON(!intel_pstate_kobject); 803 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 804 BUG_ON(rc); 805 } 806 /************************** sysfs end ************************/ 807 808 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 809 { 810 /* First disable HWP notification interrupt as we don't process them */ 811 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 812 813 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 814 } 815 816 static int atom_get_min_pstate(void) 817 { 818 u64 value; 819 820 rdmsrl(ATOM_RATIOS, value); 821 return (value >> 8) & 0x7F; 822 } 823 824 static int atom_get_max_pstate(void) 825 { 826 u64 value; 827 828 rdmsrl(ATOM_RATIOS, value); 829 return (value >> 16) & 0x7F; 830 } 831 832 static int atom_get_turbo_pstate(void) 833 { 834 u64 value; 835 836 rdmsrl(ATOM_TURBO_RATIOS, value); 837 return value & 0x7F; 838 } 839 840 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 841 { 842 u64 val; 843 int32_t vid_fp; 844 u32 vid; 845 846 val = (u64)pstate << 8; 847 if (limits->no_turbo && !limits->turbo_disabled) 848 val |= (u64)1 << 32; 849 850 vid_fp = cpudata->vid.min + mul_fp( 851 int_tofp(pstate - cpudata->pstate.min_pstate), 852 cpudata->vid.ratio); 853 854 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 855 vid = ceiling_fp(vid_fp); 856 857 if (pstate > cpudata->pstate.max_pstate) 858 vid = cpudata->vid.turbo; 859 860 return val | vid; 861 } 862 863 static int silvermont_get_scaling(void) 864 { 865 u64 value; 866 int i; 867 /* Defined in Table 35-6 from SDM (Sept 2015) */ 868 static int silvermont_freq_table[] = { 869 83300, 100000, 133300, 116700, 80000}; 870 871 rdmsrl(MSR_FSB_FREQ, value); 872 i = value & 0x7; 873 WARN_ON(i > 4); 874 875 return silvermont_freq_table[i]; 876 } 877 878 static int airmont_get_scaling(void) 879 { 880 u64 value; 881 int i; 882 /* Defined in Table 35-10 from SDM (Sept 2015) */ 883 static int airmont_freq_table[] = { 884 83300, 100000, 133300, 116700, 80000, 885 93300, 90000, 88900, 87500}; 886 887 rdmsrl(MSR_FSB_FREQ, value); 888 i = value & 0xF; 889 WARN_ON(i > 8); 890 891 return airmont_freq_table[i]; 892 } 893 894 static void atom_get_vid(struct cpudata *cpudata) 895 { 896 u64 value; 897 898 rdmsrl(ATOM_VIDS, value); 899 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 900 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 901 cpudata->vid.ratio = div_fp( 902 cpudata->vid.max - cpudata->vid.min, 903 int_tofp(cpudata->pstate.max_pstate - 904 cpudata->pstate.min_pstate)); 905 906 rdmsrl(ATOM_TURBO_VIDS, value); 907 cpudata->vid.turbo = value & 0x7f; 908 } 909 910 static int core_get_min_pstate(void) 911 { 912 u64 value; 913 914 rdmsrl(MSR_PLATFORM_INFO, value); 915 return (value >> 40) & 0xFF; 916 } 917 918 static int core_get_max_pstate_physical(void) 919 { 920 u64 value; 921 922 rdmsrl(MSR_PLATFORM_INFO, value); 923 return (value >> 8) & 0xFF; 924 } 925 926 static int core_get_max_pstate(void) 927 { 928 u64 tar; 929 u64 plat_info; 930 int max_pstate; 931 int err; 932 933 rdmsrl(MSR_PLATFORM_INFO, plat_info); 934 max_pstate = (plat_info >> 8) & 0xFF; 935 936 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 937 if (!err) { 938 /* Do some sanity checking for safety */ 939 if (plat_info & 0x600000000) { 940 u64 tdp_ctrl; 941 u64 tdp_ratio; 942 int tdp_msr; 943 944 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 945 if (err) 946 goto skip_tar; 947 948 tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; 949 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 950 if (err) 951 goto skip_tar; 952 953 /* For level 1 and 2, bits[23:16] contain the ratio */ 954 if (tdp_ctrl) 955 tdp_ratio >>= 16; 956 957 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 958 if (tdp_ratio - 1 == tar) { 959 max_pstate = tar; 960 pr_debug("max_pstate=TAC %x\n", max_pstate); 961 } else { 962 goto skip_tar; 963 } 964 } 965 } 966 967 skip_tar: 968 return max_pstate; 969 } 970 971 static int core_get_turbo_pstate(void) 972 { 973 u64 value; 974 int nont, ret; 975 976 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 977 nont = core_get_max_pstate(); 978 ret = (value) & 255; 979 if (ret <= nont) 980 ret = nont; 981 return ret; 982 } 983 984 static inline int core_get_scaling(void) 985 { 986 return 100000; 987 } 988 989 static u64 core_get_val(struct cpudata *cpudata, int pstate) 990 { 991 u64 val; 992 993 val = (u64)pstate << 8; 994 if (limits->no_turbo && !limits->turbo_disabled) 995 val |= (u64)1 << 32; 996 997 return val; 998 } 999 1000 static int knl_get_turbo_pstate(void) 1001 { 1002 u64 value; 1003 int nont, ret; 1004 1005 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 1006 nont = core_get_max_pstate(); 1007 ret = (((value) >> 8) & 0xFF); 1008 if (ret <= nont) 1009 ret = nont; 1010 return ret; 1011 } 1012 1013 static struct cpu_defaults core_params = { 1014 .pid_policy = { 1015 .sample_rate_ms = 10, 1016 .deadband = 0, 1017 .setpoint = 97, 1018 .p_gain_pct = 20, 1019 .d_gain_pct = 0, 1020 .i_gain_pct = 0, 1021 }, 1022 .funcs = { 1023 .get_max = core_get_max_pstate, 1024 .get_max_physical = core_get_max_pstate_physical, 1025 .get_min = core_get_min_pstate, 1026 .get_turbo = core_get_turbo_pstate, 1027 .get_scaling = core_get_scaling, 1028 .get_val = core_get_val, 1029 .get_target_pstate = get_target_pstate_use_performance, 1030 }, 1031 }; 1032 1033 static struct cpu_defaults silvermont_params = { 1034 .pid_policy = { 1035 .sample_rate_ms = 10, 1036 .deadband = 0, 1037 .setpoint = 60, 1038 .p_gain_pct = 14, 1039 .d_gain_pct = 0, 1040 .i_gain_pct = 4, 1041 }, 1042 .funcs = { 1043 .get_max = atom_get_max_pstate, 1044 .get_max_physical = atom_get_max_pstate, 1045 .get_min = atom_get_min_pstate, 1046 .get_turbo = atom_get_turbo_pstate, 1047 .get_val = atom_get_val, 1048 .get_scaling = silvermont_get_scaling, 1049 .get_vid = atom_get_vid, 1050 .get_target_pstate = get_target_pstate_use_cpu_load, 1051 }, 1052 }; 1053 1054 static struct cpu_defaults airmont_params = { 1055 .pid_policy = { 1056 .sample_rate_ms = 10, 1057 .deadband = 0, 1058 .setpoint = 60, 1059 .p_gain_pct = 14, 1060 .d_gain_pct = 0, 1061 .i_gain_pct = 4, 1062 }, 1063 .funcs = { 1064 .get_max = atom_get_max_pstate, 1065 .get_max_physical = atom_get_max_pstate, 1066 .get_min = atom_get_min_pstate, 1067 .get_turbo = atom_get_turbo_pstate, 1068 .get_val = atom_get_val, 1069 .get_scaling = airmont_get_scaling, 1070 .get_vid = atom_get_vid, 1071 .get_target_pstate = get_target_pstate_use_cpu_load, 1072 }, 1073 }; 1074 1075 static struct cpu_defaults knl_params = { 1076 .pid_policy = { 1077 .sample_rate_ms = 10, 1078 .deadband = 0, 1079 .setpoint = 97, 1080 .p_gain_pct = 20, 1081 .d_gain_pct = 0, 1082 .i_gain_pct = 0, 1083 }, 1084 .funcs = { 1085 .get_max = core_get_max_pstate, 1086 .get_max_physical = core_get_max_pstate_physical, 1087 .get_min = core_get_min_pstate, 1088 .get_turbo = knl_get_turbo_pstate, 1089 .get_scaling = core_get_scaling, 1090 .get_val = core_get_val, 1091 .get_target_pstate = get_target_pstate_use_performance, 1092 }, 1093 }; 1094 1095 static struct cpu_defaults bxt_params = { 1096 .pid_policy = { 1097 .sample_rate_ms = 10, 1098 .deadband = 0, 1099 .setpoint = 60, 1100 .p_gain_pct = 14, 1101 .d_gain_pct = 0, 1102 .i_gain_pct = 4, 1103 }, 1104 .funcs = { 1105 .get_max = core_get_max_pstate, 1106 .get_max_physical = core_get_max_pstate_physical, 1107 .get_min = core_get_min_pstate, 1108 .get_turbo = core_get_turbo_pstate, 1109 .get_scaling = core_get_scaling, 1110 .get_val = core_get_val, 1111 .get_target_pstate = get_target_pstate_use_cpu_load, 1112 }, 1113 }; 1114 1115 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1116 { 1117 int max_perf = cpu->pstate.turbo_pstate; 1118 int max_perf_adj; 1119 int min_perf; 1120 1121 if (limits->no_turbo || limits->turbo_disabled) 1122 max_perf = cpu->pstate.max_pstate; 1123 1124 /* 1125 * performance can be limited by user through sysfs, by cpufreq 1126 * policy, or by cpu specific default values determined through 1127 * experimentation. 1128 */ 1129 max_perf_adj = fp_toint(max_perf * limits->max_perf); 1130 *max = clamp_t(int, max_perf_adj, 1131 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1132 1133 min_perf = fp_toint(max_perf * limits->min_perf); 1134 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1135 } 1136 1137 static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate) 1138 { 1139 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1140 cpu->pstate.current_pstate = pstate; 1141 } 1142 1143 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1144 { 1145 int pstate = cpu->pstate.min_pstate; 1146 1147 intel_pstate_record_pstate(cpu, pstate); 1148 /* 1149 * Generally, there is no guarantee that this code will always run on 1150 * the CPU being updated, so force the register update to run on the 1151 * right CPU. 1152 */ 1153 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1154 pstate_funcs.get_val(cpu, pstate)); 1155 } 1156 1157 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1158 { 1159 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1160 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1161 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1162 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1163 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1164 1165 if (pstate_funcs.get_vid) 1166 pstate_funcs.get_vid(cpu); 1167 1168 intel_pstate_set_min_pstate(cpu); 1169 } 1170 1171 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1172 { 1173 struct sample *sample = &cpu->sample; 1174 1175 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1176 } 1177 1178 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1179 { 1180 u64 aperf, mperf; 1181 unsigned long flags; 1182 u64 tsc; 1183 1184 local_irq_save(flags); 1185 rdmsrl(MSR_IA32_APERF, aperf); 1186 rdmsrl(MSR_IA32_MPERF, mperf); 1187 tsc = rdtsc(); 1188 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1189 local_irq_restore(flags); 1190 return false; 1191 } 1192 local_irq_restore(flags); 1193 1194 cpu->last_sample_time = cpu->sample.time; 1195 cpu->sample.time = time; 1196 cpu->sample.aperf = aperf; 1197 cpu->sample.mperf = mperf; 1198 cpu->sample.tsc = tsc; 1199 cpu->sample.aperf -= cpu->prev_aperf; 1200 cpu->sample.mperf -= cpu->prev_mperf; 1201 cpu->sample.tsc -= cpu->prev_tsc; 1202 1203 cpu->prev_aperf = aperf; 1204 cpu->prev_mperf = mperf; 1205 cpu->prev_tsc = tsc; 1206 /* 1207 * First time this function is invoked in a given cycle, all of the 1208 * previous sample data fields are equal to zero or stale and they must 1209 * be populated with meaningful numbers for things to work, so assume 1210 * that sample.time will always be reset before setting the utilization 1211 * update hook and make the caller skip the sample then. 1212 */ 1213 return !!cpu->last_sample_time; 1214 } 1215 1216 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1217 { 1218 return mul_ext_fp(cpu->sample.core_avg_perf, 1219 cpu->pstate.max_pstate_physical * cpu->pstate.scaling); 1220 } 1221 1222 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1223 { 1224 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1225 cpu->sample.core_avg_perf); 1226 } 1227 1228 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1229 { 1230 struct sample *sample = &cpu->sample; 1231 u64 cummulative_iowait, delta_iowait_us; 1232 u64 delta_iowait_mperf; 1233 u64 mperf, now; 1234 int32_t cpu_load; 1235 1236 cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now); 1237 1238 /* 1239 * Convert iowait time into number of IO cycles spent at max_freq. 1240 * IO is considered as busy only for the cpu_load algorithm. For 1241 * performance this is not needed since we always try to reach the 1242 * maximum P-State, so we are already boosting the IOs. 1243 */ 1244 delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait; 1245 delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling * 1246 cpu->pstate.max_pstate, MSEC_PER_SEC); 1247 1248 mperf = cpu->sample.mperf + delta_iowait_mperf; 1249 cpu->prev_cummulative_iowait = cummulative_iowait; 1250 1251 /* 1252 * The load can be estimated as the ratio of the mperf counter 1253 * running at a constant frequency during active periods 1254 * (C0) and the time stamp counter running at the same frequency 1255 * also during C-states. 1256 */ 1257 cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc); 1258 cpu->sample.busy_scaled = cpu_load; 1259 1260 return get_avg_pstate(cpu) - pid_calc(&cpu->pid, cpu_load); 1261 } 1262 1263 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1264 { 1265 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; 1266 u64 duration_ns; 1267 1268 /* 1269 * perf_scaled is the average performance during the last sampling 1270 * period scaled by the ratio of the maximum P-state to the P-state 1271 * requested last time (in percent). That measures the system's 1272 * response to the previous P-state selection. 1273 */ 1274 max_pstate = cpu->pstate.max_pstate_physical; 1275 current_pstate = cpu->pstate.current_pstate; 1276 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, 1277 div_fp(100 * max_pstate, current_pstate)); 1278 1279 /* 1280 * Since our utilization update callback will not run unless we are 1281 * in C0, check if the actual elapsed time is significantly greater (3x) 1282 * than our sample interval. If it is, then we were idle for a long 1283 * enough period of time to adjust our performance metric. 1284 */ 1285 duration_ns = cpu->sample.time - cpu->last_sample_time; 1286 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1287 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1288 perf_scaled = mul_fp(perf_scaled, sample_ratio); 1289 } else { 1290 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1291 if (sample_ratio < int_tofp(1)) 1292 perf_scaled = 0; 1293 } 1294 1295 cpu->sample.busy_scaled = perf_scaled; 1296 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); 1297 } 1298 1299 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1300 { 1301 int max_perf, min_perf; 1302 1303 update_turbo_state(); 1304 1305 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1306 pstate = clamp_t(int, pstate, min_perf, max_perf); 1307 if (pstate == cpu->pstate.current_pstate) 1308 return; 1309 1310 intel_pstate_record_pstate(cpu, pstate); 1311 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1312 } 1313 1314 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1315 { 1316 int from, target_pstate; 1317 struct sample *sample; 1318 1319 from = cpu->pstate.current_pstate; 1320 1321 target_pstate = pstate_funcs.get_target_pstate(cpu); 1322 1323 intel_pstate_update_pstate(cpu, target_pstate); 1324 1325 sample = &cpu->sample; 1326 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1327 fp_toint(sample->busy_scaled), 1328 from, 1329 cpu->pstate.current_pstate, 1330 sample->mperf, 1331 sample->aperf, 1332 sample->tsc, 1333 get_avg_frequency(cpu)); 1334 } 1335 1336 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1337 unsigned long util, unsigned long max) 1338 { 1339 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1340 u64 delta_ns = time - cpu->sample.time; 1341 1342 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1343 bool sample_taken = intel_pstate_sample(cpu, time); 1344 1345 if (sample_taken) { 1346 intel_pstate_calc_avg_perf(cpu); 1347 if (!hwp_active) 1348 intel_pstate_adjust_busy_pstate(cpu); 1349 } 1350 } 1351 } 1352 1353 #define ICPU(model, policy) \ 1354 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1355 (unsigned long)&policy } 1356 1357 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1358 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), 1359 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), 1360 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), 1361 ICPU(INTEL_FAM6_IVYBRIDGE, core_params), 1362 ICPU(INTEL_FAM6_HASWELL_CORE, core_params), 1363 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), 1364 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), 1365 ICPU(INTEL_FAM6_HASWELL_X, core_params), 1366 ICPU(INTEL_FAM6_HASWELL_ULT, core_params), 1367 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), 1368 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), 1369 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), 1370 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), 1371 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1372 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), 1373 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1374 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), 1375 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), 1376 {} 1377 }; 1378 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1379 1380 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { 1381 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1382 {} 1383 }; 1384 1385 static int intel_pstate_init_cpu(unsigned int cpunum) 1386 { 1387 struct cpudata *cpu; 1388 1389 if (!all_cpu_data[cpunum]) 1390 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), 1391 GFP_KERNEL); 1392 if (!all_cpu_data[cpunum]) 1393 return -ENOMEM; 1394 1395 cpu = all_cpu_data[cpunum]; 1396 1397 cpu->cpu = cpunum; 1398 1399 if (hwp_active) { 1400 intel_pstate_hwp_enable(cpu); 1401 pid_params.sample_rate_ms = 50; 1402 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1403 } 1404 1405 intel_pstate_get_cpu_pstates(cpu); 1406 1407 intel_pstate_busy_pid_reset(cpu); 1408 1409 pr_debug("controlling: cpu %d\n", cpunum); 1410 1411 return 0; 1412 } 1413 1414 static unsigned int intel_pstate_get(unsigned int cpu_num) 1415 { 1416 struct cpudata *cpu = all_cpu_data[cpu_num]; 1417 1418 return cpu ? get_avg_frequency(cpu) : 0; 1419 } 1420 1421 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1422 { 1423 struct cpudata *cpu = all_cpu_data[cpu_num]; 1424 1425 /* Prevent intel_pstate_update_util() from using stale data. */ 1426 cpu->sample.time = 0; 1427 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1428 intel_pstate_update_util); 1429 cpu->update_util_set = true; 1430 } 1431 1432 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1433 { 1434 struct cpudata *cpu_data = all_cpu_data[cpu]; 1435 1436 if (!cpu_data->update_util_set) 1437 return; 1438 1439 cpufreq_remove_update_util_hook(cpu); 1440 cpu_data->update_util_set = false; 1441 synchronize_sched(); 1442 } 1443 1444 static void intel_pstate_set_performance_limits(struct perf_limits *limits) 1445 { 1446 limits->no_turbo = 0; 1447 limits->turbo_disabled = 0; 1448 limits->max_perf_pct = 100; 1449 limits->max_perf = int_tofp(1); 1450 limits->min_perf_pct = 100; 1451 limits->min_perf = int_tofp(1); 1452 limits->max_policy_pct = 100; 1453 limits->max_sysfs_pct = 100; 1454 limits->min_policy_pct = 0; 1455 limits->min_sysfs_pct = 0; 1456 } 1457 1458 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1459 { 1460 struct cpudata *cpu; 1461 1462 if (!policy->cpuinfo.max_freq) 1463 return -ENODEV; 1464 1465 intel_pstate_clear_update_util_hook(policy->cpu); 1466 1467 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 1468 policy->cpuinfo.max_freq, policy->max); 1469 1470 cpu = all_cpu_data[0]; 1471 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 1472 policy->max < policy->cpuinfo.max_freq && 1473 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 1474 pr_debug("policy->max > max non turbo frequency\n"); 1475 policy->max = policy->cpuinfo.max_freq; 1476 } 1477 1478 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 1479 limits = &performance_limits; 1480 if (policy->max >= policy->cpuinfo.max_freq) { 1481 pr_debug("set performance\n"); 1482 intel_pstate_set_performance_limits(limits); 1483 goto out; 1484 } 1485 } else { 1486 pr_debug("set powersave\n"); 1487 limits = &powersave_limits; 1488 } 1489 1490 limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 1491 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); 1492 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, 1493 policy->cpuinfo.max_freq); 1494 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); 1495 1496 /* Normalize user input to [min_policy_pct, max_policy_pct] */ 1497 limits->min_perf_pct = max(limits->min_policy_pct, 1498 limits->min_sysfs_pct); 1499 limits->min_perf_pct = min(limits->max_policy_pct, 1500 limits->min_perf_pct); 1501 limits->max_perf_pct = min(limits->max_policy_pct, 1502 limits->max_sysfs_pct); 1503 limits->max_perf_pct = max(limits->min_policy_pct, 1504 limits->max_perf_pct); 1505 1506 /* Make sure min_perf_pct <= max_perf_pct */ 1507 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); 1508 1509 limits->min_perf = div_fp(limits->min_perf_pct, 100); 1510 limits->max_perf = div_fp(limits->max_perf_pct, 100); 1511 limits->max_perf = round_up(limits->max_perf, FRAC_BITS); 1512 1513 out: 1514 intel_pstate_set_update_util_hook(policy->cpu); 1515 1516 intel_pstate_hwp_set_policy(policy); 1517 1518 return 0; 1519 } 1520 1521 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 1522 { 1523 cpufreq_verify_within_cpu_limits(policy); 1524 1525 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 1526 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 1527 return -EINVAL; 1528 1529 return 0; 1530 } 1531 1532 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 1533 { 1534 int cpu_num = policy->cpu; 1535 struct cpudata *cpu = all_cpu_data[cpu_num]; 1536 1537 pr_debug("CPU %d exiting\n", cpu_num); 1538 1539 intel_pstate_clear_update_util_hook(cpu_num); 1540 1541 if (hwp_active) 1542 return; 1543 1544 intel_pstate_set_min_pstate(cpu); 1545 } 1546 1547 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 1548 { 1549 struct cpudata *cpu; 1550 int rc; 1551 1552 rc = intel_pstate_init_cpu(policy->cpu); 1553 if (rc) 1554 return rc; 1555 1556 cpu = all_cpu_data[policy->cpu]; 1557 1558 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) 1559 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1560 else 1561 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1562 1563 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 1564 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1565 1566 /* cpuinfo and default policy values */ 1567 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1568 update_turbo_state(); 1569 policy->cpuinfo.max_freq = limits->turbo_disabled ? 1570 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1571 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 1572 1573 intel_pstate_init_acpi_perf_limits(policy); 1574 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1575 cpumask_set_cpu(policy->cpu, policy->cpus); 1576 1577 return 0; 1578 } 1579 1580 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 1581 { 1582 intel_pstate_exit_perf_limits(policy); 1583 1584 return 0; 1585 } 1586 1587 static struct cpufreq_driver intel_pstate_driver = { 1588 .flags = CPUFREQ_CONST_LOOPS, 1589 .verify = intel_pstate_verify_policy, 1590 .setpolicy = intel_pstate_set_policy, 1591 .resume = intel_pstate_hwp_set_policy, 1592 .get = intel_pstate_get, 1593 .init = intel_pstate_cpu_init, 1594 .exit = intel_pstate_cpu_exit, 1595 .stop_cpu = intel_pstate_stop_cpu, 1596 .name = "intel_pstate", 1597 }; 1598 1599 static int no_load __initdata; 1600 static int no_hwp __initdata; 1601 static int hwp_only __initdata; 1602 static unsigned int force_load; 1603 1604 static int intel_pstate_msrs_not_valid(void) 1605 { 1606 if (!pstate_funcs.get_max() || 1607 !pstate_funcs.get_min() || 1608 !pstate_funcs.get_turbo()) 1609 return -ENODEV; 1610 1611 return 0; 1612 } 1613 1614 static void copy_pid_params(struct pstate_adjust_policy *policy) 1615 { 1616 pid_params.sample_rate_ms = policy->sample_rate_ms; 1617 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 1618 pid_params.p_gain_pct = policy->p_gain_pct; 1619 pid_params.i_gain_pct = policy->i_gain_pct; 1620 pid_params.d_gain_pct = policy->d_gain_pct; 1621 pid_params.deadband = policy->deadband; 1622 pid_params.setpoint = policy->setpoint; 1623 } 1624 1625 static void copy_cpu_funcs(struct pstate_funcs *funcs) 1626 { 1627 pstate_funcs.get_max = funcs->get_max; 1628 pstate_funcs.get_max_physical = funcs->get_max_physical; 1629 pstate_funcs.get_min = funcs->get_min; 1630 pstate_funcs.get_turbo = funcs->get_turbo; 1631 pstate_funcs.get_scaling = funcs->get_scaling; 1632 pstate_funcs.get_val = funcs->get_val; 1633 pstate_funcs.get_vid = funcs->get_vid; 1634 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 1635 1636 } 1637 1638 #ifdef CONFIG_ACPI 1639 1640 static bool intel_pstate_no_acpi_pss(void) 1641 { 1642 int i; 1643 1644 for_each_possible_cpu(i) { 1645 acpi_status status; 1646 union acpi_object *pss; 1647 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1648 struct acpi_processor *pr = per_cpu(processors, i); 1649 1650 if (!pr) 1651 continue; 1652 1653 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1654 if (ACPI_FAILURE(status)) 1655 continue; 1656 1657 pss = buffer.pointer; 1658 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1659 kfree(pss); 1660 return false; 1661 } 1662 1663 kfree(pss); 1664 } 1665 1666 return true; 1667 } 1668 1669 static bool intel_pstate_has_acpi_ppc(void) 1670 { 1671 int i; 1672 1673 for_each_possible_cpu(i) { 1674 struct acpi_processor *pr = per_cpu(processors, i); 1675 1676 if (!pr) 1677 continue; 1678 if (acpi_has_method(pr->handle, "_PPC")) 1679 return true; 1680 } 1681 return false; 1682 } 1683 1684 enum { 1685 PSS, 1686 PPC, 1687 }; 1688 1689 struct hw_vendor_info { 1690 u16 valid; 1691 char oem_id[ACPI_OEM_ID_SIZE]; 1692 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1693 int oem_pwr_table; 1694 }; 1695 1696 /* Hardware vendor-specific info that has its own power management modes */ 1697 static struct hw_vendor_info vendor_info[] = { 1698 {1, "HP ", "ProLiant", PSS}, 1699 {1, "ORACLE", "X4-2 ", PPC}, 1700 {1, "ORACLE", "X4-2L ", PPC}, 1701 {1, "ORACLE", "X4-2B ", PPC}, 1702 {1, "ORACLE", "X3-2 ", PPC}, 1703 {1, "ORACLE", "X3-2L ", PPC}, 1704 {1, "ORACLE", "X3-2B ", PPC}, 1705 {1, "ORACLE", "X4470M2 ", PPC}, 1706 {1, "ORACLE", "X4270M3 ", PPC}, 1707 {1, "ORACLE", "X4270M2 ", PPC}, 1708 {1, "ORACLE", "X4170M2 ", PPC}, 1709 {1, "ORACLE", "X4170 M3", PPC}, 1710 {1, "ORACLE", "X4275 M3", PPC}, 1711 {1, "ORACLE", "X6-2 ", PPC}, 1712 {1, "ORACLE", "Sudbury ", PPC}, 1713 {0, "", ""}, 1714 }; 1715 1716 static bool intel_pstate_platform_pwr_mgmt_exists(void) 1717 { 1718 struct acpi_table_header hdr; 1719 struct hw_vendor_info *v_info; 1720 const struct x86_cpu_id *id; 1721 u64 misc_pwr; 1722 1723 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1724 if (id) { 1725 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1726 if ( misc_pwr & (1 << 8)) 1727 return true; 1728 } 1729 1730 if (acpi_disabled || 1731 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1732 return false; 1733 1734 for (v_info = vendor_info; v_info->valid; v_info++) { 1735 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1736 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1737 ACPI_OEM_TABLE_ID_SIZE)) 1738 switch (v_info->oem_pwr_table) { 1739 case PSS: 1740 return intel_pstate_no_acpi_pss(); 1741 case PPC: 1742 return intel_pstate_has_acpi_ppc() && 1743 (!force_load); 1744 } 1745 } 1746 1747 return false; 1748 } 1749 #else /* CONFIG_ACPI not enabled */ 1750 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1751 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1752 #endif /* CONFIG_ACPI */ 1753 1754 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 1755 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 1756 {} 1757 }; 1758 1759 static int __init intel_pstate_init(void) 1760 { 1761 int cpu, rc = 0; 1762 const struct x86_cpu_id *id; 1763 struct cpu_defaults *cpu_def; 1764 1765 if (no_load) 1766 return -ENODEV; 1767 1768 if (x86_match_cpu(hwp_support_ids) && !no_hwp) { 1769 copy_cpu_funcs(&core_params.funcs); 1770 hwp_active++; 1771 goto hwp_cpu_matched; 1772 } 1773 1774 id = x86_match_cpu(intel_pstate_cpu_ids); 1775 if (!id) 1776 return -ENODEV; 1777 1778 cpu_def = (struct cpu_defaults *)id->driver_data; 1779 1780 copy_pid_params(&cpu_def->pid_policy); 1781 copy_cpu_funcs(&cpu_def->funcs); 1782 1783 if (intel_pstate_msrs_not_valid()) 1784 return -ENODEV; 1785 1786 hwp_cpu_matched: 1787 /* 1788 * The Intel pstate driver will be ignored if the platform 1789 * firmware has its own power management modes. 1790 */ 1791 if (intel_pstate_platform_pwr_mgmt_exists()) 1792 return -ENODEV; 1793 1794 pr_info("Intel P-state driver initializing\n"); 1795 1796 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1797 if (!all_cpu_data) 1798 return -ENOMEM; 1799 1800 if (!hwp_active && hwp_only) 1801 goto out; 1802 1803 rc = cpufreq_register_driver(&intel_pstate_driver); 1804 if (rc) 1805 goto out; 1806 1807 intel_pstate_debug_expose_params(); 1808 intel_pstate_sysfs_expose_params(); 1809 1810 if (hwp_active) 1811 pr_info("HWP enabled\n"); 1812 1813 return rc; 1814 out: 1815 get_online_cpus(); 1816 for_each_online_cpu(cpu) { 1817 if (all_cpu_data[cpu]) { 1818 intel_pstate_clear_update_util_hook(cpu); 1819 kfree(all_cpu_data[cpu]); 1820 } 1821 } 1822 1823 put_online_cpus(); 1824 vfree(all_cpu_data); 1825 return -ENODEV; 1826 } 1827 device_initcall(intel_pstate_init); 1828 1829 static int __init intel_pstate_setup(char *str) 1830 { 1831 if (!str) 1832 return -EINVAL; 1833 1834 if (!strcmp(str, "disable")) 1835 no_load = 1; 1836 if (!strcmp(str, "no_hwp")) { 1837 pr_info("HWP disabled\n"); 1838 no_hwp = 1; 1839 } 1840 if (!strcmp(str, "force")) 1841 force_load = 1; 1842 if (!strcmp(str, "hwp_only")) 1843 hwp_only = 1; 1844 1845 #ifdef CONFIG_ACPI 1846 if (!strcmp(str, "support_acpi_ppc")) 1847 acpi_ppc = true; 1848 #endif 1849 1850 return 0; 1851 } 1852 early_param("intel_pstate", intel_pstate_setup); 1853 1854 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1855 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1856 MODULE_LICENSE("GPL"); 1857