1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 40 #define ATOM_RATIOS 0x66a 41 #define ATOM_VIDS 0x66b 42 #define ATOM_TURBO_RATIOS 0x66c 43 #define ATOM_TURBO_VIDS 0x66d 44 45 #ifdef CONFIG_ACPI 46 #include <acpi/processor.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define EXT_BITS 6 54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 55 56 static inline int32_t mul_fp(int32_t x, int32_t y) 57 { 58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 59 } 60 61 static inline int32_t div_fp(s64 x, s64 y) 62 { 63 return div64_s64((int64_t)x << FRAC_BITS, y); 64 } 65 66 static inline int ceiling_fp(int32_t x) 67 { 68 int mask, ret; 69 70 ret = fp_toint(x); 71 mask = (1 << FRAC_BITS) - 1; 72 if (x & mask) 73 ret += 1; 74 return ret; 75 } 76 77 static inline u64 mul_ext_fp(u64 x, u64 y) 78 { 79 return (x * y) >> EXT_FRAC_BITS; 80 } 81 82 static inline u64 div_ext_fp(u64 x, u64 y) 83 { 84 return div64_u64(x << EXT_FRAC_BITS, y); 85 } 86 87 /** 88 * struct sample - Store performance sample 89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 90 * performance during last sample period 91 * @busy_scaled: Scaled busy value which is used to calculate next 92 * P state. This can be different than core_avg_perf 93 * to account for cpu idle period 94 * @aperf: Difference of actual performance frequency clock count 95 * read from APERF MSR between last and current sample 96 * @mperf: Difference of maximum performance frequency clock count 97 * read from MPERF MSR between last and current sample 98 * @tsc: Difference of time stamp counter between last and 99 * current sample 100 * @time: Current time from scheduler 101 * 102 * This structure is used in the cpudata structure to store performance sample 103 * data for choosing next P State. 104 */ 105 struct sample { 106 int32_t core_avg_perf; 107 int32_t busy_scaled; 108 u64 aperf; 109 u64 mperf; 110 u64 tsc; 111 u64 time; 112 }; 113 114 /** 115 * struct pstate_data - Store P state data 116 * @current_pstate: Current requested P state 117 * @min_pstate: Min P state possible for this platform 118 * @max_pstate: Max P state possible for this platform 119 * @max_pstate_physical:This is physical Max P state for a processor 120 * This can be higher than the max_pstate which can 121 * be limited by platform thermal design power limits 122 * @scaling: Scaling factor to convert frequency to cpufreq 123 * frequency units 124 * @turbo_pstate: Max Turbo P state possible for this platform 125 * 126 * Stores the per cpu model P state limits and current P state. 127 */ 128 struct pstate_data { 129 int current_pstate; 130 int min_pstate; 131 int max_pstate; 132 int max_pstate_physical; 133 int scaling; 134 int turbo_pstate; 135 }; 136 137 /** 138 * struct vid_data - Stores voltage information data 139 * @min: VID data for this platform corresponding to 140 * the lowest P state 141 * @max: VID data corresponding to the highest P State. 142 * @turbo: VID data for turbo P state 143 * @ratio: Ratio of (vid max - vid min) / 144 * (max P state - Min P State) 145 * 146 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 147 * This data is used in Atom platforms, where in addition to target P state, 148 * the voltage data needs to be specified to select next P State. 149 */ 150 struct vid_data { 151 int min; 152 int max; 153 int turbo; 154 int32_t ratio; 155 }; 156 157 /** 158 * struct _pid - Stores PID data 159 * @setpoint: Target set point for busyness or performance 160 * @integral: Storage for accumulated error values 161 * @p_gain: PID proportional gain 162 * @i_gain: PID integral gain 163 * @d_gain: PID derivative gain 164 * @deadband: PID deadband 165 * @last_err: Last error storage for integral part of PID calculation 166 * 167 * Stores PID coefficients and last error for PID controller. 168 */ 169 struct _pid { 170 int setpoint; 171 int32_t integral; 172 int32_t p_gain; 173 int32_t i_gain; 174 int32_t d_gain; 175 int deadband; 176 int32_t last_err; 177 }; 178 179 /** 180 * struct perf_limits - Store user and policy limits 181 * @no_turbo: User requested turbo state from intel_pstate sysfs 182 * @turbo_disabled: Platform turbo status either from msr 183 * MSR_IA32_MISC_ENABLE or when maximum available pstate 184 * matches the maximum turbo pstate 185 * @max_perf_pct: Effective maximum performance limit in percentage, this 186 * is minimum of either limits enforced by cpufreq policy 187 * or limits from user set limits via intel_pstate sysfs 188 * @min_perf_pct: Effective minimum performance limit in percentage, this 189 * is maximum of either limits enforced by cpufreq policy 190 * or limits from user set limits via intel_pstate sysfs 191 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 192 * This value is used to limit max pstate 193 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 194 * This value is used to limit min pstate 195 * @max_policy_pct: The maximum performance in percentage enforced by 196 * cpufreq setpolicy interface 197 * @max_sysfs_pct: The maximum performance in percentage enforced by 198 * intel pstate sysfs interface, unused when per cpu 199 * controls are enforced 200 * @min_policy_pct: The minimum performance in percentage enforced by 201 * cpufreq setpolicy interface 202 * @min_sysfs_pct: The minimum performance in percentage enforced by 203 * intel pstate sysfs interface, unused when per cpu 204 * controls are enforced 205 * 206 * Storage for user and policy defined limits. 207 */ 208 struct perf_limits { 209 int no_turbo; 210 int turbo_disabled; 211 int max_perf_pct; 212 int min_perf_pct; 213 int32_t max_perf; 214 int32_t min_perf; 215 int max_policy_pct; 216 int max_sysfs_pct; 217 int min_policy_pct; 218 int min_sysfs_pct; 219 }; 220 221 /** 222 * struct cpudata - Per CPU instance data storage 223 * @cpu: CPU number for this instance data 224 * @policy: CPUFreq policy value 225 * @update_util: CPUFreq utility callback information 226 * @update_util_set: CPUFreq utility callback is set 227 * @iowait_boost: iowait-related boost fraction 228 * @last_update: Time of the last update. 229 * @pstate: Stores P state limits for this CPU 230 * @vid: Stores VID limits for this CPU 231 * @pid: Stores PID parameters for this CPU 232 * @last_sample_time: Last Sample time 233 * @prev_aperf: Last APERF value read from APERF MSR 234 * @prev_mperf: Last MPERF value read from MPERF MSR 235 * @prev_tsc: Last timestamp counter (TSC) value 236 * @prev_cummulative_iowait: IO Wait time difference from last and 237 * current sample 238 * @sample: Storage for storing last Sample data 239 * @perf_limits: Pointer to perf_limit unique to this CPU 240 * Not all field in the structure are applicable 241 * when per cpu controls are enforced 242 * @acpi_perf_data: Stores ACPI perf information read from _PSS 243 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 244 * 245 * This structure stores per CPU instance data for all CPUs. 246 */ 247 struct cpudata { 248 int cpu; 249 250 unsigned int policy; 251 struct update_util_data update_util; 252 bool update_util_set; 253 254 struct pstate_data pstate; 255 struct vid_data vid; 256 struct _pid pid; 257 258 u64 last_update; 259 u64 last_sample_time; 260 u64 prev_aperf; 261 u64 prev_mperf; 262 u64 prev_tsc; 263 u64 prev_cummulative_iowait; 264 struct sample sample; 265 struct perf_limits *perf_limits; 266 #ifdef CONFIG_ACPI 267 struct acpi_processor_performance acpi_perf_data; 268 bool valid_pss_table; 269 #endif 270 unsigned int iowait_boost; 271 }; 272 273 static struct cpudata **all_cpu_data; 274 275 /** 276 * struct pstate_adjust_policy - Stores static PID configuration data 277 * @sample_rate_ms: PID calculation sample rate in ms 278 * @sample_rate_ns: Sample rate calculation in ns 279 * @deadband: PID deadband 280 * @setpoint: PID Setpoint 281 * @p_gain_pct: PID proportional gain 282 * @i_gain_pct: PID integral gain 283 * @d_gain_pct: PID derivative gain 284 * 285 * Stores per CPU model static PID configuration data. 286 */ 287 struct pstate_adjust_policy { 288 int sample_rate_ms; 289 s64 sample_rate_ns; 290 int deadband; 291 int setpoint; 292 int p_gain_pct; 293 int d_gain_pct; 294 int i_gain_pct; 295 }; 296 297 /** 298 * struct pstate_funcs - Per CPU model specific callbacks 299 * @get_max: Callback to get maximum non turbo effective P state 300 * @get_max_physical: Callback to get maximum non turbo physical P state 301 * @get_min: Callback to get minimum P state 302 * @get_turbo: Callback to get turbo P state 303 * @get_scaling: Callback to get frequency scaling factor 304 * @get_val: Callback to convert P state to actual MSR write value 305 * @get_vid: Callback to get VID data for Atom platforms 306 * @get_target_pstate: Callback to a function to calculate next P state to use 307 * 308 * Core and Atom CPU models have different way to get P State limits. This 309 * structure is used to store those callbacks. 310 */ 311 struct pstate_funcs { 312 int (*get_max)(void); 313 int (*get_max_physical)(void); 314 int (*get_min)(void); 315 int (*get_turbo)(void); 316 int (*get_scaling)(void); 317 u64 (*get_val)(struct cpudata*, int pstate); 318 void (*get_vid)(struct cpudata *); 319 int32_t (*get_target_pstate)(struct cpudata *); 320 }; 321 322 /** 323 * struct cpu_defaults- Per CPU model default config data 324 * @pid_policy: PID config data 325 * @funcs: Callback function data 326 */ 327 struct cpu_defaults { 328 struct pstate_adjust_policy pid_policy; 329 struct pstate_funcs funcs; 330 }; 331 332 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 333 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 334 335 static struct pstate_adjust_policy pid_params __read_mostly; 336 static struct pstate_funcs pstate_funcs __read_mostly; 337 static int hwp_active __read_mostly; 338 static bool per_cpu_limits __read_mostly; 339 340 #ifdef CONFIG_ACPI 341 static bool acpi_ppc; 342 #endif 343 344 static struct perf_limits performance_limits = { 345 .no_turbo = 0, 346 .turbo_disabled = 0, 347 .max_perf_pct = 100, 348 .max_perf = int_tofp(1), 349 .min_perf_pct = 100, 350 .min_perf = int_tofp(1), 351 .max_policy_pct = 100, 352 .max_sysfs_pct = 100, 353 .min_policy_pct = 0, 354 .min_sysfs_pct = 0, 355 }; 356 357 static struct perf_limits powersave_limits = { 358 .no_turbo = 0, 359 .turbo_disabled = 0, 360 .max_perf_pct = 100, 361 .max_perf = int_tofp(1), 362 .min_perf_pct = 0, 363 .min_perf = 0, 364 .max_policy_pct = 100, 365 .max_sysfs_pct = 100, 366 .min_policy_pct = 0, 367 .min_sysfs_pct = 0, 368 }; 369 370 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 371 static struct perf_limits *limits = &performance_limits; 372 #else 373 static struct perf_limits *limits = &powersave_limits; 374 #endif 375 376 #ifdef CONFIG_ACPI 377 378 static bool intel_pstate_get_ppc_enable_status(void) 379 { 380 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 381 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 382 return true; 383 384 return acpi_ppc; 385 } 386 387 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 388 { 389 struct cpudata *cpu; 390 int ret; 391 int i; 392 393 if (hwp_active) 394 return; 395 396 if (!intel_pstate_get_ppc_enable_status()) 397 return; 398 399 cpu = all_cpu_data[policy->cpu]; 400 401 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 402 policy->cpu); 403 if (ret) 404 return; 405 406 /* 407 * Check if the control value in _PSS is for PERF_CTL MSR, which should 408 * guarantee that the states returned by it map to the states in our 409 * list directly. 410 */ 411 if (cpu->acpi_perf_data.control_register.space_id != 412 ACPI_ADR_SPACE_FIXED_HARDWARE) 413 goto err; 414 415 /* 416 * If there is only one entry _PSS, simply ignore _PSS and continue as 417 * usual without taking _PSS into account 418 */ 419 if (cpu->acpi_perf_data.state_count < 2) 420 goto err; 421 422 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 423 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 424 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 425 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 426 (u32) cpu->acpi_perf_data.states[i].core_frequency, 427 (u32) cpu->acpi_perf_data.states[i].power, 428 (u32) cpu->acpi_perf_data.states[i].control); 429 } 430 431 /* 432 * The _PSS table doesn't contain whole turbo frequency range. 433 * This just contains +1 MHZ above the max non turbo frequency, 434 * with control value corresponding to max turbo ratio. But 435 * when cpufreq set policy is called, it will call with this 436 * max frequency, which will cause a reduced performance as 437 * this driver uses real max turbo frequency as the max 438 * frequency. So correct this frequency in _PSS table to 439 * correct max turbo frequency based on the turbo state. 440 * Also need to convert to MHz as _PSS freq is in MHz. 441 */ 442 if (!limits->turbo_disabled) 443 cpu->acpi_perf_data.states[0].core_frequency = 444 policy->cpuinfo.max_freq / 1000; 445 cpu->valid_pss_table = true; 446 pr_debug("_PPC limits will be enforced\n"); 447 448 return; 449 450 err: 451 cpu->valid_pss_table = false; 452 acpi_processor_unregister_performance(policy->cpu); 453 } 454 455 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 456 { 457 struct cpudata *cpu; 458 459 cpu = all_cpu_data[policy->cpu]; 460 if (!cpu->valid_pss_table) 461 return; 462 463 acpi_processor_unregister_performance(policy->cpu); 464 } 465 466 #else 467 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 468 { 469 } 470 471 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 472 { 473 } 474 #endif 475 476 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 477 int deadband, int integral) { 478 pid->setpoint = int_tofp(setpoint); 479 pid->deadband = int_tofp(deadband); 480 pid->integral = int_tofp(integral); 481 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 482 } 483 484 static inline void pid_p_gain_set(struct _pid *pid, int percent) 485 { 486 pid->p_gain = div_fp(percent, 100); 487 } 488 489 static inline void pid_i_gain_set(struct _pid *pid, int percent) 490 { 491 pid->i_gain = div_fp(percent, 100); 492 } 493 494 static inline void pid_d_gain_set(struct _pid *pid, int percent) 495 { 496 pid->d_gain = div_fp(percent, 100); 497 } 498 499 static signed int pid_calc(struct _pid *pid, int32_t busy) 500 { 501 signed int result; 502 int32_t pterm, dterm, fp_error; 503 int32_t integral_limit; 504 505 fp_error = pid->setpoint - busy; 506 507 if (abs(fp_error) <= pid->deadband) 508 return 0; 509 510 pterm = mul_fp(pid->p_gain, fp_error); 511 512 pid->integral += fp_error; 513 514 /* 515 * We limit the integral here so that it will never 516 * get higher than 30. This prevents it from becoming 517 * too large an input over long periods of time and allows 518 * it to get factored out sooner. 519 * 520 * The value of 30 was chosen through experimentation. 521 */ 522 integral_limit = int_tofp(30); 523 if (pid->integral > integral_limit) 524 pid->integral = integral_limit; 525 if (pid->integral < -integral_limit) 526 pid->integral = -integral_limit; 527 528 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 529 pid->last_err = fp_error; 530 531 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 532 result = result + (1 << (FRAC_BITS-1)); 533 return (signed int)fp_toint(result); 534 } 535 536 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 537 { 538 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 539 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 540 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 541 542 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 543 } 544 545 static inline void intel_pstate_reset_all_pid(void) 546 { 547 unsigned int cpu; 548 549 for_each_online_cpu(cpu) { 550 if (all_cpu_data[cpu]) 551 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 552 } 553 } 554 555 static inline void update_turbo_state(void) 556 { 557 u64 misc_en; 558 struct cpudata *cpu; 559 560 cpu = all_cpu_data[0]; 561 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 562 limits->turbo_disabled = 563 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 564 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 565 } 566 567 static void intel_pstate_hwp_set(const struct cpumask *cpumask) 568 { 569 int min, hw_min, max, hw_max, cpu, range, adj_range; 570 struct perf_limits *perf_limits = limits; 571 u64 value, cap; 572 573 for_each_cpu(cpu, cpumask) { 574 int max_perf_pct, min_perf_pct; 575 576 if (per_cpu_limits) 577 perf_limits = all_cpu_data[cpu]->perf_limits; 578 579 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 580 hw_min = HWP_LOWEST_PERF(cap); 581 hw_max = HWP_HIGHEST_PERF(cap); 582 range = hw_max - hw_min; 583 584 max_perf_pct = perf_limits->max_perf_pct; 585 min_perf_pct = perf_limits->min_perf_pct; 586 587 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 588 adj_range = min_perf_pct * range / 100; 589 min = hw_min + adj_range; 590 value &= ~HWP_MIN_PERF(~0L); 591 value |= HWP_MIN_PERF(min); 592 593 adj_range = max_perf_pct * range / 100; 594 max = hw_min + adj_range; 595 if (limits->no_turbo) { 596 hw_max = HWP_GUARANTEED_PERF(cap); 597 if (hw_max < max) 598 max = hw_max; 599 } 600 601 value &= ~HWP_MAX_PERF(~0L); 602 value |= HWP_MAX_PERF(max); 603 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 604 } 605 } 606 607 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) 608 { 609 if (hwp_active) 610 intel_pstate_hwp_set(policy->cpus); 611 612 return 0; 613 } 614 615 static void intel_pstate_hwp_set_online_cpus(void) 616 { 617 get_online_cpus(); 618 intel_pstate_hwp_set(cpu_online_mask); 619 put_online_cpus(); 620 } 621 622 /************************** debugfs begin ************************/ 623 static int pid_param_set(void *data, u64 val) 624 { 625 *(u32 *)data = val; 626 intel_pstate_reset_all_pid(); 627 return 0; 628 } 629 630 static int pid_param_get(void *data, u64 *val) 631 { 632 *val = *(u32 *)data; 633 return 0; 634 } 635 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 636 637 struct pid_param { 638 char *name; 639 void *value; 640 }; 641 642 static struct pid_param pid_files[] = { 643 {"sample_rate_ms", &pid_params.sample_rate_ms}, 644 {"d_gain_pct", &pid_params.d_gain_pct}, 645 {"i_gain_pct", &pid_params.i_gain_pct}, 646 {"deadband", &pid_params.deadband}, 647 {"setpoint", &pid_params.setpoint}, 648 {"p_gain_pct", &pid_params.p_gain_pct}, 649 {NULL, NULL} 650 }; 651 652 static void __init intel_pstate_debug_expose_params(void) 653 { 654 struct dentry *debugfs_parent; 655 int i = 0; 656 657 if (hwp_active || 658 pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) 659 return; 660 661 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 662 if (IS_ERR_OR_NULL(debugfs_parent)) 663 return; 664 while (pid_files[i].name) { 665 debugfs_create_file(pid_files[i].name, 0660, 666 debugfs_parent, pid_files[i].value, 667 &fops_pid_param); 668 i++; 669 } 670 } 671 672 /************************** debugfs end ************************/ 673 674 /************************** sysfs begin ************************/ 675 #define show_one(file_name, object) \ 676 static ssize_t show_##file_name \ 677 (struct kobject *kobj, struct attribute *attr, char *buf) \ 678 { \ 679 return sprintf(buf, "%u\n", limits->object); \ 680 } 681 682 static ssize_t show_turbo_pct(struct kobject *kobj, 683 struct attribute *attr, char *buf) 684 { 685 struct cpudata *cpu; 686 int total, no_turbo, turbo_pct; 687 uint32_t turbo_fp; 688 689 cpu = all_cpu_data[0]; 690 691 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 692 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 693 turbo_fp = div_fp(no_turbo, total); 694 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 695 return sprintf(buf, "%u\n", turbo_pct); 696 } 697 698 static ssize_t show_num_pstates(struct kobject *kobj, 699 struct attribute *attr, char *buf) 700 { 701 struct cpudata *cpu; 702 int total; 703 704 cpu = all_cpu_data[0]; 705 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 706 return sprintf(buf, "%u\n", total); 707 } 708 709 static ssize_t show_no_turbo(struct kobject *kobj, 710 struct attribute *attr, char *buf) 711 { 712 ssize_t ret; 713 714 update_turbo_state(); 715 if (limits->turbo_disabled) 716 ret = sprintf(buf, "%u\n", limits->turbo_disabled); 717 else 718 ret = sprintf(buf, "%u\n", limits->no_turbo); 719 720 return ret; 721 } 722 723 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 724 const char *buf, size_t count) 725 { 726 unsigned int input; 727 int ret; 728 729 ret = sscanf(buf, "%u", &input); 730 if (ret != 1) 731 return -EINVAL; 732 733 update_turbo_state(); 734 if (limits->turbo_disabled) { 735 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 736 return -EPERM; 737 } 738 739 limits->no_turbo = clamp_t(int, input, 0, 1); 740 741 if (hwp_active) 742 intel_pstate_hwp_set_online_cpus(); 743 744 return count; 745 } 746 747 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 748 const char *buf, size_t count) 749 { 750 unsigned int input; 751 int ret; 752 753 ret = sscanf(buf, "%u", &input); 754 if (ret != 1) 755 return -EINVAL; 756 757 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); 758 limits->max_perf_pct = min(limits->max_policy_pct, 759 limits->max_sysfs_pct); 760 limits->max_perf_pct = max(limits->min_policy_pct, 761 limits->max_perf_pct); 762 limits->max_perf_pct = max(limits->min_perf_pct, 763 limits->max_perf_pct); 764 limits->max_perf = div_fp(limits->max_perf_pct, 100); 765 766 if (hwp_active) 767 intel_pstate_hwp_set_online_cpus(); 768 return count; 769 } 770 771 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 772 const char *buf, size_t count) 773 { 774 unsigned int input; 775 int ret; 776 777 ret = sscanf(buf, "%u", &input); 778 if (ret != 1) 779 return -EINVAL; 780 781 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); 782 limits->min_perf_pct = max(limits->min_policy_pct, 783 limits->min_sysfs_pct); 784 limits->min_perf_pct = min(limits->max_policy_pct, 785 limits->min_perf_pct); 786 limits->min_perf_pct = min(limits->max_perf_pct, 787 limits->min_perf_pct); 788 limits->min_perf = div_fp(limits->min_perf_pct, 100); 789 790 if (hwp_active) 791 intel_pstate_hwp_set_online_cpus(); 792 return count; 793 } 794 795 show_one(max_perf_pct, max_perf_pct); 796 show_one(min_perf_pct, min_perf_pct); 797 798 define_one_global_rw(no_turbo); 799 define_one_global_rw(max_perf_pct); 800 define_one_global_rw(min_perf_pct); 801 define_one_global_ro(turbo_pct); 802 define_one_global_ro(num_pstates); 803 804 static struct attribute *intel_pstate_attributes[] = { 805 &no_turbo.attr, 806 &turbo_pct.attr, 807 &num_pstates.attr, 808 NULL 809 }; 810 811 static struct attribute_group intel_pstate_attr_group = { 812 .attrs = intel_pstate_attributes, 813 }; 814 815 static void __init intel_pstate_sysfs_expose_params(void) 816 { 817 struct kobject *intel_pstate_kobject; 818 int rc; 819 820 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 821 &cpu_subsys.dev_root->kobj); 822 if (WARN_ON(!intel_pstate_kobject)) 823 return; 824 825 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 826 if (WARN_ON(rc)) 827 return; 828 829 /* 830 * If per cpu limits are enforced there are no global limits, so 831 * return without creating max/min_perf_pct attributes 832 */ 833 if (per_cpu_limits) 834 return; 835 836 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 837 WARN_ON(rc); 838 839 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 840 WARN_ON(rc); 841 842 } 843 /************************** sysfs end ************************/ 844 845 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 846 { 847 /* First disable HWP notification interrupt as we don't process them */ 848 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) 849 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 850 851 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 852 } 853 854 static int atom_get_min_pstate(void) 855 { 856 u64 value; 857 858 rdmsrl(ATOM_RATIOS, value); 859 return (value >> 8) & 0x7F; 860 } 861 862 static int atom_get_max_pstate(void) 863 { 864 u64 value; 865 866 rdmsrl(ATOM_RATIOS, value); 867 return (value >> 16) & 0x7F; 868 } 869 870 static int atom_get_turbo_pstate(void) 871 { 872 u64 value; 873 874 rdmsrl(ATOM_TURBO_RATIOS, value); 875 return value & 0x7F; 876 } 877 878 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 879 { 880 u64 val; 881 int32_t vid_fp; 882 u32 vid; 883 884 val = (u64)pstate << 8; 885 if (limits->no_turbo && !limits->turbo_disabled) 886 val |= (u64)1 << 32; 887 888 vid_fp = cpudata->vid.min + mul_fp( 889 int_tofp(pstate - cpudata->pstate.min_pstate), 890 cpudata->vid.ratio); 891 892 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 893 vid = ceiling_fp(vid_fp); 894 895 if (pstate > cpudata->pstate.max_pstate) 896 vid = cpudata->vid.turbo; 897 898 return val | vid; 899 } 900 901 static int silvermont_get_scaling(void) 902 { 903 u64 value; 904 int i; 905 /* Defined in Table 35-6 from SDM (Sept 2015) */ 906 static int silvermont_freq_table[] = { 907 83300, 100000, 133300, 116700, 80000}; 908 909 rdmsrl(MSR_FSB_FREQ, value); 910 i = value & 0x7; 911 WARN_ON(i > 4); 912 913 return silvermont_freq_table[i]; 914 } 915 916 static int airmont_get_scaling(void) 917 { 918 u64 value; 919 int i; 920 /* Defined in Table 35-10 from SDM (Sept 2015) */ 921 static int airmont_freq_table[] = { 922 83300, 100000, 133300, 116700, 80000, 923 93300, 90000, 88900, 87500}; 924 925 rdmsrl(MSR_FSB_FREQ, value); 926 i = value & 0xF; 927 WARN_ON(i > 8); 928 929 return airmont_freq_table[i]; 930 } 931 932 static void atom_get_vid(struct cpudata *cpudata) 933 { 934 u64 value; 935 936 rdmsrl(ATOM_VIDS, value); 937 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 938 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 939 cpudata->vid.ratio = div_fp( 940 cpudata->vid.max - cpudata->vid.min, 941 int_tofp(cpudata->pstate.max_pstate - 942 cpudata->pstate.min_pstate)); 943 944 rdmsrl(ATOM_TURBO_VIDS, value); 945 cpudata->vid.turbo = value & 0x7f; 946 } 947 948 static int core_get_min_pstate(void) 949 { 950 u64 value; 951 952 rdmsrl(MSR_PLATFORM_INFO, value); 953 return (value >> 40) & 0xFF; 954 } 955 956 static int core_get_max_pstate_physical(void) 957 { 958 u64 value; 959 960 rdmsrl(MSR_PLATFORM_INFO, value); 961 return (value >> 8) & 0xFF; 962 } 963 964 static int core_get_max_pstate(void) 965 { 966 u64 tar; 967 u64 plat_info; 968 int max_pstate; 969 int err; 970 971 rdmsrl(MSR_PLATFORM_INFO, plat_info); 972 max_pstate = (plat_info >> 8) & 0xFF; 973 974 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 975 if (!err) { 976 /* Do some sanity checking for safety */ 977 if (plat_info & 0x600000000) { 978 u64 tdp_ctrl; 979 u64 tdp_ratio; 980 int tdp_msr; 981 982 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 983 if (err) 984 goto skip_tar; 985 986 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3); 987 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 988 if (err) 989 goto skip_tar; 990 991 /* For level 1 and 2, bits[23:16] contain the ratio */ 992 if (tdp_ctrl) 993 tdp_ratio >>= 16; 994 995 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 996 if (tdp_ratio - 1 == tar) { 997 max_pstate = tar; 998 pr_debug("max_pstate=TAC %x\n", max_pstate); 999 } else { 1000 goto skip_tar; 1001 } 1002 } 1003 } 1004 1005 skip_tar: 1006 return max_pstate; 1007 } 1008 1009 static int core_get_turbo_pstate(void) 1010 { 1011 u64 value; 1012 int nont, ret; 1013 1014 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1015 nont = core_get_max_pstate(); 1016 ret = (value) & 255; 1017 if (ret <= nont) 1018 ret = nont; 1019 return ret; 1020 } 1021 1022 static inline int core_get_scaling(void) 1023 { 1024 return 100000; 1025 } 1026 1027 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1028 { 1029 u64 val; 1030 1031 val = (u64)pstate << 8; 1032 if (limits->no_turbo && !limits->turbo_disabled) 1033 val |= (u64)1 << 32; 1034 1035 return val; 1036 } 1037 1038 static int knl_get_turbo_pstate(void) 1039 { 1040 u64 value; 1041 int nont, ret; 1042 1043 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1044 nont = core_get_max_pstate(); 1045 ret = (((value) >> 8) & 0xFF); 1046 if (ret <= nont) 1047 ret = nont; 1048 return ret; 1049 } 1050 1051 static struct cpu_defaults core_params = { 1052 .pid_policy = { 1053 .sample_rate_ms = 10, 1054 .deadband = 0, 1055 .setpoint = 97, 1056 .p_gain_pct = 20, 1057 .d_gain_pct = 0, 1058 .i_gain_pct = 0, 1059 }, 1060 .funcs = { 1061 .get_max = core_get_max_pstate, 1062 .get_max_physical = core_get_max_pstate_physical, 1063 .get_min = core_get_min_pstate, 1064 .get_turbo = core_get_turbo_pstate, 1065 .get_scaling = core_get_scaling, 1066 .get_val = core_get_val, 1067 .get_target_pstate = get_target_pstate_use_performance, 1068 }, 1069 }; 1070 1071 static const struct cpu_defaults silvermont_params = { 1072 .pid_policy = { 1073 .sample_rate_ms = 10, 1074 .deadband = 0, 1075 .setpoint = 60, 1076 .p_gain_pct = 14, 1077 .d_gain_pct = 0, 1078 .i_gain_pct = 4, 1079 }, 1080 .funcs = { 1081 .get_max = atom_get_max_pstate, 1082 .get_max_physical = atom_get_max_pstate, 1083 .get_min = atom_get_min_pstate, 1084 .get_turbo = atom_get_turbo_pstate, 1085 .get_val = atom_get_val, 1086 .get_scaling = silvermont_get_scaling, 1087 .get_vid = atom_get_vid, 1088 .get_target_pstate = get_target_pstate_use_cpu_load, 1089 }, 1090 }; 1091 1092 static const struct cpu_defaults airmont_params = { 1093 .pid_policy = { 1094 .sample_rate_ms = 10, 1095 .deadband = 0, 1096 .setpoint = 60, 1097 .p_gain_pct = 14, 1098 .d_gain_pct = 0, 1099 .i_gain_pct = 4, 1100 }, 1101 .funcs = { 1102 .get_max = atom_get_max_pstate, 1103 .get_max_physical = atom_get_max_pstate, 1104 .get_min = atom_get_min_pstate, 1105 .get_turbo = atom_get_turbo_pstate, 1106 .get_val = atom_get_val, 1107 .get_scaling = airmont_get_scaling, 1108 .get_vid = atom_get_vid, 1109 .get_target_pstate = get_target_pstate_use_cpu_load, 1110 }, 1111 }; 1112 1113 static const struct cpu_defaults knl_params = { 1114 .pid_policy = { 1115 .sample_rate_ms = 10, 1116 .deadband = 0, 1117 .setpoint = 97, 1118 .p_gain_pct = 20, 1119 .d_gain_pct = 0, 1120 .i_gain_pct = 0, 1121 }, 1122 .funcs = { 1123 .get_max = core_get_max_pstate, 1124 .get_max_physical = core_get_max_pstate_physical, 1125 .get_min = core_get_min_pstate, 1126 .get_turbo = knl_get_turbo_pstate, 1127 .get_scaling = core_get_scaling, 1128 .get_val = core_get_val, 1129 .get_target_pstate = get_target_pstate_use_performance, 1130 }, 1131 }; 1132 1133 static const struct cpu_defaults bxt_params = { 1134 .pid_policy = { 1135 .sample_rate_ms = 10, 1136 .deadband = 0, 1137 .setpoint = 60, 1138 .p_gain_pct = 14, 1139 .d_gain_pct = 0, 1140 .i_gain_pct = 4, 1141 }, 1142 .funcs = { 1143 .get_max = core_get_max_pstate, 1144 .get_max_physical = core_get_max_pstate_physical, 1145 .get_min = core_get_min_pstate, 1146 .get_turbo = core_get_turbo_pstate, 1147 .get_scaling = core_get_scaling, 1148 .get_val = core_get_val, 1149 .get_target_pstate = get_target_pstate_use_cpu_load, 1150 }, 1151 }; 1152 1153 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1154 { 1155 int max_perf = cpu->pstate.turbo_pstate; 1156 int max_perf_adj; 1157 int min_perf; 1158 struct perf_limits *perf_limits = limits; 1159 1160 if (limits->no_turbo || limits->turbo_disabled) 1161 max_perf = cpu->pstate.max_pstate; 1162 1163 if (per_cpu_limits) 1164 perf_limits = cpu->perf_limits; 1165 1166 /* 1167 * performance can be limited by user through sysfs, by cpufreq 1168 * policy, or by cpu specific default values determined through 1169 * experimentation. 1170 */ 1171 max_perf_adj = fp_toint(max_perf * perf_limits->max_perf); 1172 *max = clamp_t(int, max_perf_adj, 1173 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1174 1175 min_perf = fp_toint(max_perf * perf_limits->min_perf); 1176 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1177 } 1178 1179 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1180 { 1181 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1182 cpu->pstate.current_pstate = pstate; 1183 /* 1184 * Generally, there is no guarantee that this code will always run on 1185 * the CPU being updated, so force the register update to run on the 1186 * right CPU. 1187 */ 1188 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1189 pstate_funcs.get_val(cpu, pstate)); 1190 } 1191 1192 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1193 { 1194 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1195 } 1196 1197 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1198 { 1199 int min_pstate, max_pstate; 1200 1201 update_turbo_state(); 1202 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); 1203 intel_pstate_set_pstate(cpu, max_pstate); 1204 } 1205 1206 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1207 { 1208 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1209 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1210 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1211 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1212 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1213 1214 if (pstate_funcs.get_vid) 1215 pstate_funcs.get_vid(cpu); 1216 1217 intel_pstate_set_min_pstate(cpu); 1218 } 1219 1220 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1221 { 1222 struct sample *sample = &cpu->sample; 1223 1224 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1225 } 1226 1227 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1228 { 1229 u64 aperf, mperf; 1230 unsigned long flags; 1231 u64 tsc; 1232 1233 local_irq_save(flags); 1234 rdmsrl(MSR_IA32_APERF, aperf); 1235 rdmsrl(MSR_IA32_MPERF, mperf); 1236 tsc = rdtsc(); 1237 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1238 local_irq_restore(flags); 1239 return false; 1240 } 1241 local_irq_restore(flags); 1242 1243 cpu->last_sample_time = cpu->sample.time; 1244 cpu->sample.time = time; 1245 cpu->sample.aperf = aperf; 1246 cpu->sample.mperf = mperf; 1247 cpu->sample.tsc = tsc; 1248 cpu->sample.aperf -= cpu->prev_aperf; 1249 cpu->sample.mperf -= cpu->prev_mperf; 1250 cpu->sample.tsc -= cpu->prev_tsc; 1251 1252 cpu->prev_aperf = aperf; 1253 cpu->prev_mperf = mperf; 1254 cpu->prev_tsc = tsc; 1255 /* 1256 * First time this function is invoked in a given cycle, all of the 1257 * previous sample data fields are equal to zero or stale and they must 1258 * be populated with meaningful numbers for things to work, so assume 1259 * that sample.time will always be reset before setting the utilization 1260 * update hook and make the caller skip the sample then. 1261 */ 1262 return !!cpu->last_sample_time; 1263 } 1264 1265 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1266 { 1267 return mul_ext_fp(cpu->sample.core_avg_perf, 1268 cpu->pstate.max_pstate_physical * cpu->pstate.scaling); 1269 } 1270 1271 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1272 { 1273 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1274 cpu->sample.core_avg_perf); 1275 } 1276 1277 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1278 { 1279 struct sample *sample = &cpu->sample; 1280 int32_t busy_frac, boost; 1281 int target, avg_pstate; 1282 1283 busy_frac = div_fp(sample->mperf, sample->tsc); 1284 1285 boost = cpu->iowait_boost; 1286 cpu->iowait_boost >>= 1; 1287 1288 if (busy_frac < boost) 1289 busy_frac = boost; 1290 1291 sample->busy_scaled = busy_frac * 100; 1292 1293 target = limits->no_turbo || limits->turbo_disabled ? 1294 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1295 target += target >> 2; 1296 target = mul_fp(target, busy_frac); 1297 if (target < cpu->pstate.min_pstate) 1298 target = cpu->pstate.min_pstate; 1299 1300 /* 1301 * If the average P-state during the previous cycle was higher than the 1302 * current target, add 50% of the difference to the target to reduce 1303 * possible performance oscillations and offset possible performance 1304 * loss related to moving the workload from one CPU to another within 1305 * a package/module. 1306 */ 1307 avg_pstate = get_avg_pstate(cpu); 1308 if (avg_pstate > target) 1309 target += (avg_pstate - target) >> 1; 1310 1311 return target; 1312 } 1313 1314 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1315 { 1316 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; 1317 u64 duration_ns; 1318 1319 /* 1320 * perf_scaled is the ratio of the average P-state during the last 1321 * sampling period to the P-state requested last time (in percent). 1322 * 1323 * That measures the system's response to the previous P-state 1324 * selection. 1325 */ 1326 max_pstate = cpu->pstate.max_pstate_physical; 1327 current_pstate = cpu->pstate.current_pstate; 1328 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, 1329 div_fp(100 * max_pstate, current_pstate)); 1330 1331 /* 1332 * Since our utilization update callback will not run unless we are 1333 * in C0, check if the actual elapsed time is significantly greater (3x) 1334 * than our sample interval. If it is, then we were idle for a long 1335 * enough period of time to adjust our performance metric. 1336 */ 1337 duration_ns = cpu->sample.time - cpu->last_sample_time; 1338 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1339 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1340 perf_scaled = mul_fp(perf_scaled, sample_ratio); 1341 } else { 1342 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1343 if (sample_ratio < int_tofp(1)) 1344 perf_scaled = 0; 1345 } 1346 1347 cpu->sample.busy_scaled = perf_scaled; 1348 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); 1349 } 1350 1351 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1352 { 1353 int max_perf, min_perf; 1354 1355 update_turbo_state(); 1356 1357 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1358 pstate = clamp_t(int, pstate, min_perf, max_perf); 1359 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1360 if (pstate == cpu->pstate.current_pstate) 1361 return; 1362 1363 cpu->pstate.current_pstate = pstate; 1364 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1365 } 1366 1367 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1368 { 1369 int from, target_pstate; 1370 struct sample *sample; 1371 1372 from = cpu->pstate.current_pstate; 1373 1374 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ? 1375 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu); 1376 1377 intel_pstate_update_pstate(cpu, target_pstate); 1378 1379 sample = &cpu->sample; 1380 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1381 fp_toint(sample->busy_scaled), 1382 from, 1383 cpu->pstate.current_pstate, 1384 sample->mperf, 1385 sample->aperf, 1386 sample->tsc, 1387 get_avg_frequency(cpu), 1388 fp_toint(cpu->iowait_boost * 100)); 1389 } 1390 1391 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1392 unsigned int flags) 1393 { 1394 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1395 u64 delta_ns; 1396 1397 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) { 1398 if (flags & SCHED_CPUFREQ_IOWAIT) { 1399 cpu->iowait_boost = int_tofp(1); 1400 } else if (cpu->iowait_boost) { 1401 /* Clear iowait_boost if the CPU may have been idle. */ 1402 delta_ns = time - cpu->last_update; 1403 if (delta_ns > TICK_NSEC) 1404 cpu->iowait_boost = 0; 1405 } 1406 cpu->last_update = time; 1407 } 1408 1409 delta_ns = time - cpu->sample.time; 1410 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1411 bool sample_taken = intel_pstate_sample(cpu, time); 1412 1413 if (sample_taken) { 1414 intel_pstate_calc_avg_perf(cpu); 1415 if (!hwp_active) 1416 intel_pstate_adjust_busy_pstate(cpu); 1417 } 1418 } 1419 } 1420 1421 #define ICPU(model, policy) \ 1422 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1423 (unsigned long)&policy } 1424 1425 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1426 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), 1427 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), 1428 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), 1429 ICPU(INTEL_FAM6_IVYBRIDGE, core_params), 1430 ICPU(INTEL_FAM6_HASWELL_CORE, core_params), 1431 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), 1432 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), 1433 ICPU(INTEL_FAM6_HASWELL_X, core_params), 1434 ICPU(INTEL_FAM6_HASWELL_ULT, core_params), 1435 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), 1436 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), 1437 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), 1438 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), 1439 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1440 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), 1441 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1442 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), 1443 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), 1444 {} 1445 }; 1446 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1447 1448 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1449 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1450 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1451 ICPU(INTEL_FAM6_SKYLAKE_X, core_params), 1452 {} 1453 }; 1454 1455 static int intel_pstate_init_cpu(unsigned int cpunum) 1456 { 1457 struct cpudata *cpu; 1458 1459 cpu = all_cpu_data[cpunum]; 1460 1461 if (!cpu) { 1462 unsigned int size = sizeof(struct cpudata); 1463 1464 if (per_cpu_limits) 1465 size += sizeof(struct perf_limits); 1466 1467 cpu = kzalloc(size, GFP_KERNEL); 1468 if (!cpu) 1469 return -ENOMEM; 1470 1471 all_cpu_data[cpunum] = cpu; 1472 if (per_cpu_limits) 1473 cpu->perf_limits = (struct perf_limits *)(cpu + 1); 1474 1475 } 1476 1477 cpu = all_cpu_data[cpunum]; 1478 1479 cpu->cpu = cpunum; 1480 1481 if (hwp_active) { 1482 intel_pstate_hwp_enable(cpu); 1483 pid_params.sample_rate_ms = 50; 1484 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1485 } 1486 1487 intel_pstate_get_cpu_pstates(cpu); 1488 1489 intel_pstate_busy_pid_reset(cpu); 1490 1491 pr_debug("controlling: cpu %d\n", cpunum); 1492 1493 return 0; 1494 } 1495 1496 static unsigned int intel_pstate_get(unsigned int cpu_num) 1497 { 1498 struct cpudata *cpu = all_cpu_data[cpu_num]; 1499 1500 return cpu ? get_avg_frequency(cpu) : 0; 1501 } 1502 1503 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1504 { 1505 struct cpudata *cpu = all_cpu_data[cpu_num]; 1506 1507 if (cpu->update_util_set) 1508 return; 1509 1510 /* Prevent intel_pstate_update_util() from using stale data. */ 1511 cpu->sample.time = 0; 1512 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1513 intel_pstate_update_util); 1514 cpu->update_util_set = true; 1515 } 1516 1517 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1518 { 1519 struct cpudata *cpu_data = all_cpu_data[cpu]; 1520 1521 if (!cpu_data->update_util_set) 1522 return; 1523 1524 cpufreq_remove_update_util_hook(cpu); 1525 cpu_data->update_util_set = false; 1526 synchronize_sched(); 1527 } 1528 1529 static void intel_pstate_set_performance_limits(struct perf_limits *limits) 1530 { 1531 limits->no_turbo = 0; 1532 limits->turbo_disabled = 0; 1533 limits->max_perf_pct = 100; 1534 limits->max_perf = int_tofp(1); 1535 limits->min_perf_pct = 100; 1536 limits->min_perf = int_tofp(1); 1537 limits->max_policy_pct = 100; 1538 limits->max_sysfs_pct = 100; 1539 limits->min_policy_pct = 0; 1540 limits->min_sysfs_pct = 0; 1541 } 1542 1543 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, 1544 struct perf_limits *limits) 1545 { 1546 limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 1547 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0, 100); 1548 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, 1549 policy->cpuinfo.max_freq); 1550 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100); 1551 1552 /* Normalize user input to [min_policy_pct, max_policy_pct] */ 1553 limits->min_perf_pct = max(limits->min_policy_pct, 1554 limits->min_sysfs_pct); 1555 limits->min_perf_pct = min(limits->max_policy_pct, 1556 limits->min_perf_pct); 1557 limits->max_perf_pct = min(limits->max_policy_pct, 1558 limits->max_sysfs_pct); 1559 limits->max_perf_pct = max(limits->min_policy_pct, 1560 limits->max_perf_pct); 1561 1562 /* Make sure min_perf_pct <= max_perf_pct */ 1563 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); 1564 1565 limits->min_perf = div_fp(limits->min_perf_pct, 100); 1566 limits->max_perf = div_fp(limits->max_perf_pct, 100); 1567 limits->max_perf = round_up(limits->max_perf, FRAC_BITS); 1568 1569 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, 1570 limits->max_perf_pct, limits->min_perf_pct); 1571 } 1572 1573 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1574 { 1575 struct cpudata *cpu; 1576 struct perf_limits *perf_limits = NULL; 1577 1578 if (!policy->cpuinfo.max_freq) 1579 return -ENODEV; 1580 1581 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 1582 policy->cpuinfo.max_freq, policy->max); 1583 1584 cpu = all_cpu_data[policy->cpu]; 1585 cpu->policy = policy->policy; 1586 1587 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 1588 policy->max < policy->cpuinfo.max_freq && 1589 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 1590 pr_debug("policy->max > max non turbo frequency\n"); 1591 policy->max = policy->cpuinfo.max_freq; 1592 } 1593 1594 if (per_cpu_limits) 1595 perf_limits = cpu->perf_limits; 1596 1597 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 1598 if (!perf_limits) { 1599 limits = &performance_limits; 1600 perf_limits = limits; 1601 } 1602 if (policy->max >= policy->cpuinfo.max_freq) { 1603 pr_debug("set performance\n"); 1604 intel_pstate_set_performance_limits(perf_limits); 1605 goto out; 1606 } 1607 } else { 1608 pr_debug("set powersave\n"); 1609 if (!perf_limits) { 1610 limits = &powersave_limits; 1611 perf_limits = limits; 1612 } 1613 1614 } 1615 1616 intel_pstate_update_perf_limits(policy, perf_limits); 1617 out: 1618 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 1619 /* 1620 * NOHZ_FULL CPUs need this as the governor callback may not 1621 * be invoked on them. 1622 */ 1623 intel_pstate_clear_update_util_hook(policy->cpu); 1624 intel_pstate_max_within_limits(cpu); 1625 } 1626 1627 intel_pstate_set_update_util_hook(policy->cpu); 1628 1629 intel_pstate_hwp_set_policy(policy); 1630 1631 return 0; 1632 } 1633 1634 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 1635 { 1636 cpufreq_verify_within_cpu_limits(policy); 1637 1638 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 1639 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 1640 return -EINVAL; 1641 1642 return 0; 1643 } 1644 1645 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 1646 { 1647 int cpu_num = policy->cpu; 1648 struct cpudata *cpu = all_cpu_data[cpu_num]; 1649 1650 pr_debug("CPU %d exiting\n", cpu_num); 1651 1652 intel_pstate_clear_update_util_hook(cpu_num); 1653 1654 if (hwp_active) 1655 return; 1656 1657 intel_pstate_set_min_pstate(cpu); 1658 } 1659 1660 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 1661 { 1662 struct cpudata *cpu; 1663 int rc; 1664 1665 rc = intel_pstate_init_cpu(policy->cpu); 1666 if (rc) 1667 return rc; 1668 1669 cpu = all_cpu_data[policy->cpu]; 1670 1671 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) 1672 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1673 else 1674 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1675 1676 /* 1677 * We need sane value in the cpu->perf_limits, so inherit from global 1678 * perf_limits limits, which are seeded with values based on the 1679 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up. 1680 */ 1681 if (per_cpu_limits) 1682 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits)); 1683 1684 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 1685 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1686 1687 /* cpuinfo and default policy values */ 1688 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1689 update_turbo_state(); 1690 policy->cpuinfo.max_freq = limits->turbo_disabled ? 1691 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1692 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 1693 1694 intel_pstate_init_acpi_perf_limits(policy); 1695 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1696 cpumask_set_cpu(policy->cpu, policy->cpus); 1697 1698 return 0; 1699 } 1700 1701 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 1702 { 1703 intel_pstate_exit_perf_limits(policy); 1704 1705 return 0; 1706 } 1707 1708 static struct cpufreq_driver intel_pstate_driver = { 1709 .flags = CPUFREQ_CONST_LOOPS, 1710 .verify = intel_pstate_verify_policy, 1711 .setpolicy = intel_pstate_set_policy, 1712 .resume = intel_pstate_hwp_set_policy, 1713 .get = intel_pstate_get, 1714 .init = intel_pstate_cpu_init, 1715 .exit = intel_pstate_cpu_exit, 1716 .stop_cpu = intel_pstate_stop_cpu, 1717 .name = "intel_pstate", 1718 }; 1719 1720 static int no_load __initdata; 1721 static int no_hwp __initdata; 1722 static int hwp_only __initdata; 1723 static unsigned int force_load __initdata; 1724 1725 static int __init intel_pstate_msrs_not_valid(void) 1726 { 1727 if (!pstate_funcs.get_max() || 1728 !pstate_funcs.get_min() || 1729 !pstate_funcs.get_turbo()) 1730 return -ENODEV; 1731 1732 return 0; 1733 } 1734 1735 static void __init copy_pid_params(struct pstate_adjust_policy *policy) 1736 { 1737 pid_params.sample_rate_ms = policy->sample_rate_ms; 1738 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 1739 pid_params.p_gain_pct = policy->p_gain_pct; 1740 pid_params.i_gain_pct = policy->i_gain_pct; 1741 pid_params.d_gain_pct = policy->d_gain_pct; 1742 pid_params.deadband = policy->deadband; 1743 pid_params.setpoint = policy->setpoint; 1744 } 1745 1746 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 1747 { 1748 pstate_funcs.get_max = funcs->get_max; 1749 pstate_funcs.get_max_physical = funcs->get_max_physical; 1750 pstate_funcs.get_min = funcs->get_min; 1751 pstate_funcs.get_turbo = funcs->get_turbo; 1752 pstate_funcs.get_scaling = funcs->get_scaling; 1753 pstate_funcs.get_val = funcs->get_val; 1754 pstate_funcs.get_vid = funcs->get_vid; 1755 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 1756 1757 } 1758 1759 #ifdef CONFIG_ACPI 1760 1761 static bool __init intel_pstate_no_acpi_pss(void) 1762 { 1763 int i; 1764 1765 for_each_possible_cpu(i) { 1766 acpi_status status; 1767 union acpi_object *pss; 1768 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1769 struct acpi_processor *pr = per_cpu(processors, i); 1770 1771 if (!pr) 1772 continue; 1773 1774 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1775 if (ACPI_FAILURE(status)) 1776 continue; 1777 1778 pss = buffer.pointer; 1779 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1780 kfree(pss); 1781 return false; 1782 } 1783 1784 kfree(pss); 1785 } 1786 1787 return true; 1788 } 1789 1790 static bool __init intel_pstate_has_acpi_ppc(void) 1791 { 1792 int i; 1793 1794 for_each_possible_cpu(i) { 1795 struct acpi_processor *pr = per_cpu(processors, i); 1796 1797 if (!pr) 1798 continue; 1799 if (acpi_has_method(pr->handle, "_PPC")) 1800 return true; 1801 } 1802 return false; 1803 } 1804 1805 enum { 1806 PSS, 1807 PPC, 1808 }; 1809 1810 struct hw_vendor_info { 1811 u16 valid; 1812 char oem_id[ACPI_OEM_ID_SIZE]; 1813 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1814 int oem_pwr_table; 1815 }; 1816 1817 /* Hardware vendor-specific info that has its own power management modes */ 1818 static struct hw_vendor_info vendor_info[] __initdata = { 1819 {1, "HP ", "ProLiant", PSS}, 1820 {1, "ORACLE", "X4-2 ", PPC}, 1821 {1, "ORACLE", "X4-2L ", PPC}, 1822 {1, "ORACLE", "X4-2B ", PPC}, 1823 {1, "ORACLE", "X3-2 ", PPC}, 1824 {1, "ORACLE", "X3-2L ", PPC}, 1825 {1, "ORACLE", "X3-2B ", PPC}, 1826 {1, "ORACLE", "X4470M2 ", PPC}, 1827 {1, "ORACLE", "X4270M3 ", PPC}, 1828 {1, "ORACLE", "X4270M2 ", PPC}, 1829 {1, "ORACLE", "X4170M2 ", PPC}, 1830 {1, "ORACLE", "X4170 M3", PPC}, 1831 {1, "ORACLE", "X4275 M3", PPC}, 1832 {1, "ORACLE", "X6-2 ", PPC}, 1833 {1, "ORACLE", "Sudbury ", PPC}, 1834 {0, "", ""}, 1835 }; 1836 1837 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 1838 { 1839 struct acpi_table_header hdr; 1840 struct hw_vendor_info *v_info; 1841 const struct x86_cpu_id *id; 1842 u64 misc_pwr; 1843 1844 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1845 if (id) { 1846 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1847 if ( misc_pwr & (1 << 8)) 1848 return true; 1849 } 1850 1851 if (acpi_disabled || 1852 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1853 return false; 1854 1855 for (v_info = vendor_info; v_info->valid; v_info++) { 1856 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1857 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1858 ACPI_OEM_TABLE_ID_SIZE)) 1859 switch (v_info->oem_pwr_table) { 1860 case PSS: 1861 return intel_pstate_no_acpi_pss(); 1862 case PPC: 1863 return intel_pstate_has_acpi_ppc() && 1864 (!force_load); 1865 } 1866 } 1867 1868 return false; 1869 } 1870 #else /* CONFIG_ACPI not enabled */ 1871 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1872 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1873 #endif /* CONFIG_ACPI */ 1874 1875 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 1876 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 1877 {} 1878 }; 1879 1880 static int __init intel_pstate_init(void) 1881 { 1882 int cpu, rc = 0; 1883 const struct x86_cpu_id *id; 1884 struct cpu_defaults *cpu_def; 1885 1886 if (no_load) 1887 return -ENODEV; 1888 1889 if (x86_match_cpu(hwp_support_ids) && !no_hwp) { 1890 copy_cpu_funcs(&core_params.funcs); 1891 hwp_active++; 1892 goto hwp_cpu_matched; 1893 } 1894 1895 id = x86_match_cpu(intel_pstate_cpu_ids); 1896 if (!id) 1897 return -ENODEV; 1898 1899 cpu_def = (struct cpu_defaults *)id->driver_data; 1900 1901 copy_pid_params(&cpu_def->pid_policy); 1902 copy_cpu_funcs(&cpu_def->funcs); 1903 1904 if (intel_pstate_msrs_not_valid()) 1905 return -ENODEV; 1906 1907 hwp_cpu_matched: 1908 /* 1909 * The Intel pstate driver will be ignored if the platform 1910 * firmware has its own power management modes. 1911 */ 1912 if (intel_pstate_platform_pwr_mgmt_exists()) 1913 return -ENODEV; 1914 1915 pr_info("Intel P-state driver initializing\n"); 1916 1917 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1918 if (!all_cpu_data) 1919 return -ENOMEM; 1920 1921 if (!hwp_active && hwp_only) 1922 goto out; 1923 1924 rc = cpufreq_register_driver(&intel_pstate_driver); 1925 if (rc) 1926 goto out; 1927 1928 intel_pstate_debug_expose_params(); 1929 intel_pstate_sysfs_expose_params(); 1930 1931 if (hwp_active) 1932 pr_info("HWP enabled\n"); 1933 1934 return rc; 1935 out: 1936 get_online_cpus(); 1937 for_each_online_cpu(cpu) { 1938 if (all_cpu_data[cpu]) { 1939 intel_pstate_clear_update_util_hook(cpu); 1940 kfree(all_cpu_data[cpu]); 1941 } 1942 } 1943 1944 put_online_cpus(); 1945 vfree(all_cpu_data); 1946 return -ENODEV; 1947 } 1948 device_initcall(intel_pstate_init); 1949 1950 static int __init intel_pstate_setup(char *str) 1951 { 1952 if (!str) 1953 return -EINVAL; 1954 1955 if (!strcmp(str, "disable")) 1956 no_load = 1; 1957 if (!strcmp(str, "no_hwp")) { 1958 pr_info("HWP disabled\n"); 1959 no_hwp = 1; 1960 } 1961 if (!strcmp(str, "force")) 1962 force_load = 1; 1963 if (!strcmp(str, "hwp_only")) 1964 hwp_only = 1; 1965 if (!strcmp(str, "per_cpu_perf_limits")) 1966 per_cpu_limits = true; 1967 1968 #ifdef CONFIG_ACPI 1969 if (!strcmp(str, "support_acpi_ppc")) 1970 acpi_ppc = true; 1971 #endif 1972 1973 return 0; 1974 } 1975 early_param("intel_pstate", intel_pstate_setup); 1976 1977 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1978 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1979 MODULE_LICENSE("GPL"); 1980