1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * intel_pstate.c: Native P state management for Intel processors
4  *
5  * (C) Copyright 2012 Intel Corporation
6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7  */
8 
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
24 #include <linux/fs.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
29 
30 #include <asm/cpu.h>
31 #include <asm/div64.h>
32 #include <asm/msr.h>
33 #include <asm/cpu_device_id.h>
34 #include <asm/cpufeature.h>
35 #include <asm/intel-family.h>
36 #include "../drivers/thermal/intel/thermal_interrupt.h"
37 
38 #define INTEL_PSTATE_SAMPLING_INTERVAL	(10 * NSEC_PER_MSEC)
39 
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY	20000
41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP	5000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY		500
43 
44 #ifdef CONFIG_ACPI
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
47 #endif
48 
49 #define FRAC_BITS 8
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
52 
53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
54 
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59 
60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62 	return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64 
65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67 	return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69 
70 static inline int ceiling_fp(int32_t x)
71 {
72 	int mask, ret;
73 
74 	ret = fp_toint(x);
75 	mask = (1 << FRAC_BITS) - 1;
76 	if (x & mask)
77 		ret += 1;
78 	return ret;
79 }
80 
81 static inline u64 mul_ext_fp(u64 x, u64 y)
82 {
83 	return (x * y) >> EXT_FRAC_BITS;
84 }
85 
86 static inline u64 div_ext_fp(u64 x, u64 y)
87 {
88 	return div64_u64(x << EXT_FRAC_BITS, y);
89 }
90 
91 /**
92  * struct sample -	Store performance sample
93  * @core_avg_perf:	Ratio of APERF/MPERF which is the actual average
94  *			performance during last sample period
95  * @busy_scaled:	Scaled busy value which is used to calculate next
96  *			P state. This can be different than core_avg_perf
97  *			to account for cpu idle period
98  * @aperf:		Difference of actual performance frequency clock count
99  *			read from APERF MSR between last and current sample
100  * @mperf:		Difference of maximum performance frequency clock count
101  *			read from MPERF MSR between last and current sample
102  * @tsc:		Difference of time stamp counter between last and
103  *			current sample
104  * @time:		Current time from scheduler
105  *
106  * This structure is used in the cpudata structure to store performance sample
107  * data for choosing next P State.
108  */
109 struct sample {
110 	int32_t core_avg_perf;
111 	int32_t busy_scaled;
112 	u64 aperf;
113 	u64 mperf;
114 	u64 tsc;
115 	u64 time;
116 };
117 
118 /**
119  * struct pstate_data - Store P state data
120  * @current_pstate:	Current requested P state
121  * @min_pstate:		Min P state possible for this platform
122  * @max_pstate:		Max P state possible for this platform
123  * @max_pstate_physical:This is physical Max P state for a processor
124  *			This can be higher than the max_pstate which can
125  *			be limited by platform thermal design power limits
126  * @perf_ctl_scaling:	PERF_CTL P-state to frequency scaling factor
127  * @scaling:		Scaling factor between performance and frequency
128  * @turbo_pstate:	Max Turbo P state possible for this platform
129  * @min_freq:		@min_pstate frequency in cpufreq units
130  * @max_freq:		@max_pstate frequency in cpufreq units
131  * @turbo_freq:		@turbo_pstate frequency in cpufreq units
132  *
133  * Stores the per cpu model P state limits and current P state.
134  */
135 struct pstate_data {
136 	int	current_pstate;
137 	int	min_pstate;
138 	int	max_pstate;
139 	int	max_pstate_physical;
140 	int	perf_ctl_scaling;
141 	int	scaling;
142 	int	turbo_pstate;
143 	unsigned int min_freq;
144 	unsigned int max_freq;
145 	unsigned int turbo_freq;
146 };
147 
148 /**
149  * struct vid_data -	Stores voltage information data
150  * @min:		VID data for this platform corresponding to
151  *			the lowest P state
152  * @max:		VID data corresponding to the highest P State.
153  * @turbo:		VID data for turbo P state
154  * @ratio:		Ratio of (vid max - vid min) /
155  *			(max P state - Min P State)
156  *
157  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
158  * This data is used in Atom platforms, where in addition to target P state,
159  * the voltage data needs to be specified to select next P State.
160  */
161 struct vid_data {
162 	int min;
163 	int max;
164 	int turbo;
165 	int32_t ratio;
166 };
167 
168 /**
169  * struct global_params - Global parameters, mostly tunable via sysfs.
170  * @no_turbo:		Whether or not to use turbo P-states.
171  * @turbo_disabled:	Whether or not turbo P-states are available at all,
172  *			based on the MSR_IA32_MISC_ENABLE value and whether or
173  *			not the maximum reported turbo P-state is different from
174  *			the maximum reported non-turbo one.
175  * @turbo_disabled_mf:	The @turbo_disabled value reflected by cpuinfo.max_freq.
176  * @min_perf_pct:	Minimum capacity limit in percent of the maximum turbo
177  *			P-state capacity.
178  * @max_perf_pct:	Maximum capacity limit in percent of the maximum turbo
179  *			P-state capacity.
180  */
181 struct global_params {
182 	bool no_turbo;
183 	bool turbo_disabled;
184 	bool turbo_disabled_mf;
185 	int max_perf_pct;
186 	int min_perf_pct;
187 };
188 
189 /**
190  * struct cpudata -	Per CPU instance data storage
191  * @cpu:		CPU number for this instance data
192  * @policy:		CPUFreq policy value
193  * @update_util:	CPUFreq utility callback information
194  * @update_util_set:	CPUFreq utility callback is set
195  * @iowait_boost:	iowait-related boost fraction
196  * @last_update:	Time of the last update.
197  * @pstate:		Stores P state limits for this CPU
198  * @vid:		Stores VID limits for this CPU
199  * @last_sample_time:	Last Sample time
200  * @aperf_mperf_shift:	APERF vs MPERF counting frequency difference
201  * @prev_aperf:		Last APERF value read from APERF MSR
202  * @prev_mperf:		Last MPERF value read from MPERF MSR
203  * @prev_tsc:		Last timestamp counter (TSC) value
204  * @prev_cummulative_iowait: IO Wait time difference from last and
205  *			current sample
206  * @sample:		Storage for storing last Sample data
207  * @min_perf_ratio:	Minimum capacity in terms of PERF or HWP ratios
208  * @max_perf_ratio:	Maximum capacity in terms of PERF or HWP ratios
209  * @acpi_perf_data:	Stores ACPI perf information read from _PSS
210  * @valid_pss_table:	Set to true for valid ACPI _PSS entries found
211  * @epp_powersave:	Last saved HWP energy performance preference
212  *			(EPP) or energy performance bias (EPB),
213  *			when policy switched to performance
214  * @epp_policy:		Last saved policy used to set EPP/EPB
215  * @epp_default:	Power on default HWP energy performance
216  *			preference/bias
217  * @epp_cached		Cached HWP energy-performance preference value
218  * @hwp_req_cached:	Cached value of the last HWP Request MSR
219  * @hwp_cap_cached:	Cached value of the last HWP Capabilities MSR
220  * @last_io_update:	Last time when IO wake flag was set
221  * @sched_flags:	Store scheduler flags for possible cross CPU update
222  * @hwp_boost_min:	Last HWP boosted min performance
223  * @suspended:		Whether or not the driver has been suspended.
224  * @hwp_notify_work:	workqueue for HWP notifications.
225  *
226  * This structure stores per CPU instance data for all CPUs.
227  */
228 struct cpudata {
229 	int cpu;
230 
231 	unsigned int policy;
232 	struct update_util_data update_util;
233 	bool   update_util_set;
234 
235 	struct pstate_data pstate;
236 	struct vid_data vid;
237 
238 	u64	last_update;
239 	u64	last_sample_time;
240 	u64	aperf_mperf_shift;
241 	u64	prev_aperf;
242 	u64	prev_mperf;
243 	u64	prev_tsc;
244 	u64	prev_cummulative_iowait;
245 	struct sample sample;
246 	int32_t	min_perf_ratio;
247 	int32_t	max_perf_ratio;
248 #ifdef CONFIG_ACPI
249 	struct acpi_processor_performance acpi_perf_data;
250 	bool valid_pss_table;
251 #endif
252 	unsigned int iowait_boost;
253 	s16 epp_powersave;
254 	s16 epp_policy;
255 	s16 epp_default;
256 	s16 epp_cached;
257 	u64 hwp_req_cached;
258 	u64 hwp_cap_cached;
259 	u64 last_io_update;
260 	unsigned int sched_flags;
261 	u32 hwp_boost_min;
262 	bool suspended;
263 	struct delayed_work hwp_notify_work;
264 };
265 
266 static struct cpudata **all_cpu_data;
267 
268 /**
269  * struct pstate_funcs - Per CPU model specific callbacks
270  * @get_max:		Callback to get maximum non turbo effective P state
271  * @get_max_physical:	Callback to get maximum non turbo physical P state
272  * @get_min:		Callback to get minimum P state
273  * @get_turbo:		Callback to get turbo P state
274  * @get_scaling:	Callback to get frequency scaling factor
275  * @get_cpu_scaling:	Get frequency scaling factor for a given cpu
276  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277  * @get_val:		Callback to convert P state to actual MSR write value
278  * @get_vid:		Callback to get VID data for Atom platforms
279  *
280  * Core and Atom CPU models have different way to get P State limits. This
281  * structure is used to store those callbacks.
282  */
283 struct pstate_funcs {
284 	int (*get_max)(int cpu);
285 	int (*get_max_physical)(int cpu);
286 	int (*get_min)(int cpu);
287 	int (*get_turbo)(int cpu);
288 	int (*get_scaling)(void);
289 	int (*get_cpu_scaling)(int cpu);
290 	int (*get_aperf_mperf_shift)(void);
291 	u64 (*get_val)(struct cpudata*, int pstate);
292 	void (*get_vid)(struct cpudata *);
293 };
294 
295 static struct pstate_funcs pstate_funcs __read_mostly;
296 
297 static int hwp_active __read_mostly;
298 static int hwp_mode_bdw __read_mostly;
299 static bool per_cpu_limits __read_mostly;
300 static bool hwp_boost __read_mostly;
301 static bool hwp_forced __read_mostly;
302 
303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304 
305 #ifdef CONFIG_ACPI
306 static bool acpi_ppc;
307 #endif
308 
309 static struct global_params global;
310 
311 static DEFINE_MUTEX(intel_pstate_driver_lock);
312 static DEFINE_MUTEX(intel_pstate_limits_lock);
313 
314 #ifdef CONFIG_ACPI
315 
316 static bool intel_pstate_acpi_pm_profile_server(void)
317 {
318 	if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
319 	    acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
320 		return true;
321 
322 	return false;
323 }
324 
325 static bool intel_pstate_get_ppc_enable_status(void)
326 {
327 	if (intel_pstate_acpi_pm_profile_server())
328 		return true;
329 
330 	return acpi_ppc;
331 }
332 
333 #ifdef CONFIG_ACPI_CPPC_LIB
334 
335 /* The work item is needed to avoid CPU hotplug locking issues */
336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
337 {
338 	sched_set_itmt_support();
339 }
340 
341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
342 
343 #define CPPC_MAX_PERF	U8_MAX
344 
345 static void intel_pstate_set_itmt_prio(int cpu)
346 {
347 	struct cppc_perf_caps cppc_perf;
348 	static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
349 	int ret;
350 
351 	ret = cppc_get_perf_caps(cpu, &cppc_perf);
352 	if (ret)
353 		return;
354 
355 	/*
356 	 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
357 	 * In this case we can't use CPPC.highest_perf to enable ITMT.
358 	 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
359 	 */
360 	if (cppc_perf.highest_perf == CPPC_MAX_PERF)
361 		cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
362 
363 	/*
364 	 * The priorities can be set regardless of whether or not
365 	 * sched_set_itmt_support(true) has been called and it is valid to
366 	 * update them at any time after it has been called.
367 	 */
368 	sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
369 
370 	if (max_highest_perf <= min_highest_perf) {
371 		if (cppc_perf.highest_perf > max_highest_perf)
372 			max_highest_perf = cppc_perf.highest_perf;
373 
374 		if (cppc_perf.highest_perf < min_highest_perf)
375 			min_highest_perf = cppc_perf.highest_perf;
376 
377 		if (max_highest_perf > min_highest_perf) {
378 			/*
379 			 * This code can be run during CPU online under the
380 			 * CPU hotplug locks, so sched_set_itmt_support()
381 			 * cannot be called from here.  Queue up a work item
382 			 * to invoke it.
383 			 */
384 			schedule_work(&sched_itmt_work);
385 		}
386 	}
387 }
388 
389 static int intel_pstate_get_cppc_guaranteed(int cpu)
390 {
391 	struct cppc_perf_caps cppc_perf;
392 	int ret;
393 
394 	ret = cppc_get_perf_caps(cpu, &cppc_perf);
395 	if (ret)
396 		return ret;
397 
398 	if (cppc_perf.guaranteed_perf)
399 		return cppc_perf.guaranteed_perf;
400 
401 	return cppc_perf.nominal_perf;
402 }
403 #else /* CONFIG_ACPI_CPPC_LIB */
404 static inline void intel_pstate_set_itmt_prio(int cpu)
405 {
406 }
407 #endif /* CONFIG_ACPI_CPPC_LIB */
408 
409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
410 {
411 	struct cpudata *cpu;
412 	int ret;
413 	int i;
414 
415 	if (hwp_active) {
416 		intel_pstate_set_itmt_prio(policy->cpu);
417 		return;
418 	}
419 
420 	if (!intel_pstate_get_ppc_enable_status())
421 		return;
422 
423 	cpu = all_cpu_data[policy->cpu];
424 
425 	ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
426 						  policy->cpu);
427 	if (ret)
428 		return;
429 
430 	/*
431 	 * Check if the control value in _PSS is for PERF_CTL MSR, which should
432 	 * guarantee that the states returned by it map to the states in our
433 	 * list directly.
434 	 */
435 	if (cpu->acpi_perf_data.control_register.space_id !=
436 						ACPI_ADR_SPACE_FIXED_HARDWARE)
437 		goto err;
438 
439 	/*
440 	 * If there is only one entry _PSS, simply ignore _PSS and continue as
441 	 * usual without taking _PSS into account
442 	 */
443 	if (cpu->acpi_perf_data.state_count < 2)
444 		goto err;
445 
446 	pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
447 	for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
448 		pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
449 			 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
450 			 (u32) cpu->acpi_perf_data.states[i].core_frequency,
451 			 (u32) cpu->acpi_perf_data.states[i].power,
452 			 (u32) cpu->acpi_perf_data.states[i].control);
453 	}
454 
455 	/*
456 	 * The _PSS table doesn't contain whole turbo frequency range.
457 	 * This just contains +1 MHZ above the max non turbo frequency,
458 	 * with control value corresponding to max turbo ratio. But
459 	 * when cpufreq set policy is called, it will call with this
460 	 * max frequency, which will cause a reduced performance as
461 	 * this driver uses real max turbo frequency as the max
462 	 * frequency. So correct this frequency in _PSS table to
463 	 * correct max turbo frequency based on the turbo state.
464 	 * Also need to convert to MHz as _PSS freq is in MHz.
465 	 */
466 	if (!global.turbo_disabled)
467 		cpu->acpi_perf_data.states[0].core_frequency =
468 					policy->cpuinfo.max_freq / 1000;
469 	cpu->valid_pss_table = true;
470 	pr_debug("_PPC limits will be enforced\n");
471 
472 	return;
473 
474  err:
475 	cpu->valid_pss_table = false;
476 	acpi_processor_unregister_performance(policy->cpu);
477 }
478 
479 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
480 {
481 	struct cpudata *cpu;
482 
483 	cpu = all_cpu_data[policy->cpu];
484 	if (!cpu->valid_pss_table)
485 		return;
486 
487 	acpi_processor_unregister_performance(policy->cpu);
488 }
489 #else /* CONFIG_ACPI */
490 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
491 {
492 }
493 
494 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
495 {
496 }
497 
498 static inline bool intel_pstate_acpi_pm_profile_server(void)
499 {
500 	return false;
501 }
502 #endif /* CONFIG_ACPI */
503 
504 #ifndef CONFIG_ACPI_CPPC_LIB
505 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
506 {
507 	return -ENOTSUPP;
508 }
509 #endif /* CONFIG_ACPI_CPPC_LIB */
510 
511 /**
512  * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
513  * @cpu: Target CPU.
514  *
515  * On hybrid processors, HWP may expose more performance levels than there are
516  * P-states accessible through the PERF_CTL interface.  If that happens, the
517  * scaling factor between HWP performance levels and CPU frequency will be less
518  * than the scaling factor between P-state values and CPU frequency.
519  *
520  * In that case, adjust the CPU parameters used in computations accordingly.
521  */
522 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
523 {
524 	int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
525 	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
526 	int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
527 	int scaling = cpu->pstate.scaling;
528 
529 	pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
530 	pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
531 	pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
532 	pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
533 	pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
534 	pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
535 
536 	cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
537 					   perf_ctl_scaling);
538 	cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
539 					 perf_ctl_scaling);
540 
541 	cpu->pstate.max_pstate_physical =
542 			DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling,
543 				     scaling);
544 
545 	cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
546 	/*
547 	 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
548 	 * the effective range of HWP performance levels.
549 	 */
550 	cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling);
551 }
552 
553 static inline void update_turbo_state(void)
554 {
555 	u64 misc_en;
556 	struct cpudata *cpu;
557 
558 	cpu = all_cpu_data[0];
559 	rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
560 	global.turbo_disabled =
561 		(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
562 		 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
563 }
564 
565 static int min_perf_pct_min(void)
566 {
567 	struct cpudata *cpu = all_cpu_data[0];
568 	int turbo_pstate = cpu->pstate.turbo_pstate;
569 
570 	return turbo_pstate ?
571 		(cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
572 }
573 
574 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
575 {
576 	u64 epb;
577 	int ret;
578 
579 	if (!boot_cpu_has(X86_FEATURE_EPB))
580 		return -ENXIO;
581 
582 	ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
583 	if (ret)
584 		return (s16)ret;
585 
586 	return (s16)(epb & 0x0f);
587 }
588 
589 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
590 {
591 	s16 epp;
592 
593 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
594 		/*
595 		 * When hwp_req_data is 0, means that caller didn't read
596 		 * MSR_HWP_REQUEST, so need to read and get EPP.
597 		 */
598 		if (!hwp_req_data) {
599 			epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
600 					    &hwp_req_data);
601 			if (epp)
602 				return epp;
603 		}
604 		epp = (hwp_req_data >> 24) & 0xff;
605 	} else {
606 		/* When there is no EPP present, HWP uses EPB settings */
607 		epp = intel_pstate_get_epb(cpu_data);
608 	}
609 
610 	return epp;
611 }
612 
613 static int intel_pstate_set_epb(int cpu, s16 pref)
614 {
615 	u64 epb;
616 	int ret;
617 
618 	if (!boot_cpu_has(X86_FEATURE_EPB))
619 		return -ENXIO;
620 
621 	ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
622 	if (ret)
623 		return ret;
624 
625 	epb = (epb & ~0x0f) | pref;
626 	wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
627 
628 	return 0;
629 }
630 
631 /*
632  * EPP/EPB display strings corresponding to EPP index in the
633  * energy_perf_strings[]
634  *	index		String
635  *-------------------------------------
636  *	0		default
637  *	1		performance
638  *	2		balance_performance
639  *	3		balance_power
640  *	4		power
641  */
642 
643 enum energy_perf_value_index {
644 	EPP_INDEX_DEFAULT = 0,
645 	EPP_INDEX_PERFORMANCE,
646 	EPP_INDEX_BALANCE_PERFORMANCE,
647 	EPP_INDEX_BALANCE_POWERSAVE,
648 	EPP_INDEX_POWERSAVE,
649 };
650 
651 static const char * const energy_perf_strings[] = {
652 	[EPP_INDEX_DEFAULT] = "default",
653 	[EPP_INDEX_PERFORMANCE] = "performance",
654 	[EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
655 	[EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
656 	[EPP_INDEX_POWERSAVE] = "power",
657 	NULL
658 };
659 static unsigned int epp_values[] = {
660 	[EPP_INDEX_DEFAULT] = 0, /* Unused index */
661 	[EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
662 	[EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
663 	[EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
664 	[EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
665 };
666 
667 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
668 {
669 	s16 epp;
670 	int index = -EINVAL;
671 
672 	*raw_epp = 0;
673 	epp = intel_pstate_get_epp(cpu_data, 0);
674 	if (epp < 0)
675 		return epp;
676 
677 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
678 		if (epp == epp_values[EPP_INDEX_PERFORMANCE])
679 			return EPP_INDEX_PERFORMANCE;
680 		if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
681 			return EPP_INDEX_BALANCE_PERFORMANCE;
682 		if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
683 			return EPP_INDEX_BALANCE_POWERSAVE;
684 		if (epp == epp_values[EPP_INDEX_POWERSAVE])
685 			return EPP_INDEX_POWERSAVE;
686 		*raw_epp = epp;
687 		return 0;
688 	} else if (boot_cpu_has(X86_FEATURE_EPB)) {
689 		/*
690 		 * Range:
691 		 *	0x00-0x03	:	Performance
692 		 *	0x04-0x07	:	Balance performance
693 		 *	0x08-0x0B	:	Balance power
694 		 *	0x0C-0x0F	:	Power
695 		 * The EPB is a 4 bit value, but our ranges restrict the
696 		 * value which can be set. Here only using top two bits
697 		 * effectively.
698 		 */
699 		index = (epp >> 2) + 1;
700 	}
701 
702 	return index;
703 }
704 
705 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
706 {
707 	int ret;
708 
709 	/*
710 	 * Use the cached HWP Request MSR value, because in the active mode the
711 	 * register itself may be updated by intel_pstate_hwp_boost_up() or
712 	 * intel_pstate_hwp_boost_down() at any time.
713 	 */
714 	u64 value = READ_ONCE(cpu->hwp_req_cached);
715 
716 	value &= ~GENMASK_ULL(31, 24);
717 	value |= (u64)epp << 24;
718 	/*
719 	 * The only other updater of hwp_req_cached in the active mode,
720 	 * intel_pstate_hwp_set(), is called under the same lock as this
721 	 * function, so it cannot run in parallel with the update below.
722 	 */
723 	WRITE_ONCE(cpu->hwp_req_cached, value);
724 	ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
725 	if (!ret)
726 		cpu->epp_cached = epp;
727 
728 	return ret;
729 }
730 
731 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
732 					      int pref_index, bool use_raw,
733 					      u32 raw_epp)
734 {
735 	int epp = -EINVAL;
736 	int ret;
737 
738 	if (!pref_index)
739 		epp = cpu_data->epp_default;
740 
741 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
742 		if (use_raw)
743 			epp = raw_epp;
744 		else if (epp == -EINVAL)
745 			epp = epp_values[pref_index];
746 
747 		/*
748 		 * To avoid confusion, refuse to set EPP to any values different
749 		 * from 0 (performance) if the current policy is "performance",
750 		 * because those values would be overridden.
751 		 */
752 		if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
753 			return -EBUSY;
754 
755 		ret = intel_pstate_set_epp(cpu_data, epp);
756 	} else {
757 		if (epp == -EINVAL)
758 			epp = (pref_index - 1) << 2;
759 		ret = intel_pstate_set_epb(cpu_data->cpu, epp);
760 	}
761 
762 	return ret;
763 }
764 
765 static ssize_t show_energy_performance_available_preferences(
766 				struct cpufreq_policy *policy, char *buf)
767 {
768 	int i = 0;
769 	int ret = 0;
770 
771 	while (energy_perf_strings[i] != NULL)
772 		ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
773 
774 	ret += sprintf(&buf[ret], "\n");
775 
776 	return ret;
777 }
778 
779 cpufreq_freq_attr_ro(energy_performance_available_preferences);
780 
781 static struct cpufreq_driver intel_pstate;
782 
783 static ssize_t store_energy_performance_preference(
784 		struct cpufreq_policy *policy, const char *buf, size_t count)
785 {
786 	struct cpudata *cpu = all_cpu_data[policy->cpu];
787 	char str_preference[21];
788 	bool raw = false;
789 	ssize_t ret;
790 	u32 epp = 0;
791 
792 	ret = sscanf(buf, "%20s", str_preference);
793 	if (ret != 1)
794 		return -EINVAL;
795 
796 	ret = match_string(energy_perf_strings, -1, str_preference);
797 	if (ret < 0) {
798 		if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
799 			return ret;
800 
801 		ret = kstrtouint(buf, 10, &epp);
802 		if (ret)
803 			return ret;
804 
805 		if (epp > 255)
806 			return -EINVAL;
807 
808 		raw = true;
809 	}
810 
811 	/*
812 	 * This function runs with the policy R/W semaphore held, which
813 	 * guarantees that the driver pointer will not change while it is
814 	 * running.
815 	 */
816 	if (!intel_pstate_driver)
817 		return -EAGAIN;
818 
819 	mutex_lock(&intel_pstate_limits_lock);
820 
821 	if (intel_pstate_driver == &intel_pstate) {
822 		ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
823 	} else {
824 		/*
825 		 * In the passive mode the governor needs to be stopped on the
826 		 * target CPU before the EPP update and restarted after it,
827 		 * which is super-heavy-weight, so make sure it is worth doing
828 		 * upfront.
829 		 */
830 		if (!raw)
831 			epp = ret ? epp_values[ret] : cpu->epp_default;
832 
833 		if (cpu->epp_cached != epp) {
834 			int err;
835 
836 			cpufreq_stop_governor(policy);
837 			ret = intel_pstate_set_epp(cpu, epp);
838 			err = cpufreq_start_governor(policy);
839 			if (!ret)
840 				ret = err;
841 		}
842 	}
843 
844 	mutex_unlock(&intel_pstate_limits_lock);
845 
846 	return ret ?: count;
847 }
848 
849 static ssize_t show_energy_performance_preference(
850 				struct cpufreq_policy *policy, char *buf)
851 {
852 	struct cpudata *cpu_data = all_cpu_data[policy->cpu];
853 	int preference, raw_epp;
854 
855 	preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
856 	if (preference < 0)
857 		return preference;
858 
859 	if (raw_epp)
860 		return  sprintf(buf, "%d\n", raw_epp);
861 	else
862 		return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
863 }
864 
865 cpufreq_freq_attr_rw(energy_performance_preference);
866 
867 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
868 {
869 	struct cpudata *cpu = all_cpu_data[policy->cpu];
870 	int ratio, freq;
871 
872 	ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
873 	if (ratio <= 0) {
874 		u64 cap;
875 
876 		rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
877 		ratio = HWP_GUARANTEED_PERF(cap);
878 	}
879 
880 	freq = ratio * cpu->pstate.scaling;
881 	if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
882 		freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
883 
884 	return sprintf(buf, "%d\n", freq);
885 }
886 
887 cpufreq_freq_attr_ro(base_frequency);
888 
889 static struct freq_attr *hwp_cpufreq_attrs[] = {
890 	&energy_performance_preference,
891 	&energy_performance_available_preferences,
892 	&base_frequency,
893 	NULL,
894 };
895 
896 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
897 {
898 	u64 cap;
899 
900 	rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
901 	WRITE_ONCE(cpu->hwp_cap_cached, cap);
902 	cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
903 	cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
904 }
905 
906 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
907 {
908 	int scaling = cpu->pstate.scaling;
909 
910 	__intel_pstate_get_hwp_cap(cpu);
911 
912 	cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
913 	cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
914 	if (scaling != cpu->pstate.perf_ctl_scaling) {
915 		int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
916 
917 		cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
918 						 perf_ctl_scaling);
919 		cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
920 						   perf_ctl_scaling);
921 	}
922 }
923 
924 static void intel_pstate_hwp_set(unsigned int cpu)
925 {
926 	struct cpudata *cpu_data = all_cpu_data[cpu];
927 	int max, min;
928 	u64 value;
929 	s16 epp;
930 
931 	max = cpu_data->max_perf_ratio;
932 	min = cpu_data->min_perf_ratio;
933 
934 	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
935 		min = max;
936 
937 	rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
938 
939 	value &= ~HWP_MIN_PERF(~0L);
940 	value |= HWP_MIN_PERF(min);
941 
942 	value &= ~HWP_MAX_PERF(~0L);
943 	value |= HWP_MAX_PERF(max);
944 
945 	if (cpu_data->epp_policy == cpu_data->policy)
946 		goto skip_epp;
947 
948 	cpu_data->epp_policy = cpu_data->policy;
949 
950 	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
951 		epp = intel_pstate_get_epp(cpu_data, value);
952 		cpu_data->epp_powersave = epp;
953 		/* If EPP read was failed, then don't try to write */
954 		if (epp < 0)
955 			goto skip_epp;
956 
957 		epp = 0;
958 	} else {
959 		/* skip setting EPP, when saved value is invalid */
960 		if (cpu_data->epp_powersave < 0)
961 			goto skip_epp;
962 
963 		/*
964 		 * No need to restore EPP when it is not zero. This
965 		 * means:
966 		 *  - Policy is not changed
967 		 *  - user has manually changed
968 		 *  - Error reading EPB
969 		 */
970 		epp = intel_pstate_get_epp(cpu_data, value);
971 		if (epp)
972 			goto skip_epp;
973 
974 		epp = cpu_data->epp_powersave;
975 	}
976 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
977 		value &= ~GENMASK_ULL(31, 24);
978 		value |= (u64)epp << 24;
979 	} else {
980 		intel_pstate_set_epb(cpu, epp);
981 	}
982 skip_epp:
983 	WRITE_ONCE(cpu_data->hwp_req_cached, value);
984 	wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
985 }
986 
987 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
988 
989 static void intel_pstate_hwp_offline(struct cpudata *cpu)
990 {
991 	u64 value = READ_ONCE(cpu->hwp_req_cached);
992 	int min_perf;
993 
994 	intel_pstate_disable_hwp_interrupt(cpu);
995 
996 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
997 		/*
998 		 * In case the EPP has been set to "performance" by the
999 		 * active mode "performance" scaling algorithm, replace that
1000 		 * temporary value with the cached EPP one.
1001 		 */
1002 		value &= ~GENMASK_ULL(31, 24);
1003 		value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1004 		/*
1005 		 * However, make sure that EPP will be set to "performance" when
1006 		 * the CPU is brought back online again and the "performance"
1007 		 * scaling algorithm is still in effect.
1008 		 */
1009 		cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1010 	}
1011 
1012 	/*
1013 	 * Clear the desired perf field in the cached HWP request value to
1014 	 * prevent nonzero desired values from being leaked into the active
1015 	 * mode.
1016 	 */
1017 	value &= ~HWP_DESIRED_PERF(~0L);
1018 	WRITE_ONCE(cpu->hwp_req_cached, value);
1019 
1020 	value &= ~GENMASK_ULL(31, 0);
1021 	min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1022 
1023 	/* Set hwp_max = hwp_min */
1024 	value |= HWP_MAX_PERF(min_perf);
1025 	value |= HWP_MIN_PERF(min_perf);
1026 
1027 	/* Set EPP to min */
1028 	if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1029 		value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1030 
1031 	wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1032 }
1033 
1034 #define POWER_CTL_EE_ENABLE	1
1035 #define POWER_CTL_EE_DISABLE	2
1036 
1037 static int power_ctl_ee_state;
1038 
1039 static void set_power_ctl_ee_state(bool input)
1040 {
1041 	u64 power_ctl;
1042 
1043 	mutex_lock(&intel_pstate_driver_lock);
1044 	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1045 	if (input) {
1046 		power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1047 		power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1048 	} else {
1049 		power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1050 		power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1051 	}
1052 	wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1053 	mutex_unlock(&intel_pstate_driver_lock);
1054 }
1055 
1056 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1057 
1058 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1059 {
1060 	intel_pstate_hwp_enable(cpu);
1061 	wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1062 }
1063 
1064 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1065 {
1066 	struct cpudata *cpu = all_cpu_data[policy->cpu];
1067 
1068 	pr_debug("CPU %d suspending\n", cpu->cpu);
1069 
1070 	cpu->suspended = true;
1071 
1072 	/* disable HWP interrupt and cancel any pending work */
1073 	intel_pstate_disable_hwp_interrupt(cpu);
1074 
1075 	return 0;
1076 }
1077 
1078 static int intel_pstate_resume(struct cpufreq_policy *policy)
1079 {
1080 	struct cpudata *cpu = all_cpu_data[policy->cpu];
1081 
1082 	pr_debug("CPU %d resuming\n", cpu->cpu);
1083 
1084 	/* Only restore if the system default is changed */
1085 	if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1086 		set_power_ctl_ee_state(true);
1087 	else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1088 		set_power_ctl_ee_state(false);
1089 
1090 	if (cpu->suspended && hwp_active) {
1091 		mutex_lock(&intel_pstate_limits_lock);
1092 
1093 		/* Re-enable HWP, because "online" has not done that. */
1094 		intel_pstate_hwp_reenable(cpu);
1095 
1096 		mutex_unlock(&intel_pstate_limits_lock);
1097 	}
1098 
1099 	cpu->suspended = false;
1100 
1101 	return 0;
1102 }
1103 
1104 static void intel_pstate_update_policies(void)
1105 {
1106 	int cpu;
1107 
1108 	for_each_possible_cpu(cpu)
1109 		cpufreq_update_policy(cpu);
1110 }
1111 
1112 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1113 					   struct cpufreq_policy *policy)
1114 {
1115 	policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1116 			cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1117 	refresh_frequency_limits(policy);
1118 }
1119 
1120 static void intel_pstate_update_max_freq(unsigned int cpu)
1121 {
1122 	struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1123 
1124 	if (!policy)
1125 		return;
1126 
1127 	__intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1128 
1129 	cpufreq_cpu_release(policy);
1130 }
1131 
1132 static void intel_pstate_update_limits(unsigned int cpu)
1133 {
1134 	mutex_lock(&intel_pstate_driver_lock);
1135 
1136 	update_turbo_state();
1137 	/*
1138 	 * If turbo has been turned on or off globally, policy limits for
1139 	 * all CPUs need to be updated to reflect that.
1140 	 */
1141 	if (global.turbo_disabled_mf != global.turbo_disabled) {
1142 		global.turbo_disabled_mf = global.turbo_disabled;
1143 		arch_set_max_freq_ratio(global.turbo_disabled);
1144 		for_each_possible_cpu(cpu)
1145 			intel_pstate_update_max_freq(cpu);
1146 	} else {
1147 		cpufreq_update_policy(cpu);
1148 	}
1149 
1150 	mutex_unlock(&intel_pstate_driver_lock);
1151 }
1152 
1153 /************************** sysfs begin ************************/
1154 #define show_one(file_name, object)					\
1155 	static ssize_t show_##file_name					\
1156 	(struct kobject *kobj, struct kobj_attribute *attr, char *buf)	\
1157 	{								\
1158 		return sprintf(buf, "%u\n", global.object);		\
1159 	}
1160 
1161 static ssize_t intel_pstate_show_status(char *buf);
1162 static int intel_pstate_update_status(const char *buf, size_t size);
1163 
1164 static ssize_t show_status(struct kobject *kobj,
1165 			   struct kobj_attribute *attr, char *buf)
1166 {
1167 	ssize_t ret;
1168 
1169 	mutex_lock(&intel_pstate_driver_lock);
1170 	ret = intel_pstate_show_status(buf);
1171 	mutex_unlock(&intel_pstate_driver_lock);
1172 
1173 	return ret;
1174 }
1175 
1176 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1177 			    const char *buf, size_t count)
1178 {
1179 	char *p = memchr(buf, '\n', count);
1180 	int ret;
1181 
1182 	mutex_lock(&intel_pstate_driver_lock);
1183 	ret = intel_pstate_update_status(buf, p ? p - buf : count);
1184 	mutex_unlock(&intel_pstate_driver_lock);
1185 
1186 	return ret < 0 ? ret : count;
1187 }
1188 
1189 static ssize_t show_turbo_pct(struct kobject *kobj,
1190 				struct kobj_attribute *attr, char *buf)
1191 {
1192 	struct cpudata *cpu;
1193 	int total, no_turbo, turbo_pct;
1194 	uint32_t turbo_fp;
1195 
1196 	mutex_lock(&intel_pstate_driver_lock);
1197 
1198 	if (!intel_pstate_driver) {
1199 		mutex_unlock(&intel_pstate_driver_lock);
1200 		return -EAGAIN;
1201 	}
1202 
1203 	cpu = all_cpu_data[0];
1204 
1205 	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1206 	no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1207 	turbo_fp = div_fp(no_turbo, total);
1208 	turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1209 
1210 	mutex_unlock(&intel_pstate_driver_lock);
1211 
1212 	return sprintf(buf, "%u\n", turbo_pct);
1213 }
1214 
1215 static ssize_t show_num_pstates(struct kobject *kobj,
1216 				struct kobj_attribute *attr, char *buf)
1217 {
1218 	struct cpudata *cpu;
1219 	int total;
1220 
1221 	mutex_lock(&intel_pstate_driver_lock);
1222 
1223 	if (!intel_pstate_driver) {
1224 		mutex_unlock(&intel_pstate_driver_lock);
1225 		return -EAGAIN;
1226 	}
1227 
1228 	cpu = all_cpu_data[0];
1229 	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1230 
1231 	mutex_unlock(&intel_pstate_driver_lock);
1232 
1233 	return sprintf(buf, "%u\n", total);
1234 }
1235 
1236 static ssize_t show_no_turbo(struct kobject *kobj,
1237 			     struct kobj_attribute *attr, char *buf)
1238 {
1239 	ssize_t ret;
1240 
1241 	mutex_lock(&intel_pstate_driver_lock);
1242 
1243 	if (!intel_pstate_driver) {
1244 		mutex_unlock(&intel_pstate_driver_lock);
1245 		return -EAGAIN;
1246 	}
1247 
1248 	update_turbo_state();
1249 	if (global.turbo_disabled)
1250 		ret = sprintf(buf, "%u\n", global.turbo_disabled);
1251 	else
1252 		ret = sprintf(buf, "%u\n", global.no_turbo);
1253 
1254 	mutex_unlock(&intel_pstate_driver_lock);
1255 
1256 	return ret;
1257 }
1258 
1259 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1260 			      const char *buf, size_t count)
1261 {
1262 	unsigned int input;
1263 	int ret;
1264 
1265 	ret = sscanf(buf, "%u", &input);
1266 	if (ret != 1)
1267 		return -EINVAL;
1268 
1269 	mutex_lock(&intel_pstate_driver_lock);
1270 
1271 	if (!intel_pstate_driver) {
1272 		mutex_unlock(&intel_pstate_driver_lock);
1273 		return -EAGAIN;
1274 	}
1275 
1276 	mutex_lock(&intel_pstate_limits_lock);
1277 
1278 	update_turbo_state();
1279 	if (global.turbo_disabled) {
1280 		pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1281 		mutex_unlock(&intel_pstate_limits_lock);
1282 		mutex_unlock(&intel_pstate_driver_lock);
1283 		return -EPERM;
1284 	}
1285 
1286 	global.no_turbo = clamp_t(int, input, 0, 1);
1287 
1288 	if (global.no_turbo) {
1289 		struct cpudata *cpu = all_cpu_data[0];
1290 		int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1291 
1292 		/* Squash the global minimum into the permitted range. */
1293 		if (global.min_perf_pct > pct)
1294 			global.min_perf_pct = pct;
1295 	}
1296 
1297 	mutex_unlock(&intel_pstate_limits_lock);
1298 
1299 	intel_pstate_update_policies();
1300 	arch_set_max_freq_ratio(global.no_turbo);
1301 
1302 	mutex_unlock(&intel_pstate_driver_lock);
1303 
1304 	return count;
1305 }
1306 
1307 static void update_qos_request(enum freq_qos_req_type type)
1308 {
1309 	struct freq_qos_request *req;
1310 	struct cpufreq_policy *policy;
1311 	int i;
1312 
1313 	for_each_possible_cpu(i) {
1314 		struct cpudata *cpu = all_cpu_data[i];
1315 		unsigned int freq, perf_pct;
1316 
1317 		policy = cpufreq_cpu_get(i);
1318 		if (!policy)
1319 			continue;
1320 
1321 		req = policy->driver_data;
1322 		cpufreq_cpu_put(policy);
1323 
1324 		if (!req)
1325 			continue;
1326 
1327 		if (hwp_active)
1328 			intel_pstate_get_hwp_cap(cpu);
1329 
1330 		if (type == FREQ_QOS_MIN) {
1331 			perf_pct = global.min_perf_pct;
1332 		} else {
1333 			req++;
1334 			perf_pct = global.max_perf_pct;
1335 		}
1336 
1337 		freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1338 
1339 		if (freq_qos_update_request(req, freq) < 0)
1340 			pr_warn("Failed to update freq constraint: CPU%d\n", i);
1341 	}
1342 }
1343 
1344 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1345 				  const char *buf, size_t count)
1346 {
1347 	unsigned int input;
1348 	int ret;
1349 
1350 	ret = sscanf(buf, "%u", &input);
1351 	if (ret != 1)
1352 		return -EINVAL;
1353 
1354 	mutex_lock(&intel_pstate_driver_lock);
1355 
1356 	if (!intel_pstate_driver) {
1357 		mutex_unlock(&intel_pstate_driver_lock);
1358 		return -EAGAIN;
1359 	}
1360 
1361 	mutex_lock(&intel_pstate_limits_lock);
1362 
1363 	global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1364 
1365 	mutex_unlock(&intel_pstate_limits_lock);
1366 
1367 	if (intel_pstate_driver == &intel_pstate)
1368 		intel_pstate_update_policies();
1369 	else
1370 		update_qos_request(FREQ_QOS_MAX);
1371 
1372 	mutex_unlock(&intel_pstate_driver_lock);
1373 
1374 	return count;
1375 }
1376 
1377 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1378 				  const char *buf, size_t count)
1379 {
1380 	unsigned int input;
1381 	int ret;
1382 
1383 	ret = sscanf(buf, "%u", &input);
1384 	if (ret != 1)
1385 		return -EINVAL;
1386 
1387 	mutex_lock(&intel_pstate_driver_lock);
1388 
1389 	if (!intel_pstate_driver) {
1390 		mutex_unlock(&intel_pstate_driver_lock);
1391 		return -EAGAIN;
1392 	}
1393 
1394 	mutex_lock(&intel_pstate_limits_lock);
1395 
1396 	global.min_perf_pct = clamp_t(int, input,
1397 				      min_perf_pct_min(), global.max_perf_pct);
1398 
1399 	mutex_unlock(&intel_pstate_limits_lock);
1400 
1401 	if (intel_pstate_driver == &intel_pstate)
1402 		intel_pstate_update_policies();
1403 	else
1404 		update_qos_request(FREQ_QOS_MIN);
1405 
1406 	mutex_unlock(&intel_pstate_driver_lock);
1407 
1408 	return count;
1409 }
1410 
1411 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1412 				struct kobj_attribute *attr, char *buf)
1413 {
1414 	return sprintf(buf, "%u\n", hwp_boost);
1415 }
1416 
1417 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1418 				       struct kobj_attribute *b,
1419 				       const char *buf, size_t count)
1420 {
1421 	unsigned int input;
1422 	int ret;
1423 
1424 	ret = kstrtouint(buf, 10, &input);
1425 	if (ret)
1426 		return ret;
1427 
1428 	mutex_lock(&intel_pstate_driver_lock);
1429 	hwp_boost = !!input;
1430 	intel_pstate_update_policies();
1431 	mutex_unlock(&intel_pstate_driver_lock);
1432 
1433 	return count;
1434 }
1435 
1436 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1437 				      char *buf)
1438 {
1439 	u64 power_ctl;
1440 	int enable;
1441 
1442 	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1443 	enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1444 	return sprintf(buf, "%d\n", !enable);
1445 }
1446 
1447 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1448 				       const char *buf, size_t count)
1449 {
1450 	bool input;
1451 	int ret;
1452 
1453 	ret = kstrtobool(buf, &input);
1454 	if (ret)
1455 		return ret;
1456 
1457 	set_power_ctl_ee_state(input);
1458 
1459 	return count;
1460 }
1461 
1462 show_one(max_perf_pct, max_perf_pct);
1463 show_one(min_perf_pct, min_perf_pct);
1464 
1465 define_one_global_rw(status);
1466 define_one_global_rw(no_turbo);
1467 define_one_global_rw(max_perf_pct);
1468 define_one_global_rw(min_perf_pct);
1469 define_one_global_ro(turbo_pct);
1470 define_one_global_ro(num_pstates);
1471 define_one_global_rw(hwp_dynamic_boost);
1472 define_one_global_rw(energy_efficiency);
1473 
1474 static struct attribute *intel_pstate_attributes[] = {
1475 	&status.attr,
1476 	&no_turbo.attr,
1477 	NULL
1478 };
1479 
1480 static const struct attribute_group intel_pstate_attr_group = {
1481 	.attrs = intel_pstate_attributes,
1482 };
1483 
1484 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1485 
1486 static struct kobject *intel_pstate_kobject;
1487 
1488 static void __init intel_pstate_sysfs_expose_params(void)
1489 {
1490 	int rc;
1491 
1492 	intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1493 						&cpu_subsys.dev_root->kobj);
1494 	if (WARN_ON(!intel_pstate_kobject))
1495 		return;
1496 
1497 	rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1498 	if (WARN_ON(rc))
1499 		return;
1500 
1501 	if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1502 		rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1503 		WARN_ON(rc);
1504 
1505 		rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1506 		WARN_ON(rc);
1507 	}
1508 
1509 	/*
1510 	 * If per cpu limits are enforced there are no global limits, so
1511 	 * return without creating max/min_perf_pct attributes
1512 	 */
1513 	if (per_cpu_limits)
1514 		return;
1515 
1516 	rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1517 	WARN_ON(rc);
1518 
1519 	rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1520 	WARN_ON(rc);
1521 
1522 	if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1523 		rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1524 		WARN_ON(rc);
1525 	}
1526 }
1527 
1528 static void __init intel_pstate_sysfs_remove(void)
1529 {
1530 	if (!intel_pstate_kobject)
1531 		return;
1532 
1533 	sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1534 
1535 	if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1536 		sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1537 		sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1538 	}
1539 
1540 	if (!per_cpu_limits) {
1541 		sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1542 		sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1543 
1544 		if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1545 			sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1546 	}
1547 
1548 	kobject_put(intel_pstate_kobject);
1549 }
1550 
1551 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1552 {
1553 	int rc;
1554 
1555 	if (!hwp_active)
1556 		return;
1557 
1558 	rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1559 	WARN_ON_ONCE(rc);
1560 }
1561 
1562 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1563 {
1564 	if (!hwp_active)
1565 		return;
1566 
1567 	sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1568 }
1569 
1570 /************************** sysfs end ************************/
1571 
1572 static void intel_pstate_notify_work(struct work_struct *work)
1573 {
1574 	struct cpudata *cpudata =
1575 		container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1576 	struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1577 
1578 	if (policy) {
1579 		intel_pstate_get_hwp_cap(cpudata);
1580 		__intel_pstate_update_max_freq(cpudata, policy);
1581 
1582 		cpufreq_cpu_release(policy);
1583 	}
1584 
1585 	wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1586 }
1587 
1588 static DEFINE_SPINLOCK(hwp_notify_lock);
1589 static cpumask_t hwp_intr_enable_mask;
1590 
1591 void notify_hwp_interrupt(void)
1592 {
1593 	unsigned int this_cpu = smp_processor_id();
1594 	struct cpudata *cpudata;
1595 	unsigned long flags;
1596 	u64 value;
1597 
1598 	if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1599 		return;
1600 
1601 	rdmsrl_safe(MSR_HWP_STATUS, &value);
1602 	if (!(value & 0x01))
1603 		return;
1604 
1605 	spin_lock_irqsave(&hwp_notify_lock, flags);
1606 
1607 	if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1608 		goto ack_intr;
1609 
1610 	/*
1611 	 * Currently we never free all_cpu_data. And we can't reach here
1612 	 * without this allocated. But for safety for future changes, added
1613 	 * check.
1614 	 */
1615 	if (unlikely(!READ_ONCE(all_cpu_data)))
1616 		goto ack_intr;
1617 
1618 	/*
1619 	 * The free is done during cleanup, when cpufreq registry is failed.
1620 	 * We wouldn't be here if it fails on init or switch status. But for
1621 	 * future changes, added check.
1622 	 */
1623 	cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1624 	if (unlikely(!cpudata))
1625 		goto ack_intr;
1626 
1627 	schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1628 
1629 	spin_unlock_irqrestore(&hwp_notify_lock, flags);
1630 
1631 	return;
1632 
1633 ack_intr:
1634 	wrmsrl_safe(MSR_HWP_STATUS, 0);
1635 	spin_unlock_irqrestore(&hwp_notify_lock, flags);
1636 }
1637 
1638 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1639 {
1640 	unsigned long flags;
1641 
1642 	if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1643 		return;
1644 
1645 	/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1646 	wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1647 
1648 	spin_lock_irqsave(&hwp_notify_lock, flags);
1649 	if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1650 		cancel_delayed_work(&cpudata->hwp_notify_work);
1651 	spin_unlock_irqrestore(&hwp_notify_lock, flags);
1652 }
1653 
1654 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1655 {
1656 	/* Enable HWP notification interrupt for guaranteed performance change */
1657 	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1658 		unsigned long flags;
1659 
1660 		spin_lock_irqsave(&hwp_notify_lock, flags);
1661 		INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1662 		cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1663 		spin_unlock_irqrestore(&hwp_notify_lock, flags);
1664 
1665 		/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1666 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1667 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1668 	}
1669 }
1670 
1671 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1672 {
1673 	cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1674 
1675 	/*
1676 	 * If this CPU gen doesn't call for change in balance_perf
1677 	 * EPP return.
1678 	 */
1679 	if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1680 		return;
1681 
1682 	/*
1683 	 * If the EPP is set by firmware, which means that firmware enabled HWP
1684 	 * - Is equal or less than 0x80 (default balance_perf EPP)
1685 	 * - But less performance oriented than performance EPP
1686 	 *   then use this as new balance_perf EPP.
1687 	 */
1688 	if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1689 	    cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1690 		epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1691 		return;
1692 	}
1693 
1694 	/*
1695 	 * Use hard coded value per gen to update the balance_perf
1696 	 * and default EPP.
1697 	 */
1698 	cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1699 	intel_pstate_set_epp(cpudata, cpudata->epp_default);
1700 }
1701 
1702 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1703 {
1704 	/* First disable HWP notification interrupt till we activate again */
1705 	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1706 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1707 
1708 	wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1709 
1710 	intel_pstate_enable_hwp_interrupt(cpudata);
1711 
1712 	if (cpudata->epp_default >= 0)
1713 		return;
1714 
1715 	intel_pstate_update_epp_defaults(cpudata);
1716 }
1717 
1718 static int atom_get_min_pstate(int not_used)
1719 {
1720 	u64 value;
1721 
1722 	rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1723 	return (value >> 8) & 0x7F;
1724 }
1725 
1726 static int atom_get_max_pstate(int not_used)
1727 {
1728 	u64 value;
1729 
1730 	rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1731 	return (value >> 16) & 0x7F;
1732 }
1733 
1734 static int atom_get_turbo_pstate(int not_used)
1735 {
1736 	u64 value;
1737 
1738 	rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1739 	return value & 0x7F;
1740 }
1741 
1742 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1743 {
1744 	u64 val;
1745 	int32_t vid_fp;
1746 	u32 vid;
1747 
1748 	val = (u64)pstate << 8;
1749 	if (global.no_turbo && !global.turbo_disabled)
1750 		val |= (u64)1 << 32;
1751 
1752 	vid_fp = cpudata->vid.min + mul_fp(
1753 		int_tofp(pstate - cpudata->pstate.min_pstate),
1754 		cpudata->vid.ratio);
1755 
1756 	vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1757 	vid = ceiling_fp(vid_fp);
1758 
1759 	if (pstate > cpudata->pstate.max_pstate)
1760 		vid = cpudata->vid.turbo;
1761 
1762 	return val | vid;
1763 }
1764 
1765 static int silvermont_get_scaling(void)
1766 {
1767 	u64 value;
1768 	int i;
1769 	/* Defined in Table 35-6 from SDM (Sept 2015) */
1770 	static int silvermont_freq_table[] = {
1771 		83300, 100000, 133300, 116700, 80000};
1772 
1773 	rdmsrl(MSR_FSB_FREQ, value);
1774 	i = value & 0x7;
1775 	WARN_ON(i > 4);
1776 
1777 	return silvermont_freq_table[i];
1778 }
1779 
1780 static int airmont_get_scaling(void)
1781 {
1782 	u64 value;
1783 	int i;
1784 	/* Defined in Table 35-10 from SDM (Sept 2015) */
1785 	static int airmont_freq_table[] = {
1786 		83300, 100000, 133300, 116700, 80000,
1787 		93300, 90000, 88900, 87500};
1788 
1789 	rdmsrl(MSR_FSB_FREQ, value);
1790 	i = value & 0xF;
1791 	WARN_ON(i > 8);
1792 
1793 	return airmont_freq_table[i];
1794 }
1795 
1796 static void atom_get_vid(struct cpudata *cpudata)
1797 {
1798 	u64 value;
1799 
1800 	rdmsrl(MSR_ATOM_CORE_VIDS, value);
1801 	cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1802 	cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1803 	cpudata->vid.ratio = div_fp(
1804 		cpudata->vid.max - cpudata->vid.min,
1805 		int_tofp(cpudata->pstate.max_pstate -
1806 			cpudata->pstate.min_pstate));
1807 
1808 	rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1809 	cpudata->vid.turbo = value & 0x7f;
1810 }
1811 
1812 static int core_get_min_pstate(int cpu)
1813 {
1814 	u64 value;
1815 
1816 	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1817 	return (value >> 40) & 0xFF;
1818 }
1819 
1820 static int core_get_max_pstate_physical(int cpu)
1821 {
1822 	u64 value;
1823 
1824 	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1825 	return (value >> 8) & 0xFF;
1826 }
1827 
1828 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1829 {
1830 	/* Check how many TDP levels present */
1831 	if (plat_info & 0x600000000) {
1832 		u64 tdp_ctrl;
1833 		u64 tdp_ratio;
1834 		int tdp_msr;
1835 		int err;
1836 
1837 		/* Get the TDP level (0, 1, 2) to get ratios */
1838 		err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1839 		if (err)
1840 			return err;
1841 
1842 		/* TDP MSR are continuous starting at 0x648 */
1843 		tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1844 		err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1845 		if (err)
1846 			return err;
1847 
1848 		/* For level 1 and 2, bits[23:16] contain the ratio */
1849 		if (tdp_ctrl & 0x03)
1850 			tdp_ratio >>= 16;
1851 
1852 		tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1853 		pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1854 
1855 		return (int)tdp_ratio;
1856 	}
1857 
1858 	return -ENXIO;
1859 }
1860 
1861 static int core_get_max_pstate(int cpu)
1862 {
1863 	u64 tar;
1864 	u64 plat_info;
1865 	int max_pstate;
1866 	int tdp_ratio;
1867 	int err;
1868 
1869 	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1870 	max_pstate = (plat_info >> 8) & 0xFF;
1871 
1872 	tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1873 	if (tdp_ratio <= 0)
1874 		return max_pstate;
1875 
1876 	if (hwp_active) {
1877 		/* Turbo activation ratio is not used on HWP platforms */
1878 		return tdp_ratio;
1879 	}
1880 
1881 	err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1882 	if (!err) {
1883 		int tar_levels;
1884 
1885 		/* Do some sanity checking for safety */
1886 		tar_levels = tar & 0xff;
1887 		if (tdp_ratio - 1 == tar_levels) {
1888 			max_pstate = tar_levels;
1889 			pr_debug("max_pstate=TAC %x\n", max_pstate);
1890 		}
1891 	}
1892 
1893 	return max_pstate;
1894 }
1895 
1896 static int core_get_turbo_pstate(int cpu)
1897 {
1898 	u64 value;
1899 	int nont, ret;
1900 
1901 	rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1902 	nont = core_get_max_pstate(cpu);
1903 	ret = (value) & 255;
1904 	if (ret <= nont)
1905 		ret = nont;
1906 	return ret;
1907 }
1908 
1909 static inline int core_get_scaling(void)
1910 {
1911 	return 100000;
1912 }
1913 
1914 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1915 {
1916 	u64 val;
1917 
1918 	val = (u64)pstate << 8;
1919 	if (global.no_turbo && !global.turbo_disabled)
1920 		val |= (u64)1 << 32;
1921 
1922 	return val;
1923 }
1924 
1925 static int knl_get_aperf_mperf_shift(void)
1926 {
1927 	return 10;
1928 }
1929 
1930 static int knl_get_turbo_pstate(int cpu)
1931 {
1932 	u64 value;
1933 	int nont, ret;
1934 
1935 	rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1936 	nont = core_get_max_pstate(cpu);
1937 	ret = (((value) >> 8) & 0xFF);
1938 	if (ret <= nont)
1939 		ret = nont;
1940 	return ret;
1941 }
1942 
1943 static void hybrid_get_type(void *data)
1944 {
1945 	u8 *cpu_type = data;
1946 
1947 	*cpu_type = get_this_hybrid_cpu_type();
1948 }
1949 
1950 static int hybrid_get_cpu_scaling(int cpu)
1951 {
1952 	u8 cpu_type = 0;
1953 
1954 	smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1955 	/* P-cores have a smaller perf level-to-freqency scaling factor. */
1956 	if (cpu_type == 0x40)
1957 		return 78741;
1958 
1959 	return core_get_scaling();
1960 }
1961 
1962 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1963 {
1964 	trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1965 	cpu->pstate.current_pstate = pstate;
1966 	/*
1967 	 * Generally, there is no guarantee that this code will always run on
1968 	 * the CPU being updated, so force the register update to run on the
1969 	 * right CPU.
1970 	 */
1971 	wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1972 		      pstate_funcs.get_val(cpu, pstate));
1973 }
1974 
1975 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1976 {
1977 	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1978 }
1979 
1980 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1981 {
1982 	int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1983 
1984 	update_turbo_state();
1985 	intel_pstate_set_pstate(cpu, pstate);
1986 }
1987 
1988 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1989 {
1990 	int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
1991 	int perf_ctl_scaling = pstate_funcs.get_scaling();
1992 
1993 	cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
1994 	cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
1995 	cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
1996 
1997 	if (hwp_active && !hwp_mode_bdw) {
1998 		__intel_pstate_get_hwp_cap(cpu);
1999 
2000 		if (pstate_funcs.get_cpu_scaling) {
2001 			cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2002 			if (cpu->pstate.scaling != perf_ctl_scaling)
2003 				intel_pstate_hybrid_hwp_adjust(cpu);
2004 		} else {
2005 			cpu->pstate.scaling = perf_ctl_scaling;
2006 		}
2007 	} else {
2008 		cpu->pstate.scaling = perf_ctl_scaling;
2009 		cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2010 		cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2011 	}
2012 
2013 	if (cpu->pstate.scaling == perf_ctl_scaling) {
2014 		cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2015 		cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2016 		cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2017 	}
2018 
2019 	if (pstate_funcs.get_aperf_mperf_shift)
2020 		cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2021 
2022 	if (pstate_funcs.get_vid)
2023 		pstate_funcs.get_vid(cpu);
2024 
2025 	intel_pstate_set_min_pstate(cpu);
2026 }
2027 
2028 /*
2029  * Long hold time will keep high perf limits for long time,
2030  * which negatively impacts perf/watt for some workloads,
2031  * like specpower. 3ms is based on experiements on some
2032  * workoads.
2033  */
2034 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2035 
2036 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2037 {
2038 	u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2039 	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2040 	u32 max_limit = (hwp_req & 0xff00) >> 8;
2041 	u32 min_limit = (hwp_req & 0xff);
2042 	u32 boost_level1;
2043 
2044 	/*
2045 	 * Cases to consider (User changes via sysfs or boot time):
2046 	 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2047 	 *	No boost, return.
2048 	 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2049 	 *     Should result in one level boost only for P0.
2050 	 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2051 	 *     Should result in two level boost:
2052 	 *         (min + p1)/2 and P1.
2053 	 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2054 	 *     Should result in three level boost:
2055 	 *        (min + p1)/2, P1 and P0.
2056 	 */
2057 
2058 	/* If max and min are equal or already at max, nothing to boost */
2059 	if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2060 		return;
2061 
2062 	if (!cpu->hwp_boost_min)
2063 		cpu->hwp_boost_min = min_limit;
2064 
2065 	/* level at half way mark between min and guranteed */
2066 	boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2067 
2068 	if (cpu->hwp_boost_min < boost_level1)
2069 		cpu->hwp_boost_min = boost_level1;
2070 	else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2071 		cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2072 	else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2073 		 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2074 		cpu->hwp_boost_min = max_limit;
2075 	else
2076 		return;
2077 
2078 	hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2079 	wrmsrl(MSR_HWP_REQUEST, hwp_req);
2080 	cpu->last_update = cpu->sample.time;
2081 }
2082 
2083 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2084 {
2085 	if (cpu->hwp_boost_min) {
2086 		bool expired;
2087 
2088 		/* Check if we are idle for hold time to boost down */
2089 		expired = time_after64(cpu->sample.time, cpu->last_update +
2090 				       hwp_boost_hold_time_ns);
2091 		if (expired) {
2092 			wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2093 			cpu->hwp_boost_min = 0;
2094 		}
2095 	}
2096 	cpu->last_update = cpu->sample.time;
2097 }
2098 
2099 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2100 						      u64 time)
2101 {
2102 	cpu->sample.time = time;
2103 
2104 	if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2105 		bool do_io = false;
2106 
2107 		cpu->sched_flags = 0;
2108 		/*
2109 		 * Set iowait_boost flag and update time. Since IO WAIT flag
2110 		 * is set all the time, we can't just conclude that there is
2111 		 * some IO bound activity is scheduled on this CPU with just
2112 		 * one occurrence. If we receive at least two in two
2113 		 * consecutive ticks, then we treat as boost candidate.
2114 		 */
2115 		if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2116 			do_io = true;
2117 
2118 		cpu->last_io_update = time;
2119 
2120 		if (do_io)
2121 			intel_pstate_hwp_boost_up(cpu);
2122 
2123 	} else {
2124 		intel_pstate_hwp_boost_down(cpu);
2125 	}
2126 }
2127 
2128 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2129 						u64 time, unsigned int flags)
2130 {
2131 	struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2132 
2133 	cpu->sched_flags |= flags;
2134 
2135 	if (smp_processor_id() == cpu->cpu)
2136 		intel_pstate_update_util_hwp_local(cpu, time);
2137 }
2138 
2139 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2140 {
2141 	struct sample *sample = &cpu->sample;
2142 
2143 	sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2144 }
2145 
2146 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2147 {
2148 	u64 aperf, mperf;
2149 	unsigned long flags;
2150 	u64 tsc;
2151 
2152 	local_irq_save(flags);
2153 	rdmsrl(MSR_IA32_APERF, aperf);
2154 	rdmsrl(MSR_IA32_MPERF, mperf);
2155 	tsc = rdtsc();
2156 	if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2157 		local_irq_restore(flags);
2158 		return false;
2159 	}
2160 	local_irq_restore(flags);
2161 
2162 	cpu->last_sample_time = cpu->sample.time;
2163 	cpu->sample.time = time;
2164 	cpu->sample.aperf = aperf;
2165 	cpu->sample.mperf = mperf;
2166 	cpu->sample.tsc =  tsc;
2167 	cpu->sample.aperf -= cpu->prev_aperf;
2168 	cpu->sample.mperf -= cpu->prev_mperf;
2169 	cpu->sample.tsc -= cpu->prev_tsc;
2170 
2171 	cpu->prev_aperf = aperf;
2172 	cpu->prev_mperf = mperf;
2173 	cpu->prev_tsc = tsc;
2174 	/*
2175 	 * First time this function is invoked in a given cycle, all of the
2176 	 * previous sample data fields are equal to zero or stale and they must
2177 	 * be populated with meaningful numbers for things to work, so assume
2178 	 * that sample.time will always be reset before setting the utilization
2179 	 * update hook and make the caller skip the sample then.
2180 	 */
2181 	if (cpu->last_sample_time) {
2182 		intel_pstate_calc_avg_perf(cpu);
2183 		return true;
2184 	}
2185 	return false;
2186 }
2187 
2188 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2189 {
2190 	return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2191 }
2192 
2193 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2194 {
2195 	return mul_ext_fp(cpu->pstate.max_pstate_physical,
2196 			  cpu->sample.core_avg_perf);
2197 }
2198 
2199 static inline int32_t get_target_pstate(struct cpudata *cpu)
2200 {
2201 	struct sample *sample = &cpu->sample;
2202 	int32_t busy_frac;
2203 	int target, avg_pstate;
2204 
2205 	busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2206 			   sample->tsc);
2207 
2208 	if (busy_frac < cpu->iowait_boost)
2209 		busy_frac = cpu->iowait_boost;
2210 
2211 	sample->busy_scaled = busy_frac * 100;
2212 
2213 	target = global.no_turbo || global.turbo_disabled ?
2214 			cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2215 	target += target >> 2;
2216 	target = mul_fp(target, busy_frac);
2217 	if (target < cpu->pstate.min_pstate)
2218 		target = cpu->pstate.min_pstate;
2219 
2220 	/*
2221 	 * If the average P-state during the previous cycle was higher than the
2222 	 * current target, add 50% of the difference to the target to reduce
2223 	 * possible performance oscillations and offset possible performance
2224 	 * loss related to moving the workload from one CPU to another within
2225 	 * a package/module.
2226 	 */
2227 	avg_pstate = get_avg_pstate(cpu);
2228 	if (avg_pstate > target)
2229 		target += (avg_pstate - target) >> 1;
2230 
2231 	return target;
2232 }
2233 
2234 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2235 {
2236 	int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2237 	int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2238 
2239 	return clamp_t(int, pstate, min_pstate, max_pstate);
2240 }
2241 
2242 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2243 {
2244 	if (pstate == cpu->pstate.current_pstate)
2245 		return;
2246 
2247 	cpu->pstate.current_pstate = pstate;
2248 	wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2249 }
2250 
2251 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2252 {
2253 	int from = cpu->pstate.current_pstate;
2254 	struct sample *sample;
2255 	int target_pstate;
2256 
2257 	update_turbo_state();
2258 
2259 	target_pstate = get_target_pstate(cpu);
2260 	target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2261 	trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2262 	intel_pstate_update_pstate(cpu, target_pstate);
2263 
2264 	sample = &cpu->sample;
2265 	trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2266 		fp_toint(sample->busy_scaled),
2267 		from,
2268 		cpu->pstate.current_pstate,
2269 		sample->mperf,
2270 		sample->aperf,
2271 		sample->tsc,
2272 		get_avg_frequency(cpu),
2273 		fp_toint(cpu->iowait_boost * 100));
2274 }
2275 
2276 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2277 				     unsigned int flags)
2278 {
2279 	struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2280 	u64 delta_ns;
2281 
2282 	/* Don't allow remote callbacks */
2283 	if (smp_processor_id() != cpu->cpu)
2284 		return;
2285 
2286 	delta_ns = time - cpu->last_update;
2287 	if (flags & SCHED_CPUFREQ_IOWAIT) {
2288 		/* Start over if the CPU may have been idle. */
2289 		if (delta_ns > TICK_NSEC) {
2290 			cpu->iowait_boost = ONE_EIGHTH_FP;
2291 		} else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2292 			cpu->iowait_boost <<= 1;
2293 			if (cpu->iowait_boost > int_tofp(1))
2294 				cpu->iowait_boost = int_tofp(1);
2295 		} else {
2296 			cpu->iowait_boost = ONE_EIGHTH_FP;
2297 		}
2298 	} else if (cpu->iowait_boost) {
2299 		/* Clear iowait_boost if the CPU may have been idle. */
2300 		if (delta_ns > TICK_NSEC)
2301 			cpu->iowait_boost = 0;
2302 		else
2303 			cpu->iowait_boost >>= 1;
2304 	}
2305 	cpu->last_update = time;
2306 	delta_ns = time - cpu->sample.time;
2307 	if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2308 		return;
2309 
2310 	if (intel_pstate_sample(cpu, time))
2311 		intel_pstate_adjust_pstate(cpu);
2312 }
2313 
2314 static struct pstate_funcs core_funcs = {
2315 	.get_max = core_get_max_pstate,
2316 	.get_max_physical = core_get_max_pstate_physical,
2317 	.get_min = core_get_min_pstate,
2318 	.get_turbo = core_get_turbo_pstate,
2319 	.get_scaling = core_get_scaling,
2320 	.get_val = core_get_val,
2321 };
2322 
2323 static const struct pstate_funcs silvermont_funcs = {
2324 	.get_max = atom_get_max_pstate,
2325 	.get_max_physical = atom_get_max_pstate,
2326 	.get_min = atom_get_min_pstate,
2327 	.get_turbo = atom_get_turbo_pstate,
2328 	.get_val = atom_get_val,
2329 	.get_scaling = silvermont_get_scaling,
2330 	.get_vid = atom_get_vid,
2331 };
2332 
2333 static const struct pstate_funcs airmont_funcs = {
2334 	.get_max = atom_get_max_pstate,
2335 	.get_max_physical = atom_get_max_pstate,
2336 	.get_min = atom_get_min_pstate,
2337 	.get_turbo = atom_get_turbo_pstate,
2338 	.get_val = atom_get_val,
2339 	.get_scaling = airmont_get_scaling,
2340 	.get_vid = atom_get_vid,
2341 };
2342 
2343 static const struct pstate_funcs knl_funcs = {
2344 	.get_max = core_get_max_pstate,
2345 	.get_max_physical = core_get_max_pstate_physical,
2346 	.get_min = core_get_min_pstate,
2347 	.get_turbo = knl_get_turbo_pstate,
2348 	.get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2349 	.get_scaling = core_get_scaling,
2350 	.get_val = core_get_val,
2351 };
2352 
2353 #define X86_MATCH(model, policy)					 \
2354 	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2355 					   X86_FEATURE_APERFMPERF, &policy)
2356 
2357 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2358 	X86_MATCH(SANDYBRIDGE,		core_funcs),
2359 	X86_MATCH(SANDYBRIDGE_X,	core_funcs),
2360 	X86_MATCH(ATOM_SILVERMONT,	silvermont_funcs),
2361 	X86_MATCH(IVYBRIDGE,		core_funcs),
2362 	X86_MATCH(HASWELL,		core_funcs),
2363 	X86_MATCH(BROADWELL,		core_funcs),
2364 	X86_MATCH(IVYBRIDGE_X,		core_funcs),
2365 	X86_MATCH(HASWELL_X,		core_funcs),
2366 	X86_MATCH(HASWELL_L,		core_funcs),
2367 	X86_MATCH(HASWELL_G,		core_funcs),
2368 	X86_MATCH(BROADWELL_G,		core_funcs),
2369 	X86_MATCH(ATOM_AIRMONT,		airmont_funcs),
2370 	X86_MATCH(SKYLAKE_L,		core_funcs),
2371 	X86_MATCH(BROADWELL_X,		core_funcs),
2372 	X86_MATCH(SKYLAKE,		core_funcs),
2373 	X86_MATCH(BROADWELL_D,		core_funcs),
2374 	X86_MATCH(XEON_PHI_KNL,		knl_funcs),
2375 	X86_MATCH(XEON_PHI_KNM,		knl_funcs),
2376 	X86_MATCH(ATOM_GOLDMONT,	core_funcs),
2377 	X86_MATCH(ATOM_GOLDMONT_PLUS,	core_funcs),
2378 	X86_MATCH(SKYLAKE_X,		core_funcs),
2379 	X86_MATCH(COMETLAKE,		core_funcs),
2380 	X86_MATCH(ICELAKE_X,		core_funcs),
2381 	X86_MATCH(TIGERLAKE,		core_funcs),
2382 	X86_MATCH(SAPPHIRERAPIDS_X,	core_funcs),
2383 	{}
2384 };
2385 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2386 
2387 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2388 	X86_MATCH(BROADWELL_D,		core_funcs),
2389 	X86_MATCH(BROADWELL_X,		core_funcs),
2390 	X86_MATCH(SKYLAKE_X,		core_funcs),
2391 	X86_MATCH(ICELAKE_X,		core_funcs),
2392 	X86_MATCH(SAPPHIRERAPIDS_X,	core_funcs),
2393 	{}
2394 };
2395 
2396 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2397 	X86_MATCH(KABYLAKE,		core_funcs),
2398 	{}
2399 };
2400 
2401 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2402 	X86_MATCH(SKYLAKE_X,		core_funcs),
2403 	X86_MATCH(SKYLAKE,		core_funcs),
2404 	{}
2405 };
2406 
2407 static int intel_pstate_init_cpu(unsigned int cpunum)
2408 {
2409 	struct cpudata *cpu;
2410 
2411 	cpu = all_cpu_data[cpunum];
2412 
2413 	if (!cpu) {
2414 		cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2415 		if (!cpu)
2416 			return -ENOMEM;
2417 
2418 		WRITE_ONCE(all_cpu_data[cpunum], cpu);
2419 
2420 		cpu->cpu = cpunum;
2421 
2422 		cpu->epp_default = -EINVAL;
2423 
2424 		if (hwp_active) {
2425 			const struct x86_cpu_id *id;
2426 
2427 			intel_pstate_hwp_enable(cpu);
2428 
2429 			id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2430 			if (id && intel_pstate_acpi_pm_profile_server())
2431 				hwp_boost = true;
2432 		}
2433 	} else if (hwp_active) {
2434 		/*
2435 		 * Re-enable HWP in case this happens after a resume from ACPI
2436 		 * S3 if the CPU was offline during the whole system/resume
2437 		 * cycle.
2438 		 */
2439 		intel_pstate_hwp_reenable(cpu);
2440 	}
2441 
2442 	cpu->epp_powersave = -EINVAL;
2443 	cpu->epp_policy = 0;
2444 
2445 	intel_pstate_get_cpu_pstates(cpu);
2446 
2447 	pr_debug("controlling: cpu %d\n", cpunum);
2448 
2449 	return 0;
2450 }
2451 
2452 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2453 {
2454 	struct cpudata *cpu = all_cpu_data[cpu_num];
2455 
2456 	if (hwp_active && !hwp_boost)
2457 		return;
2458 
2459 	if (cpu->update_util_set)
2460 		return;
2461 
2462 	/* Prevent intel_pstate_update_util() from using stale data. */
2463 	cpu->sample.time = 0;
2464 	cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2465 				     (hwp_active ?
2466 				      intel_pstate_update_util_hwp :
2467 				      intel_pstate_update_util));
2468 	cpu->update_util_set = true;
2469 }
2470 
2471 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2472 {
2473 	struct cpudata *cpu_data = all_cpu_data[cpu];
2474 
2475 	if (!cpu_data->update_util_set)
2476 		return;
2477 
2478 	cpufreq_remove_update_util_hook(cpu);
2479 	cpu_data->update_util_set = false;
2480 	synchronize_rcu();
2481 }
2482 
2483 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2484 {
2485 	return global.turbo_disabled || global.no_turbo ?
2486 			cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2487 }
2488 
2489 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2490 					    unsigned int policy_min,
2491 					    unsigned int policy_max)
2492 {
2493 	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2494 	int32_t max_policy_perf, min_policy_perf;
2495 
2496 	max_policy_perf = policy_max / perf_ctl_scaling;
2497 	if (policy_max == policy_min) {
2498 		min_policy_perf = max_policy_perf;
2499 	} else {
2500 		min_policy_perf = policy_min / perf_ctl_scaling;
2501 		min_policy_perf = clamp_t(int32_t, min_policy_perf,
2502 					  0, max_policy_perf);
2503 	}
2504 
2505 	/*
2506 	 * HWP needs some special consideration, because HWP_REQUEST uses
2507 	 * abstract values to represent performance rather than pure ratios.
2508 	 */
2509 	if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2510 		int scaling = cpu->pstate.scaling;
2511 		int freq;
2512 
2513 		freq = max_policy_perf * perf_ctl_scaling;
2514 		max_policy_perf = DIV_ROUND_UP(freq, scaling);
2515 		freq = min_policy_perf * perf_ctl_scaling;
2516 		min_policy_perf = DIV_ROUND_UP(freq, scaling);
2517 	}
2518 
2519 	pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2520 		 cpu->cpu, min_policy_perf, max_policy_perf);
2521 
2522 	/* Normalize user input to [min_perf, max_perf] */
2523 	if (per_cpu_limits) {
2524 		cpu->min_perf_ratio = min_policy_perf;
2525 		cpu->max_perf_ratio = max_policy_perf;
2526 	} else {
2527 		int turbo_max = cpu->pstate.turbo_pstate;
2528 		int32_t global_min, global_max;
2529 
2530 		/* Global limits are in percent of the maximum turbo P-state. */
2531 		global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2532 		global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2533 		global_min = clamp_t(int32_t, global_min, 0, global_max);
2534 
2535 		pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2536 			 global_min, global_max);
2537 
2538 		cpu->min_perf_ratio = max(min_policy_perf, global_min);
2539 		cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2540 		cpu->max_perf_ratio = min(max_policy_perf, global_max);
2541 		cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2542 
2543 		/* Make sure min_perf <= max_perf */
2544 		cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2545 					  cpu->max_perf_ratio);
2546 
2547 	}
2548 	pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2549 		 cpu->max_perf_ratio,
2550 		 cpu->min_perf_ratio);
2551 }
2552 
2553 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2554 {
2555 	struct cpudata *cpu;
2556 
2557 	if (!policy->cpuinfo.max_freq)
2558 		return -ENODEV;
2559 
2560 	pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2561 		 policy->cpuinfo.max_freq, policy->max);
2562 
2563 	cpu = all_cpu_data[policy->cpu];
2564 	cpu->policy = policy->policy;
2565 
2566 	mutex_lock(&intel_pstate_limits_lock);
2567 
2568 	intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2569 
2570 	if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2571 		/*
2572 		 * NOHZ_FULL CPUs need this as the governor callback may not
2573 		 * be invoked on them.
2574 		 */
2575 		intel_pstate_clear_update_util_hook(policy->cpu);
2576 		intel_pstate_max_within_limits(cpu);
2577 	} else {
2578 		intel_pstate_set_update_util_hook(policy->cpu);
2579 	}
2580 
2581 	if (hwp_active) {
2582 		/*
2583 		 * When hwp_boost was active before and dynamically it
2584 		 * was turned off, in that case we need to clear the
2585 		 * update util hook.
2586 		 */
2587 		if (!hwp_boost)
2588 			intel_pstate_clear_update_util_hook(policy->cpu);
2589 		intel_pstate_hwp_set(policy->cpu);
2590 	}
2591 
2592 	mutex_unlock(&intel_pstate_limits_lock);
2593 
2594 	return 0;
2595 }
2596 
2597 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2598 					   struct cpufreq_policy_data *policy)
2599 {
2600 	if (!hwp_active &&
2601 	    cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2602 	    policy->max < policy->cpuinfo.max_freq &&
2603 	    policy->max > cpu->pstate.max_freq) {
2604 		pr_debug("policy->max > max non turbo frequency\n");
2605 		policy->max = policy->cpuinfo.max_freq;
2606 	}
2607 }
2608 
2609 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2610 					   struct cpufreq_policy_data *policy)
2611 {
2612 	int max_freq;
2613 
2614 	update_turbo_state();
2615 	if (hwp_active) {
2616 		intel_pstate_get_hwp_cap(cpu);
2617 		max_freq = global.no_turbo || global.turbo_disabled ?
2618 				cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2619 	} else {
2620 		max_freq = intel_pstate_get_max_freq(cpu);
2621 	}
2622 	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2623 
2624 	intel_pstate_adjust_policy_max(cpu, policy);
2625 }
2626 
2627 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2628 {
2629 	intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2630 
2631 	return 0;
2632 }
2633 
2634 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2635 {
2636 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2637 
2638 	pr_debug("CPU %d going offline\n", cpu->cpu);
2639 
2640 	if (cpu->suspended)
2641 		return 0;
2642 
2643 	/*
2644 	 * If the CPU is an SMT thread and it goes offline with the performance
2645 	 * settings different from the minimum, it will prevent its sibling
2646 	 * from getting to lower performance levels, so force the minimum
2647 	 * performance on CPU offline to prevent that from happening.
2648 	 */
2649 	if (hwp_active)
2650 		intel_pstate_hwp_offline(cpu);
2651 	else
2652 		intel_pstate_set_min_pstate(cpu);
2653 
2654 	intel_pstate_exit_perf_limits(policy);
2655 
2656 	return 0;
2657 }
2658 
2659 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2660 {
2661 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2662 
2663 	pr_debug("CPU %d going online\n", cpu->cpu);
2664 
2665 	intel_pstate_init_acpi_perf_limits(policy);
2666 
2667 	if (hwp_active) {
2668 		/*
2669 		 * Re-enable HWP and clear the "suspended" flag to let "resume"
2670 		 * know that it need not do that.
2671 		 */
2672 		intel_pstate_hwp_reenable(cpu);
2673 		cpu->suspended = false;
2674 	}
2675 
2676 	return 0;
2677 }
2678 
2679 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2680 {
2681 	intel_pstate_clear_update_util_hook(policy->cpu);
2682 
2683 	return intel_cpufreq_cpu_offline(policy);
2684 }
2685 
2686 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2687 {
2688 	pr_debug("CPU %d exiting\n", policy->cpu);
2689 
2690 	policy->fast_switch_possible = false;
2691 
2692 	return 0;
2693 }
2694 
2695 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2696 {
2697 	struct cpudata *cpu;
2698 	int rc;
2699 
2700 	rc = intel_pstate_init_cpu(policy->cpu);
2701 	if (rc)
2702 		return rc;
2703 
2704 	cpu = all_cpu_data[policy->cpu];
2705 
2706 	cpu->max_perf_ratio = 0xFF;
2707 	cpu->min_perf_ratio = 0;
2708 
2709 	/* cpuinfo and default policy values */
2710 	policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2711 	update_turbo_state();
2712 	global.turbo_disabled_mf = global.turbo_disabled;
2713 	policy->cpuinfo.max_freq = global.turbo_disabled ?
2714 			cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2715 
2716 	policy->min = policy->cpuinfo.min_freq;
2717 	policy->max = policy->cpuinfo.max_freq;
2718 
2719 	intel_pstate_init_acpi_perf_limits(policy);
2720 
2721 	policy->fast_switch_possible = true;
2722 
2723 	return 0;
2724 }
2725 
2726 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2727 {
2728 	int ret = __intel_pstate_cpu_init(policy);
2729 
2730 	if (ret)
2731 		return ret;
2732 
2733 	/*
2734 	 * Set the policy to powersave to provide a valid fallback value in case
2735 	 * the default cpufreq governor is neither powersave nor performance.
2736 	 */
2737 	policy->policy = CPUFREQ_POLICY_POWERSAVE;
2738 
2739 	if (hwp_active) {
2740 		struct cpudata *cpu = all_cpu_data[policy->cpu];
2741 
2742 		cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2743 	}
2744 
2745 	return 0;
2746 }
2747 
2748 static struct cpufreq_driver intel_pstate = {
2749 	.flags		= CPUFREQ_CONST_LOOPS,
2750 	.verify		= intel_pstate_verify_policy,
2751 	.setpolicy	= intel_pstate_set_policy,
2752 	.suspend	= intel_pstate_suspend,
2753 	.resume		= intel_pstate_resume,
2754 	.init		= intel_pstate_cpu_init,
2755 	.exit		= intel_pstate_cpu_exit,
2756 	.offline	= intel_pstate_cpu_offline,
2757 	.online		= intel_pstate_cpu_online,
2758 	.update_limits	= intel_pstate_update_limits,
2759 	.name		= "intel_pstate",
2760 };
2761 
2762 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2763 {
2764 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2765 
2766 	intel_pstate_verify_cpu_policy(cpu, policy);
2767 	intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2768 
2769 	return 0;
2770 }
2771 
2772 /* Use of trace in passive mode:
2773  *
2774  * In passive mode the trace core_busy field (also known as the
2775  * performance field, and lablelled as such on the graphs; also known as
2776  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2777  * driver call was via the normal or fast switch path. Various graphs
2778  * output from the intel_pstate_tracer.py utility that include core_busy
2779  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2780  * so we use 10 to indicate the normal path through the driver, and
2781  * 90 to indicate the fast switch path through the driver.
2782  * The scaled_busy field is not used, and is set to 0.
2783  */
2784 
2785 #define	INTEL_PSTATE_TRACE_TARGET 10
2786 #define	INTEL_PSTATE_TRACE_FAST_SWITCH 90
2787 
2788 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2789 {
2790 	struct sample *sample;
2791 
2792 	if (!trace_pstate_sample_enabled())
2793 		return;
2794 
2795 	if (!intel_pstate_sample(cpu, ktime_get()))
2796 		return;
2797 
2798 	sample = &cpu->sample;
2799 	trace_pstate_sample(trace_type,
2800 		0,
2801 		old_pstate,
2802 		cpu->pstate.current_pstate,
2803 		sample->mperf,
2804 		sample->aperf,
2805 		sample->tsc,
2806 		get_avg_frequency(cpu),
2807 		fp_toint(cpu->iowait_boost * 100));
2808 }
2809 
2810 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2811 				     u32 desired, bool fast_switch)
2812 {
2813 	u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2814 
2815 	value &= ~HWP_MIN_PERF(~0L);
2816 	value |= HWP_MIN_PERF(min);
2817 
2818 	value &= ~HWP_MAX_PERF(~0L);
2819 	value |= HWP_MAX_PERF(max);
2820 
2821 	value &= ~HWP_DESIRED_PERF(~0L);
2822 	value |= HWP_DESIRED_PERF(desired);
2823 
2824 	if (value == prev)
2825 		return;
2826 
2827 	WRITE_ONCE(cpu->hwp_req_cached, value);
2828 	if (fast_switch)
2829 		wrmsrl(MSR_HWP_REQUEST, value);
2830 	else
2831 		wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2832 }
2833 
2834 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2835 					  u32 target_pstate, bool fast_switch)
2836 {
2837 	if (fast_switch)
2838 		wrmsrl(MSR_IA32_PERF_CTL,
2839 		       pstate_funcs.get_val(cpu, target_pstate));
2840 	else
2841 		wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2842 			      pstate_funcs.get_val(cpu, target_pstate));
2843 }
2844 
2845 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2846 				       int target_pstate, bool fast_switch)
2847 {
2848 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2849 	int old_pstate = cpu->pstate.current_pstate;
2850 
2851 	target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2852 	if (hwp_active) {
2853 		int max_pstate = policy->strict_target ?
2854 					target_pstate : cpu->max_perf_ratio;
2855 
2856 		intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2857 					 fast_switch);
2858 	} else if (target_pstate != old_pstate) {
2859 		intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2860 	}
2861 
2862 	cpu->pstate.current_pstate = target_pstate;
2863 
2864 	intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2865 			    INTEL_PSTATE_TRACE_TARGET, old_pstate);
2866 
2867 	return target_pstate;
2868 }
2869 
2870 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2871 				unsigned int target_freq,
2872 				unsigned int relation)
2873 {
2874 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2875 	struct cpufreq_freqs freqs;
2876 	int target_pstate;
2877 
2878 	update_turbo_state();
2879 
2880 	freqs.old = policy->cur;
2881 	freqs.new = target_freq;
2882 
2883 	cpufreq_freq_transition_begin(policy, &freqs);
2884 
2885 	switch (relation) {
2886 	case CPUFREQ_RELATION_L:
2887 		target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2888 		break;
2889 	case CPUFREQ_RELATION_H:
2890 		target_pstate = freqs.new / cpu->pstate.scaling;
2891 		break;
2892 	default:
2893 		target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2894 		break;
2895 	}
2896 
2897 	target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2898 
2899 	freqs.new = target_pstate * cpu->pstate.scaling;
2900 
2901 	cpufreq_freq_transition_end(policy, &freqs, false);
2902 
2903 	return 0;
2904 }
2905 
2906 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2907 					      unsigned int target_freq)
2908 {
2909 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2910 	int target_pstate;
2911 
2912 	update_turbo_state();
2913 
2914 	target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2915 
2916 	target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2917 
2918 	return target_pstate * cpu->pstate.scaling;
2919 }
2920 
2921 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2922 				      unsigned long min_perf,
2923 				      unsigned long target_perf,
2924 				      unsigned long capacity)
2925 {
2926 	struct cpudata *cpu = all_cpu_data[cpunum];
2927 	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2928 	int old_pstate = cpu->pstate.current_pstate;
2929 	int cap_pstate, min_pstate, max_pstate, target_pstate;
2930 
2931 	update_turbo_state();
2932 	cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2933 					     HWP_HIGHEST_PERF(hwp_cap);
2934 
2935 	/* Optimization: Avoid unnecessary divisions. */
2936 
2937 	target_pstate = cap_pstate;
2938 	if (target_perf < capacity)
2939 		target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2940 
2941 	min_pstate = cap_pstate;
2942 	if (min_perf < capacity)
2943 		min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2944 
2945 	if (min_pstate < cpu->pstate.min_pstate)
2946 		min_pstate = cpu->pstate.min_pstate;
2947 
2948 	if (min_pstate < cpu->min_perf_ratio)
2949 		min_pstate = cpu->min_perf_ratio;
2950 
2951 	max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2952 	if (max_pstate < min_pstate)
2953 		max_pstate = min_pstate;
2954 
2955 	target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2956 
2957 	intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2958 
2959 	cpu->pstate.current_pstate = target_pstate;
2960 	intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2961 }
2962 
2963 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2964 {
2965 	struct freq_qos_request *req;
2966 	struct cpudata *cpu;
2967 	struct device *dev;
2968 	int ret, freq;
2969 
2970 	dev = get_cpu_device(policy->cpu);
2971 	if (!dev)
2972 		return -ENODEV;
2973 
2974 	ret = __intel_pstate_cpu_init(policy);
2975 	if (ret)
2976 		return ret;
2977 
2978 	policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2979 	/* This reflects the intel_pstate_get_cpu_pstates() setting. */
2980 	policy->cur = policy->cpuinfo.min_freq;
2981 
2982 	req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2983 	if (!req) {
2984 		ret = -ENOMEM;
2985 		goto pstate_exit;
2986 	}
2987 
2988 	cpu = all_cpu_data[policy->cpu];
2989 
2990 	if (hwp_active) {
2991 		u64 value;
2992 
2993 		policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2994 
2995 		intel_pstate_get_hwp_cap(cpu);
2996 
2997 		rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
2998 		WRITE_ONCE(cpu->hwp_req_cached, value);
2999 
3000 		cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3001 	} else {
3002 		policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3003 	}
3004 
3005 	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3006 
3007 	ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3008 				   freq);
3009 	if (ret < 0) {
3010 		dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3011 		goto free_req;
3012 	}
3013 
3014 	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3015 
3016 	ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3017 				   freq);
3018 	if (ret < 0) {
3019 		dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3020 		goto remove_min_req;
3021 	}
3022 
3023 	policy->driver_data = req;
3024 
3025 	return 0;
3026 
3027 remove_min_req:
3028 	freq_qos_remove_request(req);
3029 free_req:
3030 	kfree(req);
3031 pstate_exit:
3032 	intel_pstate_exit_perf_limits(policy);
3033 
3034 	return ret;
3035 }
3036 
3037 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3038 {
3039 	struct freq_qos_request *req;
3040 
3041 	req = policy->driver_data;
3042 
3043 	freq_qos_remove_request(req + 1);
3044 	freq_qos_remove_request(req);
3045 	kfree(req);
3046 
3047 	return intel_pstate_cpu_exit(policy);
3048 }
3049 
3050 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3051 {
3052 	intel_pstate_suspend(policy);
3053 
3054 	if (hwp_active) {
3055 		struct cpudata *cpu = all_cpu_data[policy->cpu];
3056 		u64 value = READ_ONCE(cpu->hwp_req_cached);
3057 
3058 		/*
3059 		 * Clear the desired perf field in MSR_HWP_REQUEST in case
3060 		 * intel_cpufreq_adjust_perf() is in use and the last value
3061 		 * written by it may not be suitable.
3062 		 */
3063 		value &= ~HWP_DESIRED_PERF(~0L);
3064 		wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3065 		WRITE_ONCE(cpu->hwp_req_cached, value);
3066 	}
3067 
3068 	return 0;
3069 }
3070 
3071 static struct cpufreq_driver intel_cpufreq = {
3072 	.flags		= CPUFREQ_CONST_LOOPS,
3073 	.verify		= intel_cpufreq_verify_policy,
3074 	.target		= intel_cpufreq_target,
3075 	.fast_switch	= intel_cpufreq_fast_switch,
3076 	.init		= intel_cpufreq_cpu_init,
3077 	.exit		= intel_cpufreq_cpu_exit,
3078 	.offline	= intel_cpufreq_cpu_offline,
3079 	.online		= intel_pstate_cpu_online,
3080 	.suspend	= intel_cpufreq_suspend,
3081 	.resume		= intel_pstate_resume,
3082 	.update_limits	= intel_pstate_update_limits,
3083 	.name		= "intel_cpufreq",
3084 };
3085 
3086 static struct cpufreq_driver *default_driver;
3087 
3088 static void intel_pstate_driver_cleanup(void)
3089 {
3090 	unsigned int cpu;
3091 
3092 	cpus_read_lock();
3093 	for_each_online_cpu(cpu) {
3094 		if (all_cpu_data[cpu]) {
3095 			if (intel_pstate_driver == &intel_pstate)
3096 				intel_pstate_clear_update_util_hook(cpu);
3097 
3098 			spin_lock(&hwp_notify_lock);
3099 			kfree(all_cpu_data[cpu]);
3100 			WRITE_ONCE(all_cpu_data[cpu], NULL);
3101 			spin_unlock(&hwp_notify_lock);
3102 		}
3103 	}
3104 	cpus_read_unlock();
3105 
3106 	intel_pstate_driver = NULL;
3107 }
3108 
3109 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3110 {
3111 	int ret;
3112 
3113 	if (driver == &intel_pstate)
3114 		intel_pstate_sysfs_expose_hwp_dynamic_boost();
3115 
3116 	memset(&global, 0, sizeof(global));
3117 	global.max_perf_pct = 100;
3118 
3119 	intel_pstate_driver = driver;
3120 	ret = cpufreq_register_driver(intel_pstate_driver);
3121 	if (ret) {
3122 		intel_pstate_driver_cleanup();
3123 		return ret;
3124 	}
3125 
3126 	global.min_perf_pct = min_perf_pct_min();
3127 
3128 	return 0;
3129 }
3130 
3131 static ssize_t intel_pstate_show_status(char *buf)
3132 {
3133 	if (!intel_pstate_driver)
3134 		return sprintf(buf, "off\n");
3135 
3136 	return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3137 					"active" : "passive");
3138 }
3139 
3140 static int intel_pstate_update_status(const char *buf, size_t size)
3141 {
3142 	if (size == 3 && !strncmp(buf, "off", size)) {
3143 		if (!intel_pstate_driver)
3144 			return -EINVAL;
3145 
3146 		if (hwp_active)
3147 			return -EBUSY;
3148 
3149 		cpufreq_unregister_driver(intel_pstate_driver);
3150 		intel_pstate_driver_cleanup();
3151 		return 0;
3152 	}
3153 
3154 	if (size == 6 && !strncmp(buf, "active", size)) {
3155 		if (intel_pstate_driver) {
3156 			if (intel_pstate_driver == &intel_pstate)
3157 				return 0;
3158 
3159 			cpufreq_unregister_driver(intel_pstate_driver);
3160 		}
3161 
3162 		return intel_pstate_register_driver(&intel_pstate);
3163 	}
3164 
3165 	if (size == 7 && !strncmp(buf, "passive", size)) {
3166 		if (intel_pstate_driver) {
3167 			if (intel_pstate_driver == &intel_cpufreq)
3168 				return 0;
3169 
3170 			cpufreq_unregister_driver(intel_pstate_driver);
3171 			intel_pstate_sysfs_hide_hwp_dynamic_boost();
3172 		}
3173 
3174 		return intel_pstate_register_driver(&intel_cpufreq);
3175 	}
3176 
3177 	return -EINVAL;
3178 }
3179 
3180 static int no_load __initdata;
3181 static int no_hwp __initdata;
3182 static int hwp_only __initdata;
3183 static unsigned int force_load __initdata;
3184 
3185 static int __init intel_pstate_msrs_not_valid(void)
3186 {
3187 	if (!pstate_funcs.get_max(0) ||
3188 	    !pstate_funcs.get_min(0) ||
3189 	    !pstate_funcs.get_turbo(0))
3190 		return -ENODEV;
3191 
3192 	return 0;
3193 }
3194 
3195 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3196 {
3197 	pstate_funcs.get_max   = funcs->get_max;
3198 	pstate_funcs.get_max_physical = funcs->get_max_physical;
3199 	pstate_funcs.get_min   = funcs->get_min;
3200 	pstate_funcs.get_turbo = funcs->get_turbo;
3201 	pstate_funcs.get_scaling = funcs->get_scaling;
3202 	pstate_funcs.get_val   = funcs->get_val;
3203 	pstate_funcs.get_vid   = funcs->get_vid;
3204 	pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3205 }
3206 
3207 #ifdef CONFIG_ACPI
3208 
3209 static bool __init intel_pstate_no_acpi_pss(void)
3210 {
3211 	int i;
3212 
3213 	for_each_possible_cpu(i) {
3214 		acpi_status status;
3215 		union acpi_object *pss;
3216 		struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3217 		struct acpi_processor *pr = per_cpu(processors, i);
3218 
3219 		if (!pr)
3220 			continue;
3221 
3222 		status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3223 		if (ACPI_FAILURE(status))
3224 			continue;
3225 
3226 		pss = buffer.pointer;
3227 		if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3228 			kfree(pss);
3229 			return false;
3230 		}
3231 
3232 		kfree(pss);
3233 	}
3234 
3235 	pr_debug("ACPI _PSS not found\n");
3236 	return true;
3237 }
3238 
3239 static bool __init intel_pstate_no_acpi_pcch(void)
3240 {
3241 	acpi_status status;
3242 	acpi_handle handle;
3243 
3244 	status = acpi_get_handle(NULL, "\\_SB", &handle);
3245 	if (ACPI_FAILURE(status))
3246 		goto not_found;
3247 
3248 	if (acpi_has_method(handle, "PCCH"))
3249 		return false;
3250 
3251 not_found:
3252 	pr_debug("ACPI PCCH not found\n");
3253 	return true;
3254 }
3255 
3256 static bool __init intel_pstate_has_acpi_ppc(void)
3257 {
3258 	int i;
3259 
3260 	for_each_possible_cpu(i) {
3261 		struct acpi_processor *pr = per_cpu(processors, i);
3262 
3263 		if (!pr)
3264 			continue;
3265 		if (acpi_has_method(pr->handle, "_PPC"))
3266 			return true;
3267 	}
3268 	pr_debug("ACPI _PPC not found\n");
3269 	return false;
3270 }
3271 
3272 enum {
3273 	PSS,
3274 	PPC,
3275 };
3276 
3277 /* Hardware vendor-specific info that has its own power management modes */
3278 static struct acpi_platform_list plat_info[] __initdata = {
3279 	{"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3280 	{"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3281 	{"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3282 	{"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3283 	{"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3284 	{"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3285 	{"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3286 	{"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3287 	{"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3288 	{"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3289 	{"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3290 	{"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3291 	{"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3292 	{"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3293 	{"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3294 	{ } /* End */
3295 };
3296 
3297 #define BITMASK_OOB	(BIT(8) | BIT(18))
3298 
3299 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3300 {
3301 	const struct x86_cpu_id *id;
3302 	u64 misc_pwr;
3303 	int idx;
3304 
3305 	id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3306 	if (id) {
3307 		rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3308 		if (misc_pwr & BITMASK_OOB) {
3309 			pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3310 			pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3311 			return true;
3312 		}
3313 	}
3314 
3315 	idx = acpi_match_platform_list(plat_info);
3316 	if (idx < 0)
3317 		return false;
3318 
3319 	switch (plat_info[idx].data) {
3320 	case PSS:
3321 		if (!intel_pstate_no_acpi_pss())
3322 			return false;
3323 
3324 		return intel_pstate_no_acpi_pcch();
3325 	case PPC:
3326 		return intel_pstate_has_acpi_ppc() && !force_load;
3327 	}
3328 
3329 	return false;
3330 }
3331 
3332 static void intel_pstate_request_control_from_smm(void)
3333 {
3334 	/*
3335 	 * It may be unsafe to request P-states control from SMM if _PPC support
3336 	 * has not been enabled.
3337 	 */
3338 	if (acpi_ppc)
3339 		acpi_processor_pstate_control();
3340 }
3341 #else /* CONFIG_ACPI not enabled */
3342 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3343 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3344 static inline void intel_pstate_request_control_from_smm(void) {}
3345 #endif /* CONFIG_ACPI */
3346 
3347 #define INTEL_PSTATE_HWP_BROADWELL	0x01
3348 
3349 #define X86_MATCH_HWP(model, hwp_mode)					\
3350 	X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3351 					   X86_FEATURE_HWP, hwp_mode)
3352 
3353 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3354 	X86_MATCH_HWP(BROADWELL_X,	INTEL_PSTATE_HWP_BROADWELL),
3355 	X86_MATCH_HWP(BROADWELL_D,	INTEL_PSTATE_HWP_BROADWELL),
3356 	X86_MATCH_HWP(ANY,		0),
3357 	{}
3358 };
3359 
3360 static bool intel_pstate_hwp_is_enabled(void)
3361 {
3362 	u64 value;
3363 
3364 	rdmsrl(MSR_PM_ENABLE, value);
3365 	return !!(value & 0x1);
3366 }
3367 
3368 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3369 	/*
3370 	 * Set EPP value as 102, this is the max suggested EPP
3371 	 * which can result in one core turbo frequency for
3372 	 * AlderLake Mobile CPUs.
3373 	 */
3374 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3375 	{}
3376 };
3377 
3378 static int __init intel_pstate_init(void)
3379 {
3380 	static struct cpudata **_all_cpu_data;
3381 	const struct x86_cpu_id *id;
3382 	int rc;
3383 
3384 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3385 		return -ENODEV;
3386 
3387 	id = x86_match_cpu(hwp_support_ids);
3388 	if (id) {
3389 		hwp_forced = intel_pstate_hwp_is_enabled();
3390 
3391 		if (hwp_forced)
3392 			pr_info("HWP enabled by BIOS\n");
3393 		else if (no_load)
3394 			return -ENODEV;
3395 
3396 		copy_cpu_funcs(&core_funcs);
3397 		/*
3398 		 * Avoid enabling HWP for processors without EPP support,
3399 		 * because that means incomplete HWP implementation which is a
3400 		 * corner case and supporting it is generally problematic.
3401 		 *
3402 		 * If HWP is enabled already, though, there is no choice but to
3403 		 * deal with it.
3404 		 */
3405 		if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3406 			WRITE_ONCE(hwp_active, 1);
3407 			hwp_mode_bdw = id->driver_data;
3408 			intel_pstate.attr = hwp_cpufreq_attrs;
3409 			intel_cpufreq.attr = hwp_cpufreq_attrs;
3410 			intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3411 			intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3412 			if (!default_driver)
3413 				default_driver = &intel_pstate;
3414 
3415 			if (boot_cpu_has(X86_FEATURE_HYBRID_CPU))
3416 				pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling;
3417 
3418 			goto hwp_cpu_matched;
3419 		}
3420 		pr_info("HWP not enabled\n");
3421 	} else {
3422 		if (no_load)
3423 			return -ENODEV;
3424 
3425 		id = x86_match_cpu(intel_pstate_cpu_ids);
3426 		if (!id) {
3427 			pr_info("CPU model not supported\n");
3428 			return -ENODEV;
3429 		}
3430 
3431 		copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3432 	}
3433 
3434 	if (intel_pstate_msrs_not_valid()) {
3435 		pr_info("Invalid MSRs\n");
3436 		return -ENODEV;
3437 	}
3438 	/* Without HWP start in the passive mode. */
3439 	if (!default_driver)
3440 		default_driver = &intel_cpufreq;
3441 
3442 hwp_cpu_matched:
3443 	/*
3444 	 * The Intel pstate driver will be ignored if the platform
3445 	 * firmware has its own power management modes.
3446 	 */
3447 	if (intel_pstate_platform_pwr_mgmt_exists()) {
3448 		pr_info("P-states controlled by the platform\n");
3449 		return -ENODEV;
3450 	}
3451 
3452 	if (!hwp_active && hwp_only)
3453 		return -ENOTSUPP;
3454 
3455 	pr_info("Intel P-state driver initializing\n");
3456 
3457 	_all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3458 	if (!_all_cpu_data)
3459 		return -ENOMEM;
3460 
3461 	WRITE_ONCE(all_cpu_data, _all_cpu_data);
3462 
3463 	intel_pstate_request_control_from_smm();
3464 
3465 	intel_pstate_sysfs_expose_params();
3466 
3467 	if (hwp_active) {
3468 		const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3469 
3470 		if (id)
3471 			epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3472 	}
3473 
3474 	mutex_lock(&intel_pstate_driver_lock);
3475 	rc = intel_pstate_register_driver(default_driver);
3476 	mutex_unlock(&intel_pstate_driver_lock);
3477 	if (rc) {
3478 		intel_pstate_sysfs_remove();
3479 		return rc;
3480 	}
3481 
3482 	if (hwp_active) {
3483 		const struct x86_cpu_id *id;
3484 
3485 		id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3486 		if (id) {
3487 			set_power_ctl_ee_state(false);
3488 			pr_info("Disabling energy efficiency optimization\n");
3489 		}
3490 
3491 		pr_info("HWP enabled\n");
3492 	} else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3493 		pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3494 	}
3495 
3496 	return 0;
3497 }
3498 device_initcall(intel_pstate_init);
3499 
3500 static int __init intel_pstate_setup(char *str)
3501 {
3502 	if (!str)
3503 		return -EINVAL;
3504 
3505 	if (!strcmp(str, "disable"))
3506 		no_load = 1;
3507 	else if (!strcmp(str, "active"))
3508 		default_driver = &intel_pstate;
3509 	else if (!strcmp(str, "passive"))
3510 		default_driver = &intel_cpufreq;
3511 
3512 	if (!strcmp(str, "no_hwp"))
3513 		no_hwp = 1;
3514 
3515 	if (!strcmp(str, "force"))
3516 		force_load = 1;
3517 	if (!strcmp(str, "hwp_only"))
3518 		hwp_only = 1;
3519 	if (!strcmp(str, "per_cpu_perf_limits"))
3520 		per_cpu_limits = true;
3521 
3522 #ifdef CONFIG_ACPI
3523 	if (!strcmp(str, "support_acpi_ppc"))
3524 		acpi_ppc = true;
3525 #endif
3526 
3527 	return 0;
3528 }
3529 early_param("intel_pstate", intel_pstate_setup);
3530 
3531 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3532 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3533 MODULE_LICENSE("GPL");
3534