1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched/cpufreq.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/acpi.h> 30 #include <linux/vmalloc.h> 31 #include <trace/events/power.h> 32 33 #include <asm/div64.h> 34 #include <asm/msr.h> 35 #include <asm/cpu_device_id.h> 36 #include <asm/cpufeature.h> 37 #include <asm/intel-family.h> 38 39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 40 41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #include <acpi/cppc_acpi.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define EXT_BITS 6 54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 57 58 static inline int32_t mul_fp(int32_t x, int32_t y) 59 { 60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 61 } 62 63 static inline int32_t div_fp(s64 x, s64 y) 64 { 65 return div64_s64((int64_t)x << FRAC_BITS, y); 66 } 67 68 static inline int ceiling_fp(int32_t x) 69 { 70 int mask, ret; 71 72 ret = fp_toint(x); 73 mask = (1 << FRAC_BITS) - 1; 74 if (x & mask) 75 ret += 1; 76 return ret; 77 } 78 79 static inline int32_t percent_fp(int percent) 80 { 81 return div_fp(percent, 100); 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 static inline int32_t percent_ext_fp(int percent) 95 { 96 return div_ext_fp(percent, 100); 97 } 98 99 /** 100 * struct sample - Store performance sample 101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 102 * performance during last sample period 103 * @busy_scaled: Scaled busy value which is used to calculate next 104 * P state. This can be different than core_avg_perf 105 * to account for cpu idle period 106 * @aperf: Difference of actual performance frequency clock count 107 * read from APERF MSR between last and current sample 108 * @mperf: Difference of maximum performance frequency clock count 109 * read from MPERF MSR between last and current sample 110 * @tsc: Difference of time stamp counter between last and 111 * current sample 112 * @time: Current time from scheduler 113 * 114 * This structure is used in the cpudata structure to store performance sample 115 * data for choosing next P State. 116 */ 117 struct sample { 118 int32_t core_avg_perf; 119 int32_t busy_scaled; 120 u64 aperf; 121 u64 mperf; 122 u64 tsc; 123 u64 time; 124 }; 125 126 /** 127 * struct pstate_data - Store P state data 128 * @current_pstate: Current requested P state 129 * @min_pstate: Min P state possible for this platform 130 * @max_pstate: Max P state possible for this platform 131 * @max_pstate_physical:This is physical Max P state for a processor 132 * This can be higher than the max_pstate which can 133 * be limited by platform thermal design power limits 134 * @scaling: Scaling factor to convert frequency to cpufreq 135 * frequency units 136 * @turbo_pstate: Max Turbo P state possible for this platform 137 * @max_freq: @max_pstate frequency in cpufreq units 138 * @turbo_freq: @turbo_pstate frequency in cpufreq units 139 * 140 * Stores the per cpu model P state limits and current P state. 141 */ 142 struct pstate_data { 143 int current_pstate; 144 int min_pstate; 145 int max_pstate; 146 int max_pstate_physical; 147 int scaling; 148 int turbo_pstate; 149 unsigned int max_freq; 150 unsigned int turbo_freq; 151 }; 152 153 /** 154 * struct vid_data - Stores voltage information data 155 * @min: VID data for this platform corresponding to 156 * the lowest P state 157 * @max: VID data corresponding to the highest P State. 158 * @turbo: VID data for turbo P state 159 * @ratio: Ratio of (vid max - vid min) / 160 * (max P state - Min P State) 161 * 162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 163 * This data is used in Atom platforms, where in addition to target P state, 164 * the voltage data needs to be specified to select next P State. 165 */ 166 struct vid_data { 167 int min; 168 int max; 169 int turbo; 170 int32_t ratio; 171 }; 172 173 /** 174 * struct global_params - Global parameters, mostly tunable via sysfs. 175 * @no_turbo: Whether or not to use turbo P-states. 176 * @turbo_disabled: Whethet or not turbo P-states are available at all, 177 * based on the MSR_IA32_MISC_ENABLE value and whether or 178 * not the maximum reported turbo P-state is different from 179 * the maximum reported non-turbo one. 180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 183 * P-state capacity. 184 */ 185 struct global_params { 186 bool no_turbo; 187 bool turbo_disabled; 188 int max_perf_pct; 189 int min_perf_pct; 190 }; 191 192 /** 193 * struct cpudata - Per CPU instance data storage 194 * @cpu: CPU number for this instance data 195 * @policy: CPUFreq policy value 196 * @update_util: CPUFreq utility callback information 197 * @update_util_set: CPUFreq utility callback is set 198 * @iowait_boost: iowait-related boost fraction 199 * @last_update: Time of the last update. 200 * @pstate: Stores P state limits for this CPU 201 * @vid: Stores VID limits for this CPU 202 * @last_sample_time: Last Sample time 203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented 204 * This shift is a multiplier to mperf delta to 205 * calculate CPU busy. 206 * @prev_aperf: Last APERF value read from APERF MSR 207 * @prev_mperf: Last MPERF value read from MPERF MSR 208 * @prev_tsc: Last timestamp counter (TSC) value 209 * @prev_cummulative_iowait: IO Wait time difference from last and 210 * current sample 211 * @sample: Storage for storing last Sample data 212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 214 * @acpi_perf_data: Stores ACPI perf information read from _PSS 215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 216 * @epp_powersave: Last saved HWP energy performance preference 217 * (EPP) or energy performance bias (EPB), 218 * when policy switched to performance 219 * @epp_policy: Last saved policy used to set EPP/EPB 220 * @epp_default: Power on default HWP energy performance 221 * preference/bias 222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline 223 * operation 224 * @hwp_req_cached: Cached value of the last HWP Request MSR 225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 226 * @last_io_update: Last time when IO wake flag was set 227 * @sched_flags: Store scheduler flags for possible cross CPU update 228 * @hwp_boost_min: Last HWP boosted min performance 229 * 230 * This structure stores per CPU instance data for all CPUs. 231 */ 232 struct cpudata { 233 int cpu; 234 235 unsigned int policy; 236 struct update_util_data update_util; 237 bool update_util_set; 238 239 struct pstate_data pstate; 240 struct vid_data vid; 241 242 u64 last_update; 243 u64 last_sample_time; 244 u64 aperf_mperf_shift; 245 u64 prev_aperf; 246 u64 prev_mperf; 247 u64 prev_tsc; 248 u64 prev_cummulative_iowait; 249 struct sample sample; 250 int32_t min_perf_ratio; 251 int32_t max_perf_ratio; 252 #ifdef CONFIG_ACPI 253 struct acpi_processor_performance acpi_perf_data; 254 bool valid_pss_table; 255 #endif 256 unsigned int iowait_boost; 257 s16 epp_powersave; 258 s16 epp_policy; 259 s16 epp_default; 260 s16 epp_saved; 261 u64 hwp_req_cached; 262 u64 hwp_cap_cached; 263 u64 last_io_update; 264 unsigned int sched_flags; 265 u32 hwp_boost_min; 266 }; 267 268 static struct cpudata **all_cpu_data; 269 270 /** 271 * struct pstate_funcs - Per CPU model specific callbacks 272 * @get_max: Callback to get maximum non turbo effective P state 273 * @get_max_physical: Callback to get maximum non turbo physical P state 274 * @get_min: Callback to get minimum P state 275 * @get_turbo: Callback to get turbo P state 276 * @get_scaling: Callback to get frequency scaling factor 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(void); 285 int (*get_max_physical)(void); 286 int (*get_min)(void); 287 int (*get_turbo)(void); 288 int (*get_scaling)(void); 289 int (*get_aperf_mperf_shift)(void); 290 u64 (*get_val)(struct cpudata*, int pstate); 291 void (*get_vid)(struct cpudata *); 292 }; 293 294 static struct pstate_funcs pstate_funcs __read_mostly; 295 296 static int hwp_active __read_mostly; 297 static int hwp_mode_bdw __read_mostly; 298 static bool per_cpu_limits __read_mostly; 299 static bool hwp_boost __read_mostly; 300 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 302 303 #ifdef CONFIG_ACPI 304 static bool acpi_ppc; 305 #endif 306 307 static struct global_params global; 308 309 static DEFINE_MUTEX(intel_pstate_driver_lock); 310 static DEFINE_MUTEX(intel_pstate_limits_lock); 311 312 #ifdef CONFIG_ACPI 313 314 static bool intel_pstate_acpi_pm_profile_server(void) 315 { 316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 318 return true; 319 320 return false; 321 } 322 323 static bool intel_pstate_get_ppc_enable_status(void) 324 { 325 if (intel_pstate_acpi_pm_profile_server()) 326 return true; 327 328 return acpi_ppc; 329 } 330 331 #ifdef CONFIG_ACPI_CPPC_LIB 332 333 /* The work item is needed to avoid CPU hotplug locking issues */ 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 335 { 336 sched_set_itmt_support(); 337 } 338 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 340 341 static void intel_pstate_set_itmt_prio(int cpu) 342 { 343 struct cppc_perf_caps cppc_perf; 344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 345 int ret; 346 347 ret = cppc_get_perf_caps(cpu, &cppc_perf); 348 if (ret) 349 return; 350 351 /* 352 * The priorities can be set regardless of whether or not 353 * sched_set_itmt_support(true) has been called and it is valid to 354 * update them at any time after it has been called. 355 */ 356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 357 358 if (max_highest_perf <= min_highest_perf) { 359 if (cppc_perf.highest_perf > max_highest_perf) 360 max_highest_perf = cppc_perf.highest_perf; 361 362 if (cppc_perf.highest_perf < min_highest_perf) 363 min_highest_perf = cppc_perf.highest_perf; 364 365 if (max_highest_perf > min_highest_perf) { 366 /* 367 * This code can be run during CPU online under the 368 * CPU hotplug locks, so sched_set_itmt_support() 369 * cannot be called from here. Queue up a work item 370 * to invoke it. 371 */ 372 schedule_work(&sched_itmt_work); 373 } 374 } 375 } 376 #else 377 static void intel_pstate_set_itmt_prio(int cpu) 378 { 379 } 380 #endif 381 382 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 383 { 384 struct cpudata *cpu; 385 int ret; 386 int i; 387 388 if (hwp_active) { 389 intel_pstate_set_itmt_prio(policy->cpu); 390 return; 391 } 392 393 if (!intel_pstate_get_ppc_enable_status()) 394 return; 395 396 cpu = all_cpu_data[policy->cpu]; 397 398 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 399 policy->cpu); 400 if (ret) 401 return; 402 403 /* 404 * Check if the control value in _PSS is for PERF_CTL MSR, which should 405 * guarantee that the states returned by it map to the states in our 406 * list directly. 407 */ 408 if (cpu->acpi_perf_data.control_register.space_id != 409 ACPI_ADR_SPACE_FIXED_HARDWARE) 410 goto err; 411 412 /* 413 * If there is only one entry _PSS, simply ignore _PSS and continue as 414 * usual without taking _PSS into account 415 */ 416 if (cpu->acpi_perf_data.state_count < 2) 417 goto err; 418 419 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 420 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 421 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 422 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 423 (u32) cpu->acpi_perf_data.states[i].core_frequency, 424 (u32) cpu->acpi_perf_data.states[i].power, 425 (u32) cpu->acpi_perf_data.states[i].control); 426 } 427 428 /* 429 * The _PSS table doesn't contain whole turbo frequency range. 430 * This just contains +1 MHZ above the max non turbo frequency, 431 * with control value corresponding to max turbo ratio. But 432 * when cpufreq set policy is called, it will call with this 433 * max frequency, which will cause a reduced performance as 434 * this driver uses real max turbo frequency as the max 435 * frequency. So correct this frequency in _PSS table to 436 * correct max turbo frequency based on the turbo state. 437 * Also need to convert to MHz as _PSS freq is in MHz. 438 */ 439 if (!global.turbo_disabled) 440 cpu->acpi_perf_data.states[0].core_frequency = 441 policy->cpuinfo.max_freq / 1000; 442 cpu->valid_pss_table = true; 443 pr_debug("_PPC limits will be enforced\n"); 444 445 return; 446 447 err: 448 cpu->valid_pss_table = false; 449 acpi_processor_unregister_performance(policy->cpu); 450 } 451 452 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 453 { 454 struct cpudata *cpu; 455 456 cpu = all_cpu_data[policy->cpu]; 457 if (!cpu->valid_pss_table) 458 return; 459 460 acpi_processor_unregister_performance(policy->cpu); 461 } 462 #else 463 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 464 { 465 } 466 467 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 468 { 469 } 470 471 static inline bool intel_pstate_acpi_pm_profile_server(void) 472 { 473 return false; 474 } 475 #endif 476 477 static inline void update_turbo_state(void) 478 { 479 u64 misc_en; 480 struct cpudata *cpu; 481 482 cpu = all_cpu_data[0]; 483 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 484 global.turbo_disabled = 485 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 486 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 487 } 488 489 static int min_perf_pct_min(void) 490 { 491 struct cpudata *cpu = all_cpu_data[0]; 492 int turbo_pstate = cpu->pstate.turbo_pstate; 493 494 return turbo_pstate ? 495 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 496 } 497 498 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 499 { 500 u64 epb; 501 int ret; 502 503 if (!static_cpu_has(X86_FEATURE_EPB)) 504 return -ENXIO; 505 506 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 507 if (ret) 508 return (s16)ret; 509 510 return (s16)(epb & 0x0f); 511 } 512 513 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 514 { 515 s16 epp; 516 517 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 518 /* 519 * When hwp_req_data is 0, means that caller didn't read 520 * MSR_HWP_REQUEST, so need to read and get EPP. 521 */ 522 if (!hwp_req_data) { 523 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 524 &hwp_req_data); 525 if (epp) 526 return epp; 527 } 528 epp = (hwp_req_data >> 24) & 0xff; 529 } else { 530 /* When there is no EPP present, HWP uses EPB settings */ 531 epp = intel_pstate_get_epb(cpu_data); 532 } 533 534 return epp; 535 } 536 537 static int intel_pstate_set_epb(int cpu, s16 pref) 538 { 539 u64 epb; 540 int ret; 541 542 if (!static_cpu_has(X86_FEATURE_EPB)) 543 return -ENXIO; 544 545 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 546 if (ret) 547 return ret; 548 549 epb = (epb & ~0x0f) | pref; 550 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 551 552 return 0; 553 } 554 555 /* 556 * EPP/EPB display strings corresponding to EPP index in the 557 * energy_perf_strings[] 558 * index String 559 *------------------------------------- 560 * 0 default 561 * 1 performance 562 * 2 balance_performance 563 * 3 balance_power 564 * 4 power 565 */ 566 static const char * const energy_perf_strings[] = { 567 "default", 568 "performance", 569 "balance_performance", 570 "balance_power", 571 "power", 572 NULL 573 }; 574 static const unsigned int epp_values[] = { 575 HWP_EPP_PERFORMANCE, 576 HWP_EPP_BALANCE_PERFORMANCE, 577 HWP_EPP_BALANCE_POWERSAVE, 578 HWP_EPP_POWERSAVE 579 }; 580 581 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) 582 { 583 s16 epp; 584 int index = -EINVAL; 585 586 epp = intel_pstate_get_epp(cpu_data, 0); 587 if (epp < 0) 588 return epp; 589 590 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 591 if (epp == HWP_EPP_PERFORMANCE) 592 return 1; 593 if (epp <= HWP_EPP_BALANCE_PERFORMANCE) 594 return 2; 595 if (epp <= HWP_EPP_BALANCE_POWERSAVE) 596 return 3; 597 else 598 return 4; 599 } else if (static_cpu_has(X86_FEATURE_EPB)) { 600 /* 601 * Range: 602 * 0x00-0x03 : Performance 603 * 0x04-0x07 : Balance performance 604 * 0x08-0x0B : Balance power 605 * 0x0C-0x0F : Power 606 * The EPB is a 4 bit value, but our ranges restrict the 607 * value which can be set. Here only using top two bits 608 * effectively. 609 */ 610 index = (epp >> 2) + 1; 611 } 612 613 return index; 614 } 615 616 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 617 int pref_index) 618 { 619 int epp = -EINVAL; 620 int ret; 621 622 if (!pref_index) 623 epp = cpu_data->epp_default; 624 625 mutex_lock(&intel_pstate_limits_lock); 626 627 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 628 u64 value; 629 630 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); 631 if (ret) 632 goto return_pref; 633 634 value &= ~GENMASK_ULL(31, 24); 635 636 if (epp == -EINVAL) 637 epp = epp_values[pref_index - 1]; 638 639 value |= (u64)epp << 24; 640 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); 641 } else { 642 if (epp == -EINVAL) 643 epp = (pref_index - 1) << 2; 644 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 645 } 646 return_pref: 647 mutex_unlock(&intel_pstate_limits_lock); 648 649 return ret; 650 } 651 652 static ssize_t show_energy_performance_available_preferences( 653 struct cpufreq_policy *policy, char *buf) 654 { 655 int i = 0; 656 int ret = 0; 657 658 while (energy_perf_strings[i] != NULL) 659 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 660 661 ret += sprintf(&buf[ret], "\n"); 662 663 return ret; 664 } 665 666 cpufreq_freq_attr_ro(energy_performance_available_preferences); 667 668 static ssize_t store_energy_performance_preference( 669 struct cpufreq_policy *policy, const char *buf, size_t count) 670 { 671 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 672 char str_preference[21]; 673 int ret; 674 675 ret = sscanf(buf, "%20s", str_preference); 676 if (ret != 1) 677 return -EINVAL; 678 679 ret = match_string(energy_perf_strings, -1, str_preference); 680 if (ret < 0) 681 return ret; 682 683 intel_pstate_set_energy_pref_index(cpu_data, ret); 684 return count; 685 } 686 687 static ssize_t show_energy_performance_preference( 688 struct cpufreq_policy *policy, char *buf) 689 { 690 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 691 int preference; 692 693 preference = intel_pstate_get_energy_pref_index(cpu_data); 694 if (preference < 0) 695 return preference; 696 697 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 698 } 699 700 cpufreq_freq_attr_rw(energy_performance_preference); 701 702 static struct freq_attr *hwp_cpufreq_attrs[] = { 703 &energy_performance_preference, 704 &energy_performance_available_preferences, 705 NULL, 706 }; 707 708 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, 709 int *current_max) 710 { 711 u64 cap; 712 713 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 714 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap); 715 if (global.no_turbo) 716 *current_max = HWP_GUARANTEED_PERF(cap); 717 else 718 *current_max = HWP_HIGHEST_PERF(cap); 719 720 *phy_max = HWP_HIGHEST_PERF(cap); 721 } 722 723 static void intel_pstate_hwp_set(unsigned int cpu) 724 { 725 struct cpudata *cpu_data = all_cpu_data[cpu]; 726 int max, min; 727 u64 value; 728 s16 epp; 729 730 max = cpu_data->max_perf_ratio; 731 min = cpu_data->min_perf_ratio; 732 733 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 734 min = max; 735 736 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 737 738 value &= ~HWP_MIN_PERF(~0L); 739 value |= HWP_MIN_PERF(min); 740 741 value &= ~HWP_MAX_PERF(~0L); 742 value |= HWP_MAX_PERF(max); 743 744 if (cpu_data->epp_policy == cpu_data->policy) 745 goto skip_epp; 746 747 cpu_data->epp_policy = cpu_data->policy; 748 749 if (cpu_data->epp_saved >= 0) { 750 epp = cpu_data->epp_saved; 751 cpu_data->epp_saved = -EINVAL; 752 goto update_epp; 753 } 754 755 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 756 epp = intel_pstate_get_epp(cpu_data, value); 757 cpu_data->epp_powersave = epp; 758 /* If EPP read was failed, then don't try to write */ 759 if (epp < 0) 760 goto skip_epp; 761 762 epp = 0; 763 } else { 764 /* skip setting EPP, when saved value is invalid */ 765 if (cpu_data->epp_powersave < 0) 766 goto skip_epp; 767 768 /* 769 * No need to restore EPP when it is not zero. This 770 * means: 771 * - Policy is not changed 772 * - user has manually changed 773 * - Error reading EPB 774 */ 775 epp = intel_pstate_get_epp(cpu_data, value); 776 if (epp) 777 goto skip_epp; 778 779 epp = cpu_data->epp_powersave; 780 } 781 update_epp: 782 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 783 value &= ~GENMASK_ULL(31, 24); 784 value |= (u64)epp << 24; 785 } else { 786 intel_pstate_set_epb(cpu, epp); 787 } 788 skip_epp: 789 WRITE_ONCE(cpu_data->hwp_req_cached, value); 790 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 791 } 792 793 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) 794 { 795 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 796 797 if (!hwp_active) 798 return 0; 799 800 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); 801 802 return 0; 803 } 804 805 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 806 807 static int intel_pstate_resume(struct cpufreq_policy *policy) 808 { 809 if (!hwp_active) 810 return 0; 811 812 mutex_lock(&intel_pstate_limits_lock); 813 814 if (policy->cpu == 0) 815 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]); 816 817 all_cpu_data[policy->cpu]->epp_policy = 0; 818 intel_pstate_hwp_set(policy->cpu); 819 820 mutex_unlock(&intel_pstate_limits_lock); 821 822 return 0; 823 } 824 825 static void intel_pstate_update_policies(void) 826 { 827 int cpu; 828 829 for_each_possible_cpu(cpu) 830 cpufreq_update_policy(cpu); 831 } 832 833 /************************** sysfs begin ************************/ 834 #define show_one(file_name, object) \ 835 static ssize_t show_##file_name \ 836 (struct kobject *kobj, struct attribute *attr, char *buf) \ 837 { \ 838 return sprintf(buf, "%u\n", global.object); \ 839 } 840 841 static ssize_t intel_pstate_show_status(char *buf); 842 static int intel_pstate_update_status(const char *buf, size_t size); 843 844 static ssize_t show_status(struct kobject *kobj, 845 struct attribute *attr, char *buf) 846 { 847 ssize_t ret; 848 849 mutex_lock(&intel_pstate_driver_lock); 850 ret = intel_pstate_show_status(buf); 851 mutex_unlock(&intel_pstate_driver_lock); 852 853 return ret; 854 } 855 856 static ssize_t store_status(struct kobject *a, struct attribute *b, 857 const char *buf, size_t count) 858 { 859 char *p = memchr(buf, '\n', count); 860 int ret; 861 862 mutex_lock(&intel_pstate_driver_lock); 863 ret = intel_pstate_update_status(buf, p ? p - buf : count); 864 mutex_unlock(&intel_pstate_driver_lock); 865 866 return ret < 0 ? ret : count; 867 } 868 869 static ssize_t show_turbo_pct(struct kobject *kobj, 870 struct attribute *attr, char *buf) 871 { 872 struct cpudata *cpu; 873 int total, no_turbo, turbo_pct; 874 uint32_t turbo_fp; 875 876 mutex_lock(&intel_pstate_driver_lock); 877 878 if (!intel_pstate_driver) { 879 mutex_unlock(&intel_pstate_driver_lock); 880 return -EAGAIN; 881 } 882 883 cpu = all_cpu_data[0]; 884 885 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 886 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 887 turbo_fp = div_fp(no_turbo, total); 888 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 889 890 mutex_unlock(&intel_pstate_driver_lock); 891 892 return sprintf(buf, "%u\n", turbo_pct); 893 } 894 895 static ssize_t show_num_pstates(struct kobject *kobj, 896 struct attribute *attr, char *buf) 897 { 898 struct cpudata *cpu; 899 int total; 900 901 mutex_lock(&intel_pstate_driver_lock); 902 903 if (!intel_pstate_driver) { 904 mutex_unlock(&intel_pstate_driver_lock); 905 return -EAGAIN; 906 } 907 908 cpu = all_cpu_data[0]; 909 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 910 911 mutex_unlock(&intel_pstate_driver_lock); 912 913 return sprintf(buf, "%u\n", total); 914 } 915 916 static ssize_t show_no_turbo(struct kobject *kobj, 917 struct attribute *attr, char *buf) 918 { 919 ssize_t ret; 920 921 mutex_lock(&intel_pstate_driver_lock); 922 923 if (!intel_pstate_driver) { 924 mutex_unlock(&intel_pstate_driver_lock); 925 return -EAGAIN; 926 } 927 928 update_turbo_state(); 929 if (global.turbo_disabled) 930 ret = sprintf(buf, "%u\n", global.turbo_disabled); 931 else 932 ret = sprintf(buf, "%u\n", global.no_turbo); 933 934 mutex_unlock(&intel_pstate_driver_lock); 935 936 return ret; 937 } 938 939 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 940 const char *buf, size_t count) 941 { 942 unsigned int input; 943 int ret; 944 945 ret = sscanf(buf, "%u", &input); 946 if (ret != 1) 947 return -EINVAL; 948 949 mutex_lock(&intel_pstate_driver_lock); 950 951 if (!intel_pstate_driver) { 952 mutex_unlock(&intel_pstate_driver_lock); 953 return -EAGAIN; 954 } 955 956 mutex_lock(&intel_pstate_limits_lock); 957 958 update_turbo_state(); 959 if (global.turbo_disabled) { 960 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 961 mutex_unlock(&intel_pstate_limits_lock); 962 mutex_unlock(&intel_pstate_driver_lock); 963 return -EPERM; 964 } 965 966 global.no_turbo = clamp_t(int, input, 0, 1); 967 968 if (global.no_turbo) { 969 struct cpudata *cpu = all_cpu_data[0]; 970 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 971 972 /* Squash the global minimum into the permitted range. */ 973 if (global.min_perf_pct > pct) 974 global.min_perf_pct = pct; 975 } 976 977 mutex_unlock(&intel_pstate_limits_lock); 978 979 intel_pstate_update_policies(); 980 981 mutex_unlock(&intel_pstate_driver_lock); 982 983 return count; 984 } 985 986 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 987 const char *buf, size_t count) 988 { 989 unsigned int input; 990 int ret; 991 992 ret = sscanf(buf, "%u", &input); 993 if (ret != 1) 994 return -EINVAL; 995 996 mutex_lock(&intel_pstate_driver_lock); 997 998 if (!intel_pstate_driver) { 999 mutex_unlock(&intel_pstate_driver_lock); 1000 return -EAGAIN; 1001 } 1002 1003 mutex_lock(&intel_pstate_limits_lock); 1004 1005 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1006 1007 mutex_unlock(&intel_pstate_limits_lock); 1008 1009 intel_pstate_update_policies(); 1010 1011 mutex_unlock(&intel_pstate_driver_lock); 1012 1013 return count; 1014 } 1015 1016 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 1017 const char *buf, size_t count) 1018 { 1019 unsigned int input; 1020 int ret; 1021 1022 ret = sscanf(buf, "%u", &input); 1023 if (ret != 1) 1024 return -EINVAL; 1025 1026 mutex_lock(&intel_pstate_driver_lock); 1027 1028 if (!intel_pstate_driver) { 1029 mutex_unlock(&intel_pstate_driver_lock); 1030 return -EAGAIN; 1031 } 1032 1033 mutex_lock(&intel_pstate_limits_lock); 1034 1035 global.min_perf_pct = clamp_t(int, input, 1036 min_perf_pct_min(), global.max_perf_pct); 1037 1038 mutex_unlock(&intel_pstate_limits_lock); 1039 1040 intel_pstate_update_policies(); 1041 1042 mutex_unlock(&intel_pstate_driver_lock); 1043 1044 return count; 1045 } 1046 1047 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1048 struct attribute *attr, char *buf) 1049 { 1050 return sprintf(buf, "%u\n", hwp_boost); 1051 } 1052 1053 static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b, 1054 const char *buf, size_t count) 1055 { 1056 unsigned int input; 1057 int ret; 1058 1059 ret = kstrtouint(buf, 10, &input); 1060 if (ret) 1061 return ret; 1062 1063 mutex_lock(&intel_pstate_driver_lock); 1064 hwp_boost = !!input; 1065 intel_pstate_update_policies(); 1066 mutex_unlock(&intel_pstate_driver_lock); 1067 1068 return count; 1069 } 1070 1071 show_one(max_perf_pct, max_perf_pct); 1072 show_one(min_perf_pct, min_perf_pct); 1073 1074 define_one_global_rw(status); 1075 define_one_global_rw(no_turbo); 1076 define_one_global_rw(max_perf_pct); 1077 define_one_global_rw(min_perf_pct); 1078 define_one_global_ro(turbo_pct); 1079 define_one_global_ro(num_pstates); 1080 define_one_global_rw(hwp_dynamic_boost); 1081 1082 static struct attribute *intel_pstate_attributes[] = { 1083 &status.attr, 1084 &no_turbo.attr, 1085 &turbo_pct.attr, 1086 &num_pstates.attr, 1087 NULL 1088 }; 1089 1090 static const struct attribute_group intel_pstate_attr_group = { 1091 .attrs = intel_pstate_attributes, 1092 }; 1093 1094 static void __init intel_pstate_sysfs_expose_params(void) 1095 { 1096 struct kobject *intel_pstate_kobject; 1097 int rc; 1098 1099 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1100 &cpu_subsys.dev_root->kobj); 1101 if (WARN_ON(!intel_pstate_kobject)) 1102 return; 1103 1104 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1105 if (WARN_ON(rc)) 1106 return; 1107 1108 /* 1109 * If per cpu limits are enforced there are no global limits, so 1110 * return without creating max/min_perf_pct attributes 1111 */ 1112 if (per_cpu_limits) 1113 return; 1114 1115 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1116 WARN_ON(rc); 1117 1118 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1119 WARN_ON(rc); 1120 1121 if (hwp_active) { 1122 rc = sysfs_create_file(intel_pstate_kobject, 1123 &hwp_dynamic_boost.attr); 1124 WARN_ON(rc); 1125 } 1126 } 1127 /************************** sysfs end ************************/ 1128 1129 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1130 { 1131 /* First disable HWP notification interrupt as we don't process them */ 1132 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1133 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1134 1135 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1136 cpudata->epp_policy = 0; 1137 if (cpudata->epp_default == -EINVAL) 1138 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1139 } 1140 1141 #define MSR_IA32_POWER_CTL_BIT_EE 19 1142 1143 /* Disable energy efficiency optimization */ 1144 static void intel_pstate_disable_ee(int cpu) 1145 { 1146 u64 power_ctl; 1147 int ret; 1148 1149 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); 1150 if (ret) 1151 return; 1152 1153 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { 1154 pr_info("Disabling energy efficiency optimization\n"); 1155 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1156 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); 1157 } 1158 } 1159 1160 static int atom_get_min_pstate(void) 1161 { 1162 u64 value; 1163 1164 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1165 return (value >> 8) & 0x7F; 1166 } 1167 1168 static int atom_get_max_pstate(void) 1169 { 1170 u64 value; 1171 1172 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1173 return (value >> 16) & 0x7F; 1174 } 1175 1176 static int atom_get_turbo_pstate(void) 1177 { 1178 u64 value; 1179 1180 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1181 return value & 0x7F; 1182 } 1183 1184 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1185 { 1186 u64 val; 1187 int32_t vid_fp; 1188 u32 vid; 1189 1190 val = (u64)pstate << 8; 1191 if (global.no_turbo && !global.turbo_disabled) 1192 val |= (u64)1 << 32; 1193 1194 vid_fp = cpudata->vid.min + mul_fp( 1195 int_tofp(pstate - cpudata->pstate.min_pstate), 1196 cpudata->vid.ratio); 1197 1198 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1199 vid = ceiling_fp(vid_fp); 1200 1201 if (pstate > cpudata->pstate.max_pstate) 1202 vid = cpudata->vid.turbo; 1203 1204 return val | vid; 1205 } 1206 1207 static int silvermont_get_scaling(void) 1208 { 1209 u64 value; 1210 int i; 1211 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1212 static int silvermont_freq_table[] = { 1213 83300, 100000, 133300, 116700, 80000}; 1214 1215 rdmsrl(MSR_FSB_FREQ, value); 1216 i = value & 0x7; 1217 WARN_ON(i > 4); 1218 1219 return silvermont_freq_table[i]; 1220 } 1221 1222 static int airmont_get_scaling(void) 1223 { 1224 u64 value; 1225 int i; 1226 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1227 static int airmont_freq_table[] = { 1228 83300, 100000, 133300, 116700, 80000, 1229 93300, 90000, 88900, 87500}; 1230 1231 rdmsrl(MSR_FSB_FREQ, value); 1232 i = value & 0xF; 1233 WARN_ON(i > 8); 1234 1235 return airmont_freq_table[i]; 1236 } 1237 1238 static void atom_get_vid(struct cpudata *cpudata) 1239 { 1240 u64 value; 1241 1242 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1243 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1244 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1245 cpudata->vid.ratio = div_fp( 1246 cpudata->vid.max - cpudata->vid.min, 1247 int_tofp(cpudata->pstate.max_pstate - 1248 cpudata->pstate.min_pstate)); 1249 1250 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1251 cpudata->vid.turbo = value & 0x7f; 1252 } 1253 1254 static int core_get_min_pstate(void) 1255 { 1256 u64 value; 1257 1258 rdmsrl(MSR_PLATFORM_INFO, value); 1259 return (value >> 40) & 0xFF; 1260 } 1261 1262 static int core_get_max_pstate_physical(void) 1263 { 1264 u64 value; 1265 1266 rdmsrl(MSR_PLATFORM_INFO, value); 1267 return (value >> 8) & 0xFF; 1268 } 1269 1270 static int core_get_tdp_ratio(u64 plat_info) 1271 { 1272 /* Check how many TDP levels present */ 1273 if (plat_info & 0x600000000) { 1274 u64 tdp_ctrl; 1275 u64 tdp_ratio; 1276 int tdp_msr; 1277 int err; 1278 1279 /* Get the TDP level (0, 1, 2) to get ratios */ 1280 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1281 if (err) 1282 return err; 1283 1284 /* TDP MSR are continuous starting at 0x648 */ 1285 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1286 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1287 if (err) 1288 return err; 1289 1290 /* For level 1 and 2, bits[23:16] contain the ratio */ 1291 if (tdp_ctrl & 0x03) 1292 tdp_ratio >>= 16; 1293 1294 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1295 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1296 1297 return (int)tdp_ratio; 1298 } 1299 1300 return -ENXIO; 1301 } 1302 1303 static int core_get_max_pstate(void) 1304 { 1305 u64 tar; 1306 u64 plat_info; 1307 int max_pstate; 1308 int tdp_ratio; 1309 int err; 1310 1311 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1312 max_pstate = (plat_info >> 8) & 0xFF; 1313 1314 tdp_ratio = core_get_tdp_ratio(plat_info); 1315 if (tdp_ratio <= 0) 1316 return max_pstate; 1317 1318 if (hwp_active) { 1319 /* Turbo activation ratio is not used on HWP platforms */ 1320 return tdp_ratio; 1321 } 1322 1323 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1324 if (!err) { 1325 int tar_levels; 1326 1327 /* Do some sanity checking for safety */ 1328 tar_levels = tar & 0xff; 1329 if (tdp_ratio - 1 == tar_levels) { 1330 max_pstate = tar_levels; 1331 pr_debug("max_pstate=TAC %x\n", max_pstate); 1332 } 1333 } 1334 1335 return max_pstate; 1336 } 1337 1338 static int core_get_turbo_pstate(void) 1339 { 1340 u64 value; 1341 int nont, ret; 1342 1343 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1344 nont = core_get_max_pstate(); 1345 ret = (value) & 255; 1346 if (ret <= nont) 1347 ret = nont; 1348 return ret; 1349 } 1350 1351 static inline int core_get_scaling(void) 1352 { 1353 return 100000; 1354 } 1355 1356 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1357 { 1358 u64 val; 1359 1360 val = (u64)pstate << 8; 1361 if (global.no_turbo && !global.turbo_disabled) 1362 val |= (u64)1 << 32; 1363 1364 return val; 1365 } 1366 1367 static int knl_get_aperf_mperf_shift(void) 1368 { 1369 return 10; 1370 } 1371 1372 static int knl_get_turbo_pstate(void) 1373 { 1374 u64 value; 1375 int nont, ret; 1376 1377 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1378 nont = core_get_max_pstate(); 1379 ret = (((value) >> 8) & 0xFF); 1380 if (ret <= nont) 1381 ret = nont; 1382 return ret; 1383 } 1384 1385 static int intel_pstate_get_base_pstate(struct cpudata *cpu) 1386 { 1387 return global.no_turbo || global.turbo_disabled ? 1388 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1389 } 1390 1391 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1392 { 1393 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1394 cpu->pstate.current_pstate = pstate; 1395 /* 1396 * Generally, there is no guarantee that this code will always run on 1397 * the CPU being updated, so force the register update to run on the 1398 * right CPU. 1399 */ 1400 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1401 pstate_funcs.get_val(cpu, pstate)); 1402 } 1403 1404 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1405 { 1406 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1407 } 1408 1409 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1410 { 1411 int pstate; 1412 1413 update_turbo_state(); 1414 pstate = intel_pstate_get_base_pstate(cpu); 1415 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1416 intel_pstate_set_pstate(cpu, pstate); 1417 } 1418 1419 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1420 { 1421 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1422 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1423 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1424 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1425 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1426 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; 1427 1428 if (hwp_active && !hwp_mode_bdw) { 1429 unsigned int phy_max, current_max; 1430 1431 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max); 1432 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling; 1433 } else { 1434 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1435 } 1436 1437 if (pstate_funcs.get_aperf_mperf_shift) 1438 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 1439 1440 if (pstate_funcs.get_vid) 1441 pstate_funcs.get_vid(cpu); 1442 1443 intel_pstate_set_min_pstate(cpu); 1444 } 1445 1446 /* 1447 * Long hold time will keep high perf limits for long time, 1448 * which negatively impacts perf/watt for some workloads, 1449 * like specpower. 3ms is based on experiements on some 1450 * workoads. 1451 */ 1452 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 1453 1454 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 1455 { 1456 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 1457 u32 max_limit = (hwp_req & 0xff00) >> 8; 1458 u32 min_limit = (hwp_req & 0xff); 1459 u32 boost_level1; 1460 1461 /* 1462 * Cases to consider (User changes via sysfs or boot time): 1463 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 1464 * No boost, return. 1465 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 1466 * Should result in one level boost only for P0. 1467 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 1468 * Should result in two level boost: 1469 * (min + p1)/2 and P1. 1470 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 1471 * Should result in three level boost: 1472 * (min + p1)/2, P1 and P0. 1473 */ 1474 1475 /* If max and min are equal or already at max, nothing to boost */ 1476 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 1477 return; 1478 1479 if (!cpu->hwp_boost_min) 1480 cpu->hwp_boost_min = min_limit; 1481 1482 /* level at half way mark between min and guranteed */ 1483 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1; 1484 1485 if (cpu->hwp_boost_min < boost_level1) 1486 cpu->hwp_boost_min = boost_level1; 1487 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1488 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached); 1489 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) && 1490 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1491 cpu->hwp_boost_min = max_limit; 1492 else 1493 return; 1494 1495 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 1496 wrmsrl(MSR_HWP_REQUEST, hwp_req); 1497 cpu->last_update = cpu->sample.time; 1498 } 1499 1500 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 1501 { 1502 if (cpu->hwp_boost_min) { 1503 bool expired; 1504 1505 /* Check if we are idle for hold time to boost down */ 1506 expired = time_after64(cpu->sample.time, cpu->last_update + 1507 hwp_boost_hold_time_ns); 1508 if (expired) { 1509 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 1510 cpu->hwp_boost_min = 0; 1511 } 1512 } 1513 cpu->last_update = cpu->sample.time; 1514 } 1515 1516 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 1517 u64 time) 1518 { 1519 cpu->sample.time = time; 1520 1521 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 1522 bool do_io = false; 1523 1524 cpu->sched_flags = 0; 1525 /* 1526 * Set iowait_boost flag and update time. Since IO WAIT flag 1527 * is set all the time, we can't just conclude that there is 1528 * some IO bound activity is scheduled on this CPU with just 1529 * one occurrence. If we receive at least two in two 1530 * consecutive ticks, then we treat as boost candidate. 1531 */ 1532 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 1533 do_io = true; 1534 1535 cpu->last_io_update = time; 1536 1537 if (do_io) 1538 intel_pstate_hwp_boost_up(cpu); 1539 1540 } else { 1541 intel_pstate_hwp_boost_down(cpu); 1542 } 1543 } 1544 1545 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 1546 u64 time, unsigned int flags) 1547 { 1548 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1549 1550 cpu->sched_flags |= flags; 1551 1552 if (smp_processor_id() == cpu->cpu) 1553 intel_pstate_update_util_hwp_local(cpu, time); 1554 } 1555 1556 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1557 { 1558 struct sample *sample = &cpu->sample; 1559 1560 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1561 } 1562 1563 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1564 { 1565 u64 aperf, mperf; 1566 unsigned long flags; 1567 u64 tsc; 1568 1569 local_irq_save(flags); 1570 rdmsrl(MSR_IA32_APERF, aperf); 1571 rdmsrl(MSR_IA32_MPERF, mperf); 1572 tsc = rdtsc(); 1573 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1574 local_irq_restore(flags); 1575 return false; 1576 } 1577 local_irq_restore(flags); 1578 1579 cpu->last_sample_time = cpu->sample.time; 1580 cpu->sample.time = time; 1581 cpu->sample.aperf = aperf; 1582 cpu->sample.mperf = mperf; 1583 cpu->sample.tsc = tsc; 1584 cpu->sample.aperf -= cpu->prev_aperf; 1585 cpu->sample.mperf -= cpu->prev_mperf; 1586 cpu->sample.tsc -= cpu->prev_tsc; 1587 1588 cpu->prev_aperf = aperf; 1589 cpu->prev_mperf = mperf; 1590 cpu->prev_tsc = tsc; 1591 /* 1592 * First time this function is invoked in a given cycle, all of the 1593 * previous sample data fields are equal to zero or stale and they must 1594 * be populated with meaningful numbers for things to work, so assume 1595 * that sample.time will always be reset before setting the utilization 1596 * update hook and make the caller skip the sample then. 1597 */ 1598 if (cpu->last_sample_time) { 1599 intel_pstate_calc_avg_perf(cpu); 1600 return true; 1601 } 1602 return false; 1603 } 1604 1605 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1606 { 1607 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 1608 } 1609 1610 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1611 { 1612 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1613 cpu->sample.core_avg_perf); 1614 } 1615 1616 static inline int32_t get_target_pstate(struct cpudata *cpu) 1617 { 1618 struct sample *sample = &cpu->sample; 1619 int32_t busy_frac, boost; 1620 int target, avg_pstate; 1621 1622 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 1623 sample->tsc); 1624 1625 boost = cpu->iowait_boost; 1626 cpu->iowait_boost >>= 1; 1627 1628 if (busy_frac < boost) 1629 busy_frac = boost; 1630 1631 sample->busy_scaled = busy_frac * 100; 1632 1633 target = global.no_turbo || global.turbo_disabled ? 1634 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1635 target += target >> 2; 1636 target = mul_fp(target, busy_frac); 1637 if (target < cpu->pstate.min_pstate) 1638 target = cpu->pstate.min_pstate; 1639 1640 /* 1641 * If the average P-state during the previous cycle was higher than the 1642 * current target, add 50% of the difference to the target to reduce 1643 * possible performance oscillations and offset possible performance 1644 * loss related to moving the workload from one CPU to another within 1645 * a package/module. 1646 */ 1647 avg_pstate = get_avg_pstate(cpu); 1648 if (avg_pstate > target) 1649 target += (avg_pstate - target) >> 1; 1650 1651 return target; 1652 } 1653 1654 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 1655 { 1656 int max_pstate = intel_pstate_get_base_pstate(cpu); 1657 int min_pstate; 1658 1659 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 1660 max_pstate = max(min_pstate, cpu->max_perf_ratio); 1661 return clamp_t(int, pstate, min_pstate, max_pstate); 1662 } 1663 1664 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1665 { 1666 if (pstate == cpu->pstate.current_pstate) 1667 return; 1668 1669 cpu->pstate.current_pstate = pstate; 1670 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1671 } 1672 1673 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 1674 { 1675 int from = cpu->pstate.current_pstate; 1676 struct sample *sample; 1677 int target_pstate; 1678 1679 update_turbo_state(); 1680 1681 target_pstate = get_target_pstate(cpu); 1682 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 1683 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 1684 intel_pstate_update_pstate(cpu, target_pstate); 1685 1686 sample = &cpu->sample; 1687 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1688 fp_toint(sample->busy_scaled), 1689 from, 1690 cpu->pstate.current_pstate, 1691 sample->mperf, 1692 sample->aperf, 1693 sample->tsc, 1694 get_avg_frequency(cpu), 1695 fp_toint(cpu->iowait_boost * 100)); 1696 } 1697 1698 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1699 unsigned int flags) 1700 { 1701 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1702 u64 delta_ns; 1703 1704 /* Don't allow remote callbacks */ 1705 if (smp_processor_id() != cpu->cpu) 1706 return; 1707 1708 if (flags & SCHED_CPUFREQ_IOWAIT) { 1709 cpu->iowait_boost = int_tofp(1); 1710 cpu->last_update = time; 1711 /* 1712 * The last time the busy was 100% so P-state was max anyway 1713 * so avoid overhead of computation. 1714 */ 1715 if (fp_toint(cpu->sample.busy_scaled) == 100) 1716 return; 1717 1718 goto set_pstate; 1719 } else if (cpu->iowait_boost) { 1720 /* Clear iowait_boost if the CPU may have been idle. */ 1721 delta_ns = time - cpu->last_update; 1722 if (delta_ns > TICK_NSEC) 1723 cpu->iowait_boost = 0; 1724 } 1725 cpu->last_update = time; 1726 delta_ns = time - cpu->sample.time; 1727 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 1728 return; 1729 1730 set_pstate: 1731 if (intel_pstate_sample(cpu, time)) 1732 intel_pstate_adjust_pstate(cpu); 1733 } 1734 1735 static struct pstate_funcs core_funcs = { 1736 .get_max = core_get_max_pstate, 1737 .get_max_physical = core_get_max_pstate_physical, 1738 .get_min = core_get_min_pstate, 1739 .get_turbo = core_get_turbo_pstate, 1740 .get_scaling = core_get_scaling, 1741 .get_val = core_get_val, 1742 }; 1743 1744 static const struct pstate_funcs silvermont_funcs = { 1745 .get_max = atom_get_max_pstate, 1746 .get_max_physical = atom_get_max_pstate, 1747 .get_min = atom_get_min_pstate, 1748 .get_turbo = atom_get_turbo_pstate, 1749 .get_val = atom_get_val, 1750 .get_scaling = silvermont_get_scaling, 1751 .get_vid = atom_get_vid, 1752 }; 1753 1754 static const struct pstate_funcs airmont_funcs = { 1755 .get_max = atom_get_max_pstate, 1756 .get_max_physical = atom_get_max_pstate, 1757 .get_min = atom_get_min_pstate, 1758 .get_turbo = atom_get_turbo_pstate, 1759 .get_val = atom_get_val, 1760 .get_scaling = airmont_get_scaling, 1761 .get_vid = atom_get_vid, 1762 }; 1763 1764 static const struct pstate_funcs knl_funcs = { 1765 .get_max = core_get_max_pstate, 1766 .get_max_physical = core_get_max_pstate_physical, 1767 .get_min = core_get_min_pstate, 1768 .get_turbo = knl_get_turbo_pstate, 1769 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 1770 .get_scaling = core_get_scaling, 1771 .get_val = core_get_val, 1772 }; 1773 1774 #define ICPU(model, policy) \ 1775 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1776 (unsigned long)&policy } 1777 1778 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1779 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs), 1780 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs), 1781 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs), 1782 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs), 1783 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs), 1784 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs), 1785 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs), 1786 ICPU(INTEL_FAM6_HASWELL_X, core_funcs), 1787 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs), 1788 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs), 1789 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs), 1790 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs), 1791 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs), 1792 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), 1793 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs), 1794 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), 1795 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs), 1796 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs), 1797 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs), 1798 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs), 1799 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), 1800 {} 1801 }; 1802 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1803 1804 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1805 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), 1806 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), 1807 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), 1808 {} 1809 }; 1810 1811 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 1812 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs), 1813 {} 1814 }; 1815 1816 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = { 1817 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), 1818 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs), 1819 {} 1820 }; 1821 1822 static int intel_pstate_init_cpu(unsigned int cpunum) 1823 { 1824 struct cpudata *cpu; 1825 1826 cpu = all_cpu_data[cpunum]; 1827 1828 if (!cpu) { 1829 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 1830 if (!cpu) 1831 return -ENOMEM; 1832 1833 all_cpu_data[cpunum] = cpu; 1834 1835 cpu->epp_default = -EINVAL; 1836 cpu->epp_powersave = -EINVAL; 1837 cpu->epp_saved = -EINVAL; 1838 } 1839 1840 cpu = all_cpu_data[cpunum]; 1841 1842 cpu->cpu = cpunum; 1843 1844 if (hwp_active) { 1845 const struct x86_cpu_id *id; 1846 1847 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 1848 if (id) 1849 intel_pstate_disable_ee(cpunum); 1850 1851 intel_pstate_hwp_enable(cpu); 1852 1853 id = x86_match_cpu(intel_pstate_hwp_boost_ids); 1854 if (id && intel_pstate_acpi_pm_profile_server()) 1855 hwp_boost = true; 1856 } 1857 1858 intel_pstate_get_cpu_pstates(cpu); 1859 1860 pr_debug("controlling: cpu %d\n", cpunum); 1861 1862 return 0; 1863 } 1864 1865 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1866 { 1867 struct cpudata *cpu = all_cpu_data[cpu_num]; 1868 1869 if (hwp_active && !hwp_boost) 1870 return; 1871 1872 if (cpu->update_util_set) 1873 return; 1874 1875 /* Prevent intel_pstate_update_util() from using stale data. */ 1876 cpu->sample.time = 0; 1877 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1878 (hwp_active ? 1879 intel_pstate_update_util_hwp : 1880 intel_pstate_update_util)); 1881 cpu->update_util_set = true; 1882 } 1883 1884 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1885 { 1886 struct cpudata *cpu_data = all_cpu_data[cpu]; 1887 1888 if (!cpu_data->update_util_set) 1889 return; 1890 1891 cpufreq_remove_update_util_hook(cpu); 1892 cpu_data->update_util_set = false; 1893 synchronize_sched(); 1894 } 1895 1896 static int intel_pstate_get_max_freq(struct cpudata *cpu) 1897 { 1898 return global.turbo_disabled || global.no_turbo ? 1899 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 1900 } 1901 1902 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, 1903 struct cpudata *cpu) 1904 { 1905 int max_freq = intel_pstate_get_max_freq(cpu); 1906 int32_t max_policy_perf, min_policy_perf; 1907 int max_state, turbo_max; 1908 1909 /* 1910 * HWP needs some special consideration, because on BDX the 1911 * HWP_REQUEST uses abstract value to represent performance 1912 * rather than pure ratios. 1913 */ 1914 if (hwp_active) { 1915 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state); 1916 } else { 1917 max_state = intel_pstate_get_base_pstate(cpu); 1918 turbo_max = cpu->pstate.turbo_pstate; 1919 } 1920 1921 max_policy_perf = max_state * policy->max / max_freq; 1922 if (policy->max == policy->min) { 1923 min_policy_perf = max_policy_perf; 1924 } else { 1925 min_policy_perf = max_state * policy->min / max_freq; 1926 min_policy_perf = clamp_t(int32_t, min_policy_perf, 1927 0, max_policy_perf); 1928 } 1929 1930 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n", 1931 policy->cpu, max_state, 1932 min_policy_perf, max_policy_perf); 1933 1934 /* Normalize user input to [min_perf, max_perf] */ 1935 if (per_cpu_limits) { 1936 cpu->min_perf_ratio = min_policy_perf; 1937 cpu->max_perf_ratio = max_policy_perf; 1938 } else { 1939 int32_t global_min, global_max; 1940 1941 /* Global limits are in percent of the maximum turbo P-state. */ 1942 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 1943 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 1944 global_min = clamp_t(int32_t, global_min, 0, global_max); 1945 1946 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu, 1947 global_min, global_max); 1948 1949 cpu->min_perf_ratio = max(min_policy_perf, global_min); 1950 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 1951 cpu->max_perf_ratio = min(max_policy_perf, global_max); 1952 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 1953 1954 /* Make sure min_perf <= max_perf */ 1955 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 1956 cpu->max_perf_ratio); 1957 1958 } 1959 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu, 1960 cpu->max_perf_ratio, 1961 cpu->min_perf_ratio); 1962 } 1963 1964 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1965 { 1966 struct cpudata *cpu; 1967 1968 if (!policy->cpuinfo.max_freq) 1969 return -ENODEV; 1970 1971 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 1972 policy->cpuinfo.max_freq, policy->max); 1973 1974 cpu = all_cpu_data[policy->cpu]; 1975 cpu->policy = policy->policy; 1976 1977 mutex_lock(&intel_pstate_limits_lock); 1978 1979 intel_pstate_update_perf_limits(policy, cpu); 1980 1981 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 1982 /* 1983 * NOHZ_FULL CPUs need this as the governor callback may not 1984 * be invoked on them. 1985 */ 1986 intel_pstate_clear_update_util_hook(policy->cpu); 1987 intel_pstate_max_within_limits(cpu); 1988 } else { 1989 intel_pstate_set_update_util_hook(policy->cpu); 1990 } 1991 1992 if (hwp_active) { 1993 /* 1994 * When hwp_boost was active before and dynamically it 1995 * was turned off, in that case we need to clear the 1996 * update util hook. 1997 */ 1998 if (!hwp_boost) 1999 intel_pstate_clear_update_util_hook(policy->cpu); 2000 intel_pstate_hwp_set(policy->cpu); 2001 } 2002 2003 mutex_unlock(&intel_pstate_limits_lock); 2004 2005 return 0; 2006 } 2007 2008 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy, 2009 struct cpudata *cpu) 2010 { 2011 if (!hwp_active && 2012 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2013 policy->max < policy->cpuinfo.max_freq && 2014 policy->max > cpu->pstate.max_freq) { 2015 pr_debug("policy->max > max non turbo frequency\n"); 2016 policy->max = policy->cpuinfo.max_freq; 2017 } 2018 } 2019 2020 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 2021 { 2022 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2023 2024 update_turbo_state(); 2025 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 2026 intel_pstate_get_max_freq(cpu)); 2027 2028 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 2029 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 2030 return -EINVAL; 2031 2032 intel_pstate_adjust_policy_max(policy, cpu); 2033 2034 return 0; 2035 } 2036 2037 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) 2038 { 2039 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); 2040 } 2041 2042 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 2043 { 2044 pr_debug("CPU %d exiting\n", policy->cpu); 2045 2046 intel_pstate_clear_update_util_hook(policy->cpu); 2047 if (hwp_active) 2048 intel_pstate_hwp_save_state(policy); 2049 else 2050 intel_cpufreq_stop_cpu(policy); 2051 } 2052 2053 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2054 { 2055 intel_pstate_exit_perf_limits(policy); 2056 2057 policy->fast_switch_possible = false; 2058 2059 return 0; 2060 } 2061 2062 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2063 { 2064 struct cpudata *cpu; 2065 int rc; 2066 2067 rc = intel_pstate_init_cpu(policy->cpu); 2068 if (rc) 2069 return rc; 2070 2071 cpu = all_cpu_data[policy->cpu]; 2072 2073 cpu->max_perf_ratio = 0xFF; 2074 cpu->min_perf_ratio = 0; 2075 2076 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 2077 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 2078 2079 /* cpuinfo and default policy values */ 2080 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 2081 update_turbo_state(); 2082 policy->cpuinfo.max_freq = global.turbo_disabled ? 2083 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2084 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 2085 2086 if (hwp_active) { 2087 unsigned int max_freq; 2088 2089 max_freq = global.turbo_disabled ? 2090 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2091 if (max_freq < policy->cpuinfo.max_freq) 2092 policy->cpuinfo.max_freq = max_freq; 2093 } 2094 2095 intel_pstate_init_acpi_perf_limits(policy); 2096 2097 policy->fast_switch_possible = true; 2098 2099 return 0; 2100 } 2101 2102 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2103 { 2104 int ret = __intel_pstate_cpu_init(policy); 2105 2106 if (ret) 2107 return ret; 2108 2109 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) 2110 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 2111 else 2112 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2113 2114 return 0; 2115 } 2116 2117 static struct cpufreq_driver intel_pstate = { 2118 .flags = CPUFREQ_CONST_LOOPS, 2119 .verify = intel_pstate_verify_policy, 2120 .setpolicy = intel_pstate_set_policy, 2121 .suspend = intel_pstate_hwp_save_state, 2122 .resume = intel_pstate_resume, 2123 .init = intel_pstate_cpu_init, 2124 .exit = intel_pstate_cpu_exit, 2125 .stop_cpu = intel_pstate_stop_cpu, 2126 .name = "intel_pstate", 2127 }; 2128 2129 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) 2130 { 2131 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2132 2133 update_turbo_state(); 2134 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 2135 intel_pstate_get_max_freq(cpu)); 2136 2137 intel_pstate_adjust_policy_max(policy, cpu); 2138 2139 intel_pstate_update_perf_limits(policy, cpu); 2140 2141 return 0; 2142 } 2143 2144 /* Use of trace in passive mode: 2145 * 2146 * In passive mode the trace core_busy field (also known as the 2147 * performance field, and lablelled as such on the graphs; also known as 2148 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2149 * driver call was via the normal or fast switch path. Various graphs 2150 * output from the intel_pstate_tracer.py utility that include core_busy 2151 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2152 * so we use 10 to indicate the the normal path through the driver, and 2153 * 90 to indicate the fast switch path through the driver. 2154 * The scaled_busy field is not used, and is set to 0. 2155 */ 2156 2157 #define INTEL_PSTATE_TRACE_TARGET 10 2158 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2159 2160 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2161 { 2162 struct sample *sample; 2163 2164 if (!trace_pstate_sample_enabled()) 2165 return; 2166 2167 if (!intel_pstate_sample(cpu, ktime_get())) 2168 return; 2169 2170 sample = &cpu->sample; 2171 trace_pstate_sample(trace_type, 2172 0, 2173 old_pstate, 2174 cpu->pstate.current_pstate, 2175 sample->mperf, 2176 sample->aperf, 2177 sample->tsc, 2178 get_avg_frequency(cpu), 2179 fp_toint(cpu->iowait_boost * 100)); 2180 } 2181 2182 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2183 unsigned int target_freq, 2184 unsigned int relation) 2185 { 2186 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2187 struct cpufreq_freqs freqs; 2188 int target_pstate, old_pstate; 2189 2190 update_turbo_state(); 2191 2192 freqs.old = policy->cur; 2193 freqs.new = target_freq; 2194 2195 cpufreq_freq_transition_begin(policy, &freqs); 2196 switch (relation) { 2197 case CPUFREQ_RELATION_L: 2198 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2199 break; 2200 case CPUFREQ_RELATION_H: 2201 target_pstate = freqs.new / cpu->pstate.scaling; 2202 break; 2203 default: 2204 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2205 break; 2206 } 2207 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2208 old_pstate = cpu->pstate.current_pstate; 2209 if (target_pstate != cpu->pstate.current_pstate) { 2210 cpu->pstate.current_pstate = target_pstate; 2211 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, 2212 pstate_funcs.get_val(cpu, target_pstate)); 2213 } 2214 freqs.new = target_pstate * cpu->pstate.scaling; 2215 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate); 2216 cpufreq_freq_transition_end(policy, &freqs, false); 2217 2218 return 0; 2219 } 2220 2221 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2222 unsigned int target_freq) 2223 { 2224 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2225 int target_pstate, old_pstate; 2226 2227 update_turbo_state(); 2228 2229 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2230 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2231 old_pstate = cpu->pstate.current_pstate; 2232 intel_pstate_update_pstate(cpu, target_pstate); 2233 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2234 return target_pstate * cpu->pstate.scaling; 2235 } 2236 2237 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2238 { 2239 int ret = __intel_pstate_cpu_init(policy); 2240 2241 if (ret) 2242 return ret; 2243 2244 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2245 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2246 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2247 policy->cur = policy->cpuinfo.min_freq; 2248 2249 return 0; 2250 } 2251 2252 static struct cpufreq_driver intel_cpufreq = { 2253 .flags = CPUFREQ_CONST_LOOPS, 2254 .verify = intel_cpufreq_verify_policy, 2255 .target = intel_cpufreq_target, 2256 .fast_switch = intel_cpufreq_fast_switch, 2257 .init = intel_cpufreq_cpu_init, 2258 .exit = intel_pstate_cpu_exit, 2259 .stop_cpu = intel_cpufreq_stop_cpu, 2260 .name = "intel_cpufreq", 2261 }; 2262 2263 static struct cpufreq_driver *default_driver = &intel_pstate; 2264 2265 static void intel_pstate_driver_cleanup(void) 2266 { 2267 unsigned int cpu; 2268 2269 get_online_cpus(); 2270 for_each_online_cpu(cpu) { 2271 if (all_cpu_data[cpu]) { 2272 if (intel_pstate_driver == &intel_pstate) 2273 intel_pstate_clear_update_util_hook(cpu); 2274 2275 kfree(all_cpu_data[cpu]); 2276 all_cpu_data[cpu] = NULL; 2277 } 2278 } 2279 put_online_cpus(); 2280 intel_pstate_driver = NULL; 2281 } 2282 2283 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 2284 { 2285 int ret; 2286 2287 memset(&global, 0, sizeof(global)); 2288 global.max_perf_pct = 100; 2289 2290 intel_pstate_driver = driver; 2291 ret = cpufreq_register_driver(intel_pstate_driver); 2292 if (ret) { 2293 intel_pstate_driver_cleanup(); 2294 return ret; 2295 } 2296 2297 global.min_perf_pct = min_perf_pct_min(); 2298 2299 return 0; 2300 } 2301 2302 static int intel_pstate_unregister_driver(void) 2303 { 2304 if (hwp_active) 2305 return -EBUSY; 2306 2307 cpufreq_unregister_driver(intel_pstate_driver); 2308 intel_pstate_driver_cleanup(); 2309 2310 return 0; 2311 } 2312 2313 static ssize_t intel_pstate_show_status(char *buf) 2314 { 2315 if (!intel_pstate_driver) 2316 return sprintf(buf, "off\n"); 2317 2318 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 2319 "active" : "passive"); 2320 } 2321 2322 static int intel_pstate_update_status(const char *buf, size_t size) 2323 { 2324 int ret; 2325 2326 if (size == 3 && !strncmp(buf, "off", size)) 2327 return intel_pstate_driver ? 2328 intel_pstate_unregister_driver() : -EINVAL; 2329 2330 if (size == 6 && !strncmp(buf, "active", size)) { 2331 if (intel_pstate_driver) { 2332 if (intel_pstate_driver == &intel_pstate) 2333 return 0; 2334 2335 ret = intel_pstate_unregister_driver(); 2336 if (ret) 2337 return ret; 2338 } 2339 2340 return intel_pstate_register_driver(&intel_pstate); 2341 } 2342 2343 if (size == 7 && !strncmp(buf, "passive", size)) { 2344 if (intel_pstate_driver) { 2345 if (intel_pstate_driver == &intel_cpufreq) 2346 return 0; 2347 2348 ret = intel_pstate_unregister_driver(); 2349 if (ret) 2350 return ret; 2351 } 2352 2353 return intel_pstate_register_driver(&intel_cpufreq); 2354 } 2355 2356 return -EINVAL; 2357 } 2358 2359 static int no_load __initdata; 2360 static int no_hwp __initdata; 2361 static int hwp_only __initdata; 2362 static unsigned int force_load __initdata; 2363 2364 static int __init intel_pstate_msrs_not_valid(void) 2365 { 2366 if (!pstate_funcs.get_max() || 2367 !pstate_funcs.get_min() || 2368 !pstate_funcs.get_turbo()) 2369 return -ENODEV; 2370 2371 return 0; 2372 } 2373 2374 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 2375 { 2376 pstate_funcs.get_max = funcs->get_max; 2377 pstate_funcs.get_max_physical = funcs->get_max_physical; 2378 pstate_funcs.get_min = funcs->get_min; 2379 pstate_funcs.get_turbo = funcs->get_turbo; 2380 pstate_funcs.get_scaling = funcs->get_scaling; 2381 pstate_funcs.get_val = funcs->get_val; 2382 pstate_funcs.get_vid = funcs->get_vid; 2383 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 2384 } 2385 2386 #ifdef CONFIG_ACPI 2387 2388 static bool __init intel_pstate_no_acpi_pss(void) 2389 { 2390 int i; 2391 2392 for_each_possible_cpu(i) { 2393 acpi_status status; 2394 union acpi_object *pss; 2395 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2396 struct acpi_processor *pr = per_cpu(processors, i); 2397 2398 if (!pr) 2399 continue; 2400 2401 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 2402 if (ACPI_FAILURE(status)) 2403 continue; 2404 2405 pss = buffer.pointer; 2406 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 2407 kfree(pss); 2408 return false; 2409 } 2410 2411 kfree(pss); 2412 } 2413 2414 return true; 2415 } 2416 2417 static bool __init intel_pstate_no_acpi_pcch(void) 2418 { 2419 acpi_status status; 2420 acpi_handle handle; 2421 2422 status = acpi_get_handle(NULL, "\\_SB", &handle); 2423 if (ACPI_FAILURE(status)) 2424 return true; 2425 2426 return !acpi_has_method(handle, "PCCH"); 2427 } 2428 2429 static bool __init intel_pstate_has_acpi_ppc(void) 2430 { 2431 int i; 2432 2433 for_each_possible_cpu(i) { 2434 struct acpi_processor *pr = per_cpu(processors, i); 2435 2436 if (!pr) 2437 continue; 2438 if (acpi_has_method(pr->handle, "_PPC")) 2439 return true; 2440 } 2441 return false; 2442 } 2443 2444 enum { 2445 PSS, 2446 PPC, 2447 }; 2448 2449 /* Hardware vendor-specific info that has its own power management modes */ 2450 static struct acpi_platform_list plat_info[] __initdata = { 2451 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS}, 2452 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2453 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2454 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2455 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2456 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2457 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2458 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2459 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2460 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2461 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2462 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2463 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2464 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2465 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2466 { } /* End */ 2467 }; 2468 2469 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 2470 { 2471 const struct x86_cpu_id *id; 2472 u64 misc_pwr; 2473 int idx; 2474 2475 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 2476 if (id) { 2477 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 2478 if ( misc_pwr & (1 << 8)) 2479 return true; 2480 } 2481 2482 idx = acpi_match_platform_list(plat_info); 2483 if (idx < 0) 2484 return false; 2485 2486 switch (plat_info[idx].data) { 2487 case PSS: 2488 if (!intel_pstate_no_acpi_pss()) 2489 return false; 2490 2491 return intel_pstate_no_acpi_pcch(); 2492 case PPC: 2493 return intel_pstate_has_acpi_ppc() && !force_load; 2494 } 2495 2496 return false; 2497 } 2498 2499 static void intel_pstate_request_control_from_smm(void) 2500 { 2501 /* 2502 * It may be unsafe to request P-states control from SMM if _PPC support 2503 * has not been enabled. 2504 */ 2505 if (acpi_ppc) 2506 acpi_processor_pstate_control(); 2507 } 2508 #else /* CONFIG_ACPI not enabled */ 2509 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 2510 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 2511 static inline void intel_pstate_request_control_from_smm(void) {} 2512 #endif /* CONFIG_ACPI */ 2513 2514 #define INTEL_PSTATE_HWP_BROADWELL 0x01 2515 2516 #define ICPU_HWP(model, hwp_mode) \ 2517 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode } 2518 2519 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 2520 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 2521 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL), 2522 ICPU_HWP(X86_MODEL_ANY, 0), 2523 {} 2524 }; 2525 2526 static int __init intel_pstate_init(void) 2527 { 2528 const struct x86_cpu_id *id; 2529 int rc; 2530 2531 if (no_load) 2532 return -ENODEV; 2533 2534 id = x86_match_cpu(hwp_support_ids); 2535 if (id) { 2536 copy_cpu_funcs(&core_funcs); 2537 if (!no_hwp) { 2538 hwp_active++; 2539 hwp_mode_bdw = id->driver_data; 2540 intel_pstate.attr = hwp_cpufreq_attrs; 2541 goto hwp_cpu_matched; 2542 } 2543 } else { 2544 id = x86_match_cpu(intel_pstate_cpu_ids); 2545 if (!id) 2546 return -ENODEV; 2547 2548 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 2549 } 2550 2551 if (intel_pstate_msrs_not_valid()) 2552 return -ENODEV; 2553 2554 hwp_cpu_matched: 2555 /* 2556 * The Intel pstate driver will be ignored if the platform 2557 * firmware has its own power management modes. 2558 */ 2559 if (intel_pstate_platform_pwr_mgmt_exists()) 2560 return -ENODEV; 2561 2562 if (!hwp_active && hwp_only) 2563 return -ENOTSUPP; 2564 2565 pr_info("Intel P-state driver initializing\n"); 2566 2567 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 2568 if (!all_cpu_data) 2569 return -ENOMEM; 2570 2571 intel_pstate_request_control_from_smm(); 2572 2573 intel_pstate_sysfs_expose_params(); 2574 2575 mutex_lock(&intel_pstate_driver_lock); 2576 rc = intel_pstate_register_driver(default_driver); 2577 mutex_unlock(&intel_pstate_driver_lock); 2578 if (rc) 2579 return rc; 2580 2581 if (hwp_active) 2582 pr_info("HWP enabled\n"); 2583 2584 return 0; 2585 } 2586 device_initcall(intel_pstate_init); 2587 2588 static int __init intel_pstate_setup(char *str) 2589 { 2590 if (!str) 2591 return -EINVAL; 2592 2593 if (!strcmp(str, "disable")) { 2594 no_load = 1; 2595 } else if (!strcmp(str, "passive")) { 2596 pr_info("Passive mode enabled\n"); 2597 default_driver = &intel_cpufreq; 2598 no_hwp = 1; 2599 } 2600 if (!strcmp(str, "no_hwp")) { 2601 pr_info("HWP disabled\n"); 2602 no_hwp = 1; 2603 } 2604 if (!strcmp(str, "force")) 2605 force_load = 1; 2606 if (!strcmp(str, "hwp_only")) 2607 hwp_only = 1; 2608 if (!strcmp(str, "per_cpu_perf_limits")) 2609 per_cpu_limits = true; 2610 2611 #ifdef CONFIG_ACPI 2612 if (!strcmp(str, "support_acpi_ppc")) 2613 acpi_ppc = true; 2614 #endif 2615 2616 return 0; 2617 } 2618 early_param("intel_pstate", intel_pstate_setup); 2619 2620 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 2621 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 2622 MODULE_LICENSE("GPL"); 2623