1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/kernel_stat.h> 15 #include <linux/module.h> 16 #include <linux/ktime.h> 17 #include <linux/hrtimer.h> 18 #include <linux/tick.h> 19 #include <linux/slab.h> 20 #include <linux/sched.h> 21 #include <linux/list.h> 22 #include <linux/cpu.h> 23 #include <linux/cpufreq.h> 24 #include <linux/sysfs.h> 25 #include <linux/types.h> 26 #include <linux/fs.h> 27 #include <linux/debugfs.h> 28 #include <linux/acpi.h> 29 #include <trace/events/power.h> 30 31 #include <asm/div64.h> 32 #include <asm/msr.h> 33 #include <asm/cpu_device_id.h> 34 35 #define BYT_RATIOS 0x66a 36 #define BYT_VIDS 0x66b 37 #define BYT_TURBO_RATIOS 0x66c 38 #define BYT_TURBO_VIDS 0x66d 39 40 #define FRAC_BITS 8 41 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 42 #define fp_toint(X) ((X) >> FRAC_BITS) 43 44 45 static inline int32_t mul_fp(int32_t x, int32_t y) 46 { 47 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 48 } 49 50 static inline int32_t div_fp(int32_t x, int32_t y) 51 { 52 return div_s64((int64_t)x << FRAC_BITS, y); 53 } 54 55 static inline int ceiling_fp(int32_t x) 56 { 57 int mask, ret; 58 59 ret = fp_toint(x); 60 mask = (1 << FRAC_BITS) - 1; 61 if (x & mask) 62 ret += 1; 63 return ret; 64 } 65 66 struct sample { 67 int32_t core_pct_busy; 68 u64 aperf; 69 u64 mperf; 70 int freq; 71 ktime_t time; 72 }; 73 74 struct pstate_data { 75 int current_pstate; 76 int min_pstate; 77 int max_pstate; 78 int scaling; 79 int turbo_pstate; 80 }; 81 82 struct vid_data { 83 int min; 84 int max; 85 int turbo; 86 int32_t ratio; 87 }; 88 89 struct _pid { 90 int setpoint; 91 int32_t integral; 92 int32_t p_gain; 93 int32_t i_gain; 94 int32_t d_gain; 95 int deadband; 96 int32_t last_err; 97 }; 98 99 struct cpudata { 100 int cpu; 101 102 struct timer_list timer; 103 104 struct pstate_data pstate; 105 struct vid_data vid; 106 struct _pid pid; 107 108 ktime_t last_sample_time; 109 u64 prev_aperf; 110 u64 prev_mperf; 111 struct sample sample; 112 }; 113 114 static struct cpudata **all_cpu_data; 115 struct pstate_adjust_policy { 116 int sample_rate_ms; 117 int deadband; 118 int setpoint; 119 int p_gain_pct; 120 int d_gain_pct; 121 int i_gain_pct; 122 }; 123 124 struct pstate_funcs { 125 int (*get_max)(void); 126 int (*get_min)(void); 127 int (*get_turbo)(void); 128 int (*get_scaling)(void); 129 void (*set)(struct cpudata*, int pstate); 130 void (*get_vid)(struct cpudata *); 131 }; 132 133 struct cpu_defaults { 134 struct pstate_adjust_policy pid_policy; 135 struct pstate_funcs funcs; 136 }; 137 138 static struct pstate_adjust_policy pid_params; 139 static struct pstate_funcs pstate_funcs; 140 static int hwp_active; 141 142 struct perf_limits { 143 int no_turbo; 144 int turbo_disabled; 145 int max_perf_pct; 146 int min_perf_pct; 147 int32_t max_perf; 148 int32_t min_perf; 149 int max_policy_pct; 150 int max_sysfs_pct; 151 }; 152 153 static struct perf_limits limits = { 154 .no_turbo = 0, 155 .turbo_disabled = 0, 156 .max_perf_pct = 100, 157 .max_perf = int_tofp(1), 158 .min_perf_pct = 0, 159 .min_perf = 0, 160 .max_policy_pct = 100, 161 .max_sysfs_pct = 100, 162 }; 163 164 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 165 int deadband, int integral) { 166 pid->setpoint = setpoint; 167 pid->deadband = deadband; 168 pid->integral = int_tofp(integral); 169 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 170 } 171 172 static inline void pid_p_gain_set(struct _pid *pid, int percent) 173 { 174 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); 175 } 176 177 static inline void pid_i_gain_set(struct _pid *pid, int percent) 178 { 179 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); 180 } 181 182 static inline void pid_d_gain_set(struct _pid *pid, int percent) 183 { 184 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); 185 } 186 187 static signed int pid_calc(struct _pid *pid, int32_t busy) 188 { 189 signed int result; 190 int32_t pterm, dterm, fp_error; 191 int32_t integral_limit; 192 193 fp_error = int_tofp(pid->setpoint) - busy; 194 195 if (abs(fp_error) <= int_tofp(pid->deadband)) 196 return 0; 197 198 pterm = mul_fp(pid->p_gain, fp_error); 199 200 pid->integral += fp_error; 201 202 /* 203 * We limit the integral here so that it will never 204 * get higher than 30. This prevents it from becoming 205 * too large an input over long periods of time and allows 206 * it to get factored out sooner. 207 * 208 * The value of 30 was chosen through experimentation. 209 */ 210 integral_limit = int_tofp(30); 211 if (pid->integral > integral_limit) 212 pid->integral = integral_limit; 213 if (pid->integral < -integral_limit) 214 pid->integral = -integral_limit; 215 216 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 217 pid->last_err = fp_error; 218 219 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 220 result = result + (1 << (FRAC_BITS-1)); 221 return (signed int)fp_toint(result); 222 } 223 224 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 225 { 226 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 227 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 228 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 229 230 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 231 } 232 233 static inline void intel_pstate_reset_all_pid(void) 234 { 235 unsigned int cpu; 236 237 for_each_online_cpu(cpu) { 238 if (all_cpu_data[cpu]) 239 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 240 } 241 } 242 243 static inline void update_turbo_state(void) 244 { 245 u64 misc_en; 246 struct cpudata *cpu; 247 248 cpu = all_cpu_data[0]; 249 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 250 limits.turbo_disabled = 251 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 252 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 253 } 254 255 #define PCT_TO_HWP(x) (x * 255 / 100) 256 static void intel_pstate_hwp_set(void) 257 { 258 int min, max, cpu; 259 u64 value, freq; 260 261 get_online_cpus(); 262 263 for_each_online_cpu(cpu) { 264 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 265 min = PCT_TO_HWP(limits.min_perf_pct); 266 value &= ~HWP_MIN_PERF(~0L); 267 value |= HWP_MIN_PERF(min); 268 269 max = PCT_TO_HWP(limits.max_perf_pct); 270 if (limits.no_turbo) { 271 rdmsrl( MSR_HWP_CAPABILITIES, freq); 272 max = HWP_GUARANTEED_PERF(freq); 273 } 274 275 value &= ~HWP_MAX_PERF(~0L); 276 value |= HWP_MAX_PERF(max); 277 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 278 } 279 280 put_online_cpus(); 281 } 282 283 /************************** debugfs begin ************************/ 284 static int pid_param_set(void *data, u64 val) 285 { 286 *(u32 *)data = val; 287 intel_pstate_reset_all_pid(); 288 return 0; 289 } 290 291 static int pid_param_get(void *data, u64 *val) 292 { 293 *val = *(u32 *)data; 294 return 0; 295 } 296 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 297 298 struct pid_param { 299 char *name; 300 void *value; 301 }; 302 303 static struct pid_param pid_files[] = { 304 {"sample_rate_ms", &pid_params.sample_rate_ms}, 305 {"d_gain_pct", &pid_params.d_gain_pct}, 306 {"i_gain_pct", &pid_params.i_gain_pct}, 307 {"deadband", &pid_params.deadband}, 308 {"setpoint", &pid_params.setpoint}, 309 {"p_gain_pct", &pid_params.p_gain_pct}, 310 {NULL, NULL} 311 }; 312 313 static void __init intel_pstate_debug_expose_params(void) 314 { 315 struct dentry *debugfs_parent; 316 int i = 0; 317 318 if (hwp_active) 319 return; 320 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 321 if (IS_ERR_OR_NULL(debugfs_parent)) 322 return; 323 while (pid_files[i].name) { 324 debugfs_create_file(pid_files[i].name, 0660, 325 debugfs_parent, pid_files[i].value, 326 &fops_pid_param); 327 i++; 328 } 329 } 330 331 /************************** debugfs end ************************/ 332 333 /************************** sysfs begin ************************/ 334 #define show_one(file_name, object) \ 335 static ssize_t show_##file_name \ 336 (struct kobject *kobj, struct attribute *attr, char *buf) \ 337 { \ 338 return sprintf(buf, "%u\n", limits.object); \ 339 } 340 341 static ssize_t show_no_turbo(struct kobject *kobj, 342 struct attribute *attr, char *buf) 343 { 344 ssize_t ret; 345 346 update_turbo_state(); 347 if (limits.turbo_disabled) 348 ret = sprintf(buf, "%u\n", limits.turbo_disabled); 349 else 350 ret = sprintf(buf, "%u\n", limits.no_turbo); 351 352 return ret; 353 } 354 355 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 356 const char *buf, size_t count) 357 { 358 unsigned int input; 359 int ret; 360 361 ret = sscanf(buf, "%u", &input); 362 if (ret != 1) 363 return -EINVAL; 364 365 update_turbo_state(); 366 if (limits.turbo_disabled) { 367 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 368 return -EPERM; 369 } 370 371 limits.no_turbo = clamp_t(int, input, 0, 1); 372 373 if (hwp_active) 374 intel_pstate_hwp_set(); 375 376 return count; 377 } 378 379 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 380 const char *buf, size_t count) 381 { 382 unsigned int input; 383 int ret; 384 385 ret = sscanf(buf, "%u", &input); 386 if (ret != 1) 387 return -EINVAL; 388 389 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); 390 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); 391 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); 392 393 if (hwp_active) 394 intel_pstate_hwp_set(); 395 return count; 396 } 397 398 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 399 const char *buf, size_t count) 400 { 401 unsigned int input; 402 int ret; 403 404 ret = sscanf(buf, "%u", &input); 405 if (ret != 1) 406 return -EINVAL; 407 limits.min_perf_pct = clamp_t(int, input, 0 , 100); 408 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); 409 410 if (hwp_active) 411 intel_pstate_hwp_set(); 412 return count; 413 } 414 415 show_one(max_perf_pct, max_perf_pct); 416 show_one(min_perf_pct, min_perf_pct); 417 418 define_one_global_rw(no_turbo); 419 define_one_global_rw(max_perf_pct); 420 define_one_global_rw(min_perf_pct); 421 422 static struct attribute *intel_pstate_attributes[] = { 423 &no_turbo.attr, 424 &max_perf_pct.attr, 425 &min_perf_pct.attr, 426 NULL 427 }; 428 429 static struct attribute_group intel_pstate_attr_group = { 430 .attrs = intel_pstate_attributes, 431 }; 432 433 static void __init intel_pstate_sysfs_expose_params(void) 434 { 435 struct kobject *intel_pstate_kobject; 436 int rc; 437 438 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 439 &cpu_subsys.dev_root->kobj); 440 BUG_ON(!intel_pstate_kobject); 441 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 442 BUG_ON(rc); 443 } 444 /************************** sysfs end ************************/ 445 446 static void intel_pstate_hwp_enable(void) 447 { 448 hwp_active++; 449 pr_info("intel_pstate HWP enabled\n"); 450 451 wrmsrl( MSR_PM_ENABLE, 0x1); 452 } 453 454 static int byt_get_min_pstate(void) 455 { 456 u64 value; 457 458 rdmsrl(BYT_RATIOS, value); 459 return (value >> 8) & 0x7F; 460 } 461 462 static int byt_get_max_pstate(void) 463 { 464 u64 value; 465 466 rdmsrl(BYT_RATIOS, value); 467 return (value >> 16) & 0x7F; 468 } 469 470 static int byt_get_turbo_pstate(void) 471 { 472 u64 value; 473 474 rdmsrl(BYT_TURBO_RATIOS, value); 475 return value & 0x7F; 476 } 477 478 static void byt_set_pstate(struct cpudata *cpudata, int pstate) 479 { 480 u64 val; 481 int32_t vid_fp; 482 u32 vid; 483 484 val = pstate << 8; 485 if (limits.no_turbo && !limits.turbo_disabled) 486 val |= (u64)1 << 32; 487 488 vid_fp = cpudata->vid.min + mul_fp( 489 int_tofp(pstate - cpudata->pstate.min_pstate), 490 cpudata->vid.ratio); 491 492 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 493 vid = ceiling_fp(vid_fp); 494 495 if (pstate > cpudata->pstate.max_pstate) 496 vid = cpudata->vid.turbo; 497 498 val |= vid; 499 500 wrmsrl(MSR_IA32_PERF_CTL, val); 501 } 502 503 #define BYT_BCLK_FREQS 5 504 static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; 505 506 static int byt_get_scaling(void) 507 { 508 u64 value; 509 int i; 510 511 rdmsrl(MSR_FSB_FREQ, value); 512 i = value & 0x3; 513 514 BUG_ON(i > BYT_BCLK_FREQS); 515 516 return byt_freq_table[i] * 100; 517 } 518 519 static void byt_get_vid(struct cpudata *cpudata) 520 { 521 u64 value; 522 523 rdmsrl(BYT_VIDS, value); 524 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 525 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 526 cpudata->vid.ratio = div_fp( 527 cpudata->vid.max - cpudata->vid.min, 528 int_tofp(cpudata->pstate.max_pstate - 529 cpudata->pstate.min_pstate)); 530 531 rdmsrl(BYT_TURBO_VIDS, value); 532 cpudata->vid.turbo = value & 0x7f; 533 } 534 535 static int core_get_min_pstate(void) 536 { 537 u64 value; 538 539 rdmsrl(MSR_PLATFORM_INFO, value); 540 return (value >> 40) & 0xFF; 541 } 542 543 static int core_get_max_pstate(void) 544 { 545 u64 value; 546 547 rdmsrl(MSR_PLATFORM_INFO, value); 548 return (value >> 8) & 0xFF; 549 } 550 551 static int core_get_turbo_pstate(void) 552 { 553 u64 value; 554 int nont, ret; 555 556 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 557 nont = core_get_max_pstate(); 558 ret = (value) & 255; 559 if (ret <= nont) 560 ret = nont; 561 return ret; 562 } 563 564 static inline int core_get_scaling(void) 565 { 566 return 100000; 567 } 568 569 static void core_set_pstate(struct cpudata *cpudata, int pstate) 570 { 571 u64 val; 572 573 val = pstate << 8; 574 if (limits.no_turbo && !limits.turbo_disabled) 575 val |= (u64)1 << 32; 576 577 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); 578 } 579 580 static struct cpu_defaults core_params = { 581 .pid_policy = { 582 .sample_rate_ms = 10, 583 .deadband = 0, 584 .setpoint = 97, 585 .p_gain_pct = 20, 586 .d_gain_pct = 0, 587 .i_gain_pct = 0, 588 }, 589 .funcs = { 590 .get_max = core_get_max_pstate, 591 .get_min = core_get_min_pstate, 592 .get_turbo = core_get_turbo_pstate, 593 .get_scaling = core_get_scaling, 594 .set = core_set_pstate, 595 }, 596 }; 597 598 static struct cpu_defaults byt_params = { 599 .pid_policy = { 600 .sample_rate_ms = 10, 601 .deadband = 0, 602 .setpoint = 97, 603 .p_gain_pct = 14, 604 .d_gain_pct = 0, 605 .i_gain_pct = 4, 606 }, 607 .funcs = { 608 .get_max = byt_get_max_pstate, 609 .get_min = byt_get_min_pstate, 610 .get_turbo = byt_get_turbo_pstate, 611 .set = byt_set_pstate, 612 .get_scaling = byt_get_scaling, 613 .get_vid = byt_get_vid, 614 }, 615 }; 616 617 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 618 { 619 int max_perf = cpu->pstate.turbo_pstate; 620 int max_perf_adj; 621 int min_perf; 622 623 if (limits.no_turbo || limits.turbo_disabled) 624 max_perf = cpu->pstate.max_pstate; 625 626 /* 627 * performance can be limited by user through sysfs, by cpufreq 628 * policy, or by cpu specific default values determined through 629 * experimentation. 630 */ 631 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); 632 *max = clamp_t(int, max_perf_adj, 633 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 634 635 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); 636 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 637 } 638 639 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 640 { 641 int max_perf, min_perf; 642 643 update_turbo_state(); 644 645 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 646 647 pstate = clamp_t(int, pstate, min_perf, max_perf); 648 649 if (pstate == cpu->pstate.current_pstate) 650 return; 651 652 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 653 654 cpu->pstate.current_pstate = pstate; 655 656 pstate_funcs.set(cpu, pstate); 657 } 658 659 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 660 { 661 cpu->pstate.min_pstate = pstate_funcs.get_min(); 662 cpu->pstate.max_pstate = pstate_funcs.get_max(); 663 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 664 cpu->pstate.scaling = pstate_funcs.get_scaling(); 665 666 if (pstate_funcs.get_vid) 667 pstate_funcs.get_vid(cpu); 668 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 669 } 670 671 static inline void intel_pstate_calc_busy(struct cpudata *cpu) 672 { 673 struct sample *sample = &cpu->sample; 674 int64_t core_pct; 675 676 core_pct = int_tofp(sample->aperf) * int_tofp(100); 677 core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); 678 679 sample->freq = fp_toint( 680 mul_fp(int_tofp( 681 cpu->pstate.max_pstate * cpu->pstate.scaling / 100), 682 core_pct)); 683 684 sample->core_pct_busy = (int32_t)core_pct; 685 } 686 687 static inline void intel_pstate_sample(struct cpudata *cpu) 688 { 689 u64 aperf, mperf; 690 unsigned long flags; 691 692 local_irq_save(flags); 693 rdmsrl(MSR_IA32_APERF, aperf); 694 rdmsrl(MSR_IA32_MPERF, mperf); 695 local_irq_restore(flags); 696 697 cpu->last_sample_time = cpu->sample.time; 698 cpu->sample.time = ktime_get(); 699 cpu->sample.aperf = aperf; 700 cpu->sample.mperf = mperf; 701 cpu->sample.aperf -= cpu->prev_aperf; 702 cpu->sample.mperf -= cpu->prev_mperf; 703 704 intel_pstate_calc_busy(cpu); 705 706 cpu->prev_aperf = aperf; 707 cpu->prev_mperf = mperf; 708 } 709 710 static inline void intel_hwp_set_sample_time(struct cpudata *cpu) 711 { 712 int delay; 713 714 delay = msecs_to_jiffies(50); 715 mod_timer_pinned(&cpu->timer, jiffies + delay); 716 } 717 718 static inline void intel_pstate_set_sample_time(struct cpudata *cpu) 719 { 720 int delay; 721 722 delay = msecs_to_jiffies(pid_params.sample_rate_ms); 723 mod_timer_pinned(&cpu->timer, jiffies + delay); 724 } 725 726 static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) 727 { 728 int32_t core_busy, max_pstate, current_pstate, sample_ratio; 729 u32 duration_us; 730 u32 sample_time; 731 732 /* 733 * core_busy is the ratio of actual performance to max 734 * max_pstate is the max non turbo pstate available 735 * current_pstate was the pstate that was requested during 736 * the last sample period. 737 * 738 * We normalize core_busy, which was our actual percent 739 * performance to what we requested during the last sample 740 * period. The result will be a percentage of busy at a 741 * specified pstate. 742 */ 743 core_busy = cpu->sample.core_pct_busy; 744 max_pstate = int_tofp(cpu->pstate.max_pstate); 745 current_pstate = int_tofp(cpu->pstate.current_pstate); 746 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); 747 748 /* 749 * Since we have a deferred timer, it will not fire unless 750 * we are in C0. So, determine if the actual elapsed time 751 * is significantly greater (3x) than our sample interval. If it 752 * is, then we were idle for a long enough period of time 753 * to adjust our busyness. 754 */ 755 sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; 756 duration_us = (u32) ktime_us_delta(cpu->sample.time, 757 cpu->last_sample_time); 758 if (duration_us > sample_time * 3) { 759 sample_ratio = div_fp(int_tofp(sample_time), 760 int_tofp(duration_us)); 761 core_busy = mul_fp(core_busy, sample_ratio); 762 } 763 764 return core_busy; 765 } 766 767 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 768 { 769 int32_t busy_scaled; 770 struct _pid *pid; 771 signed int ctl; 772 773 pid = &cpu->pid; 774 busy_scaled = intel_pstate_get_scaled_busy(cpu); 775 776 ctl = pid_calc(pid, busy_scaled); 777 778 /* Negative values of ctl increase the pstate and vice versa */ 779 intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl); 780 } 781 782 static void intel_hwp_timer_func(unsigned long __data) 783 { 784 struct cpudata *cpu = (struct cpudata *) __data; 785 786 intel_pstate_sample(cpu); 787 intel_hwp_set_sample_time(cpu); 788 } 789 790 static void intel_pstate_timer_func(unsigned long __data) 791 { 792 struct cpudata *cpu = (struct cpudata *) __data; 793 struct sample *sample; 794 795 intel_pstate_sample(cpu); 796 797 sample = &cpu->sample; 798 799 intel_pstate_adjust_busy_pstate(cpu); 800 801 trace_pstate_sample(fp_toint(sample->core_pct_busy), 802 fp_toint(intel_pstate_get_scaled_busy(cpu)), 803 cpu->pstate.current_pstate, 804 sample->mperf, 805 sample->aperf, 806 sample->freq); 807 808 intel_pstate_set_sample_time(cpu); 809 } 810 811 #define ICPU(model, policy) \ 812 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 813 (unsigned long)&policy } 814 815 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 816 ICPU(0x2a, core_params), 817 ICPU(0x2d, core_params), 818 ICPU(0x37, byt_params), 819 ICPU(0x3a, core_params), 820 ICPU(0x3c, core_params), 821 ICPU(0x3d, core_params), 822 ICPU(0x3e, core_params), 823 ICPU(0x3f, core_params), 824 ICPU(0x45, core_params), 825 ICPU(0x46, core_params), 826 ICPU(0x47, core_params), 827 ICPU(0x4c, byt_params), 828 ICPU(0x4f, core_params), 829 ICPU(0x56, core_params), 830 {} 831 }; 832 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 833 834 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { 835 ICPU(0x56, core_params), 836 {} 837 }; 838 839 static int intel_pstate_init_cpu(unsigned int cpunum) 840 { 841 struct cpudata *cpu; 842 843 if (!all_cpu_data[cpunum]) 844 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), 845 GFP_KERNEL); 846 if (!all_cpu_data[cpunum]) 847 return -ENOMEM; 848 849 cpu = all_cpu_data[cpunum]; 850 851 cpu->cpu = cpunum; 852 intel_pstate_get_cpu_pstates(cpu); 853 854 init_timer_deferrable(&cpu->timer); 855 cpu->timer.data = (unsigned long)cpu; 856 cpu->timer.expires = jiffies + HZ/100; 857 858 if (!hwp_active) 859 cpu->timer.function = intel_pstate_timer_func; 860 else 861 cpu->timer.function = intel_hwp_timer_func; 862 863 intel_pstate_busy_pid_reset(cpu); 864 intel_pstate_sample(cpu); 865 866 add_timer_on(&cpu->timer, cpunum); 867 868 pr_debug("Intel pstate controlling: cpu %d\n", cpunum); 869 870 return 0; 871 } 872 873 static unsigned int intel_pstate_get(unsigned int cpu_num) 874 { 875 struct sample *sample; 876 struct cpudata *cpu; 877 878 cpu = all_cpu_data[cpu_num]; 879 if (!cpu) 880 return 0; 881 sample = &cpu->sample; 882 return sample->freq; 883 } 884 885 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 886 { 887 if (!policy->cpuinfo.max_freq) 888 return -ENODEV; 889 890 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 891 limits.min_perf_pct = 100; 892 limits.min_perf = int_tofp(1); 893 limits.max_policy_pct = 100; 894 limits.max_perf_pct = 100; 895 limits.max_perf = int_tofp(1); 896 limits.no_turbo = 0; 897 return 0; 898 } 899 900 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 901 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100); 902 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); 903 904 limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; 905 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); 906 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); 907 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); 908 909 if (hwp_active) 910 intel_pstate_hwp_set(); 911 912 return 0; 913 } 914 915 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 916 { 917 cpufreq_verify_within_cpu_limits(policy); 918 919 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 920 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 927 { 928 int cpu_num = policy->cpu; 929 struct cpudata *cpu = all_cpu_data[cpu_num]; 930 931 pr_info("intel_pstate CPU %d exiting\n", cpu_num); 932 933 del_timer_sync(&all_cpu_data[cpu_num]->timer); 934 if (hwp_active) 935 return; 936 937 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 938 } 939 940 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 941 { 942 struct cpudata *cpu; 943 int rc; 944 945 rc = intel_pstate_init_cpu(policy->cpu); 946 if (rc) 947 return rc; 948 949 cpu = all_cpu_data[policy->cpu]; 950 951 if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) 952 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 953 else 954 policy->policy = CPUFREQ_POLICY_POWERSAVE; 955 956 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 957 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 958 959 /* cpuinfo and default policy values */ 960 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 961 policy->cpuinfo.max_freq = 962 cpu->pstate.turbo_pstate * cpu->pstate.scaling; 963 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 964 cpumask_set_cpu(policy->cpu, policy->cpus); 965 966 return 0; 967 } 968 969 static struct cpufreq_driver intel_pstate_driver = { 970 .flags = CPUFREQ_CONST_LOOPS, 971 .verify = intel_pstate_verify_policy, 972 .setpolicy = intel_pstate_set_policy, 973 .get = intel_pstate_get, 974 .init = intel_pstate_cpu_init, 975 .stop_cpu = intel_pstate_stop_cpu, 976 .name = "intel_pstate", 977 }; 978 979 static int __initdata no_load; 980 static int __initdata no_hwp; 981 static unsigned int force_load; 982 983 static int intel_pstate_msrs_not_valid(void) 984 { 985 /* Check that all the msr's we are using are valid. */ 986 u64 aperf, mperf, tmp; 987 988 rdmsrl(MSR_IA32_APERF, aperf); 989 rdmsrl(MSR_IA32_MPERF, mperf); 990 991 if (!pstate_funcs.get_max() || 992 !pstate_funcs.get_min() || 993 !pstate_funcs.get_turbo()) 994 return -ENODEV; 995 996 rdmsrl(MSR_IA32_APERF, tmp); 997 if (!(tmp - aperf)) 998 return -ENODEV; 999 1000 rdmsrl(MSR_IA32_MPERF, tmp); 1001 if (!(tmp - mperf)) 1002 return -ENODEV; 1003 1004 return 0; 1005 } 1006 1007 static void copy_pid_params(struct pstate_adjust_policy *policy) 1008 { 1009 pid_params.sample_rate_ms = policy->sample_rate_ms; 1010 pid_params.p_gain_pct = policy->p_gain_pct; 1011 pid_params.i_gain_pct = policy->i_gain_pct; 1012 pid_params.d_gain_pct = policy->d_gain_pct; 1013 pid_params.deadband = policy->deadband; 1014 pid_params.setpoint = policy->setpoint; 1015 } 1016 1017 static void copy_cpu_funcs(struct pstate_funcs *funcs) 1018 { 1019 pstate_funcs.get_max = funcs->get_max; 1020 pstate_funcs.get_min = funcs->get_min; 1021 pstate_funcs.get_turbo = funcs->get_turbo; 1022 pstate_funcs.get_scaling = funcs->get_scaling; 1023 pstate_funcs.set = funcs->set; 1024 pstate_funcs.get_vid = funcs->get_vid; 1025 } 1026 1027 #if IS_ENABLED(CONFIG_ACPI) 1028 #include <acpi/processor.h> 1029 1030 static bool intel_pstate_no_acpi_pss(void) 1031 { 1032 int i; 1033 1034 for_each_possible_cpu(i) { 1035 acpi_status status; 1036 union acpi_object *pss; 1037 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1038 struct acpi_processor *pr = per_cpu(processors, i); 1039 1040 if (!pr) 1041 continue; 1042 1043 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1044 if (ACPI_FAILURE(status)) 1045 continue; 1046 1047 pss = buffer.pointer; 1048 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1049 kfree(pss); 1050 return false; 1051 } 1052 1053 kfree(pss); 1054 } 1055 1056 return true; 1057 } 1058 1059 static bool intel_pstate_has_acpi_ppc(void) 1060 { 1061 int i; 1062 1063 for_each_possible_cpu(i) { 1064 struct acpi_processor *pr = per_cpu(processors, i); 1065 1066 if (!pr) 1067 continue; 1068 if (acpi_has_method(pr->handle, "_PPC")) 1069 return true; 1070 } 1071 return false; 1072 } 1073 1074 enum { 1075 PSS, 1076 PPC, 1077 }; 1078 1079 struct hw_vendor_info { 1080 u16 valid; 1081 char oem_id[ACPI_OEM_ID_SIZE]; 1082 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1083 int oem_pwr_table; 1084 }; 1085 1086 /* Hardware vendor-specific info that has its own power management modes */ 1087 static struct hw_vendor_info vendor_info[] = { 1088 {1, "HP ", "ProLiant", PSS}, 1089 {1, "ORACLE", "X4-2 ", PPC}, 1090 {1, "ORACLE", "X4-2L ", PPC}, 1091 {1, "ORACLE", "X4-2B ", PPC}, 1092 {1, "ORACLE", "X3-2 ", PPC}, 1093 {1, "ORACLE", "X3-2L ", PPC}, 1094 {1, "ORACLE", "X3-2B ", PPC}, 1095 {1, "ORACLE", "X4470M2 ", PPC}, 1096 {1, "ORACLE", "X4270M3 ", PPC}, 1097 {1, "ORACLE", "X4270M2 ", PPC}, 1098 {1, "ORACLE", "X4170M2 ", PPC}, 1099 {0, "", ""}, 1100 }; 1101 1102 static bool intel_pstate_platform_pwr_mgmt_exists(void) 1103 { 1104 struct acpi_table_header hdr; 1105 struct hw_vendor_info *v_info; 1106 const struct x86_cpu_id *id; 1107 u64 misc_pwr; 1108 1109 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1110 if (id) { 1111 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1112 if ( misc_pwr & (1 << 8)) 1113 return true; 1114 } 1115 1116 if (acpi_disabled || 1117 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1118 return false; 1119 1120 for (v_info = vendor_info; v_info->valid; v_info++) { 1121 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1122 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1123 ACPI_OEM_TABLE_ID_SIZE)) 1124 switch (v_info->oem_pwr_table) { 1125 case PSS: 1126 return intel_pstate_no_acpi_pss(); 1127 case PPC: 1128 return intel_pstate_has_acpi_ppc() && 1129 (!force_load); 1130 } 1131 } 1132 1133 return false; 1134 } 1135 #else /* CONFIG_ACPI not enabled */ 1136 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1137 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1138 #endif /* CONFIG_ACPI */ 1139 1140 static int __init intel_pstate_init(void) 1141 { 1142 int cpu, rc = 0; 1143 const struct x86_cpu_id *id; 1144 struct cpu_defaults *cpu_info; 1145 struct cpuinfo_x86 *c = &boot_cpu_data; 1146 1147 if (no_load) 1148 return -ENODEV; 1149 1150 id = x86_match_cpu(intel_pstate_cpu_ids); 1151 if (!id) 1152 return -ENODEV; 1153 1154 /* 1155 * The Intel pstate driver will be ignored if the platform 1156 * firmware has its own power management modes. 1157 */ 1158 if (intel_pstate_platform_pwr_mgmt_exists()) 1159 return -ENODEV; 1160 1161 cpu_info = (struct cpu_defaults *)id->driver_data; 1162 1163 copy_pid_params(&cpu_info->pid_policy); 1164 copy_cpu_funcs(&cpu_info->funcs); 1165 1166 if (intel_pstate_msrs_not_valid()) 1167 return -ENODEV; 1168 1169 pr_info("Intel P-state driver initializing.\n"); 1170 1171 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1172 if (!all_cpu_data) 1173 return -ENOMEM; 1174 1175 if (cpu_has(c,X86_FEATURE_HWP) && !no_hwp) 1176 intel_pstate_hwp_enable(); 1177 1178 rc = cpufreq_register_driver(&intel_pstate_driver); 1179 if (rc) 1180 goto out; 1181 1182 intel_pstate_debug_expose_params(); 1183 intel_pstate_sysfs_expose_params(); 1184 1185 return rc; 1186 out: 1187 get_online_cpus(); 1188 for_each_online_cpu(cpu) { 1189 if (all_cpu_data[cpu]) { 1190 del_timer_sync(&all_cpu_data[cpu]->timer); 1191 kfree(all_cpu_data[cpu]); 1192 } 1193 } 1194 1195 put_online_cpus(); 1196 vfree(all_cpu_data); 1197 return -ENODEV; 1198 } 1199 device_initcall(intel_pstate_init); 1200 1201 static int __init intel_pstate_setup(char *str) 1202 { 1203 if (!str) 1204 return -EINVAL; 1205 1206 if (!strcmp(str, "disable")) 1207 no_load = 1; 1208 if (!strcmp(str, "no_hwp")) 1209 no_hwp = 1; 1210 if (!strcmp(str, "force")) 1211 force_load = 1; 1212 return 0; 1213 } 1214 early_param("intel_pstate", intel_pstate_setup); 1215 1216 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1217 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1218 MODULE_LICENSE("GPL"); 1219