1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched/cpufreq.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 41 42 #ifdef CONFIG_ACPI 43 #include <acpi/processor.h> 44 #include <acpi/cppc_acpi.h> 45 #endif 46 47 #define FRAC_BITS 8 48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 49 #define fp_toint(X) ((X) >> FRAC_BITS) 50 51 #define EXT_BITS 6 52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 55 56 static inline int32_t mul_fp(int32_t x, int32_t y) 57 { 58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 59 } 60 61 static inline int32_t div_fp(s64 x, s64 y) 62 { 63 return div64_s64((int64_t)x << FRAC_BITS, y); 64 } 65 66 static inline int ceiling_fp(int32_t x) 67 { 68 int mask, ret; 69 70 ret = fp_toint(x); 71 mask = (1 << FRAC_BITS) - 1; 72 if (x & mask) 73 ret += 1; 74 return ret; 75 } 76 77 static inline u64 mul_ext_fp(u64 x, u64 y) 78 { 79 return (x * y) >> EXT_FRAC_BITS; 80 } 81 82 static inline u64 div_ext_fp(u64 x, u64 y) 83 { 84 return div64_u64(x << EXT_FRAC_BITS, y); 85 } 86 87 static inline int32_t percent_ext_fp(int percent) 88 { 89 return div_ext_fp(percent, 100); 90 } 91 92 /** 93 * struct sample - Store performance sample 94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 95 * performance during last sample period 96 * @busy_scaled: Scaled busy value which is used to calculate next 97 * P state. This can be different than core_avg_perf 98 * to account for cpu idle period 99 * @aperf: Difference of actual performance frequency clock count 100 * read from APERF MSR between last and current sample 101 * @mperf: Difference of maximum performance frequency clock count 102 * read from MPERF MSR between last and current sample 103 * @tsc: Difference of time stamp counter between last and 104 * current sample 105 * @time: Current time from scheduler 106 * 107 * This structure is used in the cpudata structure to store performance sample 108 * data for choosing next P State. 109 */ 110 struct sample { 111 int32_t core_avg_perf; 112 int32_t busy_scaled; 113 u64 aperf; 114 u64 mperf; 115 u64 tsc; 116 u64 time; 117 }; 118 119 /** 120 * struct pstate_data - Store P state data 121 * @current_pstate: Current requested P state 122 * @min_pstate: Min P state possible for this platform 123 * @max_pstate: Max P state possible for this platform 124 * @max_pstate_physical:This is physical Max P state for a processor 125 * This can be higher than the max_pstate which can 126 * be limited by platform thermal design power limits 127 * @scaling: Scaling factor to convert frequency to cpufreq 128 * frequency units 129 * @turbo_pstate: Max Turbo P state possible for this platform 130 * @max_freq: @max_pstate frequency in cpufreq units 131 * @turbo_freq: @turbo_pstate frequency in cpufreq units 132 * 133 * Stores the per cpu model P state limits and current P state. 134 */ 135 struct pstate_data { 136 int current_pstate; 137 int min_pstate; 138 int max_pstate; 139 int max_pstate_physical; 140 int scaling; 141 int turbo_pstate; 142 unsigned int max_freq; 143 unsigned int turbo_freq; 144 }; 145 146 /** 147 * struct vid_data - Stores voltage information data 148 * @min: VID data for this platform corresponding to 149 * the lowest P state 150 * @max: VID data corresponding to the highest P State. 151 * @turbo: VID data for turbo P state 152 * @ratio: Ratio of (vid max - vid min) / 153 * (max P state - Min P State) 154 * 155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 156 * This data is used in Atom platforms, where in addition to target P state, 157 * the voltage data needs to be specified to select next P State. 158 */ 159 struct vid_data { 160 int min; 161 int max; 162 int turbo; 163 int32_t ratio; 164 }; 165 166 /** 167 * struct _pid - Stores PID data 168 * @setpoint: Target set point for busyness or performance 169 * @integral: Storage for accumulated error values 170 * @p_gain: PID proportional gain 171 * @i_gain: PID integral gain 172 * @d_gain: PID derivative gain 173 * @deadband: PID deadband 174 * @last_err: Last error storage for integral part of PID calculation 175 * 176 * Stores PID coefficients and last error for PID controller. 177 */ 178 struct _pid { 179 int setpoint; 180 int32_t integral; 181 int32_t p_gain; 182 int32_t i_gain; 183 int32_t d_gain; 184 int deadband; 185 int32_t last_err; 186 }; 187 188 /** 189 * struct perf_limits - Store user and policy limits 190 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 191 * This value is used to limit max pstate 192 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 193 * This value is used to limit min pstate 194 * 195 * Storage for policy defined limits. 196 */ 197 struct perf_limits { 198 int32_t max_perf; 199 int32_t min_perf; 200 }; 201 202 /** 203 * struct global_params - Global parameters, mostly tunable via sysfs. 204 * @no_turbo: Whether or not to use turbo P-states. 205 * @turbo_disabled: Whethet or not turbo P-states are available at all, 206 * based on the MSR_IA32_MISC_ENABLE value and whether or 207 * not the maximum reported turbo P-state is different from 208 * the maximum reported non-turbo one. 209 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 210 * P-state capacity. 211 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 212 * P-state capacity. 213 */ 214 struct global_params { 215 bool no_turbo; 216 bool turbo_disabled; 217 int max_perf_pct; 218 int min_perf_pct; 219 }; 220 221 /** 222 * struct cpudata - Per CPU instance data storage 223 * @cpu: CPU number for this instance data 224 * @policy: CPUFreq policy value 225 * @update_util: CPUFreq utility callback information 226 * @update_util_set: CPUFreq utility callback is set 227 * @iowait_boost: iowait-related boost fraction 228 * @last_update: Time of the last update. 229 * @pstate: Stores P state limits for this CPU 230 * @vid: Stores VID limits for this CPU 231 * @pid: Stores PID parameters for this CPU 232 * @last_sample_time: Last Sample time 233 * @prev_aperf: Last APERF value read from APERF MSR 234 * @prev_mperf: Last MPERF value read from MPERF MSR 235 * @prev_tsc: Last timestamp counter (TSC) value 236 * @prev_cummulative_iowait: IO Wait time difference from last and 237 * current sample 238 * @sample: Storage for storing last Sample data 239 * @perf_limits: Capacity limits unique to this CPU 240 * @acpi_perf_data: Stores ACPI perf information read from _PSS 241 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 242 * @epp_powersave: Last saved HWP energy performance preference 243 * (EPP) or energy performance bias (EPB), 244 * when policy switched to performance 245 * @epp_policy: Last saved policy used to set EPP/EPB 246 * @epp_default: Power on default HWP energy performance 247 * preference/bias 248 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline 249 * operation 250 * 251 * This structure stores per CPU instance data for all CPUs. 252 */ 253 struct cpudata { 254 int cpu; 255 256 unsigned int policy; 257 struct update_util_data update_util; 258 bool update_util_set; 259 260 struct pstate_data pstate; 261 struct vid_data vid; 262 struct _pid pid; 263 264 u64 last_update; 265 u64 last_sample_time; 266 u64 prev_aperf; 267 u64 prev_mperf; 268 u64 prev_tsc; 269 u64 prev_cummulative_iowait; 270 struct sample sample; 271 struct perf_limits perf_limits; 272 #ifdef CONFIG_ACPI 273 struct acpi_processor_performance acpi_perf_data; 274 bool valid_pss_table; 275 #endif 276 unsigned int iowait_boost; 277 s16 epp_powersave; 278 s16 epp_policy; 279 s16 epp_default; 280 s16 epp_saved; 281 }; 282 283 static struct cpudata **all_cpu_data; 284 285 /** 286 * struct pstate_adjust_policy - Stores static PID configuration data 287 * @sample_rate_ms: PID calculation sample rate in ms 288 * @sample_rate_ns: Sample rate calculation in ns 289 * @deadband: PID deadband 290 * @setpoint: PID Setpoint 291 * @p_gain_pct: PID proportional gain 292 * @i_gain_pct: PID integral gain 293 * @d_gain_pct: PID derivative gain 294 * 295 * Stores per CPU model static PID configuration data. 296 */ 297 struct pstate_adjust_policy { 298 int sample_rate_ms; 299 s64 sample_rate_ns; 300 int deadband; 301 int setpoint; 302 int p_gain_pct; 303 int d_gain_pct; 304 int i_gain_pct; 305 }; 306 307 /** 308 * struct pstate_funcs - Per CPU model specific callbacks 309 * @get_max: Callback to get maximum non turbo effective P state 310 * @get_max_physical: Callback to get maximum non turbo physical P state 311 * @get_min: Callback to get minimum P state 312 * @get_turbo: Callback to get turbo P state 313 * @get_scaling: Callback to get frequency scaling factor 314 * @get_val: Callback to convert P state to actual MSR write value 315 * @get_vid: Callback to get VID data for Atom platforms 316 * @get_target_pstate: Callback to a function to calculate next P state to use 317 * 318 * Core and Atom CPU models have different way to get P State limits. This 319 * structure is used to store those callbacks. 320 */ 321 struct pstate_funcs { 322 int (*get_max)(void); 323 int (*get_max_physical)(void); 324 int (*get_min)(void); 325 int (*get_turbo)(void); 326 int (*get_scaling)(void); 327 u64 (*get_val)(struct cpudata*, int pstate); 328 void (*get_vid)(struct cpudata *); 329 int32_t (*get_target_pstate)(struct cpudata *); 330 }; 331 332 /** 333 * struct cpu_defaults- Per CPU model default config data 334 * @pid_policy: PID config data 335 * @funcs: Callback function data 336 */ 337 struct cpu_defaults { 338 struct pstate_adjust_policy pid_policy; 339 struct pstate_funcs funcs; 340 }; 341 342 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 343 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 344 345 static struct pstate_adjust_policy pid_params __read_mostly; 346 static struct pstate_funcs pstate_funcs __read_mostly; 347 static int hwp_active __read_mostly; 348 static bool per_cpu_limits __read_mostly; 349 350 static bool driver_registered __read_mostly; 351 352 #ifdef CONFIG_ACPI 353 static bool acpi_ppc; 354 #endif 355 356 static struct global_params global; 357 358 static DEFINE_MUTEX(intel_pstate_driver_lock); 359 static DEFINE_MUTEX(intel_pstate_limits_lock); 360 361 #ifdef CONFIG_ACPI 362 363 static bool intel_pstate_get_ppc_enable_status(void) 364 { 365 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 366 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 367 return true; 368 369 return acpi_ppc; 370 } 371 372 #ifdef CONFIG_ACPI_CPPC_LIB 373 374 /* The work item is needed to avoid CPU hotplug locking issues */ 375 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 376 { 377 sched_set_itmt_support(); 378 } 379 380 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 381 382 static void intel_pstate_set_itmt_prio(int cpu) 383 { 384 struct cppc_perf_caps cppc_perf; 385 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 386 int ret; 387 388 ret = cppc_get_perf_caps(cpu, &cppc_perf); 389 if (ret) 390 return; 391 392 /* 393 * The priorities can be set regardless of whether or not 394 * sched_set_itmt_support(true) has been called and it is valid to 395 * update them at any time after it has been called. 396 */ 397 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 398 399 if (max_highest_perf <= min_highest_perf) { 400 if (cppc_perf.highest_perf > max_highest_perf) 401 max_highest_perf = cppc_perf.highest_perf; 402 403 if (cppc_perf.highest_perf < min_highest_perf) 404 min_highest_perf = cppc_perf.highest_perf; 405 406 if (max_highest_perf > min_highest_perf) { 407 /* 408 * This code can be run during CPU online under the 409 * CPU hotplug locks, so sched_set_itmt_support() 410 * cannot be called from here. Queue up a work item 411 * to invoke it. 412 */ 413 schedule_work(&sched_itmt_work); 414 } 415 } 416 } 417 #else 418 static void intel_pstate_set_itmt_prio(int cpu) 419 { 420 } 421 #endif 422 423 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 424 { 425 struct cpudata *cpu; 426 int ret; 427 int i; 428 429 if (hwp_active) { 430 intel_pstate_set_itmt_prio(policy->cpu); 431 return; 432 } 433 434 if (!intel_pstate_get_ppc_enable_status()) 435 return; 436 437 cpu = all_cpu_data[policy->cpu]; 438 439 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 440 policy->cpu); 441 if (ret) 442 return; 443 444 /* 445 * Check if the control value in _PSS is for PERF_CTL MSR, which should 446 * guarantee that the states returned by it map to the states in our 447 * list directly. 448 */ 449 if (cpu->acpi_perf_data.control_register.space_id != 450 ACPI_ADR_SPACE_FIXED_HARDWARE) 451 goto err; 452 453 /* 454 * If there is only one entry _PSS, simply ignore _PSS and continue as 455 * usual without taking _PSS into account 456 */ 457 if (cpu->acpi_perf_data.state_count < 2) 458 goto err; 459 460 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 461 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 462 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 463 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 464 (u32) cpu->acpi_perf_data.states[i].core_frequency, 465 (u32) cpu->acpi_perf_data.states[i].power, 466 (u32) cpu->acpi_perf_data.states[i].control); 467 } 468 469 /* 470 * The _PSS table doesn't contain whole turbo frequency range. 471 * This just contains +1 MHZ above the max non turbo frequency, 472 * with control value corresponding to max turbo ratio. But 473 * when cpufreq set policy is called, it will call with this 474 * max frequency, which will cause a reduced performance as 475 * this driver uses real max turbo frequency as the max 476 * frequency. So correct this frequency in _PSS table to 477 * correct max turbo frequency based on the turbo state. 478 * Also need to convert to MHz as _PSS freq is in MHz. 479 */ 480 if (!global.turbo_disabled) 481 cpu->acpi_perf_data.states[0].core_frequency = 482 policy->cpuinfo.max_freq / 1000; 483 cpu->valid_pss_table = true; 484 pr_debug("_PPC limits will be enforced\n"); 485 486 return; 487 488 err: 489 cpu->valid_pss_table = false; 490 acpi_processor_unregister_performance(policy->cpu); 491 } 492 493 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 494 { 495 struct cpudata *cpu; 496 497 cpu = all_cpu_data[policy->cpu]; 498 if (!cpu->valid_pss_table) 499 return; 500 501 acpi_processor_unregister_performance(policy->cpu); 502 } 503 #else 504 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 505 { 506 } 507 508 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 509 { 510 } 511 #endif 512 513 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 514 int deadband, int integral) { 515 pid->setpoint = int_tofp(setpoint); 516 pid->deadband = int_tofp(deadband); 517 pid->integral = int_tofp(integral); 518 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 519 } 520 521 static inline void pid_p_gain_set(struct _pid *pid, int percent) 522 { 523 pid->p_gain = div_fp(percent, 100); 524 } 525 526 static inline void pid_i_gain_set(struct _pid *pid, int percent) 527 { 528 pid->i_gain = div_fp(percent, 100); 529 } 530 531 static inline void pid_d_gain_set(struct _pid *pid, int percent) 532 { 533 pid->d_gain = div_fp(percent, 100); 534 } 535 536 static signed int pid_calc(struct _pid *pid, int32_t busy) 537 { 538 signed int result; 539 int32_t pterm, dterm, fp_error; 540 int32_t integral_limit; 541 542 fp_error = pid->setpoint - busy; 543 544 if (abs(fp_error) <= pid->deadband) 545 return 0; 546 547 pterm = mul_fp(pid->p_gain, fp_error); 548 549 pid->integral += fp_error; 550 551 /* 552 * We limit the integral here so that it will never 553 * get higher than 30. This prevents it from becoming 554 * too large an input over long periods of time and allows 555 * it to get factored out sooner. 556 * 557 * The value of 30 was chosen through experimentation. 558 */ 559 integral_limit = int_tofp(30); 560 if (pid->integral > integral_limit) 561 pid->integral = integral_limit; 562 if (pid->integral < -integral_limit) 563 pid->integral = -integral_limit; 564 565 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 566 pid->last_err = fp_error; 567 568 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 569 result = result + (1 << (FRAC_BITS-1)); 570 return (signed int)fp_toint(result); 571 } 572 573 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 574 { 575 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 576 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 577 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 578 579 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 580 } 581 582 static inline void intel_pstate_reset_all_pid(void) 583 { 584 unsigned int cpu; 585 586 for_each_online_cpu(cpu) { 587 if (all_cpu_data[cpu]) 588 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 589 } 590 } 591 592 static inline void update_turbo_state(void) 593 { 594 u64 misc_en; 595 struct cpudata *cpu; 596 597 cpu = all_cpu_data[0]; 598 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 599 global.turbo_disabled = 600 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 601 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 602 } 603 604 static int min_perf_pct_min(void) 605 { 606 struct cpudata *cpu = all_cpu_data[0]; 607 608 return DIV_ROUND_UP(cpu->pstate.min_pstate * 100, 609 cpu->pstate.turbo_pstate); 610 } 611 612 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 613 { 614 u64 epb; 615 int ret; 616 617 if (!static_cpu_has(X86_FEATURE_EPB)) 618 return -ENXIO; 619 620 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 621 if (ret) 622 return (s16)ret; 623 624 return (s16)(epb & 0x0f); 625 } 626 627 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 628 { 629 s16 epp; 630 631 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 632 /* 633 * When hwp_req_data is 0, means that caller didn't read 634 * MSR_HWP_REQUEST, so need to read and get EPP. 635 */ 636 if (!hwp_req_data) { 637 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 638 &hwp_req_data); 639 if (epp) 640 return epp; 641 } 642 epp = (hwp_req_data >> 24) & 0xff; 643 } else { 644 /* When there is no EPP present, HWP uses EPB settings */ 645 epp = intel_pstate_get_epb(cpu_data); 646 } 647 648 return epp; 649 } 650 651 static int intel_pstate_set_epb(int cpu, s16 pref) 652 { 653 u64 epb; 654 int ret; 655 656 if (!static_cpu_has(X86_FEATURE_EPB)) 657 return -ENXIO; 658 659 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 660 if (ret) 661 return ret; 662 663 epb = (epb & ~0x0f) | pref; 664 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 665 666 return 0; 667 } 668 669 /* 670 * EPP/EPB display strings corresponding to EPP index in the 671 * energy_perf_strings[] 672 * index String 673 *------------------------------------- 674 * 0 default 675 * 1 performance 676 * 2 balance_performance 677 * 3 balance_power 678 * 4 power 679 */ 680 static const char * const energy_perf_strings[] = { 681 "default", 682 "performance", 683 "balance_performance", 684 "balance_power", 685 "power", 686 NULL 687 }; 688 689 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) 690 { 691 s16 epp; 692 int index = -EINVAL; 693 694 epp = intel_pstate_get_epp(cpu_data, 0); 695 if (epp < 0) 696 return epp; 697 698 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 699 /* 700 * Range: 701 * 0x00-0x3F : Performance 702 * 0x40-0x7F : Balance performance 703 * 0x80-0xBF : Balance power 704 * 0xC0-0xFF : Power 705 * The EPP is a 8 bit value, but our ranges restrict the 706 * value which can be set. Here only using top two bits 707 * effectively. 708 */ 709 index = (epp >> 6) + 1; 710 } else if (static_cpu_has(X86_FEATURE_EPB)) { 711 /* 712 * Range: 713 * 0x00-0x03 : Performance 714 * 0x04-0x07 : Balance performance 715 * 0x08-0x0B : Balance power 716 * 0x0C-0x0F : Power 717 * The EPB is a 4 bit value, but our ranges restrict the 718 * value which can be set. Here only using top two bits 719 * effectively. 720 */ 721 index = (epp >> 2) + 1; 722 } 723 724 return index; 725 } 726 727 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 728 int pref_index) 729 { 730 int epp = -EINVAL; 731 int ret; 732 733 if (!pref_index) 734 epp = cpu_data->epp_default; 735 736 mutex_lock(&intel_pstate_limits_lock); 737 738 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 739 u64 value; 740 741 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); 742 if (ret) 743 goto return_pref; 744 745 value &= ~GENMASK_ULL(31, 24); 746 747 /* 748 * If epp is not default, convert from index into 749 * energy_perf_strings to epp value, by shifting 6 750 * bits left to use only top two bits in epp. 751 * The resultant epp need to shifted by 24 bits to 752 * epp position in MSR_HWP_REQUEST. 753 */ 754 if (epp == -EINVAL) 755 epp = (pref_index - 1) << 6; 756 757 value |= (u64)epp << 24; 758 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); 759 } else { 760 if (epp == -EINVAL) 761 epp = (pref_index - 1) << 2; 762 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 763 } 764 return_pref: 765 mutex_unlock(&intel_pstate_limits_lock); 766 767 return ret; 768 } 769 770 static ssize_t show_energy_performance_available_preferences( 771 struct cpufreq_policy *policy, char *buf) 772 { 773 int i = 0; 774 int ret = 0; 775 776 while (energy_perf_strings[i] != NULL) 777 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 778 779 ret += sprintf(&buf[ret], "\n"); 780 781 return ret; 782 } 783 784 cpufreq_freq_attr_ro(energy_performance_available_preferences); 785 786 static ssize_t store_energy_performance_preference( 787 struct cpufreq_policy *policy, const char *buf, size_t count) 788 { 789 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 790 char str_preference[21]; 791 int ret, i = 0; 792 793 ret = sscanf(buf, "%20s", str_preference); 794 if (ret != 1) 795 return -EINVAL; 796 797 while (energy_perf_strings[i] != NULL) { 798 if (!strcmp(str_preference, energy_perf_strings[i])) { 799 intel_pstate_set_energy_pref_index(cpu_data, i); 800 return count; 801 } 802 ++i; 803 } 804 805 return -EINVAL; 806 } 807 808 static ssize_t show_energy_performance_preference( 809 struct cpufreq_policy *policy, char *buf) 810 { 811 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 812 int preference; 813 814 preference = intel_pstate_get_energy_pref_index(cpu_data); 815 if (preference < 0) 816 return preference; 817 818 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 819 } 820 821 cpufreq_freq_attr_rw(energy_performance_preference); 822 823 static struct freq_attr *hwp_cpufreq_attrs[] = { 824 &energy_performance_preference, 825 &energy_performance_available_preferences, 826 NULL, 827 }; 828 829 static void intel_pstate_hwp_set(struct cpufreq_policy *policy) 830 { 831 int min, hw_min, max, hw_max, cpu; 832 u64 value, cap; 833 834 for_each_cpu(cpu, policy->cpus) { 835 struct cpudata *cpu_data = all_cpu_data[cpu]; 836 struct perf_limits *perf_limits = &cpu_data->perf_limits; 837 s16 epp; 838 839 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 840 hw_min = HWP_LOWEST_PERF(cap); 841 if (global.no_turbo) 842 hw_max = HWP_GUARANTEED_PERF(cap); 843 else 844 hw_max = HWP_HIGHEST_PERF(cap); 845 846 max = fp_ext_toint(hw_max * perf_limits->max_perf); 847 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 848 min = max; 849 else 850 min = fp_ext_toint(hw_max * perf_limits->min_perf); 851 852 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 853 854 value &= ~HWP_MIN_PERF(~0L); 855 value |= HWP_MIN_PERF(min); 856 857 value &= ~HWP_MAX_PERF(~0L); 858 value |= HWP_MAX_PERF(max); 859 860 if (cpu_data->epp_policy == cpu_data->policy) 861 goto skip_epp; 862 863 cpu_data->epp_policy = cpu_data->policy; 864 865 if (cpu_data->epp_saved >= 0) { 866 epp = cpu_data->epp_saved; 867 cpu_data->epp_saved = -EINVAL; 868 goto update_epp; 869 } 870 871 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 872 epp = intel_pstate_get_epp(cpu_data, value); 873 cpu_data->epp_powersave = epp; 874 /* If EPP read was failed, then don't try to write */ 875 if (epp < 0) 876 goto skip_epp; 877 878 879 epp = 0; 880 } else { 881 /* skip setting EPP, when saved value is invalid */ 882 if (cpu_data->epp_powersave < 0) 883 goto skip_epp; 884 885 /* 886 * No need to restore EPP when it is not zero. This 887 * means: 888 * - Policy is not changed 889 * - user has manually changed 890 * - Error reading EPB 891 */ 892 epp = intel_pstate_get_epp(cpu_data, value); 893 if (epp) 894 goto skip_epp; 895 896 epp = cpu_data->epp_powersave; 897 } 898 update_epp: 899 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 900 value &= ~GENMASK_ULL(31, 24); 901 value |= (u64)epp << 24; 902 } else { 903 intel_pstate_set_epb(cpu, epp); 904 } 905 skip_epp: 906 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 907 } 908 } 909 910 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) 911 { 912 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 913 914 if (!hwp_active) 915 return 0; 916 917 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); 918 919 return 0; 920 } 921 922 static int intel_pstate_resume(struct cpufreq_policy *policy) 923 { 924 if (!hwp_active) 925 return 0; 926 927 mutex_lock(&intel_pstate_limits_lock); 928 929 all_cpu_data[policy->cpu]->epp_policy = 0; 930 intel_pstate_hwp_set(policy); 931 932 mutex_unlock(&intel_pstate_limits_lock); 933 934 return 0; 935 } 936 937 static void intel_pstate_update_policies(void) 938 { 939 int cpu; 940 941 for_each_possible_cpu(cpu) 942 cpufreq_update_policy(cpu); 943 } 944 945 /************************** debugfs begin ************************/ 946 static int pid_param_set(void *data, u64 val) 947 { 948 *(u32 *)data = val; 949 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 950 intel_pstate_reset_all_pid(); 951 return 0; 952 } 953 954 static int pid_param_get(void *data, u64 *val) 955 { 956 *val = *(u32 *)data; 957 return 0; 958 } 959 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 960 961 static struct dentry *debugfs_parent; 962 963 struct pid_param { 964 char *name; 965 void *value; 966 struct dentry *dentry; 967 }; 968 969 static struct pid_param pid_files[] = { 970 {"sample_rate_ms", &pid_params.sample_rate_ms, }, 971 {"d_gain_pct", &pid_params.d_gain_pct, }, 972 {"i_gain_pct", &pid_params.i_gain_pct, }, 973 {"deadband", &pid_params.deadband, }, 974 {"setpoint", &pid_params.setpoint, }, 975 {"p_gain_pct", &pid_params.p_gain_pct, }, 976 {NULL, NULL, } 977 }; 978 979 static void intel_pstate_debug_expose_params(void) 980 { 981 int i; 982 983 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 984 if (IS_ERR_OR_NULL(debugfs_parent)) 985 return; 986 987 for (i = 0; pid_files[i].name; i++) { 988 struct dentry *dentry; 989 990 dentry = debugfs_create_file(pid_files[i].name, 0660, 991 debugfs_parent, pid_files[i].value, 992 &fops_pid_param); 993 if (!IS_ERR(dentry)) 994 pid_files[i].dentry = dentry; 995 } 996 } 997 998 static void intel_pstate_debug_hide_params(void) 999 { 1000 int i; 1001 1002 if (IS_ERR_OR_NULL(debugfs_parent)) 1003 return; 1004 1005 for (i = 0; pid_files[i].name; i++) { 1006 debugfs_remove(pid_files[i].dentry); 1007 pid_files[i].dentry = NULL; 1008 } 1009 1010 debugfs_remove(debugfs_parent); 1011 debugfs_parent = NULL; 1012 } 1013 1014 /************************** debugfs end ************************/ 1015 1016 /************************** sysfs begin ************************/ 1017 #define show_one(file_name, object) \ 1018 static ssize_t show_##file_name \ 1019 (struct kobject *kobj, struct attribute *attr, char *buf) \ 1020 { \ 1021 return sprintf(buf, "%u\n", global.object); \ 1022 } 1023 1024 static ssize_t intel_pstate_show_status(char *buf); 1025 static int intel_pstate_update_status(const char *buf, size_t size); 1026 1027 static ssize_t show_status(struct kobject *kobj, 1028 struct attribute *attr, char *buf) 1029 { 1030 ssize_t ret; 1031 1032 mutex_lock(&intel_pstate_driver_lock); 1033 ret = intel_pstate_show_status(buf); 1034 mutex_unlock(&intel_pstate_driver_lock); 1035 1036 return ret; 1037 } 1038 1039 static ssize_t store_status(struct kobject *a, struct attribute *b, 1040 const char *buf, size_t count) 1041 { 1042 char *p = memchr(buf, '\n', count); 1043 int ret; 1044 1045 mutex_lock(&intel_pstate_driver_lock); 1046 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1047 mutex_unlock(&intel_pstate_driver_lock); 1048 1049 return ret < 0 ? ret : count; 1050 } 1051 1052 static ssize_t show_turbo_pct(struct kobject *kobj, 1053 struct attribute *attr, char *buf) 1054 { 1055 struct cpudata *cpu; 1056 int total, no_turbo, turbo_pct; 1057 uint32_t turbo_fp; 1058 1059 mutex_lock(&intel_pstate_driver_lock); 1060 1061 if (!driver_registered) { 1062 mutex_unlock(&intel_pstate_driver_lock); 1063 return -EAGAIN; 1064 } 1065 1066 cpu = all_cpu_data[0]; 1067 1068 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1069 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1070 turbo_fp = div_fp(no_turbo, total); 1071 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1072 1073 mutex_unlock(&intel_pstate_driver_lock); 1074 1075 return sprintf(buf, "%u\n", turbo_pct); 1076 } 1077 1078 static ssize_t show_num_pstates(struct kobject *kobj, 1079 struct attribute *attr, char *buf) 1080 { 1081 struct cpudata *cpu; 1082 int total; 1083 1084 mutex_lock(&intel_pstate_driver_lock); 1085 1086 if (!driver_registered) { 1087 mutex_unlock(&intel_pstate_driver_lock); 1088 return -EAGAIN; 1089 } 1090 1091 cpu = all_cpu_data[0]; 1092 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1093 1094 mutex_unlock(&intel_pstate_driver_lock); 1095 1096 return sprintf(buf, "%u\n", total); 1097 } 1098 1099 static ssize_t show_no_turbo(struct kobject *kobj, 1100 struct attribute *attr, char *buf) 1101 { 1102 ssize_t ret; 1103 1104 mutex_lock(&intel_pstate_driver_lock); 1105 1106 if (!driver_registered) { 1107 mutex_unlock(&intel_pstate_driver_lock); 1108 return -EAGAIN; 1109 } 1110 1111 update_turbo_state(); 1112 if (global.turbo_disabled) 1113 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1114 else 1115 ret = sprintf(buf, "%u\n", global.no_turbo); 1116 1117 mutex_unlock(&intel_pstate_driver_lock); 1118 1119 return ret; 1120 } 1121 1122 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 1123 const char *buf, size_t count) 1124 { 1125 unsigned int input; 1126 int ret; 1127 1128 ret = sscanf(buf, "%u", &input); 1129 if (ret != 1) 1130 return -EINVAL; 1131 1132 mutex_lock(&intel_pstate_driver_lock); 1133 1134 if (!driver_registered) { 1135 mutex_unlock(&intel_pstate_driver_lock); 1136 return -EAGAIN; 1137 } 1138 1139 mutex_lock(&intel_pstate_limits_lock); 1140 1141 update_turbo_state(); 1142 if (global.turbo_disabled) { 1143 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 1144 mutex_unlock(&intel_pstate_limits_lock); 1145 mutex_unlock(&intel_pstate_driver_lock); 1146 return -EPERM; 1147 } 1148 1149 global.no_turbo = clamp_t(int, input, 0, 1); 1150 1151 if (global.no_turbo) { 1152 struct cpudata *cpu = all_cpu_data[0]; 1153 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1154 1155 /* Squash the global minimum into the permitted range. */ 1156 if (global.min_perf_pct > pct) 1157 global.min_perf_pct = pct; 1158 } 1159 1160 mutex_unlock(&intel_pstate_limits_lock); 1161 1162 intel_pstate_update_policies(); 1163 1164 mutex_unlock(&intel_pstate_driver_lock); 1165 1166 return count; 1167 } 1168 1169 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 1170 const char *buf, size_t count) 1171 { 1172 unsigned int input; 1173 int ret; 1174 1175 ret = sscanf(buf, "%u", &input); 1176 if (ret != 1) 1177 return -EINVAL; 1178 1179 mutex_lock(&intel_pstate_driver_lock); 1180 1181 if (!driver_registered) { 1182 mutex_unlock(&intel_pstate_driver_lock); 1183 return -EAGAIN; 1184 } 1185 1186 mutex_lock(&intel_pstate_limits_lock); 1187 1188 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1189 1190 mutex_unlock(&intel_pstate_limits_lock); 1191 1192 intel_pstate_update_policies(); 1193 1194 mutex_unlock(&intel_pstate_driver_lock); 1195 1196 return count; 1197 } 1198 1199 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 1200 const char *buf, size_t count) 1201 { 1202 unsigned int input; 1203 int ret; 1204 1205 ret = sscanf(buf, "%u", &input); 1206 if (ret != 1) 1207 return -EINVAL; 1208 1209 mutex_lock(&intel_pstate_driver_lock); 1210 1211 if (!driver_registered) { 1212 mutex_unlock(&intel_pstate_driver_lock); 1213 return -EAGAIN; 1214 } 1215 1216 mutex_lock(&intel_pstate_limits_lock); 1217 1218 global.min_perf_pct = clamp_t(int, input, 1219 min_perf_pct_min(), global.max_perf_pct); 1220 1221 mutex_unlock(&intel_pstate_limits_lock); 1222 1223 intel_pstate_update_policies(); 1224 1225 mutex_unlock(&intel_pstate_driver_lock); 1226 1227 return count; 1228 } 1229 1230 show_one(max_perf_pct, max_perf_pct); 1231 show_one(min_perf_pct, min_perf_pct); 1232 1233 define_one_global_rw(status); 1234 define_one_global_rw(no_turbo); 1235 define_one_global_rw(max_perf_pct); 1236 define_one_global_rw(min_perf_pct); 1237 define_one_global_ro(turbo_pct); 1238 define_one_global_ro(num_pstates); 1239 1240 static struct attribute *intel_pstate_attributes[] = { 1241 &status.attr, 1242 &no_turbo.attr, 1243 &turbo_pct.attr, 1244 &num_pstates.attr, 1245 NULL 1246 }; 1247 1248 static struct attribute_group intel_pstate_attr_group = { 1249 .attrs = intel_pstate_attributes, 1250 }; 1251 1252 static void __init intel_pstate_sysfs_expose_params(void) 1253 { 1254 struct kobject *intel_pstate_kobject; 1255 int rc; 1256 1257 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1258 &cpu_subsys.dev_root->kobj); 1259 if (WARN_ON(!intel_pstate_kobject)) 1260 return; 1261 1262 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1263 if (WARN_ON(rc)) 1264 return; 1265 1266 /* 1267 * If per cpu limits are enforced there are no global limits, so 1268 * return without creating max/min_perf_pct attributes 1269 */ 1270 if (per_cpu_limits) 1271 return; 1272 1273 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1274 WARN_ON(rc); 1275 1276 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1277 WARN_ON(rc); 1278 1279 } 1280 /************************** sysfs end ************************/ 1281 1282 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1283 { 1284 /* First disable HWP notification interrupt as we don't process them */ 1285 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1286 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1287 1288 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1289 cpudata->epp_policy = 0; 1290 if (cpudata->epp_default == -EINVAL) 1291 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1292 } 1293 1294 #define MSR_IA32_POWER_CTL_BIT_EE 19 1295 1296 /* Disable energy efficiency optimization */ 1297 static void intel_pstate_disable_ee(int cpu) 1298 { 1299 u64 power_ctl; 1300 int ret; 1301 1302 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); 1303 if (ret) 1304 return; 1305 1306 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { 1307 pr_info("Disabling energy efficiency optimization\n"); 1308 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1309 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); 1310 } 1311 } 1312 1313 static int atom_get_min_pstate(void) 1314 { 1315 u64 value; 1316 1317 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1318 return (value >> 8) & 0x7F; 1319 } 1320 1321 static int atom_get_max_pstate(void) 1322 { 1323 u64 value; 1324 1325 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1326 return (value >> 16) & 0x7F; 1327 } 1328 1329 static int atom_get_turbo_pstate(void) 1330 { 1331 u64 value; 1332 1333 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1334 return value & 0x7F; 1335 } 1336 1337 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1338 { 1339 u64 val; 1340 int32_t vid_fp; 1341 u32 vid; 1342 1343 val = (u64)pstate << 8; 1344 if (global.no_turbo && !global.turbo_disabled) 1345 val |= (u64)1 << 32; 1346 1347 vid_fp = cpudata->vid.min + mul_fp( 1348 int_tofp(pstate - cpudata->pstate.min_pstate), 1349 cpudata->vid.ratio); 1350 1351 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1352 vid = ceiling_fp(vid_fp); 1353 1354 if (pstate > cpudata->pstate.max_pstate) 1355 vid = cpudata->vid.turbo; 1356 1357 return val | vid; 1358 } 1359 1360 static int silvermont_get_scaling(void) 1361 { 1362 u64 value; 1363 int i; 1364 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1365 static int silvermont_freq_table[] = { 1366 83300, 100000, 133300, 116700, 80000}; 1367 1368 rdmsrl(MSR_FSB_FREQ, value); 1369 i = value & 0x7; 1370 WARN_ON(i > 4); 1371 1372 return silvermont_freq_table[i]; 1373 } 1374 1375 static int airmont_get_scaling(void) 1376 { 1377 u64 value; 1378 int i; 1379 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1380 static int airmont_freq_table[] = { 1381 83300, 100000, 133300, 116700, 80000, 1382 93300, 90000, 88900, 87500}; 1383 1384 rdmsrl(MSR_FSB_FREQ, value); 1385 i = value & 0xF; 1386 WARN_ON(i > 8); 1387 1388 return airmont_freq_table[i]; 1389 } 1390 1391 static void atom_get_vid(struct cpudata *cpudata) 1392 { 1393 u64 value; 1394 1395 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1396 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1397 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1398 cpudata->vid.ratio = div_fp( 1399 cpudata->vid.max - cpudata->vid.min, 1400 int_tofp(cpudata->pstate.max_pstate - 1401 cpudata->pstate.min_pstate)); 1402 1403 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1404 cpudata->vid.turbo = value & 0x7f; 1405 } 1406 1407 static int core_get_min_pstate(void) 1408 { 1409 u64 value; 1410 1411 rdmsrl(MSR_PLATFORM_INFO, value); 1412 return (value >> 40) & 0xFF; 1413 } 1414 1415 static int core_get_max_pstate_physical(void) 1416 { 1417 u64 value; 1418 1419 rdmsrl(MSR_PLATFORM_INFO, value); 1420 return (value >> 8) & 0xFF; 1421 } 1422 1423 static int core_get_tdp_ratio(u64 plat_info) 1424 { 1425 /* Check how many TDP levels present */ 1426 if (plat_info & 0x600000000) { 1427 u64 tdp_ctrl; 1428 u64 tdp_ratio; 1429 int tdp_msr; 1430 int err; 1431 1432 /* Get the TDP level (0, 1, 2) to get ratios */ 1433 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1434 if (err) 1435 return err; 1436 1437 /* TDP MSR are continuous starting at 0x648 */ 1438 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1439 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1440 if (err) 1441 return err; 1442 1443 /* For level 1 and 2, bits[23:16] contain the ratio */ 1444 if (tdp_ctrl & 0x03) 1445 tdp_ratio >>= 16; 1446 1447 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1448 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1449 1450 return (int)tdp_ratio; 1451 } 1452 1453 return -ENXIO; 1454 } 1455 1456 static int core_get_max_pstate(void) 1457 { 1458 u64 tar; 1459 u64 plat_info; 1460 int max_pstate; 1461 int tdp_ratio; 1462 int err; 1463 1464 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1465 max_pstate = (plat_info >> 8) & 0xFF; 1466 1467 tdp_ratio = core_get_tdp_ratio(plat_info); 1468 if (tdp_ratio <= 0) 1469 return max_pstate; 1470 1471 if (hwp_active) { 1472 /* Turbo activation ratio is not used on HWP platforms */ 1473 return tdp_ratio; 1474 } 1475 1476 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1477 if (!err) { 1478 int tar_levels; 1479 1480 /* Do some sanity checking for safety */ 1481 tar_levels = tar & 0xff; 1482 if (tdp_ratio - 1 == tar_levels) { 1483 max_pstate = tar_levels; 1484 pr_debug("max_pstate=TAC %x\n", max_pstate); 1485 } 1486 } 1487 1488 return max_pstate; 1489 } 1490 1491 static int core_get_turbo_pstate(void) 1492 { 1493 u64 value; 1494 int nont, ret; 1495 1496 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1497 nont = core_get_max_pstate(); 1498 ret = (value) & 255; 1499 if (ret <= nont) 1500 ret = nont; 1501 return ret; 1502 } 1503 1504 static inline int core_get_scaling(void) 1505 { 1506 return 100000; 1507 } 1508 1509 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1510 { 1511 u64 val; 1512 1513 val = (u64)pstate << 8; 1514 if (global.no_turbo && !global.turbo_disabled) 1515 val |= (u64)1 << 32; 1516 1517 return val; 1518 } 1519 1520 static int knl_get_turbo_pstate(void) 1521 { 1522 u64 value; 1523 int nont, ret; 1524 1525 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1526 nont = core_get_max_pstate(); 1527 ret = (((value) >> 8) & 0xFF); 1528 if (ret <= nont) 1529 ret = nont; 1530 return ret; 1531 } 1532 1533 static struct cpu_defaults core_params = { 1534 .pid_policy = { 1535 .sample_rate_ms = 10, 1536 .deadband = 0, 1537 .setpoint = 97, 1538 .p_gain_pct = 20, 1539 .d_gain_pct = 0, 1540 .i_gain_pct = 0, 1541 }, 1542 .funcs = { 1543 .get_max = core_get_max_pstate, 1544 .get_max_physical = core_get_max_pstate_physical, 1545 .get_min = core_get_min_pstate, 1546 .get_turbo = core_get_turbo_pstate, 1547 .get_scaling = core_get_scaling, 1548 .get_val = core_get_val, 1549 .get_target_pstate = get_target_pstate_use_performance, 1550 }, 1551 }; 1552 1553 static const struct cpu_defaults silvermont_params = { 1554 .pid_policy = { 1555 .sample_rate_ms = 10, 1556 .deadband = 0, 1557 .setpoint = 60, 1558 .p_gain_pct = 14, 1559 .d_gain_pct = 0, 1560 .i_gain_pct = 4, 1561 }, 1562 .funcs = { 1563 .get_max = atom_get_max_pstate, 1564 .get_max_physical = atom_get_max_pstate, 1565 .get_min = atom_get_min_pstate, 1566 .get_turbo = atom_get_turbo_pstate, 1567 .get_val = atom_get_val, 1568 .get_scaling = silvermont_get_scaling, 1569 .get_vid = atom_get_vid, 1570 .get_target_pstate = get_target_pstate_use_cpu_load, 1571 }, 1572 }; 1573 1574 static const struct cpu_defaults airmont_params = { 1575 .pid_policy = { 1576 .sample_rate_ms = 10, 1577 .deadband = 0, 1578 .setpoint = 60, 1579 .p_gain_pct = 14, 1580 .d_gain_pct = 0, 1581 .i_gain_pct = 4, 1582 }, 1583 .funcs = { 1584 .get_max = atom_get_max_pstate, 1585 .get_max_physical = atom_get_max_pstate, 1586 .get_min = atom_get_min_pstate, 1587 .get_turbo = atom_get_turbo_pstate, 1588 .get_val = atom_get_val, 1589 .get_scaling = airmont_get_scaling, 1590 .get_vid = atom_get_vid, 1591 .get_target_pstate = get_target_pstate_use_cpu_load, 1592 }, 1593 }; 1594 1595 static const struct cpu_defaults knl_params = { 1596 .pid_policy = { 1597 .sample_rate_ms = 10, 1598 .deadband = 0, 1599 .setpoint = 97, 1600 .p_gain_pct = 20, 1601 .d_gain_pct = 0, 1602 .i_gain_pct = 0, 1603 }, 1604 .funcs = { 1605 .get_max = core_get_max_pstate, 1606 .get_max_physical = core_get_max_pstate_physical, 1607 .get_min = core_get_min_pstate, 1608 .get_turbo = knl_get_turbo_pstate, 1609 .get_scaling = core_get_scaling, 1610 .get_val = core_get_val, 1611 .get_target_pstate = get_target_pstate_use_performance, 1612 }, 1613 }; 1614 1615 static const struct cpu_defaults bxt_params = { 1616 .pid_policy = { 1617 .sample_rate_ms = 10, 1618 .deadband = 0, 1619 .setpoint = 60, 1620 .p_gain_pct = 14, 1621 .d_gain_pct = 0, 1622 .i_gain_pct = 4, 1623 }, 1624 .funcs = { 1625 .get_max = core_get_max_pstate, 1626 .get_max_physical = core_get_max_pstate_physical, 1627 .get_min = core_get_min_pstate, 1628 .get_turbo = core_get_turbo_pstate, 1629 .get_scaling = core_get_scaling, 1630 .get_val = core_get_val, 1631 .get_target_pstate = get_target_pstate_use_cpu_load, 1632 }, 1633 }; 1634 1635 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1636 { 1637 int max_perf = cpu->pstate.turbo_pstate; 1638 int max_perf_adj; 1639 int min_perf; 1640 struct perf_limits *perf_limits = &cpu->perf_limits; 1641 1642 if (global.no_turbo || global.turbo_disabled) 1643 max_perf = cpu->pstate.max_pstate; 1644 1645 /* 1646 * performance can be limited by user through sysfs, by cpufreq 1647 * policy, or by cpu specific default values determined through 1648 * experimentation. 1649 */ 1650 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf); 1651 *max = clamp_t(int, max_perf_adj, 1652 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1653 1654 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf); 1655 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1656 } 1657 1658 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1659 { 1660 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1661 cpu->pstate.current_pstate = pstate; 1662 /* 1663 * Generally, there is no guarantee that this code will always run on 1664 * the CPU being updated, so force the register update to run on the 1665 * right CPU. 1666 */ 1667 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1668 pstate_funcs.get_val(cpu, pstate)); 1669 } 1670 1671 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1672 { 1673 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1674 } 1675 1676 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1677 { 1678 int min_pstate, max_pstate; 1679 1680 update_turbo_state(); 1681 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); 1682 intel_pstate_set_pstate(cpu, max_pstate); 1683 } 1684 1685 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1686 { 1687 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1688 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1689 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1690 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1691 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1692 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; 1693 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1694 1695 if (pstate_funcs.get_vid) 1696 pstate_funcs.get_vid(cpu); 1697 1698 intel_pstate_set_min_pstate(cpu); 1699 } 1700 1701 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1702 { 1703 struct sample *sample = &cpu->sample; 1704 1705 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1706 } 1707 1708 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1709 { 1710 u64 aperf, mperf; 1711 unsigned long flags; 1712 u64 tsc; 1713 1714 local_irq_save(flags); 1715 rdmsrl(MSR_IA32_APERF, aperf); 1716 rdmsrl(MSR_IA32_MPERF, mperf); 1717 tsc = rdtsc(); 1718 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1719 local_irq_restore(flags); 1720 return false; 1721 } 1722 local_irq_restore(flags); 1723 1724 cpu->last_sample_time = cpu->sample.time; 1725 cpu->sample.time = time; 1726 cpu->sample.aperf = aperf; 1727 cpu->sample.mperf = mperf; 1728 cpu->sample.tsc = tsc; 1729 cpu->sample.aperf -= cpu->prev_aperf; 1730 cpu->sample.mperf -= cpu->prev_mperf; 1731 cpu->sample.tsc -= cpu->prev_tsc; 1732 1733 cpu->prev_aperf = aperf; 1734 cpu->prev_mperf = mperf; 1735 cpu->prev_tsc = tsc; 1736 /* 1737 * First time this function is invoked in a given cycle, all of the 1738 * previous sample data fields are equal to zero or stale and they must 1739 * be populated with meaningful numbers for things to work, so assume 1740 * that sample.time will always be reset before setting the utilization 1741 * update hook and make the caller skip the sample then. 1742 */ 1743 return !!cpu->last_sample_time; 1744 } 1745 1746 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1747 { 1748 return mul_ext_fp(cpu->sample.core_avg_perf, 1749 cpu->pstate.max_pstate_physical * cpu->pstate.scaling); 1750 } 1751 1752 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1753 { 1754 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1755 cpu->sample.core_avg_perf); 1756 } 1757 1758 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1759 { 1760 struct sample *sample = &cpu->sample; 1761 int32_t busy_frac, boost; 1762 int target, avg_pstate; 1763 1764 busy_frac = div_fp(sample->mperf, sample->tsc); 1765 1766 boost = cpu->iowait_boost; 1767 cpu->iowait_boost >>= 1; 1768 1769 if (busy_frac < boost) 1770 busy_frac = boost; 1771 1772 sample->busy_scaled = busy_frac * 100; 1773 1774 target = global.no_turbo || global.turbo_disabled ? 1775 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1776 target += target >> 2; 1777 target = mul_fp(target, busy_frac); 1778 if (target < cpu->pstate.min_pstate) 1779 target = cpu->pstate.min_pstate; 1780 1781 /* 1782 * If the average P-state during the previous cycle was higher than the 1783 * current target, add 50% of the difference to the target to reduce 1784 * possible performance oscillations and offset possible performance 1785 * loss related to moving the workload from one CPU to another within 1786 * a package/module. 1787 */ 1788 avg_pstate = get_avg_pstate(cpu); 1789 if (avg_pstate > target) 1790 target += (avg_pstate - target) >> 1; 1791 1792 return target; 1793 } 1794 1795 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1796 { 1797 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; 1798 u64 duration_ns; 1799 1800 /* 1801 * perf_scaled is the ratio of the average P-state during the last 1802 * sampling period to the P-state requested last time (in percent). 1803 * 1804 * That measures the system's response to the previous P-state 1805 * selection. 1806 */ 1807 max_pstate = cpu->pstate.max_pstate_physical; 1808 current_pstate = cpu->pstate.current_pstate; 1809 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, 1810 div_fp(100 * max_pstate, current_pstate)); 1811 1812 /* 1813 * Since our utilization update callback will not run unless we are 1814 * in C0, check if the actual elapsed time is significantly greater (3x) 1815 * than our sample interval. If it is, then we were idle for a long 1816 * enough period of time to adjust our performance metric. 1817 */ 1818 duration_ns = cpu->sample.time - cpu->last_sample_time; 1819 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1820 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1821 perf_scaled = mul_fp(perf_scaled, sample_ratio); 1822 } else { 1823 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1824 if (sample_ratio < int_tofp(1)) 1825 perf_scaled = 0; 1826 } 1827 1828 cpu->sample.busy_scaled = perf_scaled; 1829 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); 1830 } 1831 1832 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 1833 { 1834 int max_perf, min_perf; 1835 1836 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1837 pstate = clamp_t(int, pstate, min_perf, max_perf); 1838 return pstate; 1839 } 1840 1841 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1842 { 1843 if (pstate == cpu->pstate.current_pstate) 1844 return; 1845 1846 cpu->pstate.current_pstate = pstate; 1847 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1848 } 1849 1850 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1851 { 1852 int from, target_pstate; 1853 struct sample *sample; 1854 1855 from = cpu->pstate.current_pstate; 1856 1857 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ? 1858 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu); 1859 1860 update_turbo_state(); 1861 1862 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 1863 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 1864 intel_pstate_update_pstate(cpu, target_pstate); 1865 1866 sample = &cpu->sample; 1867 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1868 fp_toint(sample->busy_scaled), 1869 from, 1870 cpu->pstate.current_pstate, 1871 sample->mperf, 1872 sample->aperf, 1873 sample->tsc, 1874 get_avg_frequency(cpu), 1875 fp_toint(cpu->iowait_boost * 100)); 1876 } 1877 1878 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1879 unsigned int flags) 1880 { 1881 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1882 u64 delta_ns; 1883 1884 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) { 1885 if (flags & SCHED_CPUFREQ_IOWAIT) { 1886 cpu->iowait_boost = int_tofp(1); 1887 } else if (cpu->iowait_boost) { 1888 /* Clear iowait_boost if the CPU may have been idle. */ 1889 delta_ns = time - cpu->last_update; 1890 if (delta_ns > TICK_NSEC) 1891 cpu->iowait_boost = 0; 1892 } 1893 cpu->last_update = time; 1894 } 1895 1896 delta_ns = time - cpu->sample.time; 1897 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1898 bool sample_taken = intel_pstate_sample(cpu, time); 1899 1900 if (sample_taken) { 1901 intel_pstate_calc_avg_perf(cpu); 1902 if (!hwp_active) 1903 intel_pstate_adjust_busy_pstate(cpu); 1904 } 1905 } 1906 } 1907 1908 #define ICPU(model, policy) \ 1909 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1910 (unsigned long)&policy } 1911 1912 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1913 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), 1914 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), 1915 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), 1916 ICPU(INTEL_FAM6_IVYBRIDGE, core_params), 1917 ICPU(INTEL_FAM6_HASWELL_CORE, core_params), 1918 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), 1919 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), 1920 ICPU(INTEL_FAM6_HASWELL_X, core_params), 1921 ICPU(INTEL_FAM6_HASWELL_ULT, core_params), 1922 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), 1923 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), 1924 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), 1925 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), 1926 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1927 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), 1928 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1929 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), 1930 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params), 1931 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), 1932 {} 1933 }; 1934 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1935 1936 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1937 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1938 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1939 ICPU(INTEL_FAM6_SKYLAKE_X, core_params), 1940 {} 1941 }; 1942 1943 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 1944 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params), 1945 {} 1946 }; 1947 1948 static int intel_pstate_init_cpu(unsigned int cpunum) 1949 { 1950 struct cpudata *cpu; 1951 1952 cpu = all_cpu_data[cpunum]; 1953 1954 if (!cpu) { 1955 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 1956 if (!cpu) 1957 return -ENOMEM; 1958 1959 all_cpu_data[cpunum] = cpu; 1960 1961 cpu->epp_default = -EINVAL; 1962 cpu->epp_powersave = -EINVAL; 1963 cpu->epp_saved = -EINVAL; 1964 } 1965 1966 cpu = all_cpu_data[cpunum]; 1967 1968 cpu->cpu = cpunum; 1969 1970 if (hwp_active) { 1971 const struct x86_cpu_id *id; 1972 1973 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 1974 if (id) 1975 intel_pstate_disable_ee(cpunum); 1976 1977 intel_pstate_hwp_enable(cpu); 1978 pid_params.sample_rate_ms = 50; 1979 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1980 } 1981 1982 intel_pstate_get_cpu_pstates(cpu); 1983 1984 intel_pstate_busy_pid_reset(cpu); 1985 1986 pr_debug("controlling: cpu %d\n", cpunum); 1987 1988 return 0; 1989 } 1990 1991 static unsigned int intel_pstate_get(unsigned int cpu_num) 1992 { 1993 struct cpudata *cpu = all_cpu_data[cpu_num]; 1994 1995 return cpu ? get_avg_frequency(cpu) : 0; 1996 } 1997 1998 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1999 { 2000 struct cpudata *cpu = all_cpu_data[cpu_num]; 2001 2002 if (cpu->update_util_set) 2003 return; 2004 2005 /* Prevent intel_pstate_update_util() from using stale data. */ 2006 cpu->sample.time = 0; 2007 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2008 intel_pstate_update_util); 2009 cpu->update_util_set = true; 2010 } 2011 2012 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2013 { 2014 struct cpudata *cpu_data = all_cpu_data[cpu]; 2015 2016 if (!cpu_data->update_util_set) 2017 return; 2018 2019 cpufreq_remove_update_util_hook(cpu); 2020 cpu_data->update_util_set = false; 2021 synchronize_sched(); 2022 } 2023 2024 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, 2025 struct cpudata *cpu) 2026 { 2027 struct perf_limits *limits = &cpu->perf_limits; 2028 int32_t max_policy_perf, min_policy_perf; 2029 2030 max_policy_perf = div_ext_fp(policy->max, policy->cpuinfo.max_freq); 2031 max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1)); 2032 if (policy->max == policy->min) { 2033 min_policy_perf = max_policy_perf; 2034 } else { 2035 min_policy_perf = div_ext_fp(policy->min, 2036 policy->cpuinfo.max_freq); 2037 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2038 0, max_policy_perf); 2039 } 2040 2041 /* Normalize user input to [min_perf, max_perf] */ 2042 if (per_cpu_limits) { 2043 limits->min_perf = min_policy_perf; 2044 limits->max_perf = max_policy_perf; 2045 } else { 2046 int32_t global_min, global_max; 2047 2048 /* Global limits are in percent of the maximum turbo P-state. */ 2049 global_max = percent_ext_fp(global.max_perf_pct); 2050 global_min = percent_ext_fp(global.min_perf_pct); 2051 if (policy->cpuinfo.max_freq != cpu->pstate.turbo_freq) { 2052 int32_t turbo_factor; 2053 2054 turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate, 2055 cpu->pstate.max_pstate); 2056 global_min = mul_ext_fp(global_min, turbo_factor); 2057 global_max = mul_ext_fp(global_max, turbo_factor); 2058 } 2059 global_min = clamp_t(int32_t, global_min, 0, global_max); 2060 2061 limits->min_perf = max(min_policy_perf, global_min); 2062 limits->min_perf = min(limits->min_perf, max_policy_perf); 2063 limits->max_perf = min(max_policy_perf, global_max); 2064 limits->max_perf = max(min_policy_perf, limits->max_perf); 2065 2066 /* Make sure min_perf <= max_perf */ 2067 limits->min_perf = min(limits->min_perf, limits->max_perf); 2068 } 2069 2070 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS); 2071 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS); 2072 2073 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, 2074 fp_ext_toint(limits->max_perf * 100), 2075 fp_ext_toint(limits->min_perf * 100)); 2076 } 2077 2078 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2079 { 2080 struct cpudata *cpu; 2081 2082 if (!policy->cpuinfo.max_freq) 2083 return -ENODEV; 2084 2085 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2086 policy->cpuinfo.max_freq, policy->max); 2087 2088 cpu = all_cpu_data[policy->cpu]; 2089 cpu->policy = policy->policy; 2090 2091 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2092 policy->max < policy->cpuinfo.max_freq && 2093 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 2094 pr_debug("policy->max > max non turbo frequency\n"); 2095 policy->max = policy->cpuinfo.max_freq; 2096 } 2097 2098 mutex_lock(&intel_pstate_limits_lock); 2099 2100 intel_pstate_update_perf_limits(policy, cpu); 2101 2102 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2103 /* 2104 * NOHZ_FULL CPUs need this as the governor callback may not 2105 * be invoked on them. 2106 */ 2107 intel_pstate_clear_update_util_hook(policy->cpu); 2108 intel_pstate_max_within_limits(cpu); 2109 } 2110 2111 intel_pstate_set_update_util_hook(policy->cpu); 2112 2113 if (hwp_active) 2114 intel_pstate_hwp_set(policy); 2115 2116 mutex_unlock(&intel_pstate_limits_lock); 2117 2118 return 0; 2119 } 2120 2121 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 2122 { 2123 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2124 2125 update_turbo_state(); 2126 policy->cpuinfo.max_freq = global.turbo_disabled || global.no_turbo ? 2127 cpu->pstate.max_freq : 2128 cpu->pstate.turbo_freq; 2129 2130 cpufreq_verify_within_cpu_limits(policy); 2131 2132 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 2133 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 2134 return -EINVAL; 2135 2136 return 0; 2137 } 2138 2139 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) 2140 { 2141 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); 2142 } 2143 2144 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 2145 { 2146 pr_debug("CPU %d exiting\n", policy->cpu); 2147 2148 intel_pstate_clear_update_util_hook(policy->cpu); 2149 if (hwp_active) 2150 intel_pstate_hwp_save_state(policy); 2151 else 2152 intel_cpufreq_stop_cpu(policy); 2153 } 2154 2155 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2156 { 2157 intel_pstate_exit_perf_limits(policy); 2158 2159 policy->fast_switch_possible = false; 2160 2161 return 0; 2162 } 2163 2164 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2165 { 2166 struct cpudata *cpu; 2167 int rc; 2168 2169 rc = intel_pstate_init_cpu(policy->cpu); 2170 if (rc) 2171 return rc; 2172 2173 cpu = all_cpu_data[policy->cpu]; 2174 2175 cpu->perf_limits.max_perf = int_ext_tofp(1); 2176 cpu->perf_limits.min_perf = 0; 2177 2178 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 2179 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 2180 2181 /* cpuinfo and default policy values */ 2182 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 2183 update_turbo_state(); 2184 policy->cpuinfo.max_freq = global.turbo_disabled ? 2185 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2186 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 2187 2188 intel_pstate_init_acpi_perf_limits(policy); 2189 cpumask_set_cpu(policy->cpu, policy->cpus); 2190 2191 policy->fast_switch_possible = true; 2192 2193 return 0; 2194 } 2195 2196 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2197 { 2198 int ret = __intel_pstate_cpu_init(policy); 2199 2200 if (ret) 2201 return ret; 2202 2203 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 2204 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) 2205 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 2206 else 2207 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2208 2209 return 0; 2210 } 2211 2212 static struct cpufreq_driver intel_pstate = { 2213 .flags = CPUFREQ_CONST_LOOPS, 2214 .verify = intel_pstate_verify_policy, 2215 .setpolicy = intel_pstate_set_policy, 2216 .suspend = intel_pstate_hwp_save_state, 2217 .resume = intel_pstate_resume, 2218 .get = intel_pstate_get, 2219 .init = intel_pstate_cpu_init, 2220 .exit = intel_pstate_cpu_exit, 2221 .stop_cpu = intel_pstate_stop_cpu, 2222 .name = "intel_pstate", 2223 }; 2224 2225 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) 2226 { 2227 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2228 2229 update_turbo_state(); 2230 policy->cpuinfo.max_freq = global.no_turbo || global.turbo_disabled ? 2231 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2232 2233 cpufreq_verify_within_cpu_limits(policy); 2234 2235 intel_pstate_update_perf_limits(policy, cpu); 2236 2237 return 0; 2238 } 2239 2240 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2241 unsigned int target_freq, 2242 unsigned int relation) 2243 { 2244 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2245 struct cpufreq_freqs freqs; 2246 int target_pstate; 2247 2248 update_turbo_state(); 2249 2250 freqs.old = policy->cur; 2251 freqs.new = target_freq; 2252 2253 cpufreq_freq_transition_begin(policy, &freqs); 2254 switch (relation) { 2255 case CPUFREQ_RELATION_L: 2256 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2257 break; 2258 case CPUFREQ_RELATION_H: 2259 target_pstate = freqs.new / cpu->pstate.scaling; 2260 break; 2261 default: 2262 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2263 break; 2264 } 2265 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2266 if (target_pstate != cpu->pstate.current_pstate) { 2267 cpu->pstate.current_pstate = target_pstate; 2268 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, 2269 pstate_funcs.get_val(cpu, target_pstate)); 2270 } 2271 freqs.new = target_pstate * cpu->pstate.scaling; 2272 cpufreq_freq_transition_end(policy, &freqs, false); 2273 2274 return 0; 2275 } 2276 2277 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2278 unsigned int target_freq) 2279 { 2280 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2281 int target_pstate; 2282 2283 update_turbo_state(); 2284 2285 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2286 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2287 intel_pstate_update_pstate(cpu, target_pstate); 2288 return target_pstate * cpu->pstate.scaling; 2289 } 2290 2291 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2292 { 2293 int ret = __intel_pstate_cpu_init(policy); 2294 2295 if (ret) 2296 return ret; 2297 2298 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2299 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2300 policy->cur = policy->cpuinfo.min_freq; 2301 2302 return 0; 2303 } 2304 2305 static struct cpufreq_driver intel_cpufreq = { 2306 .flags = CPUFREQ_CONST_LOOPS, 2307 .verify = intel_cpufreq_verify_policy, 2308 .target = intel_cpufreq_target, 2309 .fast_switch = intel_cpufreq_fast_switch, 2310 .init = intel_cpufreq_cpu_init, 2311 .exit = intel_pstate_cpu_exit, 2312 .stop_cpu = intel_cpufreq_stop_cpu, 2313 .name = "intel_cpufreq", 2314 }; 2315 2316 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate; 2317 2318 static void intel_pstate_driver_cleanup(void) 2319 { 2320 unsigned int cpu; 2321 2322 get_online_cpus(); 2323 for_each_online_cpu(cpu) { 2324 if (all_cpu_data[cpu]) { 2325 if (intel_pstate_driver == &intel_pstate) 2326 intel_pstate_clear_update_util_hook(cpu); 2327 2328 kfree(all_cpu_data[cpu]); 2329 all_cpu_data[cpu] = NULL; 2330 } 2331 } 2332 put_online_cpus(); 2333 } 2334 2335 static int intel_pstate_register_driver(void) 2336 { 2337 int ret; 2338 2339 memset(&global, 0, sizeof(global)); 2340 global.max_perf_pct = 100; 2341 2342 ret = cpufreq_register_driver(intel_pstate_driver); 2343 if (ret) { 2344 intel_pstate_driver_cleanup(); 2345 return ret; 2346 } 2347 2348 global.min_perf_pct = min_perf_pct_min(); 2349 2350 mutex_lock(&intel_pstate_limits_lock); 2351 driver_registered = true; 2352 mutex_unlock(&intel_pstate_limits_lock); 2353 2354 if (intel_pstate_driver == &intel_pstate && !hwp_active && 2355 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load) 2356 intel_pstate_debug_expose_params(); 2357 2358 return 0; 2359 } 2360 2361 static int intel_pstate_unregister_driver(void) 2362 { 2363 if (hwp_active) 2364 return -EBUSY; 2365 2366 if (intel_pstate_driver == &intel_pstate && !hwp_active && 2367 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load) 2368 intel_pstate_debug_hide_params(); 2369 2370 mutex_lock(&intel_pstate_limits_lock); 2371 driver_registered = false; 2372 mutex_unlock(&intel_pstate_limits_lock); 2373 2374 cpufreq_unregister_driver(intel_pstate_driver); 2375 intel_pstate_driver_cleanup(); 2376 2377 return 0; 2378 } 2379 2380 static ssize_t intel_pstate_show_status(char *buf) 2381 { 2382 if (!driver_registered) 2383 return sprintf(buf, "off\n"); 2384 2385 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 2386 "active" : "passive"); 2387 } 2388 2389 static int intel_pstate_update_status(const char *buf, size_t size) 2390 { 2391 int ret; 2392 2393 if (size == 3 && !strncmp(buf, "off", size)) 2394 return driver_registered ? 2395 intel_pstate_unregister_driver() : -EINVAL; 2396 2397 if (size == 6 && !strncmp(buf, "active", size)) { 2398 if (driver_registered) { 2399 if (intel_pstate_driver == &intel_pstate) 2400 return 0; 2401 2402 ret = intel_pstate_unregister_driver(); 2403 if (ret) 2404 return ret; 2405 } 2406 2407 intel_pstate_driver = &intel_pstate; 2408 return intel_pstate_register_driver(); 2409 } 2410 2411 if (size == 7 && !strncmp(buf, "passive", size)) { 2412 if (driver_registered) { 2413 if (intel_pstate_driver != &intel_pstate) 2414 return 0; 2415 2416 ret = intel_pstate_unregister_driver(); 2417 if (ret) 2418 return ret; 2419 } 2420 2421 intel_pstate_driver = &intel_cpufreq; 2422 return intel_pstate_register_driver(); 2423 } 2424 2425 return -EINVAL; 2426 } 2427 2428 static int no_load __initdata; 2429 static int no_hwp __initdata; 2430 static int hwp_only __initdata; 2431 static unsigned int force_load __initdata; 2432 2433 static int __init intel_pstate_msrs_not_valid(void) 2434 { 2435 if (!pstate_funcs.get_max() || 2436 !pstate_funcs.get_min() || 2437 !pstate_funcs.get_turbo()) 2438 return -ENODEV; 2439 2440 return 0; 2441 } 2442 2443 static void __init copy_pid_params(struct pstate_adjust_policy *policy) 2444 { 2445 pid_params.sample_rate_ms = policy->sample_rate_ms; 2446 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 2447 pid_params.p_gain_pct = policy->p_gain_pct; 2448 pid_params.i_gain_pct = policy->i_gain_pct; 2449 pid_params.d_gain_pct = policy->d_gain_pct; 2450 pid_params.deadband = policy->deadband; 2451 pid_params.setpoint = policy->setpoint; 2452 } 2453 2454 #ifdef CONFIG_ACPI 2455 static void intel_pstate_use_acpi_profile(void) 2456 { 2457 switch (acpi_gbl_FADT.preferred_profile) { 2458 case PM_MOBILE: 2459 case PM_TABLET: 2460 case PM_APPLIANCE_PC: 2461 case PM_DESKTOP: 2462 case PM_WORKSTATION: 2463 pstate_funcs.get_target_pstate = 2464 get_target_pstate_use_cpu_load; 2465 } 2466 } 2467 #else 2468 static void intel_pstate_use_acpi_profile(void) 2469 { 2470 } 2471 #endif 2472 2473 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 2474 { 2475 pstate_funcs.get_max = funcs->get_max; 2476 pstate_funcs.get_max_physical = funcs->get_max_physical; 2477 pstate_funcs.get_min = funcs->get_min; 2478 pstate_funcs.get_turbo = funcs->get_turbo; 2479 pstate_funcs.get_scaling = funcs->get_scaling; 2480 pstate_funcs.get_val = funcs->get_val; 2481 pstate_funcs.get_vid = funcs->get_vid; 2482 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 2483 2484 intel_pstate_use_acpi_profile(); 2485 } 2486 2487 #ifdef CONFIG_ACPI 2488 2489 static bool __init intel_pstate_no_acpi_pss(void) 2490 { 2491 int i; 2492 2493 for_each_possible_cpu(i) { 2494 acpi_status status; 2495 union acpi_object *pss; 2496 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2497 struct acpi_processor *pr = per_cpu(processors, i); 2498 2499 if (!pr) 2500 continue; 2501 2502 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 2503 if (ACPI_FAILURE(status)) 2504 continue; 2505 2506 pss = buffer.pointer; 2507 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 2508 kfree(pss); 2509 return false; 2510 } 2511 2512 kfree(pss); 2513 } 2514 2515 return true; 2516 } 2517 2518 static bool __init intel_pstate_has_acpi_ppc(void) 2519 { 2520 int i; 2521 2522 for_each_possible_cpu(i) { 2523 struct acpi_processor *pr = per_cpu(processors, i); 2524 2525 if (!pr) 2526 continue; 2527 if (acpi_has_method(pr->handle, "_PPC")) 2528 return true; 2529 } 2530 return false; 2531 } 2532 2533 enum { 2534 PSS, 2535 PPC, 2536 }; 2537 2538 struct hw_vendor_info { 2539 u16 valid; 2540 char oem_id[ACPI_OEM_ID_SIZE]; 2541 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 2542 int oem_pwr_table; 2543 }; 2544 2545 /* Hardware vendor-specific info that has its own power management modes */ 2546 static struct hw_vendor_info vendor_info[] __initdata = { 2547 {1, "HP ", "ProLiant", PSS}, 2548 {1, "ORACLE", "X4-2 ", PPC}, 2549 {1, "ORACLE", "X4-2L ", PPC}, 2550 {1, "ORACLE", "X4-2B ", PPC}, 2551 {1, "ORACLE", "X3-2 ", PPC}, 2552 {1, "ORACLE", "X3-2L ", PPC}, 2553 {1, "ORACLE", "X3-2B ", PPC}, 2554 {1, "ORACLE", "X4470M2 ", PPC}, 2555 {1, "ORACLE", "X4270M3 ", PPC}, 2556 {1, "ORACLE", "X4270M2 ", PPC}, 2557 {1, "ORACLE", "X4170M2 ", PPC}, 2558 {1, "ORACLE", "X4170 M3", PPC}, 2559 {1, "ORACLE", "X4275 M3", PPC}, 2560 {1, "ORACLE", "X6-2 ", PPC}, 2561 {1, "ORACLE", "Sudbury ", PPC}, 2562 {0, "", ""}, 2563 }; 2564 2565 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 2566 { 2567 struct acpi_table_header hdr; 2568 struct hw_vendor_info *v_info; 2569 const struct x86_cpu_id *id; 2570 u64 misc_pwr; 2571 2572 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 2573 if (id) { 2574 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 2575 if ( misc_pwr & (1 << 8)) 2576 return true; 2577 } 2578 2579 if (acpi_disabled || 2580 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 2581 return false; 2582 2583 for (v_info = vendor_info; v_info->valid; v_info++) { 2584 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 2585 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 2586 ACPI_OEM_TABLE_ID_SIZE)) 2587 switch (v_info->oem_pwr_table) { 2588 case PSS: 2589 return intel_pstate_no_acpi_pss(); 2590 case PPC: 2591 return intel_pstate_has_acpi_ppc() && 2592 (!force_load); 2593 } 2594 } 2595 2596 return false; 2597 } 2598 2599 static void intel_pstate_request_control_from_smm(void) 2600 { 2601 /* 2602 * It may be unsafe to request P-states control from SMM if _PPC support 2603 * has not been enabled. 2604 */ 2605 if (acpi_ppc) 2606 acpi_processor_pstate_control(); 2607 } 2608 #else /* CONFIG_ACPI not enabled */ 2609 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 2610 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 2611 static inline void intel_pstate_request_control_from_smm(void) {} 2612 #endif /* CONFIG_ACPI */ 2613 2614 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 2615 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 2616 {} 2617 }; 2618 2619 static int __init intel_pstate_init(void) 2620 { 2621 int rc; 2622 2623 if (no_load) 2624 return -ENODEV; 2625 2626 if (x86_match_cpu(hwp_support_ids)) { 2627 copy_cpu_funcs(&core_params.funcs); 2628 if (no_hwp) { 2629 pstate_funcs.get_target_pstate = get_target_pstate_use_cpu_load; 2630 } else { 2631 hwp_active++; 2632 intel_pstate.attr = hwp_cpufreq_attrs; 2633 goto hwp_cpu_matched; 2634 } 2635 } else { 2636 const struct x86_cpu_id *id; 2637 struct cpu_defaults *cpu_def; 2638 2639 id = x86_match_cpu(intel_pstate_cpu_ids); 2640 if (!id) 2641 return -ENODEV; 2642 2643 cpu_def = (struct cpu_defaults *)id->driver_data; 2644 2645 copy_pid_params(&cpu_def->pid_policy); 2646 copy_cpu_funcs(&cpu_def->funcs); 2647 } 2648 2649 if (intel_pstate_msrs_not_valid()) 2650 return -ENODEV; 2651 2652 hwp_cpu_matched: 2653 /* 2654 * The Intel pstate driver will be ignored if the platform 2655 * firmware has its own power management modes. 2656 */ 2657 if (intel_pstate_platform_pwr_mgmt_exists()) 2658 return -ENODEV; 2659 2660 if (!hwp_active && hwp_only) 2661 return -ENOTSUPP; 2662 2663 pr_info("Intel P-state driver initializing\n"); 2664 2665 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 2666 if (!all_cpu_data) 2667 return -ENOMEM; 2668 2669 intel_pstate_request_control_from_smm(); 2670 2671 intel_pstate_sysfs_expose_params(); 2672 2673 mutex_lock(&intel_pstate_driver_lock); 2674 rc = intel_pstate_register_driver(); 2675 mutex_unlock(&intel_pstate_driver_lock); 2676 if (rc) 2677 return rc; 2678 2679 if (hwp_active) 2680 pr_info("HWP enabled\n"); 2681 2682 return 0; 2683 } 2684 device_initcall(intel_pstate_init); 2685 2686 static int __init intel_pstate_setup(char *str) 2687 { 2688 if (!str) 2689 return -EINVAL; 2690 2691 if (!strcmp(str, "disable")) { 2692 no_load = 1; 2693 } else if (!strcmp(str, "passive")) { 2694 pr_info("Passive mode enabled\n"); 2695 intel_pstate_driver = &intel_cpufreq; 2696 no_hwp = 1; 2697 } 2698 if (!strcmp(str, "no_hwp")) { 2699 pr_info("HWP disabled\n"); 2700 no_hwp = 1; 2701 } 2702 if (!strcmp(str, "force")) 2703 force_load = 1; 2704 if (!strcmp(str, "hwp_only")) 2705 hwp_only = 1; 2706 if (!strcmp(str, "per_cpu_perf_limits")) 2707 per_cpu_limits = true; 2708 2709 #ifdef CONFIG_ACPI 2710 if (!strcmp(str, "support_acpi_ppc")) 2711 acpi_ppc = true; 2712 #endif 2713 2714 return 0; 2715 } 2716 early_param("intel_pstate", intel_pstate_setup); 2717 2718 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 2719 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 2720 MODULE_LICENSE("GPL"); 2721