1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched/cpufreq.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/acpi.h> 30 #include <linux/vmalloc.h> 31 #include <trace/events/power.h> 32 33 #include <asm/div64.h> 34 #include <asm/msr.h> 35 #include <asm/cpu_device_id.h> 36 #include <asm/cpufeature.h> 37 #include <asm/intel-family.h> 38 39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 40 41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #include <acpi/cppc_acpi.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define EXT_BITS 6 54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 57 58 static inline int32_t mul_fp(int32_t x, int32_t y) 59 { 60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 61 } 62 63 static inline int32_t div_fp(s64 x, s64 y) 64 { 65 return div64_s64((int64_t)x << FRAC_BITS, y); 66 } 67 68 static inline int ceiling_fp(int32_t x) 69 { 70 int mask, ret; 71 72 ret = fp_toint(x); 73 mask = (1 << FRAC_BITS) - 1; 74 if (x & mask) 75 ret += 1; 76 return ret; 77 } 78 79 static inline int32_t percent_fp(int percent) 80 { 81 return div_fp(percent, 100); 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 static inline int32_t percent_ext_fp(int percent) 95 { 96 return div_ext_fp(percent, 100); 97 } 98 99 /** 100 * struct sample - Store performance sample 101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 102 * performance during last sample period 103 * @busy_scaled: Scaled busy value which is used to calculate next 104 * P state. This can be different than core_avg_perf 105 * to account for cpu idle period 106 * @aperf: Difference of actual performance frequency clock count 107 * read from APERF MSR between last and current sample 108 * @mperf: Difference of maximum performance frequency clock count 109 * read from MPERF MSR between last and current sample 110 * @tsc: Difference of time stamp counter between last and 111 * current sample 112 * @time: Current time from scheduler 113 * 114 * This structure is used in the cpudata structure to store performance sample 115 * data for choosing next P State. 116 */ 117 struct sample { 118 int32_t core_avg_perf; 119 int32_t busy_scaled; 120 u64 aperf; 121 u64 mperf; 122 u64 tsc; 123 u64 time; 124 }; 125 126 /** 127 * struct pstate_data - Store P state data 128 * @current_pstate: Current requested P state 129 * @min_pstate: Min P state possible for this platform 130 * @max_pstate: Max P state possible for this platform 131 * @max_pstate_physical:This is physical Max P state for a processor 132 * This can be higher than the max_pstate which can 133 * be limited by platform thermal design power limits 134 * @scaling: Scaling factor to convert frequency to cpufreq 135 * frequency units 136 * @turbo_pstate: Max Turbo P state possible for this platform 137 * @max_freq: @max_pstate frequency in cpufreq units 138 * @turbo_freq: @turbo_pstate frequency in cpufreq units 139 * 140 * Stores the per cpu model P state limits and current P state. 141 */ 142 struct pstate_data { 143 int current_pstate; 144 int min_pstate; 145 int max_pstate; 146 int max_pstate_physical; 147 int scaling; 148 int turbo_pstate; 149 unsigned int max_freq; 150 unsigned int turbo_freq; 151 }; 152 153 /** 154 * struct vid_data - Stores voltage information data 155 * @min: VID data for this platform corresponding to 156 * the lowest P state 157 * @max: VID data corresponding to the highest P State. 158 * @turbo: VID data for turbo P state 159 * @ratio: Ratio of (vid max - vid min) / 160 * (max P state - Min P State) 161 * 162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 163 * This data is used in Atom platforms, where in addition to target P state, 164 * the voltage data needs to be specified to select next P State. 165 */ 166 struct vid_data { 167 int min; 168 int max; 169 int turbo; 170 int32_t ratio; 171 }; 172 173 /** 174 * struct global_params - Global parameters, mostly tunable via sysfs. 175 * @no_turbo: Whether or not to use turbo P-states. 176 * @turbo_disabled: Whethet or not turbo P-states are available at all, 177 * based on the MSR_IA32_MISC_ENABLE value and whether or 178 * not the maximum reported turbo P-state is different from 179 * the maximum reported non-turbo one. 180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 183 * P-state capacity. 184 */ 185 struct global_params { 186 bool no_turbo; 187 bool turbo_disabled; 188 int max_perf_pct; 189 int min_perf_pct; 190 }; 191 192 /** 193 * struct cpudata - Per CPU instance data storage 194 * @cpu: CPU number for this instance data 195 * @policy: CPUFreq policy value 196 * @update_util: CPUFreq utility callback information 197 * @update_util_set: CPUFreq utility callback is set 198 * @iowait_boost: iowait-related boost fraction 199 * @last_update: Time of the last update. 200 * @pstate: Stores P state limits for this CPU 201 * @vid: Stores VID limits for this CPU 202 * @last_sample_time: Last Sample time 203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented 204 * This shift is a multiplier to mperf delta to 205 * calculate CPU busy. 206 * @prev_aperf: Last APERF value read from APERF MSR 207 * @prev_mperf: Last MPERF value read from MPERF MSR 208 * @prev_tsc: Last timestamp counter (TSC) value 209 * @prev_cummulative_iowait: IO Wait time difference from last and 210 * current sample 211 * @sample: Storage for storing last Sample data 212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 214 * @acpi_perf_data: Stores ACPI perf information read from _PSS 215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 216 * @epp_powersave: Last saved HWP energy performance preference 217 * (EPP) or energy performance bias (EPB), 218 * when policy switched to performance 219 * @epp_policy: Last saved policy used to set EPP/EPB 220 * @epp_default: Power on default HWP energy performance 221 * preference/bias 222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline 223 * operation 224 * @hwp_req_cached: Cached value of the last HWP Request MSR 225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 226 * @last_io_update: Last time when IO wake flag was set 227 * @sched_flags: Store scheduler flags for possible cross CPU update 228 * @hwp_boost_min: Last HWP boosted min performance 229 * 230 * This structure stores per CPU instance data for all CPUs. 231 */ 232 struct cpudata { 233 int cpu; 234 235 unsigned int policy; 236 struct update_util_data update_util; 237 bool update_util_set; 238 239 struct pstate_data pstate; 240 struct vid_data vid; 241 242 u64 last_update; 243 u64 last_sample_time; 244 u64 aperf_mperf_shift; 245 u64 prev_aperf; 246 u64 prev_mperf; 247 u64 prev_tsc; 248 u64 prev_cummulative_iowait; 249 struct sample sample; 250 int32_t min_perf_ratio; 251 int32_t max_perf_ratio; 252 #ifdef CONFIG_ACPI 253 struct acpi_processor_performance acpi_perf_data; 254 bool valid_pss_table; 255 #endif 256 unsigned int iowait_boost; 257 s16 epp_powersave; 258 s16 epp_policy; 259 s16 epp_default; 260 s16 epp_saved; 261 u64 hwp_req_cached; 262 u64 hwp_cap_cached; 263 u64 last_io_update; 264 unsigned int sched_flags; 265 u32 hwp_boost_min; 266 }; 267 268 static struct cpudata **all_cpu_data; 269 270 /** 271 * struct pstate_funcs - Per CPU model specific callbacks 272 * @get_max: Callback to get maximum non turbo effective P state 273 * @get_max_physical: Callback to get maximum non turbo physical P state 274 * @get_min: Callback to get minimum P state 275 * @get_turbo: Callback to get turbo P state 276 * @get_scaling: Callback to get frequency scaling factor 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(void); 285 int (*get_max_physical)(void); 286 int (*get_min)(void); 287 int (*get_turbo)(void); 288 int (*get_scaling)(void); 289 int (*get_aperf_mperf_shift)(void); 290 u64 (*get_val)(struct cpudata*, int pstate); 291 void (*get_vid)(struct cpudata *); 292 }; 293 294 static struct pstate_funcs pstate_funcs __read_mostly; 295 296 static int hwp_active __read_mostly; 297 static int hwp_mode_bdw __read_mostly; 298 static bool per_cpu_limits __read_mostly; 299 static bool hwp_boost __read_mostly; 300 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 302 303 #ifdef CONFIG_ACPI 304 static bool acpi_ppc; 305 #endif 306 307 static struct global_params global; 308 309 static DEFINE_MUTEX(intel_pstate_driver_lock); 310 static DEFINE_MUTEX(intel_pstate_limits_lock); 311 312 #ifdef CONFIG_ACPI 313 314 static bool intel_pstate_acpi_pm_profile_server(void) 315 { 316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 318 return true; 319 320 return false; 321 } 322 323 static bool intel_pstate_get_ppc_enable_status(void) 324 { 325 if (intel_pstate_acpi_pm_profile_server()) 326 return true; 327 328 return acpi_ppc; 329 } 330 331 #ifdef CONFIG_ACPI_CPPC_LIB 332 333 /* The work item is needed to avoid CPU hotplug locking issues */ 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 335 { 336 sched_set_itmt_support(); 337 } 338 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 340 341 static void intel_pstate_set_itmt_prio(int cpu) 342 { 343 struct cppc_perf_caps cppc_perf; 344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 345 int ret; 346 347 ret = cppc_get_perf_caps(cpu, &cppc_perf); 348 if (ret) 349 return; 350 351 /* 352 * The priorities can be set regardless of whether or not 353 * sched_set_itmt_support(true) has been called and it is valid to 354 * update them at any time after it has been called. 355 */ 356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 357 358 if (max_highest_perf <= min_highest_perf) { 359 if (cppc_perf.highest_perf > max_highest_perf) 360 max_highest_perf = cppc_perf.highest_perf; 361 362 if (cppc_perf.highest_perf < min_highest_perf) 363 min_highest_perf = cppc_perf.highest_perf; 364 365 if (max_highest_perf > min_highest_perf) { 366 /* 367 * This code can be run during CPU online under the 368 * CPU hotplug locks, so sched_set_itmt_support() 369 * cannot be called from here. Queue up a work item 370 * to invoke it. 371 */ 372 schedule_work(&sched_itmt_work); 373 } 374 } 375 } 376 377 static int intel_pstate_get_cppc_guranteed(int cpu) 378 { 379 struct cppc_perf_caps cppc_perf; 380 int ret; 381 382 ret = cppc_get_perf_caps(cpu, &cppc_perf); 383 if (ret) 384 return ret; 385 386 return cppc_perf.guaranteed_perf; 387 } 388 389 #else /* CONFIG_ACPI_CPPC_LIB */ 390 static void intel_pstate_set_itmt_prio(int cpu) 391 { 392 } 393 #endif /* CONFIG_ACPI_CPPC_LIB */ 394 395 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 396 { 397 struct cpudata *cpu; 398 int ret; 399 int i; 400 401 if (hwp_active) { 402 intel_pstate_set_itmt_prio(policy->cpu); 403 return; 404 } 405 406 if (!intel_pstate_get_ppc_enable_status()) 407 return; 408 409 cpu = all_cpu_data[policy->cpu]; 410 411 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 412 policy->cpu); 413 if (ret) 414 return; 415 416 /* 417 * Check if the control value in _PSS is for PERF_CTL MSR, which should 418 * guarantee that the states returned by it map to the states in our 419 * list directly. 420 */ 421 if (cpu->acpi_perf_data.control_register.space_id != 422 ACPI_ADR_SPACE_FIXED_HARDWARE) 423 goto err; 424 425 /* 426 * If there is only one entry _PSS, simply ignore _PSS and continue as 427 * usual without taking _PSS into account 428 */ 429 if (cpu->acpi_perf_data.state_count < 2) 430 goto err; 431 432 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 433 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 434 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 435 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 436 (u32) cpu->acpi_perf_data.states[i].core_frequency, 437 (u32) cpu->acpi_perf_data.states[i].power, 438 (u32) cpu->acpi_perf_data.states[i].control); 439 } 440 441 /* 442 * The _PSS table doesn't contain whole turbo frequency range. 443 * This just contains +1 MHZ above the max non turbo frequency, 444 * with control value corresponding to max turbo ratio. But 445 * when cpufreq set policy is called, it will call with this 446 * max frequency, which will cause a reduced performance as 447 * this driver uses real max turbo frequency as the max 448 * frequency. So correct this frequency in _PSS table to 449 * correct max turbo frequency based on the turbo state. 450 * Also need to convert to MHz as _PSS freq is in MHz. 451 */ 452 if (!global.turbo_disabled) 453 cpu->acpi_perf_data.states[0].core_frequency = 454 policy->cpuinfo.max_freq / 1000; 455 cpu->valid_pss_table = true; 456 pr_debug("_PPC limits will be enforced\n"); 457 458 return; 459 460 err: 461 cpu->valid_pss_table = false; 462 acpi_processor_unregister_performance(policy->cpu); 463 } 464 465 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 466 { 467 struct cpudata *cpu; 468 469 cpu = all_cpu_data[policy->cpu]; 470 if (!cpu->valid_pss_table) 471 return; 472 473 acpi_processor_unregister_performance(policy->cpu); 474 } 475 #else /* CONFIG_ACPI */ 476 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 477 { 478 } 479 480 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 481 { 482 } 483 484 static inline bool intel_pstate_acpi_pm_profile_server(void) 485 { 486 return false; 487 } 488 #endif /* CONFIG_ACPI */ 489 490 #ifndef CONFIG_ACPI_CPPC_LIB 491 static int intel_pstate_get_cppc_guranteed(int cpu) 492 { 493 return -ENOTSUPP; 494 } 495 #endif /* CONFIG_ACPI_CPPC_LIB */ 496 497 static inline void update_turbo_state(void) 498 { 499 u64 misc_en; 500 struct cpudata *cpu; 501 502 cpu = all_cpu_data[0]; 503 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 504 global.turbo_disabled = 505 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 506 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 507 } 508 509 static int min_perf_pct_min(void) 510 { 511 struct cpudata *cpu = all_cpu_data[0]; 512 int turbo_pstate = cpu->pstate.turbo_pstate; 513 514 return turbo_pstate ? 515 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 516 } 517 518 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 519 { 520 u64 epb; 521 int ret; 522 523 if (!static_cpu_has(X86_FEATURE_EPB)) 524 return -ENXIO; 525 526 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 527 if (ret) 528 return (s16)ret; 529 530 return (s16)(epb & 0x0f); 531 } 532 533 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 534 { 535 s16 epp; 536 537 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 538 /* 539 * When hwp_req_data is 0, means that caller didn't read 540 * MSR_HWP_REQUEST, so need to read and get EPP. 541 */ 542 if (!hwp_req_data) { 543 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 544 &hwp_req_data); 545 if (epp) 546 return epp; 547 } 548 epp = (hwp_req_data >> 24) & 0xff; 549 } else { 550 /* When there is no EPP present, HWP uses EPB settings */ 551 epp = intel_pstate_get_epb(cpu_data); 552 } 553 554 return epp; 555 } 556 557 static int intel_pstate_set_epb(int cpu, s16 pref) 558 { 559 u64 epb; 560 int ret; 561 562 if (!static_cpu_has(X86_FEATURE_EPB)) 563 return -ENXIO; 564 565 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 566 if (ret) 567 return ret; 568 569 epb = (epb & ~0x0f) | pref; 570 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 571 572 return 0; 573 } 574 575 /* 576 * EPP/EPB display strings corresponding to EPP index in the 577 * energy_perf_strings[] 578 * index String 579 *------------------------------------- 580 * 0 default 581 * 1 performance 582 * 2 balance_performance 583 * 3 balance_power 584 * 4 power 585 */ 586 static const char * const energy_perf_strings[] = { 587 "default", 588 "performance", 589 "balance_performance", 590 "balance_power", 591 "power", 592 NULL 593 }; 594 static const unsigned int epp_values[] = { 595 HWP_EPP_PERFORMANCE, 596 HWP_EPP_BALANCE_PERFORMANCE, 597 HWP_EPP_BALANCE_POWERSAVE, 598 HWP_EPP_POWERSAVE 599 }; 600 601 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) 602 { 603 s16 epp; 604 int index = -EINVAL; 605 606 epp = intel_pstate_get_epp(cpu_data, 0); 607 if (epp < 0) 608 return epp; 609 610 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 611 if (epp == HWP_EPP_PERFORMANCE) 612 return 1; 613 if (epp <= HWP_EPP_BALANCE_PERFORMANCE) 614 return 2; 615 if (epp <= HWP_EPP_BALANCE_POWERSAVE) 616 return 3; 617 else 618 return 4; 619 } else if (static_cpu_has(X86_FEATURE_EPB)) { 620 /* 621 * Range: 622 * 0x00-0x03 : Performance 623 * 0x04-0x07 : Balance performance 624 * 0x08-0x0B : Balance power 625 * 0x0C-0x0F : Power 626 * The EPB is a 4 bit value, but our ranges restrict the 627 * value which can be set. Here only using top two bits 628 * effectively. 629 */ 630 index = (epp >> 2) + 1; 631 } 632 633 return index; 634 } 635 636 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 637 int pref_index) 638 { 639 int epp = -EINVAL; 640 int ret; 641 642 if (!pref_index) 643 epp = cpu_data->epp_default; 644 645 mutex_lock(&intel_pstate_limits_lock); 646 647 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 648 u64 value; 649 650 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); 651 if (ret) 652 goto return_pref; 653 654 value &= ~GENMASK_ULL(31, 24); 655 656 if (epp == -EINVAL) 657 epp = epp_values[pref_index - 1]; 658 659 value |= (u64)epp << 24; 660 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); 661 } else { 662 if (epp == -EINVAL) 663 epp = (pref_index - 1) << 2; 664 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 665 } 666 return_pref: 667 mutex_unlock(&intel_pstate_limits_lock); 668 669 return ret; 670 } 671 672 static ssize_t show_energy_performance_available_preferences( 673 struct cpufreq_policy *policy, char *buf) 674 { 675 int i = 0; 676 int ret = 0; 677 678 while (energy_perf_strings[i] != NULL) 679 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 680 681 ret += sprintf(&buf[ret], "\n"); 682 683 return ret; 684 } 685 686 cpufreq_freq_attr_ro(energy_performance_available_preferences); 687 688 static ssize_t store_energy_performance_preference( 689 struct cpufreq_policy *policy, const char *buf, size_t count) 690 { 691 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 692 char str_preference[21]; 693 int ret; 694 695 ret = sscanf(buf, "%20s", str_preference); 696 if (ret != 1) 697 return -EINVAL; 698 699 ret = match_string(energy_perf_strings, -1, str_preference); 700 if (ret < 0) 701 return ret; 702 703 intel_pstate_set_energy_pref_index(cpu_data, ret); 704 return count; 705 } 706 707 static ssize_t show_energy_performance_preference( 708 struct cpufreq_policy *policy, char *buf) 709 { 710 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 711 int preference; 712 713 preference = intel_pstate_get_energy_pref_index(cpu_data); 714 if (preference < 0) 715 return preference; 716 717 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 718 } 719 720 cpufreq_freq_attr_rw(energy_performance_preference); 721 722 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 723 { 724 struct cpudata *cpu; 725 u64 cap; 726 int ratio; 727 728 ratio = intel_pstate_get_cppc_guranteed(policy->cpu); 729 if (ratio <= 0) { 730 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 731 ratio = HWP_GUARANTEED_PERF(cap); 732 } 733 734 cpu = all_cpu_data[policy->cpu]; 735 736 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling); 737 } 738 739 cpufreq_freq_attr_ro(base_frequency); 740 741 static struct freq_attr *hwp_cpufreq_attrs[] = { 742 &energy_performance_preference, 743 &energy_performance_available_preferences, 744 &base_frequency, 745 NULL, 746 }; 747 748 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, 749 int *current_max) 750 { 751 u64 cap; 752 753 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 754 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap); 755 if (global.no_turbo) 756 *current_max = HWP_GUARANTEED_PERF(cap); 757 else 758 *current_max = HWP_HIGHEST_PERF(cap); 759 760 *phy_max = HWP_HIGHEST_PERF(cap); 761 } 762 763 static void intel_pstate_hwp_set(unsigned int cpu) 764 { 765 struct cpudata *cpu_data = all_cpu_data[cpu]; 766 int max, min; 767 u64 value; 768 s16 epp; 769 770 max = cpu_data->max_perf_ratio; 771 min = cpu_data->min_perf_ratio; 772 773 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 774 min = max; 775 776 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 777 778 value &= ~HWP_MIN_PERF(~0L); 779 value |= HWP_MIN_PERF(min); 780 781 value &= ~HWP_MAX_PERF(~0L); 782 value |= HWP_MAX_PERF(max); 783 784 if (cpu_data->epp_policy == cpu_data->policy) 785 goto skip_epp; 786 787 cpu_data->epp_policy = cpu_data->policy; 788 789 if (cpu_data->epp_saved >= 0) { 790 epp = cpu_data->epp_saved; 791 cpu_data->epp_saved = -EINVAL; 792 goto update_epp; 793 } 794 795 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 796 epp = intel_pstate_get_epp(cpu_data, value); 797 cpu_data->epp_powersave = epp; 798 /* If EPP read was failed, then don't try to write */ 799 if (epp < 0) 800 goto skip_epp; 801 802 epp = 0; 803 } else { 804 /* skip setting EPP, when saved value is invalid */ 805 if (cpu_data->epp_powersave < 0) 806 goto skip_epp; 807 808 /* 809 * No need to restore EPP when it is not zero. This 810 * means: 811 * - Policy is not changed 812 * - user has manually changed 813 * - Error reading EPB 814 */ 815 epp = intel_pstate_get_epp(cpu_data, value); 816 if (epp) 817 goto skip_epp; 818 819 epp = cpu_data->epp_powersave; 820 } 821 update_epp: 822 if (static_cpu_has(X86_FEATURE_HWP_EPP)) { 823 value &= ~GENMASK_ULL(31, 24); 824 value |= (u64)epp << 24; 825 } else { 826 intel_pstate_set_epb(cpu, epp); 827 } 828 skip_epp: 829 WRITE_ONCE(cpu_data->hwp_req_cached, value); 830 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 831 } 832 833 static void intel_pstate_hwp_force_min_perf(int cpu) 834 { 835 u64 value; 836 int min_perf; 837 838 value = all_cpu_data[cpu]->hwp_req_cached; 839 value &= ~GENMASK_ULL(31, 0); 840 min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached); 841 842 /* Set hwp_max = hwp_min */ 843 value |= HWP_MAX_PERF(min_perf); 844 value |= HWP_MIN_PERF(min_perf); 845 846 /* Set EPP/EPB to min */ 847 if (static_cpu_has(X86_FEATURE_HWP_EPP)) 848 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 849 else 850 intel_pstate_set_epb(cpu, HWP_EPP_BALANCE_POWERSAVE); 851 852 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 853 } 854 855 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) 856 { 857 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 858 859 if (!hwp_active) 860 return 0; 861 862 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); 863 864 return 0; 865 } 866 867 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 868 869 static int intel_pstate_resume(struct cpufreq_policy *policy) 870 { 871 if (!hwp_active) 872 return 0; 873 874 mutex_lock(&intel_pstate_limits_lock); 875 876 if (policy->cpu == 0) 877 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]); 878 879 all_cpu_data[policy->cpu]->epp_policy = 0; 880 intel_pstate_hwp_set(policy->cpu); 881 882 mutex_unlock(&intel_pstate_limits_lock); 883 884 return 0; 885 } 886 887 static void intel_pstate_update_policies(void) 888 { 889 int cpu; 890 891 for_each_possible_cpu(cpu) 892 cpufreq_update_policy(cpu); 893 } 894 895 /************************** sysfs begin ************************/ 896 #define show_one(file_name, object) \ 897 static ssize_t show_##file_name \ 898 (struct kobject *kobj, struct attribute *attr, char *buf) \ 899 { \ 900 return sprintf(buf, "%u\n", global.object); \ 901 } 902 903 static ssize_t intel_pstate_show_status(char *buf); 904 static int intel_pstate_update_status(const char *buf, size_t size); 905 906 static ssize_t show_status(struct kobject *kobj, 907 struct attribute *attr, char *buf) 908 { 909 ssize_t ret; 910 911 mutex_lock(&intel_pstate_driver_lock); 912 ret = intel_pstate_show_status(buf); 913 mutex_unlock(&intel_pstate_driver_lock); 914 915 return ret; 916 } 917 918 static ssize_t store_status(struct kobject *a, struct attribute *b, 919 const char *buf, size_t count) 920 { 921 char *p = memchr(buf, '\n', count); 922 int ret; 923 924 mutex_lock(&intel_pstate_driver_lock); 925 ret = intel_pstate_update_status(buf, p ? p - buf : count); 926 mutex_unlock(&intel_pstate_driver_lock); 927 928 return ret < 0 ? ret : count; 929 } 930 931 static ssize_t show_turbo_pct(struct kobject *kobj, 932 struct attribute *attr, char *buf) 933 { 934 struct cpudata *cpu; 935 int total, no_turbo, turbo_pct; 936 uint32_t turbo_fp; 937 938 mutex_lock(&intel_pstate_driver_lock); 939 940 if (!intel_pstate_driver) { 941 mutex_unlock(&intel_pstate_driver_lock); 942 return -EAGAIN; 943 } 944 945 cpu = all_cpu_data[0]; 946 947 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 948 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 949 turbo_fp = div_fp(no_turbo, total); 950 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 951 952 mutex_unlock(&intel_pstate_driver_lock); 953 954 return sprintf(buf, "%u\n", turbo_pct); 955 } 956 957 static ssize_t show_num_pstates(struct kobject *kobj, 958 struct attribute *attr, char *buf) 959 { 960 struct cpudata *cpu; 961 int total; 962 963 mutex_lock(&intel_pstate_driver_lock); 964 965 if (!intel_pstate_driver) { 966 mutex_unlock(&intel_pstate_driver_lock); 967 return -EAGAIN; 968 } 969 970 cpu = all_cpu_data[0]; 971 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 972 973 mutex_unlock(&intel_pstate_driver_lock); 974 975 return sprintf(buf, "%u\n", total); 976 } 977 978 static ssize_t show_no_turbo(struct kobject *kobj, 979 struct attribute *attr, char *buf) 980 { 981 ssize_t ret; 982 983 mutex_lock(&intel_pstate_driver_lock); 984 985 if (!intel_pstate_driver) { 986 mutex_unlock(&intel_pstate_driver_lock); 987 return -EAGAIN; 988 } 989 990 update_turbo_state(); 991 if (global.turbo_disabled) 992 ret = sprintf(buf, "%u\n", global.turbo_disabled); 993 else 994 ret = sprintf(buf, "%u\n", global.no_turbo); 995 996 mutex_unlock(&intel_pstate_driver_lock); 997 998 return ret; 999 } 1000 1001 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 1002 const char *buf, size_t count) 1003 { 1004 unsigned int input; 1005 int ret; 1006 1007 ret = sscanf(buf, "%u", &input); 1008 if (ret != 1) 1009 return -EINVAL; 1010 1011 mutex_lock(&intel_pstate_driver_lock); 1012 1013 if (!intel_pstate_driver) { 1014 mutex_unlock(&intel_pstate_driver_lock); 1015 return -EAGAIN; 1016 } 1017 1018 mutex_lock(&intel_pstate_limits_lock); 1019 1020 update_turbo_state(); 1021 if (global.turbo_disabled) { 1022 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 1023 mutex_unlock(&intel_pstate_limits_lock); 1024 mutex_unlock(&intel_pstate_driver_lock); 1025 return -EPERM; 1026 } 1027 1028 global.no_turbo = clamp_t(int, input, 0, 1); 1029 1030 if (global.no_turbo) { 1031 struct cpudata *cpu = all_cpu_data[0]; 1032 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1033 1034 /* Squash the global minimum into the permitted range. */ 1035 if (global.min_perf_pct > pct) 1036 global.min_perf_pct = pct; 1037 } 1038 1039 mutex_unlock(&intel_pstate_limits_lock); 1040 1041 intel_pstate_update_policies(); 1042 1043 mutex_unlock(&intel_pstate_driver_lock); 1044 1045 return count; 1046 } 1047 1048 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 1049 const char *buf, size_t count) 1050 { 1051 unsigned int input; 1052 int ret; 1053 1054 ret = sscanf(buf, "%u", &input); 1055 if (ret != 1) 1056 return -EINVAL; 1057 1058 mutex_lock(&intel_pstate_driver_lock); 1059 1060 if (!intel_pstate_driver) { 1061 mutex_unlock(&intel_pstate_driver_lock); 1062 return -EAGAIN; 1063 } 1064 1065 mutex_lock(&intel_pstate_limits_lock); 1066 1067 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1068 1069 mutex_unlock(&intel_pstate_limits_lock); 1070 1071 intel_pstate_update_policies(); 1072 1073 mutex_unlock(&intel_pstate_driver_lock); 1074 1075 return count; 1076 } 1077 1078 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 1079 const char *buf, size_t count) 1080 { 1081 unsigned int input; 1082 int ret; 1083 1084 ret = sscanf(buf, "%u", &input); 1085 if (ret != 1) 1086 return -EINVAL; 1087 1088 mutex_lock(&intel_pstate_driver_lock); 1089 1090 if (!intel_pstate_driver) { 1091 mutex_unlock(&intel_pstate_driver_lock); 1092 return -EAGAIN; 1093 } 1094 1095 mutex_lock(&intel_pstate_limits_lock); 1096 1097 global.min_perf_pct = clamp_t(int, input, 1098 min_perf_pct_min(), global.max_perf_pct); 1099 1100 mutex_unlock(&intel_pstate_limits_lock); 1101 1102 intel_pstate_update_policies(); 1103 1104 mutex_unlock(&intel_pstate_driver_lock); 1105 1106 return count; 1107 } 1108 1109 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1110 struct attribute *attr, char *buf) 1111 { 1112 return sprintf(buf, "%u\n", hwp_boost); 1113 } 1114 1115 static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b, 1116 const char *buf, size_t count) 1117 { 1118 unsigned int input; 1119 int ret; 1120 1121 ret = kstrtouint(buf, 10, &input); 1122 if (ret) 1123 return ret; 1124 1125 mutex_lock(&intel_pstate_driver_lock); 1126 hwp_boost = !!input; 1127 intel_pstate_update_policies(); 1128 mutex_unlock(&intel_pstate_driver_lock); 1129 1130 return count; 1131 } 1132 1133 show_one(max_perf_pct, max_perf_pct); 1134 show_one(min_perf_pct, min_perf_pct); 1135 1136 define_one_global_rw(status); 1137 define_one_global_rw(no_turbo); 1138 define_one_global_rw(max_perf_pct); 1139 define_one_global_rw(min_perf_pct); 1140 define_one_global_ro(turbo_pct); 1141 define_one_global_ro(num_pstates); 1142 define_one_global_rw(hwp_dynamic_boost); 1143 1144 static struct attribute *intel_pstate_attributes[] = { 1145 &status.attr, 1146 &no_turbo.attr, 1147 &turbo_pct.attr, 1148 &num_pstates.attr, 1149 NULL 1150 }; 1151 1152 static const struct attribute_group intel_pstate_attr_group = { 1153 .attrs = intel_pstate_attributes, 1154 }; 1155 1156 static void __init intel_pstate_sysfs_expose_params(void) 1157 { 1158 struct kobject *intel_pstate_kobject; 1159 int rc; 1160 1161 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1162 &cpu_subsys.dev_root->kobj); 1163 if (WARN_ON(!intel_pstate_kobject)) 1164 return; 1165 1166 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1167 if (WARN_ON(rc)) 1168 return; 1169 1170 /* 1171 * If per cpu limits are enforced there are no global limits, so 1172 * return without creating max/min_perf_pct attributes 1173 */ 1174 if (per_cpu_limits) 1175 return; 1176 1177 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1178 WARN_ON(rc); 1179 1180 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1181 WARN_ON(rc); 1182 1183 if (hwp_active) { 1184 rc = sysfs_create_file(intel_pstate_kobject, 1185 &hwp_dynamic_boost.attr); 1186 WARN_ON(rc); 1187 } 1188 } 1189 /************************** sysfs end ************************/ 1190 1191 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1192 { 1193 /* First disable HWP notification interrupt as we don't process them */ 1194 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1195 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1196 1197 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1198 cpudata->epp_policy = 0; 1199 if (cpudata->epp_default == -EINVAL) 1200 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1201 } 1202 1203 #define MSR_IA32_POWER_CTL_BIT_EE 19 1204 1205 /* Disable energy efficiency optimization */ 1206 static void intel_pstate_disable_ee(int cpu) 1207 { 1208 u64 power_ctl; 1209 int ret; 1210 1211 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); 1212 if (ret) 1213 return; 1214 1215 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { 1216 pr_info("Disabling energy efficiency optimization\n"); 1217 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1218 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); 1219 } 1220 } 1221 1222 static int atom_get_min_pstate(void) 1223 { 1224 u64 value; 1225 1226 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1227 return (value >> 8) & 0x7F; 1228 } 1229 1230 static int atom_get_max_pstate(void) 1231 { 1232 u64 value; 1233 1234 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1235 return (value >> 16) & 0x7F; 1236 } 1237 1238 static int atom_get_turbo_pstate(void) 1239 { 1240 u64 value; 1241 1242 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1243 return value & 0x7F; 1244 } 1245 1246 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1247 { 1248 u64 val; 1249 int32_t vid_fp; 1250 u32 vid; 1251 1252 val = (u64)pstate << 8; 1253 if (global.no_turbo && !global.turbo_disabled) 1254 val |= (u64)1 << 32; 1255 1256 vid_fp = cpudata->vid.min + mul_fp( 1257 int_tofp(pstate - cpudata->pstate.min_pstate), 1258 cpudata->vid.ratio); 1259 1260 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1261 vid = ceiling_fp(vid_fp); 1262 1263 if (pstate > cpudata->pstate.max_pstate) 1264 vid = cpudata->vid.turbo; 1265 1266 return val | vid; 1267 } 1268 1269 static int silvermont_get_scaling(void) 1270 { 1271 u64 value; 1272 int i; 1273 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1274 static int silvermont_freq_table[] = { 1275 83300, 100000, 133300, 116700, 80000}; 1276 1277 rdmsrl(MSR_FSB_FREQ, value); 1278 i = value & 0x7; 1279 WARN_ON(i > 4); 1280 1281 return silvermont_freq_table[i]; 1282 } 1283 1284 static int airmont_get_scaling(void) 1285 { 1286 u64 value; 1287 int i; 1288 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1289 static int airmont_freq_table[] = { 1290 83300, 100000, 133300, 116700, 80000, 1291 93300, 90000, 88900, 87500}; 1292 1293 rdmsrl(MSR_FSB_FREQ, value); 1294 i = value & 0xF; 1295 WARN_ON(i > 8); 1296 1297 return airmont_freq_table[i]; 1298 } 1299 1300 static void atom_get_vid(struct cpudata *cpudata) 1301 { 1302 u64 value; 1303 1304 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1305 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1306 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1307 cpudata->vid.ratio = div_fp( 1308 cpudata->vid.max - cpudata->vid.min, 1309 int_tofp(cpudata->pstate.max_pstate - 1310 cpudata->pstate.min_pstate)); 1311 1312 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1313 cpudata->vid.turbo = value & 0x7f; 1314 } 1315 1316 static int core_get_min_pstate(void) 1317 { 1318 u64 value; 1319 1320 rdmsrl(MSR_PLATFORM_INFO, value); 1321 return (value >> 40) & 0xFF; 1322 } 1323 1324 static int core_get_max_pstate_physical(void) 1325 { 1326 u64 value; 1327 1328 rdmsrl(MSR_PLATFORM_INFO, value); 1329 return (value >> 8) & 0xFF; 1330 } 1331 1332 static int core_get_tdp_ratio(u64 plat_info) 1333 { 1334 /* Check how many TDP levels present */ 1335 if (plat_info & 0x600000000) { 1336 u64 tdp_ctrl; 1337 u64 tdp_ratio; 1338 int tdp_msr; 1339 int err; 1340 1341 /* Get the TDP level (0, 1, 2) to get ratios */ 1342 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1343 if (err) 1344 return err; 1345 1346 /* TDP MSR are continuous starting at 0x648 */ 1347 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1348 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1349 if (err) 1350 return err; 1351 1352 /* For level 1 and 2, bits[23:16] contain the ratio */ 1353 if (tdp_ctrl & 0x03) 1354 tdp_ratio >>= 16; 1355 1356 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1357 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1358 1359 return (int)tdp_ratio; 1360 } 1361 1362 return -ENXIO; 1363 } 1364 1365 static int core_get_max_pstate(void) 1366 { 1367 u64 tar; 1368 u64 plat_info; 1369 int max_pstate; 1370 int tdp_ratio; 1371 int err; 1372 1373 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1374 max_pstate = (plat_info >> 8) & 0xFF; 1375 1376 tdp_ratio = core_get_tdp_ratio(plat_info); 1377 if (tdp_ratio <= 0) 1378 return max_pstate; 1379 1380 if (hwp_active) { 1381 /* Turbo activation ratio is not used on HWP platforms */ 1382 return tdp_ratio; 1383 } 1384 1385 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1386 if (!err) { 1387 int tar_levels; 1388 1389 /* Do some sanity checking for safety */ 1390 tar_levels = tar & 0xff; 1391 if (tdp_ratio - 1 == tar_levels) { 1392 max_pstate = tar_levels; 1393 pr_debug("max_pstate=TAC %x\n", max_pstate); 1394 } 1395 } 1396 1397 return max_pstate; 1398 } 1399 1400 static int core_get_turbo_pstate(void) 1401 { 1402 u64 value; 1403 int nont, ret; 1404 1405 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1406 nont = core_get_max_pstate(); 1407 ret = (value) & 255; 1408 if (ret <= nont) 1409 ret = nont; 1410 return ret; 1411 } 1412 1413 static inline int core_get_scaling(void) 1414 { 1415 return 100000; 1416 } 1417 1418 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1419 { 1420 u64 val; 1421 1422 val = (u64)pstate << 8; 1423 if (global.no_turbo && !global.turbo_disabled) 1424 val |= (u64)1 << 32; 1425 1426 return val; 1427 } 1428 1429 static int knl_get_aperf_mperf_shift(void) 1430 { 1431 return 10; 1432 } 1433 1434 static int knl_get_turbo_pstate(void) 1435 { 1436 u64 value; 1437 int nont, ret; 1438 1439 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1440 nont = core_get_max_pstate(); 1441 ret = (((value) >> 8) & 0xFF); 1442 if (ret <= nont) 1443 ret = nont; 1444 return ret; 1445 } 1446 1447 static int intel_pstate_get_base_pstate(struct cpudata *cpu) 1448 { 1449 return global.no_turbo || global.turbo_disabled ? 1450 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1451 } 1452 1453 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1454 { 1455 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1456 cpu->pstate.current_pstate = pstate; 1457 /* 1458 * Generally, there is no guarantee that this code will always run on 1459 * the CPU being updated, so force the register update to run on the 1460 * right CPU. 1461 */ 1462 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1463 pstate_funcs.get_val(cpu, pstate)); 1464 } 1465 1466 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1467 { 1468 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1469 } 1470 1471 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1472 { 1473 int pstate; 1474 1475 update_turbo_state(); 1476 pstate = intel_pstate_get_base_pstate(cpu); 1477 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1478 intel_pstate_set_pstate(cpu, pstate); 1479 } 1480 1481 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1482 { 1483 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1484 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1485 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1486 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1487 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1488 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; 1489 1490 if (hwp_active && !hwp_mode_bdw) { 1491 unsigned int phy_max, current_max; 1492 1493 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max); 1494 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling; 1495 } else { 1496 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1497 } 1498 1499 if (pstate_funcs.get_aperf_mperf_shift) 1500 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 1501 1502 if (pstate_funcs.get_vid) 1503 pstate_funcs.get_vid(cpu); 1504 1505 intel_pstate_set_min_pstate(cpu); 1506 } 1507 1508 /* 1509 * Long hold time will keep high perf limits for long time, 1510 * which negatively impacts perf/watt for some workloads, 1511 * like specpower. 3ms is based on experiements on some 1512 * workoads. 1513 */ 1514 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 1515 1516 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 1517 { 1518 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 1519 u32 max_limit = (hwp_req & 0xff00) >> 8; 1520 u32 min_limit = (hwp_req & 0xff); 1521 u32 boost_level1; 1522 1523 /* 1524 * Cases to consider (User changes via sysfs or boot time): 1525 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 1526 * No boost, return. 1527 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 1528 * Should result in one level boost only for P0. 1529 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 1530 * Should result in two level boost: 1531 * (min + p1)/2 and P1. 1532 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 1533 * Should result in three level boost: 1534 * (min + p1)/2, P1 and P0. 1535 */ 1536 1537 /* If max and min are equal or already at max, nothing to boost */ 1538 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 1539 return; 1540 1541 if (!cpu->hwp_boost_min) 1542 cpu->hwp_boost_min = min_limit; 1543 1544 /* level at half way mark between min and guranteed */ 1545 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1; 1546 1547 if (cpu->hwp_boost_min < boost_level1) 1548 cpu->hwp_boost_min = boost_level1; 1549 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1550 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached); 1551 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) && 1552 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1553 cpu->hwp_boost_min = max_limit; 1554 else 1555 return; 1556 1557 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 1558 wrmsrl(MSR_HWP_REQUEST, hwp_req); 1559 cpu->last_update = cpu->sample.time; 1560 } 1561 1562 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 1563 { 1564 if (cpu->hwp_boost_min) { 1565 bool expired; 1566 1567 /* Check if we are idle for hold time to boost down */ 1568 expired = time_after64(cpu->sample.time, cpu->last_update + 1569 hwp_boost_hold_time_ns); 1570 if (expired) { 1571 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 1572 cpu->hwp_boost_min = 0; 1573 } 1574 } 1575 cpu->last_update = cpu->sample.time; 1576 } 1577 1578 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 1579 u64 time) 1580 { 1581 cpu->sample.time = time; 1582 1583 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 1584 bool do_io = false; 1585 1586 cpu->sched_flags = 0; 1587 /* 1588 * Set iowait_boost flag and update time. Since IO WAIT flag 1589 * is set all the time, we can't just conclude that there is 1590 * some IO bound activity is scheduled on this CPU with just 1591 * one occurrence. If we receive at least two in two 1592 * consecutive ticks, then we treat as boost candidate. 1593 */ 1594 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 1595 do_io = true; 1596 1597 cpu->last_io_update = time; 1598 1599 if (do_io) 1600 intel_pstate_hwp_boost_up(cpu); 1601 1602 } else { 1603 intel_pstate_hwp_boost_down(cpu); 1604 } 1605 } 1606 1607 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 1608 u64 time, unsigned int flags) 1609 { 1610 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1611 1612 cpu->sched_flags |= flags; 1613 1614 if (smp_processor_id() == cpu->cpu) 1615 intel_pstate_update_util_hwp_local(cpu, time); 1616 } 1617 1618 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1619 { 1620 struct sample *sample = &cpu->sample; 1621 1622 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1623 } 1624 1625 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1626 { 1627 u64 aperf, mperf; 1628 unsigned long flags; 1629 u64 tsc; 1630 1631 local_irq_save(flags); 1632 rdmsrl(MSR_IA32_APERF, aperf); 1633 rdmsrl(MSR_IA32_MPERF, mperf); 1634 tsc = rdtsc(); 1635 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1636 local_irq_restore(flags); 1637 return false; 1638 } 1639 local_irq_restore(flags); 1640 1641 cpu->last_sample_time = cpu->sample.time; 1642 cpu->sample.time = time; 1643 cpu->sample.aperf = aperf; 1644 cpu->sample.mperf = mperf; 1645 cpu->sample.tsc = tsc; 1646 cpu->sample.aperf -= cpu->prev_aperf; 1647 cpu->sample.mperf -= cpu->prev_mperf; 1648 cpu->sample.tsc -= cpu->prev_tsc; 1649 1650 cpu->prev_aperf = aperf; 1651 cpu->prev_mperf = mperf; 1652 cpu->prev_tsc = tsc; 1653 /* 1654 * First time this function is invoked in a given cycle, all of the 1655 * previous sample data fields are equal to zero or stale and they must 1656 * be populated with meaningful numbers for things to work, so assume 1657 * that sample.time will always be reset before setting the utilization 1658 * update hook and make the caller skip the sample then. 1659 */ 1660 if (cpu->last_sample_time) { 1661 intel_pstate_calc_avg_perf(cpu); 1662 return true; 1663 } 1664 return false; 1665 } 1666 1667 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1668 { 1669 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 1670 } 1671 1672 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1673 { 1674 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1675 cpu->sample.core_avg_perf); 1676 } 1677 1678 static inline int32_t get_target_pstate(struct cpudata *cpu) 1679 { 1680 struct sample *sample = &cpu->sample; 1681 int32_t busy_frac, boost; 1682 int target, avg_pstate; 1683 1684 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 1685 sample->tsc); 1686 1687 boost = cpu->iowait_boost; 1688 cpu->iowait_boost >>= 1; 1689 1690 if (busy_frac < boost) 1691 busy_frac = boost; 1692 1693 sample->busy_scaled = busy_frac * 100; 1694 1695 target = global.no_turbo || global.turbo_disabled ? 1696 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1697 target += target >> 2; 1698 target = mul_fp(target, busy_frac); 1699 if (target < cpu->pstate.min_pstate) 1700 target = cpu->pstate.min_pstate; 1701 1702 /* 1703 * If the average P-state during the previous cycle was higher than the 1704 * current target, add 50% of the difference to the target to reduce 1705 * possible performance oscillations and offset possible performance 1706 * loss related to moving the workload from one CPU to another within 1707 * a package/module. 1708 */ 1709 avg_pstate = get_avg_pstate(cpu); 1710 if (avg_pstate > target) 1711 target += (avg_pstate - target) >> 1; 1712 1713 return target; 1714 } 1715 1716 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 1717 { 1718 int max_pstate = intel_pstate_get_base_pstate(cpu); 1719 int min_pstate; 1720 1721 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 1722 max_pstate = max(min_pstate, cpu->max_perf_ratio); 1723 return clamp_t(int, pstate, min_pstate, max_pstate); 1724 } 1725 1726 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1727 { 1728 if (pstate == cpu->pstate.current_pstate) 1729 return; 1730 1731 cpu->pstate.current_pstate = pstate; 1732 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1733 } 1734 1735 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 1736 { 1737 int from = cpu->pstate.current_pstate; 1738 struct sample *sample; 1739 int target_pstate; 1740 1741 update_turbo_state(); 1742 1743 target_pstate = get_target_pstate(cpu); 1744 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 1745 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 1746 intel_pstate_update_pstate(cpu, target_pstate); 1747 1748 sample = &cpu->sample; 1749 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1750 fp_toint(sample->busy_scaled), 1751 from, 1752 cpu->pstate.current_pstate, 1753 sample->mperf, 1754 sample->aperf, 1755 sample->tsc, 1756 get_avg_frequency(cpu), 1757 fp_toint(cpu->iowait_boost * 100)); 1758 } 1759 1760 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1761 unsigned int flags) 1762 { 1763 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1764 u64 delta_ns; 1765 1766 /* Don't allow remote callbacks */ 1767 if (smp_processor_id() != cpu->cpu) 1768 return; 1769 1770 if (flags & SCHED_CPUFREQ_IOWAIT) { 1771 cpu->iowait_boost = int_tofp(1); 1772 cpu->last_update = time; 1773 /* 1774 * The last time the busy was 100% so P-state was max anyway 1775 * so avoid overhead of computation. 1776 */ 1777 if (fp_toint(cpu->sample.busy_scaled) == 100) 1778 return; 1779 1780 goto set_pstate; 1781 } else if (cpu->iowait_boost) { 1782 /* Clear iowait_boost if the CPU may have been idle. */ 1783 delta_ns = time - cpu->last_update; 1784 if (delta_ns > TICK_NSEC) 1785 cpu->iowait_boost = 0; 1786 } 1787 cpu->last_update = time; 1788 delta_ns = time - cpu->sample.time; 1789 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 1790 return; 1791 1792 set_pstate: 1793 if (intel_pstate_sample(cpu, time)) 1794 intel_pstate_adjust_pstate(cpu); 1795 } 1796 1797 static struct pstate_funcs core_funcs = { 1798 .get_max = core_get_max_pstate, 1799 .get_max_physical = core_get_max_pstate_physical, 1800 .get_min = core_get_min_pstate, 1801 .get_turbo = core_get_turbo_pstate, 1802 .get_scaling = core_get_scaling, 1803 .get_val = core_get_val, 1804 }; 1805 1806 static const struct pstate_funcs silvermont_funcs = { 1807 .get_max = atom_get_max_pstate, 1808 .get_max_physical = atom_get_max_pstate, 1809 .get_min = atom_get_min_pstate, 1810 .get_turbo = atom_get_turbo_pstate, 1811 .get_val = atom_get_val, 1812 .get_scaling = silvermont_get_scaling, 1813 .get_vid = atom_get_vid, 1814 }; 1815 1816 static const struct pstate_funcs airmont_funcs = { 1817 .get_max = atom_get_max_pstate, 1818 .get_max_physical = atom_get_max_pstate, 1819 .get_min = atom_get_min_pstate, 1820 .get_turbo = atom_get_turbo_pstate, 1821 .get_val = atom_get_val, 1822 .get_scaling = airmont_get_scaling, 1823 .get_vid = atom_get_vid, 1824 }; 1825 1826 static const struct pstate_funcs knl_funcs = { 1827 .get_max = core_get_max_pstate, 1828 .get_max_physical = core_get_max_pstate_physical, 1829 .get_min = core_get_min_pstate, 1830 .get_turbo = knl_get_turbo_pstate, 1831 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 1832 .get_scaling = core_get_scaling, 1833 .get_val = core_get_val, 1834 }; 1835 1836 #define ICPU(model, policy) \ 1837 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1838 (unsigned long)&policy } 1839 1840 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1841 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs), 1842 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs), 1843 ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs), 1844 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs), 1845 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs), 1846 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs), 1847 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs), 1848 ICPU(INTEL_FAM6_HASWELL_X, core_funcs), 1849 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs), 1850 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs), 1851 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs), 1852 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs), 1853 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs), 1854 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), 1855 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs), 1856 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), 1857 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs), 1858 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs), 1859 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs), 1860 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, core_funcs), 1861 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), 1862 {} 1863 }; 1864 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1865 1866 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1867 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), 1868 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), 1869 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), 1870 {} 1871 }; 1872 1873 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 1874 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs), 1875 {} 1876 }; 1877 1878 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = { 1879 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), 1880 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs), 1881 {} 1882 }; 1883 1884 static int intel_pstate_init_cpu(unsigned int cpunum) 1885 { 1886 struct cpudata *cpu; 1887 1888 cpu = all_cpu_data[cpunum]; 1889 1890 if (!cpu) { 1891 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 1892 if (!cpu) 1893 return -ENOMEM; 1894 1895 all_cpu_data[cpunum] = cpu; 1896 1897 cpu->epp_default = -EINVAL; 1898 cpu->epp_powersave = -EINVAL; 1899 cpu->epp_saved = -EINVAL; 1900 } 1901 1902 cpu = all_cpu_data[cpunum]; 1903 1904 cpu->cpu = cpunum; 1905 1906 if (hwp_active) { 1907 const struct x86_cpu_id *id; 1908 1909 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 1910 if (id) 1911 intel_pstate_disable_ee(cpunum); 1912 1913 intel_pstate_hwp_enable(cpu); 1914 1915 id = x86_match_cpu(intel_pstate_hwp_boost_ids); 1916 if (id && intel_pstate_acpi_pm_profile_server()) 1917 hwp_boost = true; 1918 } 1919 1920 intel_pstate_get_cpu_pstates(cpu); 1921 1922 pr_debug("controlling: cpu %d\n", cpunum); 1923 1924 return 0; 1925 } 1926 1927 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1928 { 1929 struct cpudata *cpu = all_cpu_data[cpu_num]; 1930 1931 if (hwp_active && !hwp_boost) 1932 return; 1933 1934 if (cpu->update_util_set) 1935 return; 1936 1937 /* Prevent intel_pstate_update_util() from using stale data. */ 1938 cpu->sample.time = 0; 1939 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1940 (hwp_active ? 1941 intel_pstate_update_util_hwp : 1942 intel_pstate_update_util)); 1943 cpu->update_util_set = true; 1944 } 1945 1946 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1947 { 1948 struct cpudata *cpu_data = all_cpu_data[cpu]; 1949 1950 if (!cpu_data->update_util_set) 1951 return; 1952 1953 cpufreq_remove_update_util_hook(cpu); 1954 cpu_data->update_util_set = false; 1955 synchronize_sched(); 1956 } 1957 1958 static int intel_pstate_get_max_freq(struct cpudata *cpu) 1959 { 1960 return global.turbo_disabled || global.no_turbo ? 1961 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 1962 } 1963 1964 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, 1965 struct cpudata *cpu) 1966 { 1967 int max_freq = intel_pstate_get_max_freq(cpu); 1968 int32_t max_policy_perf, min_policy_perf; 1969 int max_state, turbo_max; 1970 1971 /* 1972 * HWP needs some special consideration, because on BDX the 1973 * HWP_REQUEST uses abstract value to represent performance 1974 * rather than pure ratios. 1975 */ 1976 if (hwp_active) { 1977 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state); 1978 } else { 1979 max_state = intel_pstate_get_base_pstate(cpu); 1980 turbo_max = cpu->pstate.turbo_pstate; 1981 } 1982 1983 max_policy_perf = max_state * policy->max / max_freq; 1984 if (policy->max == policy->min) { 1985 min_policy_perf = max_policy_perf; 1986 } else { 1987 min_policy_perf = max_state * policy->min / max_freq; 1988 min_policy_perf = clamp_t(int32_t, min_policy_perf, 1989 0, max_policy_perf); 1990 } 1991 1992 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n", 1993 policy->cpu, max_state, 1994 min_policy_perf, max_policy_perf); 1995 1996 /* Normalize user input to [min_perf, max_perf] */ 1997 if (per_cpu_limits) { 1998 cpu->min_perf_ratio = min_policy_perf; 1999 cpu->max_perf_ratio = max_policy_perf; 2000 } else { 2001 int32_t global_min, global_max; 2002 2003 /* Global limits are in percent of the maximum turbo P-state. */ 2004 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2005 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2006 global_min = clamp_t(int32_t, global_min, 0, global_max); 2007 2008 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu, 2009 global_min, global_max); 2010 2011 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2012 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2013 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2014 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2015 2016 /* Make sure min_perf <= max_perf */ 2017 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2018 cpu->max_perf_ratio); 2019 2020 } 2021 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu, 2022 cpu->max_perf_ratio, 2023 cpu->min_perf_ratio); 2024 } 2025 2026 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2027 { 2028 struct cpudata *cpu; 2029 2030 if (!policy->cpuinfo.max_freq) 2031 return -ENODEV; 2032 2033 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2034 policy->cpuinfo.max_freq, policy->max); 2035 2036 cpu = all_cpu_data[policy->cpu]; 2037 cpu->policy = policy->policy; 2038 2039 mutex_lock(&intel_pstate_limits_lock); 2040 2041 intel_pstate_update_perf_limits(policy, cpu); 2042 2043 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2044 /* 2045 * NOHZ_FULL CPUs need this as the governor callback may not 2046 * be invoked on them. 2047 */ 2048 intel_pstate_clear_update_util_hook(policy->cpu); 2049 intel_pstate_max_within_limits(cpu); 2050 } else { 2051 intel_pstate_set_update_util_hook(policy->cpu); 2052 } 2053 2054 if (hwp_active) { 2055 /* 2056 * When hwp_boost was active before and dynamically it 2057 * was turned off, in that case we need to clear the 2058 * update util hook. 2059 */ 2060 if (!hwp_boost) 2061 intel_pstate_clear_update_util_hook(policy->cpu); 2062 intel_pstate_hwp_set(policy->cpu); 2063 } 2064 2065 mutex_unlock(&intel_pstate_limits_lock); 2066 2067 return 0; 2068 } 2069 2070 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy, 2071 struct cpudata *cpu) 2072 { 2073 if (!hwp_active && 2074 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2075 policy->max < policy->cpuinfo.max_freq && 2076 policy->max > cpu->pstate.max_freq) { 2077 pr_debug("policy->max > max non turbo frequency\n"); 2078 policy->max = policy->cpuinfo.max_freq; 2079 } 2080 } 2081 2082 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 2083 { 2084 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2085 2086 update_turbo_state(); 2087 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 2088 intel_pstate_get_max_freq(cpu)); 2089 2090 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 2091 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 2092 return -EINVAL; 2093 2094 intel_pstate_adjust_policy_max(policy, cpu); 2095 2096 return 0; 2097 } 2098 2099 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) 2100 { 2101 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); 2102 } 2103 2104 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 2105 { 2106 pr_debug("CPU %d exiting\n", policy->cpu); 2107 2108 intel_pstate_clear_update_util_hook(policy->cpu); 2109 if (hwp_active) { 2110 intel_pstate_hwp_save_state(policy); 2111 intel_pstate_hwp_force_min_perf(policy->cpu); 2112 } else { 2113 intel_cpufreq_stop_cpu(policy); 2114 } 2115 } 2116 2117 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2118 { 2119 intel_pstate_exit_perf_limits(policy); 2120 2121 policy->fast_switch_possible = false; 2122 2123 return 0; 2124 } 2125 2126 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2127 { 2128 struct cpudata *cpu; 2129 int rc; 2130 2131 rc = intel_pstate_init_cpu(policy->cpu); 2132 if (rc) 2133 return rc; 2134 2135 cpu = all_cpu_data[policy->cpu]; 2136 2137 cpu->max_perf_ratio = 0xFF; 2138 cpu->min_perf_ratio = 0; 2139 2140 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 2141 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 2142 2143 /* cpuinfo and default policy values */ 2144 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 2145 update_turbo_state(); 2146 policy->cpuinfo.max_freq = global.turbo_disabled ? 2147 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2148 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 2149 2150 if (hwp_active) { 2151 unsigned int max_freq; 2152 2153 max_freq = global.turbo_disabled ? 2154 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2155 if (max_freq < policy->cpuinfo.max_freq) 2156 policy->cpuinfo.max_freq = max_freq; 2157 } 2158 2159 intel_pstate_init_acpi_perf_limits(policy); 2160 2161 policy->fast_switch_possible = true; 2162 2163 return 0; 2164 } 2165 2166 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2167 { 2168 int ret = __intel_pstate_cpu_init(policy); 2169 2170 if (ret) 2171 return ret; 2172 2173 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) 2174 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 2175 else 2176 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2177 2178 return 0; 2179 } 2180 2181 static struct cpufreq_driver intel_pstate = { 2182 .flags = CPUFREQ_CONST_LOOPS, 2183 .verify = intel_pstate_verify_policy, 2184 .setpolicy = intel_pstate_set_policy, 2185 .suspend = intel_pstate_hwp_save_state, 2186 .resume = intel_pstate_resume, 2187 .init = intel_pstate_cpu_init, 2188 .exit = intel_pstate_cpu_exit, 2189 .stop_cpu = intel_pstate_stop_cpu, 2190 .name = "intel_pstate", 2191 }; 2192 2193 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) 2194 { 2195 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2196 2197 update_turbo_state(); 2198 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 2199 intel_pstate_get_max_freq(cpu)); 2200 2201 intel_pstate_adjust_policy_max(policy, cpu); 2202 2203 intel_pstate_update_perf_limits(policy, cpu); 2204 2205 return 0; 2206 } 2207 2208 /* Use of trace in passive mode: 2209 * 2210 * In passive mode the trace core_busy field (also known as the 2211 * performance field, and lablelled as such on the graphs; also known as 2212 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2213 * driver call was via the normal or fast switch path. Various graphs 2214 * output from the intel_pstate_tracer.py utility that include core_busy 2215 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2216 * so we use 10 to indicate the the normal path through the driver, and 2217 * 90 to indicate the fast switch path through the driver. 2218 * The scaled_busy field is not used, and is set to 0. 2219 */ 2220 2221 #define INTEL_PSTATE_TRACE_TARGET 10 2222 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2223 2224 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2225 { 2226 struct sample *sample; 2227 2228 if (!trace_pstate_sample_enabled()) 2229 return; 2230 2231 if (!intel_pstate_sample(cpu, ktime_get())) 2232 return; 2233 2234 sample = &cpu->sample; 2235 trace_pstate_sample(trace_type, 2236 0, 2237 old_pstate, 2238 cpu->pstate.current_pstate, 2239 sample->mperf, 2240 sample->aperf, 2241 sample->tsc, 2242 get_avg_frequency(cpu), 2243 fp_toint(cpu->iowait_boost * 100)); 2244 } 2245 2246 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2247 unsigned int target_freq, 2248 unsigned int relation) 2249 { 2250 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2251 struct cpufreq_freqs freqs; 2252 int target_pstate, old_pstate; 2253 2254 update_turbo_state(); 2255 2256 freqs.old = policy->cur; 2257 freqs.new = target_freq; 2258 2259 cpufreq_freq_transition_begin(policy, &freqs); 2260 switch (relation) { 2261 case CPUFREQ_RELATION_L: 2262 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2263 break; 2264 case CPUFREQ_RELATION_H: 2265 target_pstate = freqs.new / cpu->pstate.scaling; 2266 break; 2267 default: 2268 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2269 break; 2270 } 2271 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2272 old_pstate = cpu->pstate.current_pstate; 2273 if (target_pstate != cpu->pstate.current_pstate) { 2274 cpu->pstate.current_pstate = target_pstate; 2275 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, 2276 pstate_funcs.get_val(cpu, target_pstate)); 2277 } 2278 freqs.new = target_pstate * cpu->pstate.scaling; 2279 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate); 2280 cpufreq_freq_transition_end(policy, &freqs, false); 2281 2282 return 0; 2283 } 2284 2285 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2286 unsigned int target_freq) 2287 { 2288 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2289 int target_pstate, old_pstate; 2290 2291 update_turbo_state(); 2292 2293 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2294 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2295 old_pstate = cpu->pstate.current_pstate; 2296 intel_pstate_update_pstate(cpu, target_pstate); 2297 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2298 return target_pstate * cpu->pstate.scaling; 2299 } 2300 2301 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2302 { 2303 int ret = __intel_pstate_cpu_init(policy); 2304 2305 if (ret) 2306 return ret; 2307 2308 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2309 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2310 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2311 policy->cur = policy->cpuinfo.min_freq; 2312 2313 return 0; 2314 } 2315 2316 static struct cpufreq_driver intel_cpufreq = { 2317 .flags = CPUFREQ_CONST_LOOPS, 2318 .verify = intel_cpufreq_verify_policy, 2319 .target = intel_cpufreq_target, 2320 .fast_switch = intel_cpufreq_fast_switch, 2321 .init = intel_cpufreq_cpu_init, 2322 .exit = intel_pstate_cpu_exit, 2323 .stop_cpu = intel_cpufreq_stop_cpu, 2324 .name = "intel_cpufreq", 2325 }; 2326 2327 static struct cpufreq_driver *default_driver = &intel_pstate; 2328 2329 static void intel_pstate_driver_cleanup(void) 2330 { 2331 unsigned int cpu; 2332 2333 get_online_cpus(); 2334 for_each_online_cpu(cpu) { 2335 if (all_cpu_data[cpu]) { 2336 if (intel_pstate_driver == &intel_pstate) 2337 intel_pstate_clear_update_util_hook(cpu); 2338 2339 kfree(all_cpu_data[cpu]); 2340 all_cpu_data[cpu] = NULL; 2341 } 2342 } 2343 put_online_cpus(); 2344 intel_pstate_driver = NULL; 2345 } 2346 2347 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 2348 { 2349 int ret; 2350 2351 memset(&global, 0, sizeof(global)); 2352 global.max_perf_pct = 100; 2353 2354 intel_pstate_driver = driver; 2355 ret = cpufreq_register_driver(intel_pstate_driver); 2356 if (ret) { 2357 intel_pstate_driver_cleanup(); 2358 return ret; 2359 } 2360 2361 global.min_perf_pct = min_perf_pct_min(); 2362 2363 return 0; 2364 } 2365 2366 static int intel_pstate_unregister_driver(void) 2367 { 2368 if (hwp_active) 2369 return -EBUSY; 2370 2371 cpufreq_unregister_driver(intel_pstate_driver); 2372 intel_pstate_driver_cleanup(); 2373 2374 return 0; 2375 } 2376 2377 static ssize_t intel_pstate_show_status(char *buf) 2378 { 2379 if (!intel_pstate_driver) 2380 return sprintf(buf, "off\n"); 2381 2382 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 2383 "active" : "passive"); 2384 } 2385 2386 static int intel_pstate_update_status(const char *buf, size_t size) 2387 { 2388 int ret; 2389 2390 if (size == 3 && !strncmp(buf, "off", size)) 2391 return intel_pstate_driver ? 2392 intel_pstate_unregister_driver() : -EINVAL; 2393 2394 if (size == 6 && !strncmp(buf, "active", size)) { 2395 if (intel_pstate_driver) { 2396 if (intel_pstate_driver == &intel_pstate) 2397 return 0; 2398 2399 ret = intel_pstate_unregister_driver(); 2400 if (ret) 2401 return ret; 2402 } 2403 2404 return intel_pstate_register_driver(&intel_pstate); 2405 } 2406 2407 if (size == 7 && !strncmp(buf, "passive", size)) { 2408 if (intel_pstate_driver) { 2409 if (intel_pstate_driver == &intel_cpufreq) 2410 return 0; 2411 2412 ret = intel_pstate_unregister_driver(); 2413 if (ret) 2414 return ret; 2415 } 2416 2417 return intel_pstate_register_driver(&intel_cpufreq); 2418 } 2419 2420 return -EINVAL; 2421 } 2422 2423 static int no_load __initdata; 2424 static int no_hwp __initdata; 2425 static int hwp_only __initdata; 2426 static unsigned int force_load __initdata; 2427 2428 static int __init intel_pstate_msrs_not_valid(void) 2429 { 2430 if (!pstate_funcs.get_max() || 2431 !pstate_funcs.get_min() || 2432 !pstate_funcs.get_turbo()) 2433 return -ENODEV; 2434 2435 return 0; 2436 } 2437 2438 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 2439 { 2440 pstate_funcs.get_max = funcs->get_max; 2441 pstate_funcs.get_max_physical = funcs->get_max_physical; 2442 pstate_funcs.get_min = funcs->get_min; 2443 pstate_funcs.get_turbo = funcs->get_turbo; 2444 pstate_funcs.get_scaling = funcs->get_scaling; 2445 pstate_funcs.get_val = funcs->get_val; 2446 pstate_funcs.get_vid = funcs->get_vid; 2447 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 2448 } 2449 2450 #ifdef CONFIG_ACPI 2451 2452 static bool __init intel_pstate_no_acpi_pss(void) 2453 { 2454 int i; 2455 2456 for_each_possible_cpu(i) { 2457 acpi_status status; 2458 union acpi_object *pss; 2459 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2460 struct acpi_processor *pr = per_cpu(processors, i); 2461 2462 if (!pr) 2463 continue; 2464 2465 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 2466 if (ACPI_FAILURE(status)) 2467 continue; 2468 2469 pss = buffer.pointer; 2470 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 2471 kfree(pss); 2472 return false; 2473 } 2474 2475 kfree(pss); 2476 } 2477 2478 return true; 2479 } 2480 2481 static bool __init intel_pstate_no_acpi_pcch(void) 2482 { 2483 acpi_status status; 2484 acpi_handle handle; 2485 2486 status = acpi_get_handle(NULL, "\\_SB", &handle); 2487 if (ACPI_FAILURE(status)) 2488 return true; 2489 2490 return !acpi_has_method(handle, "PCCH"); 2491 } 2492 2493 static bool __init intel_pstate_has_acpi_ppc(void) 2494 { 2495 int i; 2496 2497 for_each_possible_cpu(i) { 2498 struct acpi_processor *pr = per_cpu(processors, i); 2499 2500 if (!pr) 2501 continue; 2502 if (acpi_has_method(pr->handle, "_PPC")) 2503 return true; 2504 } 2505 return false; 2506 } 2507 2508 enum { 2509 PSS, 2510 PPC, 2511 }; 2512 2513 /* Hardware vendor-specific info that has its own power management modes */ 2514 static struct acpi_platform_list plat_info[] __initdata = { 2515 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS}, 2516 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2517 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2518 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2519 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2520 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2521 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2522 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2523 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2524 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2525 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2526 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2527 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2528 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2529 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, 2530 { } /* End */ 2531 }; 2532 2533 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 2534 { 2535 const struct x86_cpu_id *id; 2536 u64 misc_pwr; 2537 int idx; 2538 2539 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 2540 if (id) { 2541 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 2542 if ( misc_pwr & (1 << 8)) 2543 return true; 2544 } 2545 2546 idx = acpi_match_platform_list(plat_info); 2547 if (idx < 0) 2548 return false; 2549 2550 switch (plat_info[idx].data) { 2551 case PSS: 2552 if (!intel_pstate_no_acpi_pss()) 2553 return false; 2554 2555 return intel_pstate_no_acpi_pcch(); 2556 case PPC: 2557 return intel_pstate_has_acpi_ppc() && !force_load; 2558 } 2559 2560 return false; 2561 } 2562 2563 static void intel_pstate_request_control_from_smm(void) 2564 { 2565 /* 2566 * It may be unsafe to request P-states control from SMM if _PPC support 2567 * has not been enabled. 2568 */ 2569 if (acpi_ppc) 2570 acpi_processor_pstate_control(); 2571 } 2572 #else /* CONFIG_ACPI not enabled */ 2573 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 2574 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 2575 static inline void intel_pstate_request_control_from_smm(void) {} 2576 #endif /* CONFIG_ACPI */ 2577 2578 #define INTEL_PSTATE_HWP_BROADWELL 0x01 2579 2580 #define ICPU_HWP(model, hwp_mode) \ 2581 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode } 2582 2583 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 2584 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 2585 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL), 2586 ICPU_HWP(X86_MODEL_ANY, 0), 2587 {} 2588 }; 2589 2590 static int __init intel_pstate_init(void) 2591 { 2592 const struct x86_cpu_id *id; 2593 int rc; 2594 2595 if (no_load) 2596 return -ENODEV; 2597 2598 id = x86_match_cpu(hwp_support_ids); 2599 if (id) { 2600 copy_cpu_funcs(&core_funcs); 2601 if (!no_hwp) { 2602 hwp_active++; 2603 hwp_mode_bdw = id->driver_data; 2604 intel_pstate.attr = hwp_cpufreq_attrs; 2605 goto hwp_cpu_matched; 2606 } 2607 } else { 2608 id = x86_match_cpu(intel_pstate_cpu_ids); 2609 if (!id) 2610 return -ENODEV; 2611 2612 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 2613 } 2614 2615 if (intel_pstate_msrs_not_valid()) 2616 return -ENODEV; 2617 2618 hwp_cpu_matched: 2619 /* 2620 * The Intel pstate driver will be ignored if the platform 2621 * firmware has its own power management modes. 2622 */ 2623 if (intel_pstate_platform_pwr_mgmt_exists()) 2624 return -ENODEV; 2625 2626 if (!hwp_active && hwp_only) 2627 return -ENOTSUPP; 2628 2629 pr_info("Intel P-state driver initializing\n"); 2630 2631 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 2632 if (!all_cpu_data) 2633 return -ENOMEM; 2634 2635 intel_pstate_request_control_from_smm(); 2636 2637 intel_pstate_sysfs_expose_params(); 2638 2639 mutex_lock(&intel_pstate_driver_lock); 2640 rc = intel_pstate_register_driver(default_driver); 2641 mutex_unlock(&intel_pstate_driver_lock); 2642 if (rc) 2643 return rc; 2644 2645 if (hwp_active) 2646 pr_info("HWP enabled\n"); 2647 2648 return 0; 2649 } 2650 device_initcall(intel_pstate_init); 2651 2652 static int __init intel_pstate_setup(char *str) 2653 { 2654 if (!str) 2655 return -EINVAL; 2656 2657 if (!strcmp(str, "disable")) { 2658 no_load = 1; 2659 } else if (!strcmp(str, "passive")) { 2660 pr_info("Passive mode enabled\n"); 2661 default_driver = &intel_cpufreq; 2662 no_hwp = 1; 2663 } 2664 if (!strcmp(str, "no_hwp")) { 2665 pr_info("HWP disabled\n"); 2666 no_hwp = 1; 2667 } 2668 if (!strcmp(str, "force")) 2669 force_load = 1; 2670 if (!strcmp(str, "hwp_only")) 2671 hwp_only = 1; 2672 if (!strcmp(str, "per_cpu_perf_limits")) 2673 per_cpu_limits = true; 2674 2675 #ifdef CONFIG_ACPI 2676 if (!strcmp(str, "support_acpi_ppc")) 2677 acpi_ppc = true; 2678 #endif 2679 2680 return 0; 2681 } 2682 early_param("intel_pstate", intel_pstate_setup); 2683 2684 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 2685 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 2686 MODULE_LICENSE("GPL"); 2687