1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 39 #define ATOM_RATIOS 0x66a 40 #define ATOM_VIDS 0x66b 41 #define ATOM_TURBO_RATIOS 0x66c 42 #define ATOM_TURBO_VIDS 0x66d 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #endif 47 48 #define FRAC_BITS 8 49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 50 #define fp_toint(X) ((X) >> FRAC_BITS) 51 52 #define EXT_BITS 6 53 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 54 55 static inline int32_t mul_fp(int32_t x, int32_t y) 56 { 57 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 58 } 59 60 static inline int32_t div_fp(s64 x, s64 y) 61 { 62 return div64_s64((int64_t)x << FRAC_BITS, y); 63 } 64 65 static inline int ceiling_fp(int32_t x) 66 { 67 int mask, ret; 68 69 ret = fp_toint(x); 70 mask = (1 << FRAC_BITS) - 1; 71 if (x & mask) 72 ret += 1; 73 return ret; 74 } 75 76 static inline u64 mul_ext_fp(u64 x, u64 y) 77 { 78 return (x * y) >> EXT_FRAC_BITS; 79 } 80 81 static inline u64 div_ext_fp(u64 x, u64 y) 82 { 83 return div64_u64(x << EXT_FRAC_BITS, y); 84 } 85 86 /** 87 * struct sample - Store performance sample 88 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 89 * performance during last sample period 90 * @busy_scaled: Scaled busy value which is used to calculate next 91 * P state. This can be different than core_avg_perf 92 * to account for cpu idle period 93 * @aperf: Difference of actual performance frequency clock count 94 * read from APERF MSR between last and current sample 95 * @mperf: Difference of maximum performance frequency clock count 96 * read from MPERF MSR between last and current sample 97 * @tsc: Difference of time stamp counter between last and 98 * current sample 99 * @freq: Effective frequency calculated from APERF/MPERF 100 * @time: Current time from scheduler 101 * 102 * This structure is used in the cpudata structure to store performance sample 103 * data for choosing next P State. 104 */ 105 struct sample { 106 int32_t core_avg_perf; 107 int32_t busy_scaled; 108 u64 aperf; 109 u64 mperf; 110 u64 tsc; 111 int freq; 112 u64 time; 113 }; 114 115 /** 116 * struct pstate_data - Store P state data 117 * @current_pstate: Current requested P state 118 * @min_pstate: Min P state possible for this platform 119 * @max_pstate: Max P state possible for this platform 120 * @max_pstate_physical:This is physical Max P state for a processor 121 * This can be higher than the max_pstate which can 122 * be limited by platform thermal design power limits 123 * @scaling: Scaling factor to convert frequency to cpufreq 124 * frequency units 125 * @turbo_pstate: Max Turbo P state possible for this platform 126 * 127 * Stores the per cpu model P state limits and current P state. 128 */ 129 struct pstate_data { 130 int current_pstate; 131 int min_pstate; 132 int max_pstate; 133 int max_pstate_physical; 134 int scaling; 135 int turbo_pstate; 136 }; 137 138 /** 139 * struct vid_data - Stores voltage information data 140 * @min: VID data for this platform corresponding to 141 * the lowest P state 142 * @max: VID data corresponding to the highest P State. 143 * @turbo: VID data for turbo P state 144 * @ratio: Ratio of (vid max - vid min) / 145 * (max P state - Min P State) 146 * 147 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 148 * This data is used in Atom platforms, where in addition to target P state, 149 * the voltage data needs to be specified to select next P State. 150 */ 151 struct vid_data { 152 int min; 153 int max; 154 int turbo; 155 int32_t ratio; 156 }; 157 158 /** 159 * struct _pid - Stores PID data 160 * @setpoint: Target set point for busyness or performance 161 * @integral: Storage for accumulated error values 162 * @p_gain: PID proportional gain 163 * @i_gain: PID integral gain 164 * @d_gain: PID derivative gain 165 * @deadband: PID deadband 166 * @last_err: Last error storage for integral part of PID calculation 167 * 168 * Stores PID coefficients and last error for PID controller. 169 */ 170 struct _pid { 171 int setpoint; 172 int32_t integral; 173 int32_t p_gain; 174 int32_t i_gain; 175 int32_t d_gain; 176 int deadband; 177 int32_t last_err; 178 }; 179 180 /** 181 * struct cpudata - Per CPU instance data storage 182 * @cpu: CPU number for this instance data 183 * @update_util: CPUFreq utility callback information 184 * @update_util_set: CPUFreq utility callback is set 185 * @pstate: Stores P state limits for this CPU 186 * @vid: Stores VID limits for this CPU 187 * @pid: Stores PID parameters for this CPU 188 * @last_sample_time: Last Sample time 189 * @prev_aperf: Last APERF value read from APERF MSR 190 * @prev_mperf: Last MPERF value read from MPERF MSR 191 * @prev_tsc: Last timestamp counter (TSC) value 192 * @prev_cummulative_iowait: IO Wait time difference from last and 193 * current sample 194 * @sample: Storage for storing last Sample data 195 * @acpi_perf_data: Stores ACPI perf information read from _PSS 196 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 197 * 198 * This structure stores per CPU instance data for all CPUs. 199 */ 200 struct cpudata { 201 int cpu; 202 203 struct update_util_data update_util; 204 bool update_util_set; 205 206 struct pstate_data pstate; 207 struct vid_data vid; 208 struct _pid pid; 209 210 u64 last_sample_time; 211 u64 prev_aperf; 212 u64 prev_mperf; 213 u64 prev_tsc; 214 u64 prev_cummulative_iowait; 215 struct sample sample; 216 #ifdef CONFIG_ACPI 217 struct acpi_processor_performance acpi_perf_data; 218 bool valid_pss_table; 219 #endif 220 }; 221 222 static struct cpudata **all_cpu_data; 223 224 /** 225 * struct pid_adjust_policy - Stores static PID configuration data 226 * @sample_rate_ms: PID calculation sample rate in ms 227 * @sample_rate_ns: Sample rate calculation in ns 228 * @deadband: PID deadband 229 * @setpoint: PID Setpoint 230 * @p_gain_pct: PID proportional gain 231 * @i_gain_pct: PID integral gain 232 * @d_gain_pct: PID derivative gain 233 * 234 * Stores per CPU model static PID configuration data. 235 */ 236 struct pstate_adjust_policy { 237 int sample_rate_ms; 238 s64 sample_rate_ns; 239 int deadband; 240 int setpoint; 241 int p_gain_pct; 242 int d_gain_pct; 243 int i_gain_pct; 244 }; 245 246 /** 247 * struct pstate_funcs - Per CPU model specific callbacks 248 * @get_max: Callback to get maximum non turbo effective P state 249 * @get_max_physical: Callback to get maximum non turbo physical P state 250 * @get_min: Callback to get minimum P state 251 * @get_turbo: Callback to get turbo P state 252 * @get_scaling: Callback to get frequency scaling factor 253 * @get_val: Callback to convert P state to actual MSR write value 254 * @get_vid: Callback to get VID data for Atom platforms 255 * @get_target_pstate: Callback to a function to calculate next P state to use 256 * 257 * Core and Atom CPU models have different way to get P State limits. This 258 * structure is used to store those callbacks. 259 */ 260 struct pstate_funcs { 261 int (*get_max)(void); 262 int (*get_max_physical)(void); 263 int (*get_min)(void); 264 int (*get_turbo)(void); 265 int (*get_scaling)(void); 266 u64 (*get_val)(struct cpudata*, int pstate); 267 void (*get_vid)(struct cpudata *); 268 int32_t (*get_target_pstate)(struct cpudata *); 269 }; 270 271 /** 272 * struct cpu_defaults- Per CPU model default config data 273 * @pid_policy: PID config data 274 * @funcs: Callback function data 275 */ 276 struct cpu_defaults { 277 struct pstate_adjust_policy pid_policy; 278 struct pstate_funcs funcs; 279 }; 280 281 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 282 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 283 284 static struct pstate_adjust_policy pid_params; 285 static struct pstate_funcs pstate_funcs; 286 static int hwp_active; 287 288 #ifdef CONFIG_ACPI 289 static bool acpi_ppc; 290 #endif 291 292 /** 293 * struct perf_limits - Store user and policy limits 294 * @no_turbo: User requested turbo state from intel_pstate sysfs 295 * @turbo_disabled: Platform turbo status either from msr 296 * MSR_IA32_MISC_ENABLE or when maximum available pstate 297 * matches the maximum turbo pstate 298 * @max_perf_pct: Effective maximum performance limit in percentage, this 299 * is minimum of either limits enforced by cpufreq policy 300 * or limits from user set limits via intel_pstate sysfs 301 * @min_perf_pct: Effective minimum performance limit in percentage, this 302 * is maximum of either limits enforced by cpufreq policy 303 * or limits from user set limits via intel_pstate sysfs 304 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 305 * This value is used to limit max pstate 306 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 307 * This value is used to limit min pstate 308 * @max_policy_pct: The maximum performance in percentage enforced by 309 * cpufreq setpolicy interface 310 * @max_sysfs_pct: The maximum performance in percentage enforced by 311 * intel pstate sysfs interface 312 * @min_policy_pct: The minimum performance in percentage enforced by 313 * cpufreq setpolicy interface 314 * @min_sysfs_pct: The minimum performance in percentage enforced by 315 * intel pstate sysfs interface 316 * 317 * Storage for user and policy defined limits. 318 */ 319 struct perf_limits { 320 int no_turbo; 321 int turbo_disabled; 322 int max_perf_pct; 323 int min_perf_pct; 324 int32_t max_perf; 325 int32_t min_perf; 326 int max_policy_pct; 327 int max_sysfs_pct; 328 int min_policy_pct; 329 int min_sysfs_pct; 330 }; 331 332 static struct perf_limits performance_limits = { 333 .no_turbo = 0, 334 .turbo_disabled = 0, 335 .max_perf_pct = 100, 336 .max_perf = int_tofp(1), 337 .min_perf_pct = 100, 338 .min_perf = int_tofp(1), 339 .max_policy_pct = 100, 340 .max_sysfs_pct = 100, 341 .min_policy_pct = 0, 342 .min_sysfs_pct = 0, 343 }; 344 345 static struct perf_limits powersave_limits = { 346 .no_turbo = 0, 347 .turbo_disabled = 0, 348 .max_perf_pct = 100, 349 .max_perf = int_tofp(1), 350 .min_perf_pct = 0, 351 .min_perf = 0, 352 .max_policy_pct = 100, 353 .max_sysfs_pct = 100, 354 .min_policy_pct = 0, 355 .min_sysfs_pct = 0, 356 }; 357 358 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 359 static struct perf_limits *limits = &performance_limits; 360 #else 361 static struct perf_limits *limits = &powersave_limits; 362 #endif 363 364 #ifdef CONFIG_ACPI 365 366 static bool intel_pstate_get_ppc_enable_status(void) 367 { 368 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 369 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 370 return true; 371 372 return acpi_ppc; 373 } 374 375 /* 376 * The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and 377 * in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and 378 * max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state 379 * ratio, out of it only high 8 bits are used. For example 0x1700 is setting 380 * target ratio 0x17. The _PSS control value stores in a format which can be 381 * directly written to PERF_CTL MSR. But in intel_pstate driver this shift 382 * occurs during write to PERF_CTL (E.g. for cores core_set_pstate()). 383 * This function converts the _PSS control value to intel pstate driver format 384 * for comparison and assignment. 385 */ 386 static int convert_to_native_pstate_format(struct cpudata *cpu, int index) 387 { 388 return cpu->acpi_perf_data.states[index].control >> 8; 389 } 390 391 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 392 { 393 struct cpudata *cpu; 394 int turbo_pss_ctl; 395 int ret; 396 int i; 397 398 if (hwp_active) 399 return; 400 401 if (!intel_pstate_get_ppc_enable_status()) 402 return; 403 404 cpu = all_cpu_data[policy->cpu]; 405 406 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 407 policy->cpu); 408 if (ret) 409 return; 410 411 /* 412 * Check if the control value in _PSS is for PERF_CTL MSR, which should 413 * guarantee that the states returned by it map to the states in our 414 * list directly. 415 */ 416 if (cpu->acpi_perf_data.control_register.space_id != 417 ACPI_ADR_SPACE_FIXED_HARDWARE) 418 goto err; 419 420 /* 421 * If there is only one entry _PSS, simply ignore _PSS and continue as 422 * usual without taking _PSS into account 423 */ 424 if (cpu->acpi_perf_data.state_count < 2) 425 goto err; 426 427 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 428 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 429 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 430 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 431 (u32) cpu->acpi_perf_data.states[i].core_frequency, 432 (u32) cpu->acpi_perf_data.states[i].power, 433 (u32) cpu->acpi_perf_data.states[i].control); 434 } 435 436 /* 437 * The _PSS table doesn't contain whole turbo frequency range. 438 * This just contains +1 MHZ above the max non turbo frequency, 439 * with control value corresponding to max turbo ratio. But 440 * when cpufreq set policy is called, it will call with this 441 * max frequency, which will cause a reduced performance as 442 * this driver uses real max turbo frequency as the max 443 * frequency. So correct this frequency in _PSS table to 444 * correct max turbo frequency based on the turbo ratio. 445 * Also need to convert to MHz as _PSS freq is in MHz. 446 */ 447 turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0); 448 if (turbo_pss_ctl > cpu->pstate.max_pstate) 449 cpu->acpi_perf_data.states[0].core_frequency = 450 policy->cpuinfo.max_freq / 1000; 451 cpu->valid_pss_table = true; 452 pr_info("_PPC limits will be enforced\n"); 453 454 return; 455 456 err: 457 cpu->valid_pss_table = false; 458 acpi_processor_unregister_performance(policy->cpu); 459 } 460 461 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 462 { 463 struct cpudata *cpu; 464 465 cpu = all_cpu_data[policy->cpu]; 466 if (!cpu->valid_pss_table) 467 return; 468 469 acpi_processor_unregister_performance(policy->cpu); 470 } 471 472 #else 473 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 474 { 475 } 476 477 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 478 { 479 } 480 #endif 481 482 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 483 int deadband, int integral) { 484 pid->setpoint = int_tofp(setpoint); 485 pid->deadband = int_tofp(deadband); 486 pid->integral = int_tofp(integral); 487 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 488 } 489 490 static inline void pid_p_gain_set(struct _pid *pid, int percent) 491 { 492 pid->p_gain = div_fp(percent, 100); 493 } 494 495 static inline void pid_i_gain_set(struct _pid *pid, int percent) 496 { 497 pid->i_gain = div_fp(percent, 100); 498 } 499 500 static inline void pid_d_gain_set(struct _pid *pid, int percent) 501 { 502 pid->d_gain = div_fp(percent, 100); 503 } 504 505 static signed int pid_calc(struct _pid *pid, int32_t busy) 506 { 507 signed int result; 508 int32_t pterm, dterm, fp_error; 509 int32_t integral_limit; 510 511 fp_error = pid->setpoint - busy; 512 513 if (abs(fp_error) <= pid->deadband) 514 return 0; 515 516 pterm = mul_fp(pid->p_gain, fp_error); 517 518 pid->integral += fp_error; 519 520 /* 521 * We limit the integral here so that it will never 522 * get higher than 30. This prevents it from becoming 523 * too large an input over long periods of time and allows 524 * it to get factored out sooner. 525 * 526 * The value of 30 was chosen through experimentation. 527 */ 528 integral_limit = int_tofp(30); 529 if (pid->integral > integral_limit) 530 pid->integral = integral_limit; 531 if (pid->integral < -integral_limit) 532 pid->integral = -integral_limit; 533 534 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 535 pid->last_err = fp_error; 536 537 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 538 result = result + (1 << (FRAC_BITS-1)); 539 return (signed int)fp_toint(result); 540 } 541 542 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 543 { 544 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 545 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 546 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 547 548 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 549 } 550 551 static inline void intel_pstate_reset_all_pid(void) 552 { 553 unsigned int cpu; 554 555 for_each_online_cpu(cpu) { 556 if (all_cpu_data[cpu]) 557 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 558 } 559 } 560 561 static inline void update_turbo_state(void) 562 { 563 u64 misc_en; 564 struct cpudata *cpu; 565 566 cpu = all_cpu_data[0]; 567 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 568 limits->turbo_disabled = 569 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 570 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 571 } 572 573 static void intel_pstate_hwp_set(const struct cpumask *cpumask) 574 { 575 int min, hw_min, max, hw_max, cpu, range, adj_range; 576 u64 value, cap; 577 578 rdmsrl(MSR_HWP_CAPABILITIES, cap); 579 hw_min = HWP_LOWEST_PERF(cap); 580 hw_max = HWP_HIGHEST_PERF(cap); 581 range = hw_max - hw_min; 582 583 for_each_cpu(cpu, cpumask) { 584 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 585 adj_range = limits->min_perf_pct * range / 100; 586 min = hw_min + adj_range; 587 value &= ~HWP_MIN_PERF(~0L); 588 value |= HWP_MIN_PERF(min); 589 590 adj_range = limits->max_perf_pct * range / 100; 591 max = hw_min + adj_range; 592 if (limits->no_turbo) { 593 hw_max = HWP_GUARANTEED_PERF(cap); 594 if (hw_max < max) 595 max = hw_max; 596 } 597 598 value &= ~HWP_MAX_PERF(~0L); 599 value |= HWP_MAX_PERF(max); 600 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 601 } 602 } 603 604 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) 605 { 606 if (hwp_active) 607 intel_pstate_hwp_set(policy->cpus); 608 609 return 0; 610 } 611 612 static void intel_pstate_hwp_set_online_cpus(void) 613 { 614 get_online_cpus(); 615 intel_pstate_hwp_set(cpu_online_mask); 616 put_online_cpus(); 617 } 618 619 /************************** debugfs begin ************************/ 620 static int pid_param_set(void *data, u64 val) 621 { 622 *(u32 *)data = val; 623 intel_pstate_reset_all_pid(); 624 return 0; 625 } 626 627 static int pid_param_get(void *data, u64 *val) 628 { 629 *val = *(u32 *)data; 630 return 0; 631 } 632 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 633 634 struct pid_param { 635 char *name; 636 void *value; 637 }; 638 639 static struct pid_param pid_files[] = { 640 {"sample_rate_ms", &pid_params.sample_rate_ms}, 641 {"d_gain_pct", &pid_params.d_gain_pct}, 642 {"i_gain_pct", &pid_params.i_gain_pct}, 643 {"deadband", &pid_params.deadband}, 644 {"setpoint", &pid_params.setpoint}, 645 {"p_gain_pct", &pid_params.p_gain_pct}, 646 {NULL, NULL} 647 }; 648 649 static void __init intel_pstate_debug_expose_params(void) 650 { 651 struct dentry *debugfs_parent; 652 int i = 0; 653 654 if (hwp_active) 655 return; 656 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 657 if (IS_ERR_OR_NULL(debugfs_parent)) 658 return; 659 while (pid_files[i].name) { 660 debugfs_create_file(pid_files[i].name, 0660, 661 debugfs_parent, pid_files[i].value, 662 &fops_pid_param); 663 i++; 664 } 665 } 666 667 /************************** debugfs end ************************/ 668 669 /************************** sysfs begin ************************/ 670 #define show_one(file_name, object) \ 671 static ssize_t show_##file_name \ 672 (struct kobject *kobj, struct attribute *attr, char *buf) \ 673 { \ 674 return sprintf(buf, "%u\n", limits->object); \ 675 } 676 677 static ssize_t show_turbo_pct(struct kobject *kobj, 678 struct attribute *attr, char *buf) 679 { 680 struct cpudata *cpu; 681 int total, no_turbo, turbo_pct; 682 uint32_t turbo_fp; 683 684 cpu = all_cpu_data[0]; 685 686 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 687 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 688 turbo_fp = div_fp(no_turbo, total); 689 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 690 return sprintf(buf, "%u\n", turbo_pct); 691 } 692 693 static ssize_t show_num_pstates(struct kobject *kobj, 694 struct attribute *attr, char *buf) 695 { 696 struct cpudata *cpu; 697 int total; 698 699 cpu = all_cpu_data[0]; 700 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 701 return sprintf(buf, "%u\n", total); 702 } 703 704 static ssize_t show_no_turbo(struct kobject *kobj, 705 struct attribute *attr, char *buf) 706 { 707 ssize_t ret; 708 709 update_turbo_state(); 710 if (limits->turbo_disabled) 711 ret = sprintf(buf, "%u\n", limits->turbo_disabled); 712 else 713 ret = sprintf(buf, "%u\n", limits->no_turbo); 714 715 return ret; 716 } 717 718 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 719 const char *buf, size_t count) 720 { 721 unsigned int input; 722 int ret; 723 724 ret = sscanf(buf, "%u", &input); 725 if (ret != 1) 726 return -EINVAL; 727 728 update_turbo_state(); 729 if (limits->turbo_disabled) { 730 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 731 return -EPERM; 732 } 733 734 limits->no_turbo = clamp_t(int, input, 0, 1); 735 736 if (hwp_active) 737 intel_pstate_hwp_set_online_cpus(); 738 739 return count; 740 } 741 742 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 743 const char *buf, size_t count) 744 { 745 unsigned int input; 746 int ret; 747 748 ret = sscanf(buf, "%u", &input); 749 if (ret != 1) 750 return -EINVAL; 751 752 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); 753 limits->max_perf_pct = min(limits->max_policy_pct, 754 limits->max_sysfs_pct); 755 limits->max_perf_pct = max(limits->min_policy_pct, 756 limits->max_perf_pct); 757 limits->max_perf_pct = max(limits->min_perf_pct, 758 limits->max_perf_pct); 759 limits->max_perf = div_fp(limits->max_perf_pct, 100); 760 761 if (hwp_active) 762 intel_pstate_hwp_set_online_cpus(); 763 return count; 764 } 765 766 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 767 const char *buf, size_t count) 768 { 769 unsigned int input; 770 int ret; 771 772 ret = sscanf(buf, "%u", &input); 773 if (ret != 1) 774 return -EINVAL; 775 776 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); 777 limits->min_perf_pct = max(limits->min_policy_pct, 778 limits->min_sysfs_pct); 779 limits->min_perf_pct = min(limits->max_policy_pct, 780 limits->min_perf_pct); 781 limits->min_perf_pct = min(limits->max_perf_pct, 782 limits->min_perf_pct); 783 limits->min_perf = div_fp(limits->min_perf_pct, 100); 784 785 if (hwp_active) 786 intel_pstate_hwp_set_online_cpus(); 787 return count; 788 } 789 790 show_one(max_perf_pct, max_perf_pct); 791 show_one(min_perf_pct, min_perf_pct); 792 793 define_one_global_rw(no_turbo); 794 define_one_global_rw(max_perf_pct); 795 define_one_global_rw(min_perf_pct); 796 define_one_global_ro(turbo_pct); 797 define_one_global_ro(num_pstates); 798 799 static struct attribute *intel_pstate_attributes[] = { 800 &no_turbo.attr, 801 &max_perf_pct.attr, 802 &min_perf_pct.attr, 803 &turbo_pct.attr, 804 &num_pstates.attr, 805 NULL 806 }; 807 808 static struct attribute_group intel_pstate_attr_group = { 809 .attrs = intel_pstate_attributes, 810 }; 811 812 static void __init intel_pstate_sysfs_expose_params(void) 813 { 814 struct kobject *intel_pstate_kobject; 815 int rc; 816 817 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 818 &cpu_subsys.dev_root->kobj); 819 BUG_ON(!intel_pstate_kobject); 820 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 821 BUG_ON(rc); 822 } 823 /************************** sysfs end ************************/ 824 825 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 826 { 827 /* First disable HWP notification interrupt as we don't process them */ 828 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 829 830 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 831 } 832 833 static int atom_get_min_pstate(void) 834 { 835 u64 value; 836 837 rdmsrl(ATOM_RATIOS, value); 838 return (value >> 8) & 0x7F; 839 } 840 841 static int atom_get_max_pstate(void) 842 { 843 u64 value; 844 845 rdmsrl(ATOM_RATIOS, value); 846 return (value >> 16) & 0x7F; 847 } 848 849 static int atom_get_turbo_pstate(void) 850 { 851 u64 value; 852 853 rdmsrl(ATOM_TURBO_RATIOS, value); 854 return value & 0x7F; 855 } 856 857 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 858 { 859 u64 val; 860 int32_t vid_fp; 861 u32 vid; 862 863 val = (u64)pstate << 8; 864 if (limits->no_turbo && !limits->turbo_disabled) 865 val |= (u64)1 << 32; 866 867 vid_fp = cpudata->vid.min + mul_fp( 868 int_tofp(pstate - cpudata->pstate.min_pstate), 869 cpudata->vid.ratio); 870 871 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 872 vid = ceiling_fp(vid_fp); 873 874 if (pstate > cpudata->pstate.max_pstate) 875 vid = cpudata->vid.turbo; 876 877 return val | vid; 878 } 879 880 static int silvermont_get_scaling(void) 881 { 882 u64 value; 883 int i; 884 /* Defined in Table 35-6 from SDM (Sept 2015) */ 885 static int silvermont_freq_table[] = { 886 83300, 100000, 133300, 116700, 80000}; 887 888 rdmsrl(MSR_FSB_FREQ, value); 889 i = value & 0x7; 890 WARN_ON(i > 4); 891 892 return silvermont_freq_table[i]; 893 } 894 895 static int airmont_get_scaling(void) 896 { 897 u64 value; 898 int i; 899 /* Defined in Table 35-10 from SDM (Sept 2015) */ 900 static int airmont_freq_table[] = { 901 83300, 100000, 133300, 116700, 80000, 902 93300, 90000, 88900, 87500}; 903 904 rdmsrl(MSR_FSB_FREQ, value); 905 i = value & 0xF; 906 WARN_ON(i > 8); 907 908 return airmont_freq_table[i]; 909 } 910 911 static void atom_get_vid(struct cpudata *cpudata) 912 { 913 u64 value; 914 915 rdmsrl(ATOM_VIDS, value); 916 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 917 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 918 cpudata->vid.ratio = div_fp( 919 cpudata->vid.max - cpudata->vid.min, 920 int_tofp(cpudata->pstate.max_pstate - 921 cpudata->pstate.min_pstate)); 922 923 rdmsrl(ATOM_TURBO_VIDS, value); 924 cpudata->vid.turbo = value & 0x7f; 925 } 926 927 static int core_get_min_pstate(void) 928 { 929 u64 value; 930 931 rdmsrl(MSR_PLATFORM_INFO, value); 932 return (value >> 40) & 0xFF; 933 } 934 935 static int core_get_max_pstate_physical(void) 936 { 937 u64 value; 938 939 rdmsrl(MSR_PLATFORM_INFO, value); 940 return (value >> 8) & 0xFF; 941 } 942 943 static int core_get_max_pstate(void) 944 { 945 u64 tar; 946 u64 plat_info; 947 int max_pstate; 948 int err; 949 950 rdmsrl(MSR_PLATFORM_INFO, plat_info); 951 max_pstate = (plat_info >> 8) & 0xFF; 952 953 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 954 if (!err) { 955 /* Do some sanity checking for safety */ 956 if (plat_info & 0x600000000) { 957 u64 tdp_ctrl; 958 u64 tdp_ratio; 959 int tdp_msr; 960 961 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 962 if (err) 963 goto skip_tar; 964 965 tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; 966 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 967 if (err) 968 goto skip_tar; 969 970 /* For level 1 and 2, bits[23:16] contain the ratio */ 971 if (tdp_ctrl) 972 tdp_ratio >>= 16; 973 974 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 975 if (tdp_ratio - 1 == tar) { 976 max_pstate = tar; 977 pr_debug("max_pstate=TAC %x\n", max_pstate); 978 } else { 979 goto skip_tar; 980 } 981 } 982 } 983 984 skip_tar: 985 return max_pstate; 986 } 987 988 static int core_get_turbo_pstate(void) 989 { 990 u64 value; 991 int nont, ret; 992 993 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 994 nont = core_get_max_pstate(); 995 ret = (value) & 255; 996 if (ret <= nont) 997 ret = nont; 998 return ret; 999 } 1000 1001 static inline int core_get_scaling(void) 1002 { 1003 return 100000; 1004 } 1005 1006 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1007 { 1008 u64 val; 1009 1010 val = (u64)pstate << 8; 1011 if (limits->no_turbo && !limits->turbo_disabled) 1012 val |= (u64)1 << 32; 1013 1014 return val; 1015 } 1016 1017 static int knl_get_turbo_pstate(void) 1018 { 1019 u64 value; 1020 int nont, ret; 1021 1022 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 1023 nont = core_get_max_pstate(); 1024 ret = (((value) >> 8) & 0xFF); 1025 if (ret <= nont) 1026 ret = nont; 1027 return ret; 1028 } 1029 1030 static struct cpu_defaults core_params = { 1031 .pid_policy = { 1032 .sample_rate_ms = 10, 1033 .deadband = 0, 1034 .setpoint = 97, 1035 .p_gain_pct = 20, 1036 .d_gain_pct = 0, 1037 .i_gain_pct = 0, 1038 }, 1039 .funcs = { 1040 .get_max = core_get_max_pstate, 1041 .get_max_physical = core_get_max_pstate_physical, 1042 .get_min = core_get_min_pstate, 1043 .get_turbo = core_get_turbo_pstate, 1044 .get_scaling = core_get_scaling, 1045 .get_val = core_get_val, 1046 .get_target_pstate = get_target_pstate_use_performance, 1047 }, 1048 }; 1049 1050 static struct cpu_defaults silvermont_params = { 1051 .pid_policy = { 1052 .sample_rate_ms = 10, 1053 .deadband = 0, 1054 .setpoint = 60, 1055 .p_gain_pct = 14, 1056 .d_gain_pct = 0, 1057 .i_gain_pct = 4, 1058 }, 1059 .funcs = { 1060 .get_max = atom_get_max_pstate, 1061 .get_max_physical = atom_get_max_pstate, 1062 .get_min = atom_get_min_pstate, 1063 .get_turbo = atom_get_turbo_pstate, 1064 .get_val = atom_get_val, 1065 .get_scaling = silvermont_get_scaling, 1066 .get_vid = atom_get_vid, 1067 .get_target_pstate = get_target_pstate_use_cpu_load, 1068 }, 1069 }; 1070 1071 static struct cpu_defaults airmont_params = { 1072 .pid_policy = { 1073 .sample_rate_ms = 10, 1074 .deadband = 0, 1075 .setpoint = 60, 1076 .p_gain_pct = 14, 1077 .d_gain_pct = 0, 1078 .i_gain_pct = 4, 1079 }, 1080 .funcs = { 1081 .get_max = atom_get_max_pstate, 1082 .get_max_physical = atom_get_max_pstate, 1083 .get_min = atom_get_min_pstate, 1084 .get_turbo = atom_get_turbo_pstate, 1085 .get_val = atom_get_val, 1086 .get_scaling = airmont_get_scaling, 1087 .get_vid = atom_get_vid, 1088 .get_target_pstate = get_target_pstate_use_cpu_load, 1089 }, 1090 }; 1091 1092 static struct cpu_defaults knl_params = { 1093 .pid_policy = { 1094 .sample_rate_ms = 10, 1095 .deadband = 0, 1096 .setpoint = 97, 1097 .p_gain_pct = 20, 1098 .d_gain_pct = 0, 1099 .i_gain_pct = 0, 1100 }, 1101 .funcs = { 1102 .get_max = core_get_max_pstate, 1103 .get_max_physical = core_get_max_pstate_physical, 1104 .get_min = core_get_min_pstate, 1105 .get_turbo = knl_get_turbo_pstate, 1106 .get_scaling = core_get_scaling, 1107 .get_val = core_get_val, 1108 .get_target_pstate = get_target_pstate_use_performance, 1109 }, 1110 }; 1111 1112 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1113 { 1114 int max_perf = cpu->pstate.turbo_pstate; 1115 int max_perf_adj; 1116 int min_perf; 1117 1118 if (limits->no_turbo || limits->turbo_disabled) 1119 max_perf = cpu->pstate.max_pstate; 1120 1121 /* 1122 * performance can be limited by user through sysfs, by cpufreq 1123 * policy, or by cpu specific default values determined through 1124 * experimentation. 1125 */ 1126 max_perf_adj = fp_toint(max_perf * limits->max_perf); 1127 *max = clamp_t(int, max_perf_adj, 1128 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1129 1130 min_perf = fp_toint(max_perf * limits->min_perf); 1131 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1132 } 1133 1134 static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate) 1135 { 1136 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1137 cpu->pstate.current_pstate = pstate; 1138 } 1139 1140 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1141 { 1142 int pstate = cpu->pstate.min_pstate; 1143 1144 intel_pstate_record_pstate(cpu, pstate); 1145 /* 1146 * Generally, there is no guarantee that this code will always run on 1147 * the CPU being updated, so force the register update to run on the 1148 * right CPU. 1149 */ 1150 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1151 pstate_funcs.get_val(cpu, pstate)); 1152 } 1153 1154 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1155 { 1156 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1157 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1158 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1159 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1160 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1161 1162 if (pstate_funcs.get_vid) 1163 pstate_funcs.get_vid(cpu); 1164 1165 intel_pstate_set_min_pstate(cpu); 1166 } 1167 1168 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1169 { 1170 struct sample *sample = &cpu->sample; 1171 1172 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1173 } 1174 1175 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1176 { 1177 u64 aperf, mperf; 1178 unsigned long flags; 1179 u64 tsc; 1180 1181 local_irq_save(flags); 1182 rdmsrl(MSR_IA32_APERF, aperf); 1183 rdmsrl(MSR_IA32_MPERF, mperf); 1184 tsc = rdtsc(); 1185 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1186 local_irq_restore(flags); 1187 return false; 1188 } 1189 local_irq_restore(flags); 1190 1191 cpu->last_sample_time = cpu->sample.time; 1192 cpu->sample.time = time; 1193 cpu->sample.aperf = aperf; 1194 cpu->sample.mperf = mperf; 1195 cpu->sample.tsc = tsc; 1196 cpu->sample.aperf -= cpu->prev_aperf; 1197 cpu->sample.mperf -= cpu->prev_mperf; 1198 cpu->sample.tsc -= cpu->prev_tsc; 1199 1200 cpu->prev_aperf = aperf; 1201 cpu->prev_mperf = mperf; 1202 cpu->prev_tsc = tsc; 1203 /* 1204 * First time this function is invoked in a given cycle, all of the 1205 * previous sample data fields are equal to zero or stale and they must 1206 * be populated with meaningful numbers for things to work, so assume 1207 * that sample.time will always be reset before setting the utilization 1208 * update hook and make the caller skip the sample then. 1209 */ 1210 return !!cpu->last_sample_time; 1211 } 1212 1213 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1214 { 1215 return mul_ext_fp(cpu->sample.core_avg_perf, 1216 cpu->pstate.max_pstate_physical * cpu->pstate.scaling); 1217 } 1218 1219 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1220 { 1221 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1222 cpu->sample.core_avg_perf); 1223 } 1224 1225 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1226 { 1227 struct sample *sample = &cpu->sample; 1228 u64 cummulative_iowait, delta_iowait_us; 1229 u64 delta_iowait_mperf; 1230 u64 mperf, now; 1231 int32_t cpu_load; 1232 1233 cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now); 1234 1235 /* 1236 * Convert iowait time into number of IO cycles spent at max_freq. 1237 * IO is considered as busy only for the cpu_load algorithm. For 1238 * performance this is not needed since we always try to reach the 1239 * maximum P-State, so we are already boosting the IOs. 1240 */ 1241 delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait; 1242 delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling * 1243 cpu->pstate.max_pstate, MSEC_PER_SEC); 1244 1245 mperf = cpu->sample.mperf + delta_iowait_mperf; 1246 cpu->prev_cummulative_iowait = cummulative_iowait; 1247 1248 /* 1249 * The load can be estimated as the ratio of the mperf counter 1250 * running at a constant frequency during active periods 1251 * (C0) and the time stamp counter running at the same frequency 1252 * also during C-states. 1253 */ 1254 cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc); 1255 cpu->sample.busy_scaled = cpu_load; 1256 1257 return get_avg_pstate(cpu) - pid_calc(&cpu->pid, cpu_load); 1258 } 1259 1260 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1261 { 1262 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; 1263 u64 duration_ns; 1264 1265 /* 1266 * perf_scaled is the average performance during the last sampling 1267 * period scaled by the ratio of the maximum P-state to the P-state 1268 * requested last time (in percent). That measures the system's 1269 * response to the previous P-state selection. 1270 */ 1271 max_pstate = cpu->pstate.max_pstate_physical; 1272 current_pstate = cpu->pstate.current_pstate; 1273 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, 1274 div_fp(100 * max_pstate, current_pstate)); 1275 1276 /* 1277 * Since our utilization update callback will not run unless we are 1278 * in C0, check if the actual elapsed time is significantly greater (3x) 1279 * than our sample interval. If it is, then we were idle for a long 1280 * enough period of time to adjust our performance metric. 1281 */ 1282 duration_ns = cpu->sample.time - cpu->last_sample_time; 1283 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1284 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1285 perf_scaled = mul_fp(perf_scaled, sample_ratio); 1286 } else { 1287 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1288 if (sample_ratio < int_tofp(1)) 1289 perf_scaled = 0; 1290 } 1291 1292 cpu->sample.busy_scaled = perf_scaled; 1293 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); 1294 } 1295 1296 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1297 { 1298 int max_perf, min_perf; 1299 1300 update_turbo_state(); 1301 1302 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1303 pstate = clamp_t(int, pstate, min_perf, max_perf); 1304 if (pstate == cpu->pstate.current_pstate) 1305 return; 1306 1307 intel_pstate_record_pstate(cpu, pstate); 1308 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1309 } 1310 1311 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1312 { 1313 int from, target_pstate; 1314 struct sample *sample; 1315 1316 from = cpu->pstate.current_pstate; 1317 1318 target_pstate = pstate_funcs.get_target_pstate(cpu); 1319 1320 intel_pstate_update_pstate(cpu, target_pstate); 1321 1322 sample = &cpu->sample; 1323 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1324 fp_toint(sample->busy_scaled), 1325 from, 1326 cpu->pstate.current_pstate, 1327 sample->mperf, 1328 sample->aperf, 1329 sample->tsc, 1330 get_avg_frequency(cpu)); 1331 } 1332 1333 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1334 unsigned long util, unsigned long max) 1335 { 1336 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1337 u64 delta_ns = time - cpu->sample.time; 1338 1339 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1340 bool sample_taken = intel_pstate_sample(cpu, time); 1341 1342 if (sample_taken) { 1343 intel_pstate_calc_avg_perf(cpu); 1344 if (!hwp_active) 1345 intel_pstate_adjust_busy_pstate(cpu); 1346 } 1347 } 1348 } 1349 1350 #define ICPU(model, policy) \ 1351 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1352 (unsigned long)&policy } 1353 1354 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1355 ICPU(0x2a, core_params), 1356 ICPU(0x2d, core_params), 1357 ICPU(0x37, silvermont_params), 1358 ICPU(0x3a, core_params), 1359 ICPU(0x3c, core_params), 1360 ICPU(0x3d, core_params), 1361 ICPU(0x3e, core_params), 1362 ICPU(0x3f, core_params), 1363 ICPU(0x45, core_params), 1364 ICPU(0x46, core_params), 1365 ICPU(0x47, core_params), 1366 ICPU(0x4c, airmont_params), 1367 ICPU(0x4e, core_params), 1368 ICPU(0x4f, core_params), 1369 ICPU(0x5e, core_params), 1370 ICPU(0x56, core_params), 1371 ICPU(0x57, knl_params), 1372 {} 1373 }; 1374 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1375 1376 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { 1377 ICPU(0x56, core_params), 1378 {} 1379 }; 1380 1381 static int intel_pstate_init_cpu(unsigned int cpunum) 1382 { 1383 struct cpudata *cpu; 1384 1385 if (!all_cpu_data[cpunum]) 1386 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), 1387 GFP_KERNEL); 1388 if (!all_cpu_data[cpunum]) 1389 return -ENOMEM; 1390 1391 cpu = all_cpu_data[cpunum]; 1392 1393 cpu->cpu = cpunum; 1394 1395 if (hwp_active) { 1396 intel_pstate_hwp_enable(cpu); 1397 pid_params.sample_rate_ms = 50; 1398 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1399 } 1400 1401 intel_pstate_get_cpu_pstates(cpu); 1402 1403 intel_pstate_busy_pid_reset(cpu); 1404 1405 pr_debug("controlling: cpu %d\n", cpunum); 1406 1407 return 0; 1408 } 1409 1410 static unsigned int intel_pstate_get(unsigned int cpu_num) 1411 { 1412 struct cpudata *cpu = all_cpu_data[cpu_num]; 1413 1414 return cpu ? get_avg_frequency(cpu) : 0; 1415 } 1416 1417 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1418 { 1419 struct cpudata *cpu = all_cpu_data[cpu_num]; 1420 1421 /* Prevent intel_pstate_update_util() from using stale data. */ 1422 cpu->sample.time = 0; 1423 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1424 intel_pstate_update_util); 1425 cpu->update_util_set = true; 1426 } 1427 1428 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1429 { 1430 struct cpudata *cpu_data = all_cpu_data[cpu]; 1431 1432 if (!cpu_data->update_util_set) 1433 return; 1434 1435 cpufreq_remove_update_util_hook(cpu); 1436 cpu_data->update_util_set = false; 1437 synchronize_sched(); 1438 } 1439 1440 static void intel_pstate_set_performance_limits(struct perf_limits *limits) 1441 { 1442 limits->no_turbo = 0; 1443 limits->turbo_disabled = 0; 1444 limits->max_perf_pct = 100; 1445 limits->max_perf = int_tofp(1); 1446 limits->min_perf_pct = 100; 1447 limits->min_perf = int_tofp(1); 1448 limits->max_policy_pct = 100; 1449 limits->max_sysfs_pct = 100; 1450 limits->min_policy_pct = 0; 1451 limits->min_sysfs_pct = 0; 1452 } 1453 1454 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1455 { 1456 struct cpudata *cpu; 1457 1458 if (!policy->cpuinfo.max_freq) 1459 return -ENODEV; 1460 1461 intel_pstate_clear_update_util_hook(policy->cpu); 1462 1463 cpu = all_cpu_data[0]; 1464 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 1465 policy->max < policy->cpuinfo.max_freq && 1466 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 1467 pr_debug("policy->max > max non turbo frequency\n"); 1468 policy->max = policy->cpuinfo.max_freq; 1469 } 1470 1471 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 1472 limits = &performance_limits; 1473 if (policy->max >= policy->cpuinfo.max_freq) { 1474 pr_debug("set performance\n"); 1475 intel_pstate_set_performance_limits(limits); 1476 goto out; 1477 } 1478 } else { 1479 pr_debug("set powersave\n"); 1480 limits = &powersave_limits; 1481 } 1482 1483 limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 1484 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); 1485 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, 1486 policy->cpuinfo.max_freq); 1487 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); 1488 1489 /* Normalize user input to [min_policy_pct, max_policy_pct] */ 1490 limits->min_perf_pct = max(limits->min_policy_pct, 1491 limits->min_sysfs_pct); 1492 limits->min_perf_pct = min(limits->max_policy_pct, 1493 limits->min_perf_pct); 1494 limits->max_perf_pct = min(limits->max_policy_pct, 1495 limits->max_sysfs_pct); 1496 limits->max_perf_pct = max(limits->min_policy_pct, 1497 limits->max_perf_pct); 1498 limits->max_perf = round_up(limits->max_perf, FRAC_BITS); 1499 1500 /* Make sure min_perf_pct <= max_perf_pct */ 1501 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); 1502 1503 limits->min_perf = div_fp(limits->min_perf_pct, 100); 1504 limits->max_perf = div_fp(limits->max_perf_pct, 100); 1505 1506 out: 1507 intel_pstate_set_update_util_hook(policy->cpu); 1508 1509 intel_pstate_hwp_set_policy(policy); 1510 1511 return 0; 1512 } 1513 1514 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 1515 { 1516 cpufreq_verify_within_cpu_limits(policy); 1517 1518 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 1519 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 1520 return -EINVAL; 1521 1522 return 0; 1523 } 1524 1525 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 1526 { 1527 int cpu_num = policy->cpu; 1528 struct cpudata *cpu = all_cpu_data[cpu_num]; 1529 1530 pr_debug("CPU %d exiting\n", cpu_num); 1531 1532 intel_pstate_clear_update_util_hook(cpu_num); 1533 1534 if (hwp_active) 1535 return; 1536 1537 intel_pstate_set_min_pstate(cpu); 1538 } 1539 1540 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 1541 { 1542 struct cpudata *cpu; 1543 int rc; 1544 1545 rc = intel_pstate_init_cpu(policy->cpu); 1546 if (rc) 1547 return rc; 1548 1549 cpu = all_cpu_data[policy->cpu]; 1550 1551 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) 1552 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1553 else 1554 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1555 1556 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 1557 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1558 1559 /* cpuinfo and default policy values */ 1560 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1561 policy->cpuinfo.max_freq = 1562 cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1563 intel_pstate_init_acpi_perf_limits(policy); 1564 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1565 cpumask_set_cpu(policy->cpu, policy->cpus); 1566 1567 return 0; 1568 } 1569 1570 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 1571 { 1572 intel_pstate_exit_perf_limits(policy); 1573 1574 return 0; 1575 } 1576 1577 static struct cpufreq_driver intel_pstate_driver = { 1578 .flags = CPUFREQ_CONST_LOOPS, 1579 .verify = intel_pstate_verify_policy, 1580 .setpolicy = intel_pstate_set_policy, 1581 .resume = intel_pstate_hwp_set_policy, 1582 .get = intel_pstate_get, 1583 .init = intel_pstate_cpu_init, 1584 .exit = intel_pstate_cpu_exit, 1585 .stop_cpu = intel_pstate_stop_cpu, 1586 .name = "intel_pstate", 1587 }; 1588 1589 static int __initdata no_load; 1590 static int __initdata no_hwp; 1591 static int __initdata hwp_only; 1592 static unsigned int force_load; 1593 1594 static int intel_pstate_msrs_not_valid(void) 1595 { 1596 if (!pstate_funcs.get_max() || 1597 !pstate_funcs.get_min() || 1598 !pstate_funcs.get_turbo()) 1599 return -ENODEV; 1600 1601 return 0; 1602 } 1603 1604 static void copy_pid_params(struct pstate_adjust_policy *policy) 1605 { 1606 pid_params.sample_rate_ms = policy->sample_rate_ms; 1607 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 1608 pid_params.p_gain_pct = policy->p_gain_pct; 1609 pid_params.i_gain_pct = policy->i_gain_pct; 1610 pid_params.d_gain_pct = policy->d_gain_pct; 1611 pid_params.deadband = policy->deadband; 1612 pid_params.setpoint = policy->setpoint; 1613 } 1614 1615 static void copy_cpu_funcs(struct pstate_funcs *funcs) 1616 { 1617 pstate_funcs.get_max = funcs->get_max; 1618 pstate_funcs.get_max_physical = funcs->get_max_physical; 1619 pstate_funcs.get_min = funcs->get_min; 1620 pstate_funcs.get_turbo = funcs->get_turbo; 1621 pstate_funcs.get_scaling = funcs->get_scaling; 1622 pstate_funcs.get_val = funcs->get_val; 1623 pstate_funcs.get_vid = funcs->get_vid; 1624 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 1625 1626 } 1627 1628 #ifdef CONFIG_ACPI 1629 1630 static bool intel_pstate_no_acpi_pss(void) 1631 { 1632 int i; 1633 1634 for_each_possible_cpu(i) { 1635 acpi_status status; 1636 union acpi_object *pss; 1637 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1638 struct acpi_processor *pr = per_cpu(processors, i); 1639 1640 if (!pr) 1641 continue; 1642 1643 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1644 if (ACPI_FAILURE(status)) 1645 continue; 1646 1647 pss = buffer.pointer; 1648 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1649 kfree(pss); 1650 return false; 1651 } 1652 1653 kfree(pss); 1654 } 1655 1656 return true; 1657 } 1658 1659 static bool intel_pstate_has_acpi_ppc(void) 1660 { 1661 int i; 1662 1663 for_each_possible_cpu(i) { 1664 struct acpi_processor *pr = per_cpu(processors, i); 1665 1666 if (!pr) 1667 continue; 1668 if (acpi_has_method(pr->handle, "_PPC")) 1669 return true; 1670 } 1671 return false; 1672 } 1673 1674 enum { 1675 PSS, 1676 PPC, 1677 }; 1678 1679 struct hw_vendor_info { 1680 u16 valid; 1681 char oem_id[ACPI_OEM_ID_SIZE]; 1682 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1683 int oem_pwr_table; 1684 }; 1685 1686 /* Hardware vendor-specific info that has its own power management modes */ 1687 static struct hw_vendor_info vendor_info[] = { 1688 {1, "HP ", "ProLiant", PSS}, 1689 {1, "ORACLE", "X4-2 ", PPC}, 1690 {1, "ORACLE", "X4-2L ", PPC}, 1691 {1, "ORACLE", "X4-2B ", PPC}, 1692 {1, "ORACLE", "X3-2 ", PPC}, 1693 {1, "ORACLE", "X3-2L ", PPC}, 1694 {1, "ORACLE", "X3-2B ", PPC}, 1695 {1, "ORACLE", "X4470M2 ", PPC}, 1696 {1, "ORACLE", "X4270M3 ", PPC}, 1697 {1, "ORACLE", "X4270M2 ", PPC}, 1698 {1, "ORACLE", "X4170M2 ", PPC}, 1699 {1, "ORACLE", "X4170 M3", PPC}, 1700 {1, "ORACLE", "X4275 M3", PPC}, 1701 {1, "ORACLE", "X6-2 ", PPC}, 1702 {1, "ORACLE", "Sudbury ", PPC}, 1703 {0, "", ""}, 1704 }; 1705 1706 static bool intel_pstate_platform_pwr_mgmt_exists(void) 1707 { 1708 struct acpi_table_header hdr; 1709 struct hw_vendor_info *v_info; 1710 const struct x86_cpu_id *id; 1711 u64 misc_pwr; 1712 1713 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1714 if (id) { 1715 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1716 if ( misc_pwr & (1 << 8)) 1717 return true; 1718 } 1719 1720 if (acpi_disabled || 1721 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1722 return false; 1723 1724 for (v_info = vendor_info; v_info->valid; v_info++) { 1725 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1726 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1727 ACPI_OEM_TABLE_ID_SIZE)) 1728 switch (v_info->oem_pwr_table) { 1729 case PSS: 1730 return intel_pstate_no_acpi_pss(); 1731 case PPC: 1732 return intel_pstate_has_acpi_ppc() && 1733 (!force_load); 1734 } 1735 } 1736 1737 return false; 1738 } 1739 #else /* CONFIG_ACPI not enabled */ 1740 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1741 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1742 #endif /* CONFIG_ACPI */ 1743 1744 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 1745 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 1746 {} 1747 }; 1748 1749 static int __init intel_pstate_init(void) 1750 { 1751 int cpu, rc = 0; 1752 const struct x86_cpu_id *id; 1753 struct cpu_defaults *cpu_def; 1754 1755 if (no_load) 1756 return -ENODEV; 1757 1758 if (x86_match_cpu(hwp_support_ids) && !no_hwp) { 1759 copy_cpu_funcs(&core_params.funcs); 1760 hwp_active++; 1761 goto hwp_cpu_matched; 1762 } 1763 1764 id = x86_match_cpu(intel_pstate_cpu_ids); 1765 if (!id) 1766 return -ENODEV; 1767 1768 cpu_def = (struct cpu_defaults *)id->driver_data; 1769 1770 copy_pid_params(&cpu_def->pid_policy); 1771 copy_cpu_funcs(&cpu_def->funcs); 1772 1773 if (intel_pstate_msrs_not_valid()) 1774 return -ENODEV; 1775 1776 hwp_cpu_matched: 1777 /* 1778 * The Intel pstate driver will be ignored if the platform 1779 * firmware has its own power management modes. 1780 */ 1781 if (intel_pstate_platform_pwr_mgmt_exists()) 1782 return -ENODEV; 1783 1784 pr_info("Intel P-state driver initializing\n"); 1785 1786 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1787 if (!all_cpu_data) 1788 return -ENOMEM; 1789 1790 if (!hwp_active && hwp_only) 1791 goto out; 1792 1793 rc = cpufreq_register_driver(&intel_pstate_driver); 1794 if (rc) 1795 goto out; 1796 1797 intel_pstate_debug_expose_params(); 1798 intel_pstate_sysfs_expose_params(); 1799 1800 if (hwp_active) 1801 pr_info("HWP enabled\n"); 1802 1803 return rc; 1804 out: 1805 get_online_cpus(); 1806 for_each_online_cpu(cpu) { 1807 if (all_cpu_data[cpu]) { 1808 intel_pstate_clear_update_util_hook(cpu); 1809 kfree(all_cpu_data[cpu]); 1810 } 1811 } 1812 1813 put_online_cpus(); 1814 vfree(all_cpu_data); 1815 return -ENODEV; 1816 } 1817 device_initcall(intel_pstate_init); 1818 1819 static int __init intel_pstate_setup(char *str) 1820 { 1821 if (!str) 1822 return -EINVAL; 1823 1824 if (!strcmp(str, "disable")) 1825 no_load = 1; 1826 if (!strcmp(str, "no_hwp")) { 1827 pr_info("HWP disabled\n"); 1828 no_hwp = 1; 1829 } 1830 if (!strcmp(str, "force")) 1831 force_load = 1; 1832 if (!strcmp(str, "hwp_only")) 1833 hwp_only = 1; 1834 1835 #ifdef CONFIG_ACPI 1836 if (!strcmp(str, "support_acpi_ppc")) 1837 acpi_ppc = true; 1838 #endif 1839 1840 return 0; 1841 } 1842 early_param("intel_pstate", intel_pstate_setup); 1843 1844 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1845 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1846 MODULE_LICENSE("GPL"); 1847