1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/div64.h> 31 #include <asm/msr.h> 32 #include <asm/cpu_device_id.h> 33 #include <asm/cpufeature.h> 34 #include <asm/intel-family.h> 35 36 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 37 38 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 39 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 40 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 41 42 #ifdef CONFIG_ACPI 43 #include <acpi/processor.h> 44 #include <acpi/cppc_acpi.h> 45 #endif 46 47 #define FRAC_BITS 8 48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 49 #define fp_toint(X) ((X) >> FRAC_BITS) 50 51 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 52 53 #define EXT_BITS 6 54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 57 58 static inline int32_t mul_fp(int32_t x, int32_t y) 59 { 60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 61 } 62 63 static inline int32_t div_fp(s64 x, s64 y) 64 { 65 return div64_s64((int64_t)x << FRAC_BITS, y); 66 } 67 68 static inline int ceiling_fp(int32_t x) 69 { 70 int mask, ret; 71 72 ret = fp_toint(x); 73 mask = (1 << FRAC_BITS) - 1; 74 if (x & mask) 75 ret += 1; 76 return ret; 77 } 78 79 static inline int32_t percent_fp(int percent) 80 { 81 return div_fp(percent, 100); 82 } 83 84 static inline u64 mul_ext_fp(u64 x, u64 y) 85 { 86 return (x * y) >> EXT_FRAC_BITS; 87 } 88 89 static inline u64 div_ext_fp(u64 x, u64 y) 90 { 91 return div64_u64(x << EXT_FRAC_BITS, y); 92 } 93 94 static inline int32_t percent_ext_fp(int percent) 95 { 96 return div_ext_fp(percent, 100); 97 } 98 99 /** 100 * struct sample - Store performance sample 101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 102 * performance during last sample period 103 * @busy_scaled: Scaled busy value which is used to calculate next 104 * P state. This can be different than core_avg_perf 105 * to account for cpu idle period 106 * @aperf: Difference of actual performance frequency clock count 107 * read from APERF MSR between last and current sample 108 * @mperf: Difference of maximum performance frequency clock count 109 * read from MPERF MSR between last and current sample 110 * @tsc: Difference of time stamp counter between last and 111 * current sample 112 * @time: Current time from scheduler 113 * 114 * This structure is used in the cpudata structure to store performance sample 115 * data for choosing next P State. 116 */ 117 struct sample { 118 int32_t core_avg_perf; 119 int32_t busy_scaled; 120 u64 aperf; 121 u64 mperf; 122 u64 tsc; 123 u64 time; 124 }; 125 126 /** 127 * struct pstate_data - Store P state data 128 * @current_pstate: Current requested P state 129 * @min_pstate: Min P state possible for this platform 130 * @max_pstate: Max P state possible for this platform 131 * @max_pstate_physical:This is physical Max P state for a processor 132 * This can be higher than the max_pstate which can 133 * be limited by platform thermal design power limits 134 * @scaling: Scaling factor to convert frequency to cpufreq 135 * frequency units 136 * @turbo_pstate: Max Turbo P state possible for this platform 137 * @max_freq: @max_pstate frequency in cpufreq units 138 * @turbo_freq: @turbo_pstate frequency in cpufreq units 139 * 140 * Stores the per cpu model P state limits and current P state. 141 */ 142 struct pstate_data { 143 int current_pstate; 144 int min_pstate; 145 int max_pstate; 146 int max_pstate_physical; 147 int scaling; 148 int turbo_pstate; 149 unsigned int max_freq; 150 unsigned int turbo_freq; 151 }; 152 153 /** 154 * struct vid_data - Stores voltage information data 155 * @min: VID data for this platform corresponding to 156 * the lowest P state 157 * @max: VID data corresponding to the highest P State. 158 * @turbo: VID data for turbo P state 159 * @ratio: Ratio of (vid max - vid min) / 160 * (max P state - Min P State) 161 * 162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 163 * This data is used in Atom platforms, where in addition to target P state, 164 * the voltage data needs to be specified to select next P State. 165 */ 166 struct vid_data { 167 int min; 168 int max; 169 int turbo; 170 int32_t ratio; 171 }; 172 173 /** 174 * struct global_params - Global parameters, mostly tunable via sysfs. 175 * @no_turbo: Whether or not to use turbo P-states. 176 * @turbo_disabled: Whether or not turbo P-states are available at all, 177 * based on the MSR_IA32_MISC_ENABLE value and whether or 178 * not the maximum reported turbo P-state is different from 179 * the maximum reported non-turbo one. 180 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 181 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 182 * P-state capacity. 183 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 184 * P-state capacity. 185 */ 186 struct global_params { 187 bool no_turbo; 188 bool turbo_disabled; 189 bool turbo_disabled_mf; 190 int max_perf_pct; 191 int min_perf_pct; 192 }; 193 194 /** 195 * struct cpudata - Per CPU instance data storage 196 * @cpu: CPU number for this instance data 197 * @policy: CPUFreq policy value 198 * @update_util: CPUFreq utility callback information 199 * @update_util_set: CPUFreq utility callback is set 200 * @iowait_boost: iowait-related boost fraction 201 * @last_update: Time of the last update. 202 * @pstate: Stores P state limits for this CPU 203 * @vid: Stores VID limits for this CPU 204 * @last_sample_time: Last Sample time 205 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 206 * @prev_aperf: Last APERF value read from APERF MSR 207 * @prev_mperf: Last MPERF value read from MPERF MSR 208 * @prev_tsc: Last timestamp counter (TSC) value 209 * @prev_cummulative_iowait: IO Wait time difference from last and 210 * current sample 211 * @sample: Storage for storing last Sample data 212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 214 * @acpi_perf_data: Stores ACPI perf information read from _PSS 215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 216 * @epp_powersave: Last saved HWP energy performance preference 217 * (EPP) or energy performance bias (EPB), 218 * when policy switched to performance 219 * @epp_policy: Last saved policy used to set EPP/EPB 220 * @epp_default: Power on default HWP energy performance 221 * preference/bias 222 * @epp_cached Cached HWP energy-performance preference value 223 * @hwp_req_cached: Cached value of the last HWP Request MSR 224 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 225 * @last_io_update: Last time when IO wake flag was set 226 * @sched_flags: Store scheduler flags for possible cross CPU update 227 * @hwp_boost_min: Last HWP boosted min performance 228 * @suspended: Whether or not the driver has been suspended. 229 * 230 * This structure stores per CPU instance data for all CPUs. 231 */ 232 struct cpudata { 233 int cpu; 234 235 unsigned int policy; 236 struct update_util_data update_util; 237 bool update_util_set; 238 239 struct pstate_data pstate; 240 struct vid_data vid; 241 242 u64 last_update; 243 u64 last_sample_time; 244 u64 aperf_mperf_shift; 245 u64 prev_aperf; 246 u64 prev_mperf; 247 u64 prev_tsc; 248 u64 prev_cummulative_iowait; 249 struct sample sample; 250 int32_t min_perf_ratio; 251 int32_t max_perf_ratio; 252 #ifdef CONFIG_ACPI 253 struct acpi_processor_performance acpi_perf_data; 254 bool valid_pss_table; 255 #endif 256 unsigned int iowait_boost; 257 s16 epp_powersave; 258 s16 epp_policy; 259 s16 epp_default; 260 s16 epp_cached; 261 u64 hwp_req_cached; 262 u64 hwp_cap_cached; 263 u64 last_io_update; 264 unsigned int sched_flags; 265 u32 hwp_boost_min; 266 bool suspended; 267 }; 268 269 static struct cpudata **all_cpu_data; 270 271 /** 272 * struct pstate_funcs - Per CPU model specific callbacks 273 * @get_max: Callback to get maximum non turbo effective P state 274 * @get_max_physical: Callback to get maximum non turbo physical P state 275 * @get_min: Callback to get minimum P state 276 * @get_turbo: Callback to get turbo P state 277 * @get_scaling: Callback to get frequency scaling factor 278 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 279 * @get_val: Callback to convert P state to actual MSR write value 280 * @get_vid: Callback to get VID data for Atom platforms 281 * 282 * Core and Atom CPU models have different way to get P State limits. This 283 * structure is used to store those callbacks. 284 */ 285 struct pstate_funcs { 286 int (*get_max)(void); 287 int (*get_max_physical)(void); 288 int (*get_min)(void); 289 int (*get_turbo)(void); 290 int (*get_scaling)(void); 291 int (*get_aperf_mperf_shift)(void); 292 u64 (*get_val)(struct cpudata*, int pstate); 293 void (*get_vid)(struct cpudata *); 294 }; 295 296 static struct pstate_funcs pstate_funcs __read_mostly; 297 298 static int hwp_active __read_mostly; 299 static int hwp_mode_bdw __read_mostly; 300 static bool per_cpu_limits __read_mostly; 301 static bool hwp_boost __read_mostly; 302 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 304 305 #ifdef CONFIG_ACPI 306 static bool acpi_ppc; 307 #endif 308 309 static struct global_params global; 310 311 static DEFINE_MUTEX(intel_pstate_driver_lock); 312 static DEFINE_MUTEX(intel_pstate_limits_lock); 313 314 #ifdef CONFIG_ACPI 315 316 static bool intel_pstate_acpi_pm_profile_server(void) 317 { 318 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 319 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 320 return true; 321 322 return false; 323 } 324 325 static bool intel_pstate_get_ppc_enable_status(void) 326 { 327 if (intel_pstate_acpi_pm_profile_server()) 328 return true; 329 330 return acpi_ppc; 331 } 332 333 #ifdef CONFIG_ACPI_CPPC_LIB 334 335 /* The work item is needed to avoid CPU hotplug locking issues */ 336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 337 { 338 sched_set_itmt_support(); 339 } 340 341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 342 343 static void intel_pstate_set_itmt_prio(int cpu) 344 { 345 struct cppc_perf_caps cppc_perf; 346 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 347 int ret; 348 349 ret = cppc_get_perf_caps(cpu, &cppc_perf); 350 if (ret) 351 return; 352 353 /* 354 * The priorities can be set regardless of whether or not 355 * sched_set_itmt_support(true) has been called and it is valid to 356 * update them at any time after it has been called. 357 */ 358 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 359 360 if (max_highest_perf <= min_highest_perf) { 361 if (cppc_perf.highest_perf > max_highest_perf) 362 max_highest_perf = cppc_perf.highest_perf; 363 364 if (cppc_perf.highest_perf < min_highest_perf) 365 min_highest_perf = cppc_perf.highest_perf; 366 367 if (max_highest_perf > min_highest_perf) { 368 /* 369 * This code can be run during CPU online under the 370 * CPU hotplug locks, so sched_set_itmt_support() 371 * cannot be called from here. Queue up a work item 372 * to invoke it. 373 */ 374 schedule_work(&sched_itmt_work); 375 } 376 } 377 } 378 379 static int intel_pstate_get_cppc_guranteed(int cpu) 380 { 381 struct cppc_perf_caps cppc_perf; 382 int ret; 383 384 ret = cppc_get_perf_caps(cpu, &cppc_perf); 385 if (ret) 386 return ret; 387 388 if (cppc_perf.guaranteed_perf) 389 return cppc_perf.guaranteed_perf; 390 391 return cppc_perf.nominal_perf; 392 } 393 394 #else /* CONFIG_ACPI_CPPC_LIB */ 395 static void intel_pstate_set_itmt_prio(int cpu) 396 { 397 } 398 #endif /* CONFIG_ACPI_CPPC_LIB */ 399 400 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 401 { 402 struct cpudata *cpu; 403 int ret; 404 int i; 405 406 if (hwp_active) { 407 intel_pstate_set_itmt_prio(policy->cpu); 408 return; 409 } 410 411 if (!intel_pstate_get_ppc_enable_status()) 412 return; 413 414 cpu = all_cpu_data[policy->cpu]; 415 416 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 417 policy->cpu); 418 if (ret) 419 return; 420 421 /* 422 * Check if the control value in _PSS is for PERF_CTL MSR, which should 423 * guarantee that the states returned by it map to the states in our 424 * list directly. 425 */ 426 if (cpu->acpi_perf_data.control_register.space_id != 427 ACPI_ADR_SPACE_FIXED_HARDWARE) 428 goto err; 429 430 /* 431 * If there is only one entry _PSS, simply ignore _PSS and continue as 432 * usual without taking _PSS into account 433 */ 434 if (cpu->acpi_perf_data.state_count < 2) 435 goto err; 436 437 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 438 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 439 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 440 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 441 (u32) cpu->acpi_perf_data.states[i].core_frequency, 442 (u32) cpu->acpi_perf_data.states[i].power, 443 (u32) cpu->acpi_perf_data.states[i].control); 444 } 445 446 /* 447 * The _PSS table doesn't contain whole turbo frequency range. 448 * This just contains +1 MHZ above the max non turbo frequency, 449 * with control value corresponding to max turbo ratio. But 450 * when cpufreq set policy is called, it will call with this 451 * max frequency, which will cause a reduced performance as 452 * this driver uses real max turbo frequency as the max 453 * frequency. So correct this frequency in _PSS table to 454 * correct max turbo frequency based on the turbo state. 455 * Also need to convert to MHz as _PSS freq is in MHz. 456 */ 457 if (!global.turbo_disabled) 458 cpu->acpi_perf_data.states[0].core_frequency = 459 policy->cpuinfo.max_freq / 1000; 460 cpu->valid_pss_table = true; 461 pr_debug("_PPC limits will be enforced\n"); 462 463 return; 464 465 err: 466 cpu->valid_pss_table = false; 467 acpi_processor_unregister_performance(policy->cpu); 468 } 469 470 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 471 { 472 struct cpudata *cpu; 473 474 cpu = all_cpu_data[policy->cpu]; 475 if (!cpu->valid_pss_table) 476 return; 477 478 acpi_processor_unregister_performance(policy->cpu); 479 } 480 #else /* CONFIG_ACPI */ 481 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 482 { 483 } 484 485 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 486 { 487 } 488 489 static inline bool intel_pstate_acpi_pm_profile_server(void) 490 { 491 return false; 492 } 493 #endif /* CONFIG_ACPI */ 494 495 #ifndef CONFIG_ACPI_CPPC_LIB 496 static int intel_pstate_get_cppc_guranteed(int cpu) 497 { 498 return -ENOTSUPP; 499 } 500 #endif /* CONFIG_ACPI_CPPC_LIB */ 501 502 static inline void update_turbo_state(void) 503 { 504 u64 misc_en; 505 struct cpudata *cpu; 506 507 cpu = all_cpu_data[0]; 508 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 509 global.turbo_disabled = 510 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 511 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 512 } 513 514 static int min_perf_pct_min(void) 515 { 516 struct cpudata *cpu = all_cpu_data[0]; 517 int turbo_pstate = cpu->pstate.turbo_pstate; 518 519 return turbo_pstate ? 520 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 521 } 522 523 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 524 { 525 u64 epb; 526 int ret; 527 528 if (!boot_cpu_has(X86_FEATURE_EPB)) 529 return -ENXIO; 530 531 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 532 if (ret) 533 return (s16)ret; 534 535 return (s16)(epb & 0x0f); 536 } 537 538 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 539 { 540 s16 epp; 541 542 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 543 /* 544 * When hwp_req_data is 0, means that caller didn't read 545 * MSR_HWP_REQUEST, so need to read and get EPP. 546 */ 547 if (!hwp_req_data) { 548 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 549 &hwp_req_data); 550 if (epp) 551 return epp; 552 } 553 epp = (hwp_req_data >> 24) & 0xff; 554 } else { 555 /* When there is no EPP present, HWP uses EPB settings */ 556 epp = intel_pstate_get_epb(cpu_data); 557 } 558 559 return epp; 560 } 561 562 static int intel_pstate_set_epb(int cpu, s16 pref) 563 { 564 u64 epb; 565 int ret; 566 567 if (!boot_cpu_has(X86_FEATURE_EPB)) 568 return -ENXIO; 569 570 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 571 if (ret) 572 return ret; 573 574 epb = (epb & ~0x0f) | pref; 575 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 576 577 return 0; 578 } 579 580 /* 581 * EPP/EPB display strings corresponding to EPP index in the 582 * energy_perf_strings[] 583 * index String 584 *------------------------------------- 585 * 0 default 586 * 1 performance 587 * 2 balance_performance 588 * 3 balance_power 589 * 4 power 590 */ 591 static const char * const energy_perf_strings[] = { 592 "default", 593 "performance", 594 "balance_performance", 595 "balance_power", 596 "power", 597 NULL 598 }; 599 static const unsigned int epp_values[] = { 600 HWP_EPP_PERFORMANCE, 601 HWP_EPP_BALANCE_PERFORMANCE, 602 HWP_EPP_BALANCE_POWERSAVE, 603 HWP_EPP_POWERSAVE 604 }; 605 606 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 607 { 608 s16 epp; 609 int index = -EINVAL; 610 611 *raw_epp = 0; 612 epp = intel_pstate_get_epp(cpu_data, 0); 613 if (epp < 0) 614 return epp; 615 616 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 617 if (epp == HWP_EPP_PERFORMANCE) 618 return 1; 619 if (epp == HWP_EPP_BALANCE_PERFORMANCE) 620 return 2; 621 if (epp == HWP_EPP_BALANCE_POWERSAVE) 622 return 3; 623 if (epp == HWP_EPP_POWERSAVE) 624 return 4; 625 *raw_epp = epp; 626 return 0; 627 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 628 /* 629 * Range: 630 * 0x00-0x03 : Performance 631 * 0x04-0x07 : Balance performance 632 * 0x08-0x0B : Balance power 633 * 0x0C-0x0F : Power 634 * The EPB is a 4 bit value, but our ranges restrict the 635 * value which can be set. Here only using top two bits 636 * effectively. 637 */ 638 index = (epp >> 2) + 1; 639 } 640 641 return index; 642 } 643 644 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 645 { 646 int ret; 647 648 /* 649 * Use the cached HWP Request MSR value, because in the active mode the 650 * register itself may be updated by intel_pstate_hwp_boost_up() or 651 * intel_pstate_hwp_boost_down() at any time. 652 */ 653 u64 value = READ_ONCE(cpu->hwp_req_cached); 654 655 value &= ~GENMASK_ULL(31, 24); 656 value |= (u64)epp << 24; 657 /* 658 * The only other updater of hwp_req_cached in the active mode, 659 * intel_pstate_hwp_set(), is called under the same lock as this 660 * function, so it cannot run in parallel with the update below. 661 */ 662 WRITE_ONCE(cpu->hwp_req_cached, value); 663 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 664 if (!ret) 665 cpu->epp_cached = epp; 666 667 return ret; 668 } 669 670 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 671 int pref_index, bool use_raw, 672 u32 raw_epp) 673 { 674 int epp = -EINVAL; 675 int ret; 676 677 if (!pref_index) 678 epp = cpu_data->epp_default; 679 680 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 681 if (use_raw) 682 epp = raw_epp; 683 else if (epp == -EINVAL) 684 epp = epp_values[pref_index - 1]; 685 686 /* 687 * To avoid confusion, refuse to set EPP to any values different 688 * from 0 (performance) if the current policy is "performance", 689 * because those values would be overridden. 690 */ 691 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 692 return -EBUSY; 693 694 ret = intel_pstate_set_epp(cpu_data, epp); 695 } else { 696 if (epp == -EINVAL) 697 epp = (pref_index - 1) << 2; 698 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 699 } 700 701 return ret; 702 } 703 704 static ssize_t show_energy_performance_available_preferences( 705 struct cpufreq_policy *policy, char *buf) 706 { 707 int i = 0; 708 int ret = 0; 709 710 while (energy_perf_strings[i] != NULL) 711 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 712 713 ret += sprintf(&buf[ret], "\n"); 714 715 return ret; 716 } 717 718 cpufreq_freq_attr_ro(energy_performance_available_preferences); 719 720 static struct cpufreq_driver intel_pstate; 721 722 static ssize_t store_energy_performance_preference( 723 struct cpufreq_policy *policy, const char *buf, size_t count) 724 { 725 struct cpudata *cpu = all_cpu_data[policy->cpu]; 726 char str_preference[21]; 727 bool raw = false; 728 ssize_t ret; 729 u32 epp = 0; 730 731 ret = sscanf(buf, "%20s", str_preference); 732 if (ret != 1) 733 return -EINVAL; 734 735 ret = match_string(energy_perf_strings, -1, str_preference); 736 if (ret < 0) { 737 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 738 return ret; 739 740 ret = kstrtouint(buf, 10, &epp); 741 if (ret) 742 return ret; 743 744 if (epp > 255) 745 return -EINVAL; 746 747 raw = true; 748 } 749 750 /* 751 * This function runs with the policy R/W semaphore held, which 752 * guarantees that the driver pointer will not change while it is 753 * running. 754 */ 755 if (!intel_pstate_driver) 756 return -EAGAIN; 757 758 mutex_lock(&intel_pstate_limits_lock); 759 760 if (intel_pstate_driver == &intel_pstate) { 761 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 762 } else { 763 /* 764 * In the passive mode the governor needs to be stopped on the 765 * target CPU before the EPP update and restarted after it, 766 * which is super-heavy-weight, so make sure it is worth doing 767 * upfront. 768 */ 769 if (!raw) 770 epp = ret ? epp_values[ret - 1] : cpu->epp_default; 771 772 if (cpu->epp_cached != epp) { 773 int err; 774 775 cpufreq_stop_governor(policy); 776 ret = intel_pstate_set_epp(cpu, epp); 777 err = cpufreq_start_governor(policy); 778 if (!ret) 779 ret = err; 780 } 781 } 782 783 mutex_unlock(&intel_pstate_limits_lock); 784 785 return ret ?: count; 786 } 787 788 static ssize_t show_energy_performance_preference( 789 struct cpufreq_policy *policy, char *buf) 790 { 791 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 792 int preference, raw_epp; 793 794 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 795 if (preference < 0) 796 return preference; 797 798 if (raw_epp) 799 return sprintf(buf, "%d\n", raw_epp); 800 else 801 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 802 } 803 804 cpufreq_freq_attr_rw(energy_performance_preference); 805 806 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 807 { 808 struct cpudata *cpu; 809 u64 cap; 810 int ratio; 811 812 ratio = intel_pstate_get_cppc_guranteed(policy->cpu); 813 if (ratio <= 0) { 814 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 815 ratio = HWP_GUARANTEED_PERF(cap); 816 } 817 818 cpu = all_cpu_data[policy->cpu]; 819 820 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling); 821 } 822 823 cpufreq_freq_attr_ro(base_frequency); 824 825 static struct freq_attr *hwp_cpufreq_attrs[] = { 826 &energy_performance_preference, 827 &energy_performance_available_preferences, 828 &base_frequency, 829 NULL, 830 }; 831 832 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, 833 int *current_max) 834 { 835 u64 cap; 836 837 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 838 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap); 839 if (global.no_turbo || global.turbo_disabled) 840 *current_max = HWP_GUARANTEED_PERF(cap); 841 else 842 *current_max = HWP_HIGHEST_PERF(cap); 843 844 *phy_max = HWP_HIGHEST_PERF(cap); 845 } 846 847 static void intel_pstate_hwp_set(unsigned int cpu) 848 { 849 struct cpudata *cpu_data = all_cpu_data[cpu]; 850 int max, min; 851 u64 value; 852 s16 epp; 853 854 max = cpu_data->max_perf_ratio; 855 min = cpu_data->min_perf_ratio; 856 857 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 858 min = max; 859 860 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 861 862 value &= ~HWP_MIN_PERF(~0L); 863 value |= HWP_MIN_PERF(min); 864 865 value &= ~HWP_MAX_PERF(~0L); 866 value |= HWP_MAX_PERF(max); 867 868 if (cpu_data->epp_policy == cpu_data->policy) 869 goto skip_epp; 870 871 cpu_data->epp_policy = cpu_data->policy; 872 873 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 874 epp = intel_pstate_get_epp(cpu_data, value); 875 cpu_data->epp_powersave = epp; 876 /* If EPP read was failed, then don't try to write */ 877 if (epp < 0) 878 goto skip_epp; 879 880 epp = 0; 881 } else { 882 /* skip setting EPP, when saved value is invalid */ 883 if (cpu_data->epp_powersave < 0) 884 goto skip_epp; 885 886 /* 887 * No need to restore EPP when it is not zero. This 888 * means: 889 * - Policy is not changed 890 * - user has manually changed 891 * - Error reading EPB 892 */ 893 epp = intel_pstate_get_epp(cpu_data, value); 894 if (epp) 895 goto skip_epp; 896 897 epp = cpu_data->epp_powersave; 898 } 899 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 900 value &= ~GENMASK_ULL(31, 24); 901 value |= (u64)epp << 24; 902 } else { 903 intel_pstate_set_epb(cpu, epp); 904 } 905 skip_epp: 906 WRITE_ONCE(cpu_data->hwp_req_cached, value); 907 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 908 } 909 910 static void intel_pstate_hwp_offline(struct cpudata *cpu) 911 { 912 u64 value = READ_ONCE(cpu->hwp_req_cached); 913 int min_perf; 914 915 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 916 /* 917 * In case the EPP has been set to "performance" by the 918 * active mode "performance" scaling algorithm, replace that 919 * temporary value with the cached EPP one. 920 */ 921 value &= ~GENMASK_ULL(31, 24); 922 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 923 WRITE_ONCE(cpu->hwp_req_cached, value); 924 } 925 926 value &= ~GENMASK_ULL(31, 0); 927 min_perf = HWP_LOWEST_PERF(cpu->hwp_cap_cached); 928 929 /* Set hwp_max = hwp_min */ 930 value |= HWP_MAX_PERF(min_perf); 931 value |= HWP_MIN_PERF(min_perf); 932 933 /* Set EPP to min */ 934 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 935 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 936 937 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 938 } 939 940 #define POWER_CTL_EE_ENABLE 1 941 #define POWER_CTL_EE_DISABLE 2 942 943 static int power_ctl_ee_state; 944 945 static void set_power_ctl_ee_state(bool input) 946 { 947 u64 power_ctl; 948 949 mutex_lock(&intel_pstate_driver_lock); 950 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 951 if (input) { 952 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 953 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 954 } else { 955 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 956 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 957 } 958 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 959 mutex_unlock(&intel_pstate_driver_lock); 960 } 961 962 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 963 964 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 965 { 966 intel_pstate_hwp_enable(cpu); 967 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 968 } 969 970 static int intel_pstate_suspend(struct cpufreq_policy *policy) 971 { 972 struct cpudata *cpu = all_cpu_data[policy->cpu]; 973 974 pr_debug("CPU %d suspending\n", cpu->cpu); 975 976 cpu->suspended = true; 977 978 return 0; 979 } 980 981 static int intel_pstate_resume(struct cpufreq_policy *policy) 982 { 983 struct cpudata *cpu = all_cpu_data[policy->cpu]; 984 985 pr_debug("CPU %d resuming\n", cpu->cpu); 986 987 /* Only restore if the system default is changed */ 988 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 989 set_power_ctl_ee_state(true); 990 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 991 set_power_ctl_ee_state(false); 992 993 if (cpu->suspended && hwp_active) { 994 mutex_lock(&intel_pstate_limits_lock); 995 996 /* Re-enable HWP, because "online" has not done that. */ 997 intel_pstate_hwp_reenable(cpu); 998 999 mutex_unlock(&intel_pstate_limits_lock); 1000 } 1001 1002 cpu->suspended = false; 1003 1004 return 0; 1005 } 1006 1007 static void intel_pstate_update_policies(void) 1008 { 1009 int cpu; 1010 1011 for_each_possible_cpu(cpu) 1012 cpufreq_update_policy(cpu); 1013 } 1014 1015 static void intel_pstate_update_max_freq(unsigned int cpu) 1016 { 1017 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1018 struct cpudata *cpudata; 1019 1020 if (!policy) 1021 return; 1022 1023 cpudata = all_cpu_data[cpu]; 1024 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 1025 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1026 1027 refresh_frequency_limits(policy); 1028 1029 cpufreq_cpu_release(policy); 1030 } 1031 1032 static void intel_pstate_update_limits(unsigned int cpu) 1033 { 1034 mutex_lock(&intel_pstate_driver_lock); 1035 1036 update_turbo_state(); 1037 /* 1038 * If turbo has been turned on or off globally, policy limits for 1039 * all CPUs need to be updated to reflect that. 1040 */ 1041 if (global.turbo_disabled_mf != global.turbo_disabled) { 1042 global.turbo_disabled_mf = global.turbo_disabled; 1043 arch_set_max_freq_ratio(global.turbo_disabled); 1044 for_each_possible_cpu(cpu) 1045 intel_pstate_update_max_freq(cpu); 1046 } else { 1047 cpufreq_update_policy(cpu); 1048 } 1049 1050 mutex_unlock(&intel_pstate_driver_lock); 1051 } 1052 1053 /************************** sysfs begin ************************/ 1054 #define show_one(file_name, object) \ 1055 static ssize_t show_##file_name \ 1056 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1057 { \ 1058 return sprintf(buf, "%u\n", global.object); \ 1059 } 1060 1061 static ssize_t intel_pstate_show_status(char *buf); 1062 static int intel_pstate_update_status(const char *buf, size_t size); 1063 1064 static ssize_t show_status(struct kobject *kobj, 1065 struct kobj_attribute *attr, char *buf) 1066 { 1067 ssize_t ret; 1068 1069 mutex_lock(&intel_pstate_driver_lock); 1070 ret = intel_pstate_show_status(buf); 1071 mutex_unlock(&intel_pstate_driver_lock); 1072 1073 return ret; 1074 } 1075 1076 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1077 const char *buf, size_t count) 1078 { 1079 char *p = memchr(buf, '\n', count); 1080 int ret; 1081 1082 mutex_lock(&intel_pstate_driver_lock); 1083 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1084 mutex_unlock(&intel_pstate_driver_lock); 1085 1086 return ret < 0 ? ret : count; 1087 } 1088 1089 static ssize_t show_turbo_pct(struct kobject *kobj, 1090 struct kobj_attribute *attr, char *buf) 1091 { 1092 struct cpudata *cpu; 1093 int total, no_turbo, turbo_pct; 1094 uint32_t turbo_fp; 1095 1096 mutex_lock(&intel_pstate_driver_lock); 1097 1098 if (!intel_pstate_driver) { 1099 mutex_unlock(&intel_pstate_driver_lock); 1100 return -EAGAIN; 1101 } 1102 1103 cpu = all_cpu_data[0]; 1104 1105 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1106 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1107 turbo_fp = div_fp(no_turbo, total); 1108 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1109 1110 mutex_unlock(&intel_pstate_driver_lock); 1111 1112 return sprintf(buf, "%u\n", turbo_pct); 1113 } 1114 1115 static ssize_t show_num_pstates(struct kobject *kobj, 1116 struct kobj_attribute *attr, char *buf) 1117 { 1118 struct cpudata *cpu; 1119 int total; 1120 1121 mutex_lock(&intel_pstate_driver_lock); 1122 1123 if (!intel_pstate_driver) { 1124 mutex_unlock(&intel_pstate_driver_lock); 1125 return -EAGAIN; 1126 } 1127 1128 cpu = all_cpu_data[0]; 1129 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1130 1131 mutex_unlock(&intel_pstate_driver_lock); 1132 1133 return sprintf(buf, "%u\n", total); 1134 } 1135 1136 static ssize_t show_no_turbo(struct kobject *kobj, 1137 struct kobj_attribute *attr, char *buf) 1138 { 1139 ssize_t ret; 1140 1141 mutex_lock(&intel_pstate_driver_lock); 1142 1143 if (!intel_pstate_driver) { 1144 mutex_unlock(&intel_pstate_driver_lock); 1145 return -EAGAIN; 1146 } 1147 1148 update_turbo_state(); 1149 if (global.turbo_disabled) 1150 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1151 else 1152 ret = sprintf(buf, "%u\n", global.no_turbo); 1153 1154 mutex_unlock(&intel_pstate_driver_lock); 1155 1156 return ret; 1157 } 1158 1159 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1160 const char *buf, size_t count) 1161 { 1162 unsigned int input; 1163 int ret; 1164 1165 ret = sscanf(buf, "%u", &input); 1166 if (ret != 1) 1167 return -EINVAL; 1168 1169 mutex_lock(&intel_pstate_driver_lock); 1170 1171 if (!intel_pstate_driver) { 1172 mutex_unlock(&intel_pstate_driver_lock); 1173 return -EAGAIN; 1174 } 1175 1176 mutex_lock(&intel_pstate_limits_lock); 1177 1178 update_turbo_state(); 1179 if (global.turbo_disabled) { 1180 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1181 mutex_unlock(&intel_pstate_limits_lock); 1182 mutex_unlock(&intel_pstate_driver_lock); 1183 return -EPERM; 1184 } 1185 1186 global.no_turbo = clamp_t(int, input, 0, 1); 1187 1188 if (global.no_turbo) { 1189 struct cpudata *cpu = all_cpu_data[0]; 1190 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1191 1192 /* Squash the global minimum into the permitted range. */ 1193 if (global.min_perf_pct > pct) 1194 global.min_perf_pct = pct; 1195 } 1196 1197 mutex_unlock(&intel_pstate_limits_lock); 1198 1199 intel_pstate_update_policies(); 1200 1201 mutex_unlock(&intel_pstate_driver_lock); 1202 1203 return count; 1204 } 1205 1206 static void update_qos_request(enum freq_qos_req_type type) 1207 { 1208 int max_state, turbo_max, freq, i, perf_pct; 1209 struct freq_qos_request *req; 1210 struct cpufreq_policy *policy; 1211 1212 for_each_possible_cpu(i) { 1213 struct cpudata *cpu = all_cpu_data[i]; 1214 1215 policy = cpufreq_cpu_get(i); 1216 if (!policy) 1217 continue; 1218 1219 req = policy->driver_data; 1220 cpufreq_cpu_put(policy); 1221 1222 if (!req) 1223 continue; 1224 1225 if (hwp_active) 1226 intel_pstate_get_hwp_max(i, &turbo_max, &max_state); 1227 else 1228 turbo_max = cpu->pstate.turbo_pstate; 1229 1230 if (type == FREQ_QOS_MIN) { 1231 perf_pct = global.min_perf_pct; 1232 } else { 1233 req++; 1234 perf_pct = global.max_perf_pct; 1235 } 1236 1237 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100); 1238 freq *= cpu->pstate.scaling; 1239 1240 if (freq_qos_update_request(req, freq) < 0) 1241 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1242 } 1243 } 1244 1245 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1246 const char *buf, size_t count) 1247 { 1248 unsigned int input; 1249 int ret; 1250 1251 ret = sscanf(buf, "%u", &input); 1252 if (ret != 1) 1253 return -EINVAL; 1254 1255 mutex_lock(&intel_pstate_driver_lock); 1256 1257 if (!intel_pstate_driver) { 1258 mutex_unlock(&intel_pstate_driver_lock); 1259 return -EAGAIN; 1260 } 1261 1262 mutex_lock(&intel_pstate_limits_lock); 1263 1264 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1265 1266 mutex_unlock(&intel_pstate_limits_lock); 1267 1268 if (intel_pstate_driver == &intel_pstate) 1269 intel_pstate_update_policies(); 1270 else 1271 update_qos_request(FREQ_QOS_MAX); 1272 1273 mutex_unlock(&intel_pstate_driver_lock); 1274 1275 return count; 1276 } 1277 1278 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1279 const char *buf, size_t count) 1280 { 1281 unsigned int input; 1282 int ret; 1283 1284 ret = sscanf(buf, "%u", &input); 1285 if (ret != 1) 1286 return -EINVAL; 1287 1288 mutex_lock(&intel_pstate_driver_lock); 1289 1290 if (!intel_pstate_driver) { 1291 mutex_unlock(&intel_pstate_driver_lock); 1292 return -EAGAIN; 1293 } 1294 1295 mutex_lock(&intel_pstate_limits_lock); 1296 1297 global.min_perf_pct = clamp_t(int, input, 1298 min_perf_pct_min(), global.max_perf_pct); 1299 1300 mutex_unlock(&intel_pstate_limits_lock); 1301 1302 if (intel_pstate_driver == &intel_pstate) 1303 intel_pstate_update_policies(); 1304 else 1305 update_qos_request(FREQ_QOS_MIN); 1306 1307 mutex_unlock(&intel_pstate_driver_lock); 1308 1309 return count; 1310 } 1311 1312 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1313 struct kobj_attribute *attr, char *buf) 1314 { 1315 return sprintf(buf, "%u\n", hwp_boost); 1316 } 1317 1318 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1319 struct kobj_attribute *b, 1320 const char *buf, size_t count) 1321 { 1322 unsigned int input; 1323 int ret; 1324 1325 ret = kstrtouint(buf, 10, &input); 1326 if (ret) 1327 return ret; 1328 1329 mutex_lock(&intel_pstate_driver_lock); 1330 hwp_boost = !!input; 1331 intel_pstate_update_policies(); 1332 mutex_unlock(&intel_pstate_driver_lock); 1333 1334 return count; 1335 } 1336 1337 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1338 char *buf) 1339 { 1340 u64 power_ctl; 1341 int enable; 1342 1343 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1344 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1345 return sprintf(buf, "%d\n", !enable); 1346 } 1347 1348 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1349 const char *buf, size_t count) 1350 { 1351 bool input; 1352 int ret; 1353 1354 ret = kstrtobool(buf, &input); 1355 if (ret) 1356 return ret; 1357 1358 set_power_ctl_ee_state(input); 1359 1360 return count; 1361 } 1362 1363 show_one(max_perf_pct, max_perf_pct); 1364 show_one(min_perf_pct, min_perf_pct); 1365 1366 define_one_global_rw(status); 1367 define_one_global_rw(no_turbo); 1368 define_one_global_rw(max_perf_pct); 1369 define_one_global_rw(min_perf_pct); 1370 define_one_global_ro(turbo_pct); 1371 define_one_global_ro(num_pstates); 1372 define_one_global_rw(hwp_dynamic_boost); 1373 define_one_global_rw(energy_efficiency); 1374 1375 static struct attribute *intel_pstate_attributes[] = { 1376 &status.attr, 1377 &no_turbo.attr, 1378 &turbo_pct.attr, 1379 &num_pstates.attr, 1380 NULL 1381 }; 1382 1383 static const struct attribute_group intel_pstate_attr_group = { 1384 .attrs = intel_pstate_attributes, 1385 }; 1386 1387 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1388 1389 static struct kobject *intel_pstate_kobject; 1390 1391 static void __init intel_pstate_sysfs_expose_params(void) 1392 { 1393 int rc; 1394 1395 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1396 &cpu_subsys.dev_root->kobj); 1397 if (WARN_ON(!intel_pstate_kobject)) 1398 return; 1399 1400 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1401 if (WARN_ON(rc)) 1402 return; 1403 1404 /* 1405 * If per cpu limits are enforced there are no global limits, so 1406 * return without creating max/min_perf_pct attributes 1407 */ 1408 if (per_cpu_limits) 1409 return; 1410 1411 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1412 WARN_ON(rc); 1413 1414 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1415 WARN_ON(rc); 1416 1417 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1418 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1419 WARN_ON(rc); 1420 } 1421 } 1422 1423 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1424 { 1425 int rc; 1426 1427 if (!hwp_active) 1428 return; 1429 1430 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1431 WARN_ON_ONCE(rc); 1432 } 1433 1434 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1435 { 1436 if (!hwp_active) 1437 return; 1438 1439 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1440 } 1441 1442 /************************** sysfs end ************************/ 1443 1444 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1445 { 1446 /* First disable HWP notification interrupt as we don't process them */ 1447 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1448 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1449 1450 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1451 if (cpudata->epp_default == -EINVAL) 1452 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1453 } 1454 1455 static int atom_get_min_pstate(void) 1456 { 1457 u64 value; 1458 1459 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1460 return (value >> 8) & 0x7F; 1461 } 1462 1463 static int atom_get_max_pstate(void) 1464 { 1465 u64 value; 1466 1467 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1468 return (value >> 16) & 0x7F; 1469 } 1470 1471 static int atom_get_turbo_pstate(void) 1472 { 1473 u64 value; 1474 1475 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1476 return value & 0x7F; 1477 } 1478 1479 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1480 { 1481 u64 val; 1482 int32_t vid_fp; 1483 u32 vid; 1484 1485 val = (u64)pstate << 8; 1486 if (global.no_turbo && !global.turbo_disabled) 1487 val |= (u64)1 << 32; 1488 1489 vid_fp = cpudata->vid.min + mul_fp( 1490 int_tofp(pstate - cpudata->pstate.min_pstate), 1491 cpudata->vid.ratio); 1492 1493 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1494 vid = ceiling_fp(vid_fp); 1495 1496 if (pstate > cpudata->pstate.max_pstate) 1497 vid = cpudata->vid.turbo; 1498 1499 return val | vid; 1500 } 1501 1502 static int silvermont_get_scaling(void) 1503 { 1504 u64 value; 1505 int i; 1506 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1507 static int silvermont_freq_table[] = { 1508 83300, 100000, 133300, 116700, 80000}; 1509 1510 rdmsrl(MSR_FSB_FREQ, value); 1511 i = value & 0x7; 1512 WARN_ON(i > 4); 1513 1514 return silvermont_freq_table[i]; 1515 } 1516 1517 static int airmont_get_scaling(void) 1518 { 1519 u64 value; 1520 int i; 1521 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1522 static int airmont_freq_table[] = { 1523 83300, 100000, 133300, 116700, 80000, 1524 93300, 90000, 88900, 87500}; 1525 1526 rdmsrl(MSR_FSB_FREQ, value); 1527 i = value & 0xF; 1528 WARN_ON(i > 8); 1529 1530 return airmont_freq_table[i]; 1531 } 1532 1533 static void atom_get_vid(struct cpudata *cpudata) 1534 { 1535 u64 value; 1536 1537 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1538 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1539 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1540 cpudata->vid.ratio = div_fp( 1541 cpudata->vid.max - cpudata->vid.min, 1542 int_tofp(cpudata->pstate.max_pstate - 1543 cpudata->pstate.min_pstate)); 1544 1545 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1546 cpudata->vid.turbo = value & 0x7f; 1547 } 1548 1549 static int core_get_min_pstate(void) 1550 { 1551 u64 value; 1552 1553 rdmsrl(MSR_PLATFORM_INFO, value); 1554 return (value >> 40) & 0xFF; 1555 } 1556 1557 static int core_get_max_pstate_physical(void) 1558 { 1559 u64 value; 1560 1561 rdmsrl(MSR_PLATFORM_INFO, value); 1562 return (value >> 8) & 0xFF; 1563 } 1564 1565 static int core_get_tdp_ratio(u64 plat_info) 1566 { 1567 /* Check how many TDP levels present */ 1568 if (plat_info & 0x600000000) { 1569 u64 tdp_ctrl; 1570 u64 tdp_ratio; 1571 int tdp_msr; 1572 int err; 1573 1574 /* Get the TDP level (0, 1, 2) to get ratios */ 1575 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1576 if (err) 1577 return err; 1578 1579 /* TDP MSR are continuous starting at 0x648 */ 1580 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1581 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1582 if (err) 1583 return err; 1584 1585 /* For level 1 and 2, bits[23:16] contain the ratio */ 1586 if (tdp_ctrl & 0x03) 1587 tdp_ratio >>= 16; 1588 1589 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1590 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1591 1592 return (int)tdp_ratio; 1593 } 1594 1595 return -ENXIO; 1596 } 1597 1598 static int core_get_max_pstate(void) 1599 { 1600 u64 tar; 1601 u64 plat_info; 1602 int max_pstate; 1603 int tdp_ratio; 1604 int err; 1605 1606 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1607 max_pstate = (plat_info >> 8) & 0xFF; 1608 1609 tdp_ratio = core_get_tdp_ratio(plat_info); 1610 if (tdp_ratio <= 0) 1611 return max_pstate; 1612 1613 if (hwp_active) { 1614 /* Turbo activation ratio is not used on HWP platforms */ 1615 return tdp_ratio; 1616 } 1617 1618 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1619 if (!err) { 1620 int tar_levels; 1621 1622 /* Do some sanity checking for safety */ 1623 tar_levels = tar & 0xff; 1624 if (tdp_ratio - 1 == tar_levels) { 1625 max_pstate = tar_levels; 1626 pr_debug("max_pstate=TAC %x\n", max_pstate); 1627 } 1628 } 1629 1630 return max_pstate; 1631 } 1632 1633 static int core_get_turbo_pstate(void) 1634 { 1635 u64 value; 1636 int nont, ret; 1637 1638 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1639 nont = core_get_max_pstate(); 1640 ret = (value) & 255; 1641 if (ret <= nont) 1642 ret = nont; 1643 return ret; 1644 } 1645 1646 static inline int core_get_scaling(void) 1647 { 1648 return 100000; 1649 } 1650 1651 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1652 { 1653 u64 val; 1654 1655 val = (u64)pstate << 8; 1656 if (global.no_turbo && !global.turbo_disabled) 1657 val |= (u64)1 << 32; 1658 1659 return val; 1660 } 1661 1662 static int knl_get_aperf_mperf_shift(void) 1663 { 1664 return 10; 1665 } 1666 1667 static int knl_get_turbo_pstate(void) 1668 { 1669 u64 value; 1670 int nont, ret; 1671 1672 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1673 nont = core_get_max_pstate(); 1674 ret = (((value) >> 8) & 0xFF); 1675 if (ret <= nont) 1676 ret = nont; 1677 return ret; 1678 } 1679 1680 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1681 { 1682 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1683 cpu->pstate.current_pstate = pstate; 1684 /* 1685 * Generally, there is no guarantee that this code will always run on 1686 * the CPU being updated, so force the register update to run on the 1687 * right CPU. 1688 */ 1689 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1690 pstate_funcs.get_val(cpu, pstate)); 1691 } 1692 1693 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1694 { 1695 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1696 } 1697 1698 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1699 { 1700 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1701 1702 update_turbo_state(); 1703 intel_pstate_set_pstate(cpu, pstate); 1704 } 1705 1706 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1707 { 1708 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1709 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1710 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1711 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1712 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1713 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; 1714 1715 if (hwp_active && !hwp_mode_bdw) { 1716 unsigned int phy_max, current_max; 1717 1718 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max); 1719 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling; 1720 cpu->pstate.turbo_pstate = phy_max; 1721 } else { 1722 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1723 } 1724 1725 if (pstate_funcs.get_aperf_mperf_shift) 1726 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 1727 1728 if (pstate_funcs.get_vid) 1729 pstate_funcs.get_vid(cpu); 1730 1731 intel_pstate_set_min_pstate(cpu); 1732 } 1733 1734 /* 1735 * Long hold time will keep high perf limits for long time, 1736 * which negatively impacts perf/watt for some workloads, 1737 * like specpower. 3ms is based on experiements on some 1738 * workoads. 1739 */ 1740 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 1741 1742 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 1743 { 1744 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 1745 u32 max_limit = (hwp_req & 0xff00) >> 8; 1746 u32 min_limit = (hwp_req & 0xff); 1747 u32 boost_level1; 1748 1749 /* 1750 * Cases to consider (User changes via sysfs or boot time): 1751 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 1752 * No boost, return. 1753 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 1754 * Should result in one level boost only for P0. 1755 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 1756 * Should result in two level boost: 1757 * (min + p1)/2 and P1. 1758 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 1759 * Should result in three level boost: 1760 * (min + p1)/2, P1 and P0. 1761 */ 1762 1763 /* If max and min are equal or already at max, nothing to boost */ 1764 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 1765 return; 1766 1767 if (!cpu->hwp_boost_min) 1768 cpu->hwp_boost_min = min_limit; 1769 1770 /* level at half way mark between min and guranteed */ 1771 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1; 1772 1773 if (cpu->hwp_boost_min < boost_level1) 1774 cpu->hwp_boost_min = boost_level1; 1775 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1776 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached); 1777 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) && 1778 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1779 cpu->hwp_boost_min = max_limit; 1780 else 1781 return; 1782 1783 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 1784 wrmsrl(MSR_HWP_REQUEST, hwp_req); 1785 cpu->last_update = cpu->sample.time; 1786 } 1787 1788 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 1789 { 1790 if (cpu->hwp_boost_min) { 1791 bool expired; 1792 1793 /* Check if we are idle for hold time to boost down */ 1794 expired = time_after64(cpu->sample.time, cpu->last_update + 1795 hwp_boost_hold_time_ns); 1796 if (expired) { 1797 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 1798 cpu->hwp_boost_min = 0; 1799 } 1800 } 1801 cpu->last_update = cpu->sample.time; 1802 } 1803 1804 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 1805 u64 time) 1806 { 1807 cpu->sample.time = time; 1808 1809 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 1810 bool do_io = false; 1811 1812 cpu->sched_flags = 0; 1813 /* 1814 * Set iowait_boost flag and update time. Since IO WAIT flag 1815 * is set all the time, we can't just conclude that there is 1816 * some IO bound activity is scheduled on this CPU with just 1817 * one occurrence. If we receive at least two in two 1818 * consecutive ticks, then we treat as boost candidate. 1819 */ 1820 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 1821 do_io = true; 1822 1823 cpu->last_io_update = time; 1824 1825 if (do_io) 1826 intel_pstate_hwp_boost_up(cpu); 1827 1828 } else { 1829 intel_pstate_hwp_boost_down(cpu); 1830 } 1831 } 1832 1833 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 1834 u64 time, unsigned int flags) 1835 { 1836 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1837 1838 cpu->sched_flags |= flags; 1839 1840 if (smp_processor_id() == cpu->cpu) 1841 intel_pstate_update_util_hwp_local(cpu, time); 1842 } 1843 1844 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1845 { 1846 struct sample *sample = &cpu->sample; 1847 1848 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1849 } 1850 1851 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1852 { 1853 u64 aperf, mperf; 1854 unsigned long flags; 1855 u64 tsc; 1856 1857 local_irq_save(flags); 1858 rdmsrl(MSR_IA32_APERF, aperf); 1859 rdmsrl(MSR_IA32_MPERF, mperf); 1860 tsc = rdtsc(); 1861 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1862 local_irq_restore(flags); 1863 return false; 1864 } 1865 local_irq_restore(flags); 1866 1867 cpu->last_sample_time = cpu->sample.time; 1868 cpu->sample.time = time; 1869 cpu->sample.aperf = aperf; 1870 cpu->sample.mperf = mperf; 1871 cpu->sample.tsc = tsc; 1872 cpu->sample.aperf -= cpu->prev_aperf; 1873 cpu->sample.mperf -= cpu->prev_mperf; 1874 cpu->sample.tsc -= cpu->prev_tsc; 1875 1876 cpu->prev_aperf = aperf; 1877 cpu->prev_mperf = mperf; 1878 cpu->prev_tsc = tsc; 1879 /* 1880 * First time this function is invoked in a given cycle, all of the 1881 * previous sample data fields are equal to zero or stale and they must 1882 * be populated with meaningful numbers for things to work, so assume 1883 * that sample.time will always be reset before setting the utilization 1884 * update hook and make the caller skip the sample then. 1885 */ 1886 if (cpu->last_sample_time) { 1887 intel_pstate_calc_avg_perf(cpu); 1888 return true; 1889 } 1890 return false; 1891 } 1892 1893 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1894 { 1895 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 1896 } 1897 1898 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1899 { 1900 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1901 cpu->sample.core_avg_perf); 1902 } 1903 1904 static inline int32_t get_target_pstate(struct cpudata *cpu) 1905 { 1906 struct sample *sample = &cpu->sample; 1907 int32_t busy_frac; 1908 int target, avg_pstate; 1909 1910 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 1911 sample->tsc); 1912 1913 if (busy_frac < cpu->iowait_boost) 1914 busy_frac = cpu->iowait_boost; 1915 1916 sample->busy_scaled = busy_frac * 100; 1917 1918 target = global.no_turbo || global.turbo_disabled ? 1919 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1920 target += target >> 2; 1921 target = mul_fp(target, busy_frac); 1922 if (target < cpu->pstate.min_pstate) 1923 target = cpu->pstate.min_pstate; 1924 1925 /* 1926 * If the average P-state during the previous cycle was higher than the 1927 * current target, add 50% of the difference to the target to reduce 1928 * possible performance oscillations and offset possible performance 1929 * loss related to moving the workload from one CPU to another within 1930 * a package/module. 1931 */ 1932 avg_pstate = get_avg_pstate(cpu); 1933 if (avg_pstate > target) 1934 target += (avg_pstate - target) >> 1; 1935 1936 return target; 1937 } 1938 1939 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 1940 { 1941 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 1942 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 1943 1944 return clamp_t(int, pstate, min_pstate, max_pstate); 1945 } 1946 1947 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1948 { 1949 if (pstate == cpu->pstate.current_pstate) 1950 return; 1951 1952 cpu->pstate.current_pstate = pstate; 1953 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1954 } 1955 1956 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 1957 { 1958 int from = cpu->pstate.current_pstate; 1959 struct sample *sample; 1960 int target_pstate; 1961 1962 update_turbo_state(); 1963 1964 target_pstate = get_target_pstate(cpu); 1965 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 1966 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 1967 intel_pstate_update_pstate(cpu, target_pstate); 1968 1969 sample = &cpu->sample; 1970 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1971 fp_toint(sample->busy_scaled), 1972 from, 1973 cpu->pstate.current_pstate, 1974 sample->mperf, 1975 sample->aperf, 1976 sample->tsc, 1977 get_avg_frequency(cpu), 1978 fp_toint(cpu->iowait_boost * 100)); 1979 } 1980 1981 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1982 unsigned int flags) 1983 { 1984 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1985 u64 delta_ns; 1986 1987 /* Don't allow remote callbacks */ 1988 if (smp_processor_id() != cpu->cpu) 1989 return; 1990 1991 delta_ns = time - cpu->last_update; 1992 if (flags & SCHED_CPUFREQ_IOWAIT) { 1993 /* Start over if the CPU may have been idle. */ 1994 if (delta_ns > TICK_NSEC) { 1995 cpu->iowait_boost = ONE_EIGHTH_FP; 1996 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 1997 cpu->iowait_boost <<= 1; 1998 if (cpu->iowait_boost > int_tofp(1)) 1999 cpu->iowait_boost = int_tofp(1); 2000 } else { 2001 cpu->iowait_boost = ONE_EIGHTH_FP; 2002 } 2003 } else if (cpu->iowait_boost) { 2004 /* Clear iowait_boost if the CPU may have been idle. */ 2005 if (delta_ns > TICK_NSEC) 2006 cpu->iowait_boost = 0; 2007 else 2008 cpu->iowait_boost >>= 1; 2009 } 2010 cpu->last_update = time; 2011 delta_ns = time - cpu->sample.time; 2012 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2013 return; 2014 2015 if (intel_pstate_sample(cpu, time)) 2016 intel_pstate_adjust_pstate(cpu); 2017 } 2018 2019 static struct pstate_funcs core_funcs = { 2020 .get_max = core_get_max_pstate, 2021 .get_max_physical = core_get_max_pstate_physical, 2022 .get_min = core_get_min_pstate, 2023 .get_turbo = core_get_turbo_pstate, 2024 .get_scaling = core_get_scaling, 2025 .get_val = core_get_val, 2026 }; 2027 2028 static const struct pstate_funcs silvermont_funcs = { 2029 .get_max = atom_get_max_pstate, 2030 .get_max_physical = atom_get_max_pstate, 2031 .get_min = atom_get_min_pstate, 2032 .get_turbo = atom_get_turbo_pstate, 2033 .get_val = atom_get_val, 2034 .get_scaling = silvermont_get_scaling, 2035 .get_vid = atom_get_vid, 2036 }; 2037 2038 static const struct pstate_funcs airmont_funcs = { 2039 .get_max = atom_get_max_pstate, 2040 .get_max_physical = atom_get_max_pstate, 2041 .get_min = atom_get_min_pstate, 2042 .get_turbo = atom_get_turbo_pstate, 2043 .get_val = atom_get_val, 2044 .get_scaling = airmont_get_scaling, 2045 .get_vid = atom_get_vid, 2046 }; 2047 2048 static const struct pstate_funcs knl_funcs = { 2049 .get_max = core_get_max_pstate, 2050 .get_max_physical = core_get_max_pstate_physical, 2051 .get_min = core_get_min_pstate, 2052 .get_turbo = knl_get_turbo_pstate, 2053 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2054 .get_scaling = core_get_scaling, 2055 .get_val = core_get_val, 2056 }; 2057 2058 #define X86_MATCH(model, policy) \ 2059 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2060 X86_FEATURE_APERFMPERF, &policy) 2061 2062 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2063 X86_MATCH(SANDYBRIDGE, core_funcs), 2064 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2065 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2066 X86_MATCH(IVYBRIDGE, core_funcs), 2067 X86_MATCH(HASWELL, core_funcs), 2068 X86_MATCH(BROADWELL, core_funcs), 2069 X86_MATCH(IVYBRIDGE_X, core_funcs), 2070 X86_MATCH(HASWELL_X, core_funcs), 2071 X86_MATCH(HASWELL_L, core_funcs), 2072 X86_MATCH(HASWELL_G, core_funcs), 2073 X86_MATCH(BROADWELL_G, core_funcs), 2074 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2075 X86_MATCH(SKYLAKE_L, core_funcs), 2076 X86_MATCH(BROADWELL_X, core_funcs), 2077 X86_MATCH(SKYLAKE, core_funcs), 2078 X86_MATCH(BROADWELL_D, core_funcs), 2079 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2080 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2081 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2082 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2083 X86_MATCH(SKYLAKE_X, core_funcs), 2084 {} 2085 }; 2086 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2087 2088 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2089 X86_MATCH(BROADWELL_D, core_funcs), 2090 X86_MATCH(BROADWELL_X, core_funcs), 2091 X86_MATCH(SKYLAKE_X, core_funcs), 2092 {} 2093 }; 2094 2095 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2096 X86_MATCH(KABYLAKE, core_funcs), 2097 {} 2098 }; 2099 2100 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = { 2101 X86_MATCH(SKYLAKE_X, core_funcs), 2102 X86_MATCH(SKYLAKE, core_funcs), 2103 {} 2104 }; 2105 2106 static int intel_pstate_init_cpu(unsigned int cpunum) 2107 { 2108 struct cpudata *cpu; 2109 2110 cpu = all_cpu_data[cpunum]; 2111 2112 if (!cpu) { 2113 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2114 if (!cpu) 2115 return -ENOMEM; 2116 2117 all_cpu_data[cpunum] = cpu; 2118 2119 cpu->cpu = cpunum; 2120 2121 cpu->epp_default = -EINVAL; 2122 2123 if (hwp_active) { 2124 const struct x86_cpu_id *id; 2125 2126 intel_pstate_hwp_enable(cpu); 2127 2128 id = x86_match_cpu(intel_pstate_hwp_boost_ids); 2129 if (id && intel_pstate_acpi_pm_profile_server()) 2130 hwp_boost = true; 2131 } 2132 } else if (hwp_active) { 2133 /* 2134 * Re-enable HWP in case this happens after a resume from ACPI 2135 * S3 if the CPU was offline during the whole system/resume 2136 * cycle. 2137 */ 2138 intel_pstate_hwp_reenable(cpu); 2139 } 2140 2141 cpu->epp_powersave = -EINVAL; 2142 cpu->epp_policy = 0; 2143 2144 intel_pstate_get_cpu_pstates(cpu); 2145 2146 pr_debug("controlling: cpu %d\n", cpunum); 2147 2148 return 0; 2149 } 2150 2151 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2152 { 2153 struct cpudata *cpu = all_cpu_data[cpu_num]; 2154 2155 if (hwp_active && !hwp_boost) 2156 return; 2157 2158 if (cpu->update_util_set) 2159 return; 2160 2161 /* Prevent intel_pstate_update_util() from using stale data. */ 2162 cpu->sample.time = 0; 2163 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2164 (hwp_active ? 2165 intel_pstate_update_util_hwp : 2166 intel_pstate_update_util)); 2167 cpu->update_util_set = true; 2168 } 2169 2170 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2171 { 2172 struct cpudata *cpu_data = all_cpu_data[cpu]; 2173 2174 if (!cpu_data->update_util_set) 2175 return; 2176 2177 cpufreq_remove_update_util_hook(cpu); 2178 cpu_data->update_util_set = false; 2179 synchronize_rcu(); 2180 } 2181 2182 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2183 { 2184 return global.turbo_disabled || global.no_turbo ? 2185 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2186 } 2187 2188 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2189 unsigned int policy_min, 2190 unsigned int policy_max) 2191 { 2192 int max_freq = intel_pstate_get_max_freq(cpu); 2193 int32_t max_policy_perf, min_policy_perf; 2194 int max_state, turbo_max; 2195 2196 /* 2197 * HWP needs some special consideration, because on BDX the 2198 * HWP_REQUEST uses abstract value to represent performance 2199 * rather than pure ratios. 2200 */ 2201 if (hwp_active) { 2202 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state); 2203 } else { 2204 max_state = global.no_turbo || global.turbo_disabled ? 2205 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2206 turbo_max = cpu->pstate.turbo_pstate; 2207 } 2208 2209 max_policy_perf = max_state * policy_max / max_freq; 2210 if (policy_max == policy_min) { 2211 min_policy_perf = max_policy_perf; 2212 } else { 2213 min_policy_perf = max_state * policy_min / max_freq; 2214 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2215 0, max_policy_perf); 2216 } 2217 2218 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n", 2219 cpu->cpu, max_state, min_policy_perf, max_policy_perf); 2220 2221 /* Normalize user input to [min_perf, max_perf] */ 2222 if (per_cpu_limits) { 2223 cpu->min_perf_ratio = min_policy_perf; 2224 cpu->max_perf_ratio = max_policy_perf; 2225 } else { 2226 int32_t global_min, global_max; 2227 2228 /* Global limits are in percent of the maximum turbo P-state. */ 2229 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2230 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2231 global_min = clamp_t(int32_t, global_min, 0, global_max); 2232 2233 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2234 global_min, global_max); 2235 2236 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2237 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2238 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2239 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2240 2241 /* Make sure min_perf <= max_perf */ 2242 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2243 cpu->max_perf_ratio); 2244 2245 } 2246 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2247 cpu->max_perf_ratio, 2248 cpu->min_perf_ratio); 2249 } 2250 2251 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2252 { 2253 struct cpudata *cpu; 2254 2255 if (!policy->cpuinfo.max_freq) 2256 return -ENODEV; 2257 2258 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2259 policy->cpuinfo.max_freq, policy->max); 2260 2261 cpu = all_cpu_data[policy->cpu]; 2262 cpu->policy = policy->policy; 2263 2264 mutex_lock(&intel_pstate_limits_lock); 2265 2266 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2267 2268 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2269 /* 2270 * NOHZ_FULL CPUs need this as the governor callback may not 2271 * be invoked on them. 2272 */ 2273 intel_pstate_clear_update_util_hook(policy->cpu); 2274 intel_pstate_max_within_limits(cpu); 2275 } else { 2276 intel_pstate_set_update_util_hook(policy->cpu); 2277 } 2278 2279 if (hwp_active) { 2280 /* 2281 * When hwp_boost was active before and dynamically it 2282 * was turned off, in that case we need to clear the 2283 * update util hook. 2284 */ 2285 if (!hwp_boost) 2286 intel_pstate_clear_update_util_hook(policy->cpu); 2287 intel_pstate_hwp_set(policy->cpu); 2288 } 2289 2290 mutex_unlock(&intel_pstate_limits_lock); 2291 2292 return 0; 2293 } 2294 2295 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2296 struct cpufreq_policy_data *policy) 2297 { 2298 if (!hwp_active && 2299 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2300 policy->max < policy->cpuinfo.max_freq && 2301 policy->max > cpu->pstate.max_freq) { 2302 pr_debug("policy->max > max non turbo frequency\n"); 2303 policy->max = policy->cpuinfo.max_freq; 2304 } 2305 } 2306 2307 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2308 struct cpufreq_policy_data *policy) 2309 { 2310 update_turbo_state(); 2311 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 2312 intel_pstate_get_max_freq(cpu)); 2313 2314 intel_pstate_adjust_policy_max(cpu, policy); 2315 } 2316 2317 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2318 { 2319 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2320 2321 return 0; 2322 } 2323 2324 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2325 { 2326 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2327 2328 pr_debug("CPU %d going offline\n", cpu->cpu); 2329 2330 if (cpu->suspended) 2331 return 0; 2332 2333 /* 2334 * If the CPU is an SMT thread and it goes offline with the performance 2335 * settings different from the minimum, it will prevent its sibling 2336 * from getting to lower performance levels, so force the minimum 2337 * performance on CPU offline to prevent that from happening. 2338 */ 2339 if (hwp_active) 2340 intel_pstate_hwp_offline(cpu); 2341 else 2342 intel_pstate_set_min_pstate(cpu); 2343 2344 intel_pstate_exit_perf_limits(policy); 2345 2346 return 0; 2347 } 2348 2349 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2350 { 2351 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2352 2353 pr_debug("CPU %d going online\n", cpu->cpu); 2354 2355 intel_pstate_init_acpi_perf_limits(policy); 2356 2357 if (hwp_active) { 2358 /* 2359 * Re-enable HWP and clear the "suspended" flag to let "resume" 2360 * know that it need not do that. 2361 */ 2362 intel_pstate_hwp_reenable(cpu); 2363 cpu->suspended = false; 2364 } 2365 2366 return 0; 2367 } 2368 2369 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 2370 { 2371 pr_debug("CPU %d stopping\n", policy->cpu); 2372 2373 intel_pstate_clear_update_util_hook(policy->cpu); 2374 } 2375 2376 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2377 { 2378 pr_debug("CPU %d exiting\n", policy->cpu); 2379 2380 policy->fast_switch_possible = false; 2381 2382 return 0; 2383 } 2384 2385 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2386 { 2387 struct cpudata *cpu; 2388 int rc; 2389 2390 rc = intel_pstate_init_cpu(policy->cpu); 2391 if (rc) 2392 return rc; 2393 2394 cpu = all_cpu_data[policy->cpu]; 2395 2396 cpu->max_perf_ratio = 0xFF; 2397 cpu->min_perf_ratio = 0; 2398 2399 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 2400 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 2401 2402 /* cpuinfo and default policy values */ 2403 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 2404 update_turbo_state(); 2405 global.turbo_disabled_mf = global.turbo_disabled; 2406 policy->cpuinfo.max_freq = global.turbo_disabled ? 2407 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2408 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 2409 2410 if (hwp_active) { 2411 unsigned int max_freq; 2412 2413 max_freq = global.turbo_disabled ? 2414 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2415 if (max_freq < policy->cpuinfo.max_freq) 2416 policy->cpuinfo.max_freq = max_freq; 2417 } 2418 2419 intel_pstate_init_acpi_perf_limits(policy); 2420 2421 policy->fast_switch_possible = true; 2422 2423 return 0; 2424 } 2425 2426 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2427 { 2428 int ret = __intel_pstate_cpu_init(policy); 2429 2430 if (ret) 2431 return ret; 2432 2433 /* 2434 * Set the policy to powersave to provide a valid fallback value in case 2435 * the default cpufreq governor is neither powersave nor performance. 2436 */ 2437 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2438 2439 if (hwp_active) { 2440 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2441 2442 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2443 } 2444 2445 return 0; 2446 } 2447 2448 static struct cpufreq_driver intel_pstate = { 2449 .flags = CPUFREQ_CONST_LOOPS, 2450 .verify = intel_pstate_verify_policy, 2451 .setpolicy = intel_pstate_set_policy, 2452 .suspend = intel_pstate_suspend, 2453 .resume = intel_pstate_resume, 2454 .init = intel_pstate_cpu_init, 2455 .exit = intel_pstate_cpu_exit, 2456 .stop_cpu = intel_pstate_stop_cpu, 2457 .offline = intel_pstate_cpu_offline, 2458 .online = intel_pstate_cpu_online, 2459 .update_limits = intel_pstate_update_limits, 2460 .name = "intel_pstate", 2461 }; 2462 2463 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2464 { 2465 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2466 2467 intel_pstate_verify_cpu_policy(cpu, policy); 2468 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2469 2470 return 0; 2471 } 2472 2473 /* Use of trace in passive mode: 2474 * 2475 * In passive mode the trace core_busy field (also known as the 2476 * performance field, and lablelled as such on the graphs; also known as 2477 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2478 * driver call was via the normal or fast switch path. Various graphs 2479 * output from the intel_pstate_tracer.py utility that include core_busy 2480 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2481 * so we use 10 to indicate the the normal path through the driver, and 2482 * 90 to indicate the fast switch path through the driver. 2483 * The scaled_busy field is not used, and is set to 0. 2484 */ 2485 2486 #define INTEL_PSTATE_TRACE_TARGET 10 2487 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2488 2489 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2490 { 2491 struct sample *sample; 2492 2493 if (!trace_pstate_sample_enabled()) 2494 return; 2495 2496 if (!intel_pstate_sample(cpu, ktime_get())) 2497 return; 2498 2499 sample = &cpu->sample; 2500 trace_pstate_sample(trace_type, 2501 0, 2502 old_pstate, 2503 cpu->pstate.current_pstate, 2504 sample->mperf, 2505 sample->aperf, 2506 sample->tsc, 2507 get_avg_frequency(cpu), 2508 fp_toint(cpu->iowait_boost * 100)); 2509 } 2510 2511 static void intel_cpufreq_adjust_hwp(struct cpudata *cpu, u32 target_pstate, 2512 bool fast_switch) 2513 { 2514 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2515 2516 value &= ~HWP_MIN_PERF(~0L); 2517 value |= HWP_MIN_PERF(target_pstate); 2518 2519 /* 2520 * The entire MSR needs to be updated in order to update the HWP min 2521 * field in it, so opportunistically update the max too if needed. 2522 */ 2523 value &= ~HWP_MAX_PERF(~0L); 2524 value |= HWP_MAX_PERF(cpu->max_perf_ratio); 2525 2526 if (value == prev) 2527 return; 2528 2529 WRITE_ONCE(cpu->hwp_req_cached, value); 2530 if (fast_switch) 2531 wrmsrl(MSR_HWP_REQUEST, value); 2532 else 2533 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2534 } 2535 2536 static void intel_cpufreq_adjust_perf_ctl(struct cpudata *cpu, 2537 u32 target_pstate, bool fast_switch) 2538 { 2539 if (fast_switch) 2540 wrmsrl(MSR_IA32_PERF_CTL, 2541 pstate_funcs.get_val(cpu, target_pstate)); 2542 else 2543 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2544 pstate_funcs.get_val(cpu, target_pstate)); 2545 } 2546 2547 static int intel_cpufreq_update_pstate(struct cpudata *cpu, int target_pstate, 2548 bool fast_switch) 2549 { 2550 int old_pstate = cpu->pstate.current_pstate; 2551 2552 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2553 if (target_pstate != old_pstate) { 2554 cpu->pstate.current_pstate = target_pstate; 2555 if (hwp_active) 2556 intel_cpufreq_adjust_hwp(cpu, target_pstate, 2557 fast_switch); 2558 else 2559 intel_cpufreq_adjust_perf_ctl(cpu, target_pstate, 2560 fast_switch); 2561 } 2562 2563 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2564 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2565 2566 return target_pstate; 2567 } 2568 2569 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2570 unsigned int target_freq, 2571 unsigned int relation) 2572 { 2573 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2574 struct cpufreq_freqs freqs; 2575 int target_pstate; 2576 2577 update_turbo_state(); 2578 2579 freqs.old = policy->cur; 2580 freqs.new = target_freq; 2581 2582 cpufreq_freq_transition_begin(policy, &freqs); 2583 2584 switch (relation) { 2585 case CPUFREQ_RELATION_L: 2586 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2587 break; 2588 case CPUFREQ_RELATION_H: 2589 target_pstate = freqs.new / cpu->pstate.scaling; 2590 break; 2591 default: 2592 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2593 break; 2594 } 2595 2596 target_pstate = intel_cpufreq_update_pstate(cpu, target_pstate, false); 2597 2598 freqs.new = target_pstate * cpu->pstate.scaling; 2599 2600 cpufreq_freq_transition_end(policy, &freqs, false); 2601 2602 return 0; 2603 } 2604 2605 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2606 unsigned int target_freq) 2607 { 2608 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2609 int target_pstate; 2610 2611 update_turbo_state(); 2612 2613 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2614 2615 target_pstate = intel_cpufreq_update_pstate(cpu, target_pstate, true); 2616 2617 return target_pstate * cpu->pstate.scaling; 2618 } 2619 2620 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2621 { 2622 int max_state, turbo_max, min_freq, max_freq, ret; 2623 struct freq_qos_request *req; 2624 struct cpudata *cpu; 2625 struct device *dev; 2626 2627 dev = get_cpu_device(policy->cpu); 2628 if (!dev) 2629 return -ENODEV; 2630 2631 ret = __intel_pstate_cpu_init(policy); 2632 if (ret) 2633 return ret; 2634 2635 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2636 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2637 policy->cur = policy->cpuinfo.min_freq; 2638 2639 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2640 if (!req) { 2641 ret = -ENOMEM; 2642 goto pstate_exit; 2643 } 2644 2645 cpu = all_cpu_data[policy->cpu]; 2646 2647 if (hwp_active) { 2648 u64 value; 2649 2650 intel_pstate_get_hwp_max(policy->cpu, &turbo_max, &max_state); 2651 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2652 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 2653 WRITE_ONCE(cpu->hwp_req_cached, value); 2654 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 2655 } else { 2656 turbo_max = cpu->pstate.turbo_pstate; 2657 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2658 } 2659 2660 min_freq = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2661 min_freq *= cpu->pstate.scaling; 2662 max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2663 max_freq *= cpu->pstate.scaling; 2664 2665 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 2666 min_freq); 2667 if (ret < 0) { 2668 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 2669 goto free_req; 2670 } 2671 2672 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 2673 max_freq); 2674 if (ret < 0) { 2675 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 2676 goto remove_min_req; 2677 } 2678 2679 policy->driver_data = req; 2680 2681 return 0; 2682 2683 remove_min_req: 2684 freq_qos_remove_request(req); 2685 free_req: 2686 kfree(req); 2687 pstate_exit: 2688 intel_pstate_exit_perf_limits(policy); 2689 2690 return ret; 2691 } 2692 2693 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 2694 { 2695 struct freq_qos_request *req; 2696 2697 req = policy->driver_data; 2698 2699 freq_qos_remove_request(req + 1); 2700 freq_qos_remove_request(req); 2701 kfree(req); 2702 2703 return intel_pstate_cpu_exit(policy); 2704 } 2705 2706 static struct cpufreq_driver intel_cpufreq = { 2707 .flags = CPUFREQ_CONST_LOOPS, 2708 .verify = intel_cpufreq_verify_policy, 2709 .target = intel_cpufreq_target, 2710 .fast_switch = intel_cpufreq_fast_switch, 2711 .init = intel_cpufreq_cpu_init, 2712 .exit = intel_cpufreq_cpu_exit, 2713 .offline = intel_pstate_cpu_offline, 2714 .online = intel_pstate_cpu_online, 2715 .suspend = intel_pstate_suspend, 2716 .resume = intel_pstate_resume, 2717 .update_limits = intel_pstate_update_limits, 2718 .name = "intel_cpufreq", 2719 }; 2720 2721 static struct cpufreq_driver *default_driver; 2722 2723 static void intel_pstate_driver_cleanup(void) 2724 { 2725 unsigned int cpu; 2726 2727 get_online_cpus(); 2728 for_each_online_cpu(cpu) { 2729 if (all_cpu_data[cpu]) { 2730 if (intel_pstate_driver == &intel_pstate) 2731 intel_pstate_clear_update_util_hook(cpu); 2732 2733 kfree(all_cpu_data[cpu]); 2734 all_cpu_data[cpu] = NULL; 2735 } 2736 } 2737 put_online_cpus(); 2738 2739 intel_pstate_driver = NULL; 2740 } 2741 2742 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 2743 { 2744 int ret; 2745 2746 if (driver == &intel_pstate) 2747 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 2748 2749 memset(&global, 0, sizeof(global)); 2750 global.max_perf_pct = 100; 2751 2752 intel_pstate_driver = driver; 2753 ret = cpufreq_register_driver(intel_pstate_driver); 2754 if (ret) { 2755 intel_pstate_driver_cleanup(); 2756 return ret; 2757 } 2758 2759 global.min_perf_pct = min_perf_pct_min(); 2760 2761 return 0; 2762 } 2763 2764 static ssize_t intel_pstate_show_status(char *buf) 2765 { 2766 if (!intel_pstate_driver) 2767 return sprintf(buf, "off\n"); 2768 2769 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 2770 "active" : "passive"); 2771 } 2772 2773 static int intel_pstate_update_status(const char *buf, size_t size) 2774 { 2775 if (size == 3 && !strncmp(buf, "off", size)) { 2776 if (!intel_pstate_driver) 2777 return -EINVAL; 2778 2779 if (hwp_active) 2780 return -EBUSY; 2781 2782 cpufreq_unregister_driver(intel_pstate_driver); 2783 intel_pstate_driver_cleanup(); 2784 } 2785 2786 if (size == 6 && !strncmp(buf, "active", size)) { 2787 if (intel_pstate_driver) { 2788 if (intel_pstate_driver == &intel_pstate) 2789 return 0; 2790 2791 cpufreq_unregister_driver(intel_pstate_driver); 2792 } 2793 2794 return intel_pstate_register_driver(&intel_pstate); 2795 } 2796 2797 if (size == 7 && !strncmp(buf, "passive", size)) { 2798 if (intel_pstate_driver) { 2799 if (intel_pstate_driver == &intel_cpufreq) 2800 return 0; 2801 2802 cpufreq_unregister_driver(intel_pstate_driver); 2803 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 2804 } 2805 2806 return intel_pstate_register_driver(&intel_cpufreq); 2807 } 2808 2809 return -EINVAL; 2810 } 2811 2812 static int no_load __initdata; 2813 static int no_hwp __initdata; 2814 static int hwp_only __initdata; 2815 static unsigned int force_load __initdata; 2816 2817 static int __init intel_pstate_msrs_not_valid(void) 2818 { 2819 if (!pstate_funcs.get_max() || 2820 !pstate_funcs.get_min() || 2821 !pstate_funcs.get_turbo()) 2822 return -ENODEV; 2823 2824 return 0; 2825 } 2826 2827 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 2828 { 2829 pstate_funcs.get_max = funcs->get_max; 2830 pstate_funcs.get_max_physical = funcs->get_max_physical; 2831 pstate_funcs.get_min = funcs->get_min; 2832 pstate_funcs.get_turbo = funcs->get_turbo; 2833 pstate_funcs.get_scaling = funcs->get_scaling; 2834 pstate_funcs.get_val = funcs->get_val; 2835 pstate_funcs.get_vid = funcs->get_vid; 2836 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 2837 } 2838 2839 #ifdef CONFIG_ACPI 2840 2841 static bool __init intel_pstate_no_acpi_pss(void) 2842 { 2843 int i; 2844 2845 for_each_possible_cpu(i) { 2846 acpi_status status; 2847 union acpi_object *pss; 2848 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2849 struct acpi_processor *pr = per_cpu(processors, i); 2850 2851 if (!pr) 2852 continue; 2853 2854 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 2855 if (ACPI_FAILURE(status)) 2856 continue; 2857 2858 pss = buffer.pointer; 2859 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 2860 kfree(pss); 2861 return false; 2862 } 2863 2864 kfree(pss); 2865 } 2866 2867 pr_debug("ACPI _PSS not found\n"); 2868 return true; 2869 } 2870 2871 static bool __init intel_pstate_no_acpi_pcch(void) 2872 { 2873 acpi_status status; 2874 acpi_handle handle; 2875 2876 status = acpi_get_handle(NULL, "\\_SB", &handle); 2877 if (ACPI_FAILURE(status)) 2878 goto not_found; 2879 2880 if (acpi_has_method(handle, "PCCH")) 2881 return false; 2882 2883 not_found: 2884 pr_debug("ACPI PCCH not found\n"); 2885 return true; 2886 } 2887 2888 static bool __init intel_pstate_has_acpi_ppc(void) 2889 { 2890 int i; 2891 2892 for_each_possible_cpu(i) { 2893 struct acpi_processor *pr = per_cpu(processors, i); 2894 2895 if (!pr) 2896 continue; 2897 if (acpi_has_method(pr->handle, "_PPC")) 2898 return true; 2899 } 2900 pr_debug("ACPI _PPC not found\n"); 2901 return false; 2902 } 2903 2904 enum { 2905 PSS, 2906 PPC, 2907 }; 2908 2909 /* Hardware vendor-specific info that has its own power management modes */ 2910 static struct acpi_platform_list plat_info[] __initdata = { 2911 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 2912 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2913 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2914 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2915 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2916 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2917 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2918 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2919 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2920 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2921 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2922 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2923 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2924 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2925 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2926 { } /* End */ 2927 }; 2928 2929 #define BITMASK_OOB (BIT(8) | BIT(18)) 2930 2931 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 2932 { 2933 const struct x86_cpu_id *id; 2934 u64 misc_pwr; 2935 int idx; 2936 2937 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 2938 if (id) { 2939 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 2940 if (misc_pwr & BITMASK_OOB) { 2941 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 2942 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 2943 return true; 2944 } 2945 } 2946 2947 idx = acpi_match_platform_list(plat_info); 2948 if (idx < 0) 2949 return false; 2950 2951 switch (plat_info[idx].data) { 2952 case PSS: 2953 if (!intel_pstate_no_acpi_pss()) 2954 return false; 2955 2956 return intel_pstate_no_acpi_pcch(); 2957 case PPC: 2958 return intel_pstate_has_acpi_ppc() && !force_load; 2959 } 2960 2961 return false; 2962 } 2963 2964 static void intel_pstate_request_control_from_smm(void) 2965 { 2966 /* 2967 * It may be unsafe to request P-states control from SMM if _PPC support 2968 * has not been enabled. 2969 */ 2970 if (acpi_ppc) 2971 acpi_processor_pstate_control(); 2972 } 2973 #else /* CONFIG_ACPI not enabled */ 2974 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 2975 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 2976 static inline void intel_pstate_request_control_from_smm(void) {} 2977 #endif /* CONFIG_ACPI */ 2978 2979 #define INTEL_PSTATE_HWP_BROADWELL 0x01 2980 2981 #define X86_MATCH_HWP(model, hwp_mode) \ 2982 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2983 X86_FEATURE_HWP, hwp_mode) 2984 2985 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 2986 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 2987 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 2988 X86_MATCH_HWP(ANY, 0), 2989 {} 2990 }; 2991 2992 static int __init intel_pstate_init(void) 2993 { 2994 const struct x86_cpu_id *id; 2995 int rc; 2996 2997 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2998 return -ENODEV; 2999 3000 if (no_load) 3001 return -ENODEV; 3002 3003 id = x86_match_cpu(hwp_support_ids); 3004 if (id) { 3005 copy_cpu_funcs(&core_funcs); 3006 /* 3007 * Avoid enabling HWP for processors without EPP support, 3008 * because that means incomplete HWP implementation which is a 3009 * corner case and supporting it is generally problematic. 3010 */ 3011 if (!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) { 3012 hwp_active++; 3013 hwp_mode_bdw = id->driver_data; 3014 intel_pstate.attr = hwp_cpufreq_attrs; 3015 intel_cpufreq.attr = hwp_cpufreq_attrs; 3016 if (!default_driver) 3017 default_driver = &intel_pstate; 3018 3019 goto hwp_cpu_matched; 3020 } 3021 } else { 3022 id = x86_match_cpu(intel_pstate_cpu_ids); 3023 if (!id) { 3024 pr_info("CPU model not supported\n"); 3025 return -ENODEV; 3026 } 3027 3028 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3029 } 3030 3031 if (intel_pstate_msrs_not_valid()) { 3032 pr_info("Invalid MSRs\n"); 3033 return -ENODEV; 3034 } 3035 /* Without HWP start in the passive mode. */ 3036 if (!default_driver) 3037 default_driver = &intel_cpufreq; 3038 3039 hwp_cpu_matched: 3040 /* 3041 * The Intel pstate driver will be ignored if the platform 3042 * firmware has its own power management modes. 3043 */ 3044 if (intel_pstate_platform_pwr_mgmt_exists()) { 3045 pr_info("P-states controlled by the platform\n"); 3046 return -ENODEV; 3047 } 3048 3049 if (!hwp_active && hwp_only) 3050 return -ENOTSUPP; 3051 3052 pr_info("Intel P-state driver initializing\n"); 3053 3054 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3055 if (!all_cpu_data) 3056 return -ENOMEM; 3057 3058 intel_pstate_request_control_from_smm(); 3059 3060 intel_pstate_sysfs_expose_params(); 3061 3062 mutex_lock(&intel_pstate_driver_lock); 3063 rc = intel_pstate_register_driver(default_driver); 3064 mutex_unlock(&intel_pstate_driver_lock); 3065 if (rc) 3066 return rc; 3067 3068 if (hwp_active) { 3069 const struct x86_cpu_id *id; 3070 3071 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3072 if (id) { 3073 set_power_ctl_ee_state(false); 3074 pr_info("Disabling energy efficiency optimization\n"); 3075 } 3076 3077 pr_info("HWP enabled\n"); 3078 } 3079 3080 return 0; 3081 } 3082 device_initcall(intel_pstate_init); 3083 3084 static int __init intel_pstate_setup(char *str) 3085 { 3086 if (!str) 3087 return -EINVAL; 3088 3089 if (!strcmp(str, "disable")) 3090 no_load = 1; 3091 else if (!strcmp(str, "active")) 3092 default_driver = &intel_pstate; 3093 else if (!strcmp(str, "passive")) 3094 default_driver = &intel_cpufreq; 3095 3096 if (!strcmp(str, "no_hwp")) { 3097 pr_info("HWP disabled\n"); 3098 no_hwp = 1; 3099 } 3100 if (!strcmp(str, "force")) 3101 force_load = 1; 3102 if (!strcmp(str, "hwp_only")) 3103 hwp_only = 1; 3104 if (!strcmp(str, "per_cpu_perf_limits")) 3105 per_cpu_limits = true; 3106 3107 #ifdef CONFIG_ACPI 3108 if (!strcmp(str, "support_acpi_ppc")) 3109 acpi_ppc = true; 3110 #endif 3111 3112 return 0; 3113 } 3114 early_param("intel_pstate", intel_pstate_setup); 3115 3116 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3117 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3118 MODULE_LICENSE("GPL"); 3119