1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/div64.h> 31 #include <asm/msr.h> 32 #include <asm/cpu_device_id.h> 33 #include <asm/cpufeature.h> 34 #include <asm/intel-family.h> 35 #include "../drivers/thermal/intel/thermal_interrupt.h" 36 37 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 38 39 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 40 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 41 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 42 43 #ifdef CONFIG_ACPI 44 #include <acpi/processor.h> 45 #include <acpi/cppc_acpi.h> 46 #endif 47 48 #define FRAC_BITS 8 49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 50 #define fp_toint(X) ((X) >> FRAC_BITS) 51 52 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 53 54 #define EXT_BITS 6 55 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 56 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 57 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 58 59 static inline int32_t mul_fp(int32_t x, int32_t y) 60 { 61 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 62 } 63 64 static inline int32_t div_fp(s64 x, s64 y) 65 { 66 return div64_s64((int64_t)x << FRAC_BITS, y); 67 } 68 69 static inline int ceiling_fp(int32_t x) 70 { 71 int mask, ret; 72 73 ret = fp_toint(x); 74 mask = (1 << FRAC_BITS) - 1; 75 if (x & mask) 76 ret += 1; 77 return ret; 78 } 79 80 static inline u64 mul_ext_fp(u64 x, u64 y) 81 { 82 return (x * y) >> EXT_FRAC_BITS; 83 } 84 85 static inline u64 div_ext_fp(u64 x, u64 y) 86 { 87 return div64_u64(x << EXT_FRAC_BITS, y); 88 } 89 90 /** 91 * struct sample - Store performance sample 92 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 93 * performance during last sample period 94 * @busy_scaled: Scaled busy value which is used to calculate next 95 * P state. This can be different than core_avg_perf 96 * to account for cpu idle period 97 * @aperf: Difference of actual performance frequency clock count 98 * read from APERF MSR between last and current sample 99 * @mperf: Difference of maximum performance frequency clock count 100 * read from MPERF MSR between last and current sample 101 * @tsc: Difference of time stamp counter between last and 102 * current sample 103 * @time: Current time from scheduler 104 * 105 * This structure is used in the cpudata structure to store performance sample 106 * data for choosing next P State. 107 */ 108 struct sample { 109 int32_t core_avg_perf; 110 int32_t busy_scaled; 111 u64 aperf; 112 u64 mperf; 113 u64 tsc; 114 u64 time; 115 }; 116 117 /** 118 * struct pstate_data - Store P state data 119 * @current_pstate: Current requested P state 120 * @min_pstate: Min P state possible for this platform 121 * @max_pstate: Max P state possible for this platform 122 * @max_pstate_physical:This is physical Max P state for a processor 123 * This can be higher than the max_pstate which can 124 * be limited by platform thermal design power limits 125 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 126 * @scaling: Scaling factor between performance and frequency 127 * @turbo_pstate: Max Turbo P state possible for this platform 128 * @min_freq: @min_pstate frequency in cpufreq units 129 * @max_freq: @max_pstate frequency in cpufreq units 130 * @turbo_freq: @turbo_pstate frequency in cpufreq units 131 * 132 * Stores the per cpu model P state limits and current P state. 133 */ 134 struct pstate_data { 135 int current_pstate; 136 int min_pstate; 137 int max_pstate; 138 int max_pstate_physical; 139 int perf_ctl_scaling; 140 int scaling; 141 int turbo_pstate; 142 unsigned int min_freq; 143 unsigned int max_freq; 144 unsigned int turbo_freq; 145 }; 146 147 /** 148 * struct vid_data - Stores voltage information data 149 * @min: VID data for this platform corresponding to 150 * the lowest P state 151 * @max: VID data corresponding to the highest P State. 152 * @turbo: VID data for turbo P state 153 * @ratio: Ratio of (vid max - vid min) / 154 * (max P state - Min P State) 155 * 156 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 157 * This data is used in Atom platforms, where in addition to target P state, 158 * the voltage data needs to be specified to select next P State. 159 */ 160 struct vid_data { 161 int min; 162 int max; 163 int turbo; 164 int32_t ratio; 165 }; 166 167 /** 168 * struct global_params - Global parameters, mostly tunable via sysfs. 169 * @no_turbo: Whether or not to use turbo P-states. 170 * @turbo_disabled: Whether or not turbo P-states are available at all, 171 * based on the MSR_IA32_MISC_ENABLE value and whether or 172 * not the maximum reported turbo P-state is different from 173 * the maximum reported non-turbo one. 174 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 175 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 176 * P-state capacity. 177 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 178 * P-state capacity. 179 */ 180 struct global_params { 181 bool no_turbo; 182 bool turbo_disabled; 183 bool turbo_disabled_mf; 184 int max_perf_pct; 185 int min_perf_pct; 186 }; 187 188 /** 189 * struct cpudata - Per CPU instance data storage 190 * @cpu: CPU number for this instance data 191 * @policy: CPUFreq policy value 192 * @update_util: CPUFreq utility callback information 193 * @update_util_set: CPUFreq utility callback is set 194 * @iowait_boost: iowait-related boost fraction 195 * @last_update: Time of the last update. 196 * @pstate: Stores P state limits for this CPU 197 * @vid: Stores VID limits for this CPU 198 * @last_sample_time: Last Sample time 199 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 200 * @prev_aperf: Last APERF value read from APERF MSR 201 * @prev_mperf: Last MPERF value read from MPERF MSR 202 * @prev_tsc: Last timestamp counter (TSC) value 203 * @prev_cummulative_iowait: IO Wait time difference from last and 204 * current sample 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @sched_flags: Store scheduler flags for possible cross CPU update 221 * @hwp_boost_min: Last HWP boosted min performance 222 * @suspended: Whether or not the driver has been suspended. 223 * @hwp_notify_work: workqueue for HWP notifications. 224 * 225 * This structure stores per CPU instance data for all CPUs. 226 */ 227 struct cpudata { 228 int cpu; 229 230 unsigned int policy; 231 struct update_util_data update_util; 232 bool update_util_set; 233 234 struct pstate_data pstate; 235 struct vid_data vid; 236 237 u64 last_update; 238 u64 last_sample_time; 239 u64 aperf_mperf_shift; 240 u64 prev_aperf; 241 u64 prev_mperf; 242 u64 prev_tsc; 243 u64 prev_cummulative_iowait; 244 struct sample sample; 245 int32_t min_perf_ratio; 246 int32_t max_perf_ratio; 247 #ifdef CONFIG_ACPI 248 struct acpi_processor_performance acpi_perf_data; 249 bool valid_pss_table; 250 #endif 251 unsigned int iowait_boost; 252 s16 epp_powersave; 253 s16 epp_policy; 254 s16 epp_default; 255 s16 epp_cached; 256 u64 hwp_req_cached; 257 u64 hwp_cap_cached; 258 u64 last_io_update; 259 unsigned int sched_flags; 260 u32 hwp_boost_min; 261 bool suspended; 262 struct delayed_work hwp_notify_work; 263 }; 264 265 static struct cpudata **all_cpu_data; 266 267 /** 268 * struct pstate_funcs - Per CPU model specific callbacks 269 * @get_max: Callback to get maximum non turbo effective P state 270 * @get_max_physical: Callback to get maximum non turbo physical P state 271 * @get_min: Callback to get minimum P state 272 * @get_turbo: Callback to get turbo P state 273 * @get_scaling: Callback to get frequency scaling factor 274 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 275 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 276 * @get_val: Callback to convert P state to actual MSR write value 277 * @get_vid: Callback to get VID data for Atom platforms 278 * 279 * Core and Atom CPU models have different way to get P State limits. This 280 * structure is used to store those callbacks. 281 */ 282 struct pstate_funcs { 283 int (*get_max)(void); 284 int (*get_max_physical)(void); 285 int (*get_min)(void); 286 int (*get_turbo)(void); 287 int (*get_scaling)(void); 288 int (*get_cpu_scaling)(int cpu); 289 int (*get_aperf_mperf_shift)(void); 290 u64 (*get_val)(struct cpudata*, int pstate); 291 void (*get_vid)(struct cpudata *); 292 }; 293 294 static struct pstate_funcs pstate_funcs __read_mostly; 295 296 static int hwp_active __read_mostly; 297 static int hwp_mode_bdw __read_mostly; 298 static bool per_cpu_limits __read_mostly; 299 static bool hwp_boost __read_mostly; 300 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 302 303 #ifdef CONFIG_ACPI 304 static bool acpi_ppc; 305 #endif 306 307 static struct global_params global; 308 309 static DEFINE_MUTEX(intel_pstate_driver_lock); 310 static DEFINE_MUTEX(intel_pstate_limits_lock); 311 312 #ifdef CONFIG_ACPI 313 314 static bool intel_pstate_acpi_pm_profile_server(void) 315 { 316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 318 return true; 319 320 return false; 321 } 322 323 static bool intel_pstate_get_ppc_enable_status(void) 324 { 325 if (intel_pstate_acpi_pm_profile_server()) 326 return true; 327 328 return acpi_ppc; 329 } 330 331 #ifdef CONFIG_ACPI_CPPC_LIB 332 333 /* The work item is needed to avoid CPU hotplug locking issues */ 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 335 { 336 sched_set_itmt_support(); 337 } 338 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 340 341 #define CPPC_MAX_PERF U8_MAX 342 343 static void intel_pstate_set_itmt_prio(int cpu) 344 { 345 struct cppc_perf_caps cppc_perf; 346 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 347 int ret; 348 349 ret = cppc_get_perf_caps(cpu, &cppc_perf); 350 if (ret) 351 return; 352 353 /* 354 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. 355 * In this case we can't use CPPC.highest_perf to enable ITMT. 356 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. 357 */ 358 if (cppc_perf.highest_perf == CPPC_MAX_PERF) 359 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 360 361 /* 362 * The priorities can be set regardless of whether or not 363 * sched_set_itmt_support(true) has been called and it is valid to 364 * update them at any time after it has been called. 365 */ 366 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 367 368 if (max_highest_perf <= min_highest_perf) { 369 if (cppc_perf.highest_perf > max_highest_perf) 370 max_highest_perf = cppc_perf.highest_perf; 371 372 if (cppc_perf.highest_perf < min_highest_perf) 373 min_highest_perf = cppc_perf.highest_perf; 374 375 if (max_highest_perf > min_highest_perf) { 376 /* 377 * This code can be run during CPU online under the 378 * CPU hotplug locks, so sched_set_itmt_support() 379 * cannot be called from here. Queue up a work item 380 * to invoke it. 381 */ 382 schedule_work(&sched_itmt_work); 383 } 384 } 385 } 386 387 static int intel_pstate_get_cppc_guaranteed(int cpu) 388 { 389 struct cppc_perf_caps cppc_perf; 390 int ret; 391 392 ret = cppc_get_perf_caps(cpu, &cppc_perf); 393 if (ret) 394 return ret; 395 396 if (cppc_perf.guaranteed_perf) 397 return cppc_perf.guaranteed_perf; 398 399 return cppc_perf.nominal_perf; 400 } 401 402 static u32 intel_pstate_cppc_nominal(int cpu) 403 { 404 u64 nominal_perf; 405 406 if (cppc_get_nominal_perf(cpu, &nominal_perf)) 407 return 0; 408 409 return nominal_perf; 410 } 411 #else /* CONFIG_ACPI_CPPC_LIB */ 412 static inline void intel_pstate_set_itmt_prio(int cpu) 413 { 414 } 415 #endif /* CONFIG_ACPI_CPPC_LIB */ 416 417 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 418 { 419 struct cpudata *cpu; 420 int ret; 421 int i; 422 423 if (hwp_active) { 424 intel_pstate_set_itmt_prio(policy->cpu); 425 return; 426 } 427 428 if (!intel_pstate_get_ppc_enable_status()) 429 return; 430 431 cpu = all_cpu_data[policy->cpu]; 432 433 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 434 policy->cpu); 435 if (ret) 436 return; 437 438 /* 439 * Check if the control value in _PSS is for PERF_CTL MSR, which should 440 * guarantee that the states returned by it map to the states in our 441 * list directly. 442 */ 443 if (cpu->acpi_perf_data.control_register.space_id != 444 ACPI_ADR_SPACE_FIXED_HARDWARE) 445 goto err; 446 447 /* 448 * If there is only one entry _PSS, simply ignore _PSS and continue as 449 * usual without taking _PSS into account 450 */ 451 if (cpu->acpi_perf_data.state_count < 2) 452 goto err; 453 454 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 455 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 456 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 457 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 458 (u32) cpu->acpi_perf_data.states[i].core_frequency, 459 (u32) cpu->acpi_perf_data.states[i].power, 460 (u32) cpu->acpi_perf_data.states[i].control); 461 } 462 463 /* 464 * The _PSS table doesn't contain whole turbo frequency range. 465 * This just contains +1 MHZ above the max non turbo frequency, 466 * with control value corresponding to max turbo ratio. But 467 * when cpufreq set policy is called, it will call with this 468 * max frequency, which will cause a reduced performance as 469 * this driver uses real max turbo frequency as the max 470 * frequency. So correct this frequency in _PSS table to 471 * correct max turbo frequency based on the turbo state. 472 * Also need to convert to MHz as _PSS freq is in MHz. 473 */ 474 if (!global.turbo_disabled) 475 cpu->acpi_perf_data.states[0].core_frequency = 476 policy->cpuinfo.max_freq / 1000; 477 cpu->valid_pss_table = true; 478 pr_debug("_PPC limits will be enforced\n"); 479 480 return; 481 482 err: 483 cpu->valid_pss_table = false; 484 acpi_processor_unregister_performance(policy->cpu); 485 } 486 487 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 488 { 489 struct cpudata *cpu; 490 491 cpu = all_cpu_data[policy->cpu]; 492 if (!cpu->valid_pss_table) 493 return; 494 495 acpi_processor_unregister_performance(policy->cpu); 496 } 497 #else /* CONFIG_ACPI */ 498 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 499 { 500 } 501 502 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 503 { 504 } 505 506 static inline bool intel_pstate_acpi_pm_profile_server(void) 507 { 508 return false; 509 } 510 #endif /* CONFIG_ACPI */ 511 512 #ifndef CONFIG_ACPI_CPPC_LIB 513 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 514 { 515 return -ENOTSUPP; 516 } 517 #endif /* CONFIG_ACPI_CPPC_LIB */ 518 519 /** 520 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 521 * @cpu: Target CPU. 522 * 523 * On hybrid processors, HWP may expose more performance levels than there are 524 * P-states accessible through the PERF_CTL interface. If that happens, the 525 * scaling factor between HWP performance levels and CPU frequency will be less 526 * than the scaling factor between P-state values and CPU frequency. 527 * 528 * In that case, adjust the CPU parameters used in computations accordingly. 529 */ 530 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 531 { 532 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 533 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 534 int perf_ctl_turbo = pstate_funcs.get_turbo(); 535 int turbo_freq = perf_ctl_turbo * perf_ctl_scaling; 536 int scaling = cpu->pstate.scaling; 537 538 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 539 pr_debug("CPU%d: perf_ctl_max = %d\n", cpu->cpu, pstate_funcs.get_max()); 540 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 541 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 542 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 543 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 544 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 545 546 /* 547 * If the product of the HWP performance scaling factor and the HWP_CAP 548 * highest performance is greater than the maximum turbo frequency 549 * corresponding to the pstate_funcs.get_turbo() return value, the 550 * scaling factor is too high, so recompute it to make the HWP_CAP 551 * highest performance correspond to the maximum turbo frequency. 552 */ 553 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 554 if (turbo_freq < cpu->pstate.turbo_freq) { 555 cpu->pstate.turbo_freq = turbo_freq; 556 scaling = DIV_ROUND_UP(turbo_freq, cpu->pstate.turbo_pstate); 557 cpu->pstate.scaling = scaling; 558 559 pr_debug("CPU%d: refined HWP-to-frequency scaling factor: %d\n", 560 cpu->cpu, scaling); 561 } 562 563 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 564 perf_ctl_scaling); 565 566 cpu->pstate.max_pstate_physical = 567 DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling, 568 scaling); 569 570 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 571 /* 572 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 573 * the effective range of HWP performance levels. 574 */ 575 cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling); 576 } 577 578 static inline void update_turbo_state(void) 579 { 580 u64 misc_en; 581 struct cpudata *cpu; 582 583 cpu = all_cpu_data[0]; 584 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 585 global.turbo_disabled = 586 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 587 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 588 } 589 590 static int min_perf_pct_min(void) 591 { 592 struct cpudata *cpu = all_cpu_data[0]; 593 int turbo_pstate = cpu->pstate.turbo_pstate; 594 595 return turbo_pstate ? 596 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 597 } 598 599 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 600 { 601 u64 epb; 602 int ret; 603 604 if (!boot_cpu_has(X86_FEATURE_EPB)) 605 return -ENXIO; 606 607 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 608 if (ret) 609 return (s16)ret; 610 611 return (s16)(epb & 0x0f); 612 } 613 614 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 615 { 616 s16 epp; 617 618 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 619 /* 620 * When hwp_req_data is 0, means that caller didn't read 621 * MSR_HWP_REQUEST, so need to read and get EPP. 622 */ 623 if (!hwp_req_data) { 624 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 625 &hwp_req_data); 626 if (epp) 627 return epp; 628 } 629 epp = (hwp_req_data >> 24) & 0xff; 630 } else { 631 /* When there is no EPP present, HWP uses EPB settings */ 632 epp = intel_pstate_get_epb(cpu_data); 633 } 634 635 return epp; 636 } 637 638 static int intel_pstate_set_epb(int cpu, s16 pref) 639 { 640 u64 epb; 641 int ret; 642 643 if (!boot_cpu_has(X86_FEATURE_EPB)) 644 return -ENXIO; 645 646 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 647 if (ret) 648 return ret; 649 650 epb = (epb & ~0x0f) | pref; 651 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 652 653 return 0; 654 } 655 656 /* 657 * EPP/EPB display strings corresponding to EPP index in the 658 * energy_perf_strings[] 659 * index String 660 *------------------------------------- 661 * 0 default 662 * 1 performance 663 * 2 balance_performance 664 * 3 balance_power 665 * 4 power 666 */ 667 static const char * const energy_perf_strings[] = { 668 "default", 669 "performance", 670 "balance_performance", 671 "balance_power", 672 "power", 673 NULL 674 }; 675 static const unsigned int epp_values[] = { 676 HWP_EPP_PERFORMANCE, 677 HWP_EPP_BALANCE_PERFORMANCE, 678 HWP_EPP_BALANCE_POWERSAVE, 679 HWP_EPP_POWERSAVE 680 }; 681 682 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 683 { 684 s16 epp; 685 int index = -EINVAL; 686 687 *raw_epp = 0; 688 epp = intel_pstate_get_epp(cpu_data, 0); 689 if (epp < 0) 690 return epp; 691 692 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 693 if (epp == HWP_EPP_PERFORMANCE) 694 return 1; 695 if (epp == HWP_EPP_BALANCE_PERFORMANCE) 696 return 2; 697 if (epp == HWP_EPP_BALANCE_POWERSAVE) 698 return 3; 699 if (epp == HWP_EPP_POWERSAVE) 700 return 4; 701 *raw_epp = epp; 702 return 0; 703 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 704 /* 705 * Range: 706 * 0x00-0x03 : Performance 707 * 0x04-0x07 : Balance performance 708 * 0x08-0x0B : Balance power 709 * 0x0C-0x0F : Power 710 * The EPB is a 4 bit value, but our ranges restrict the 711 * value which can be set. Here only using top two bits 712 * effectively. 713 */ 714 index = (epp >> 2) + 1; 715 } 716 717 return index; 718 } 719 720 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 721 { 722 int ret; 723 724 /* 725 * Use the cached HWP Request MSR value, because in the active mode the 726 * register itself may be updated by intel_pstate_hwp_boost_up() or 727 * intel_pstate_hwp_boost_down() at any time. 728 */ 729 u64 value = READ_ONCE(cpu->hwp_req_cached); 730 731 value &= ~GENMASK_ULL(31, 24); 732 value |= (u64)epp << 24; 733 /* 734 * The only other updater of hwp_req_cached in the active mode, 735 * intel_pstate_hwp_set(), is called under the same lock as this 736 * function, so it cannot run in parallel with the update below. 737 */ 738 WRITE_ONCE(cpu->hwp_req_cached, value); 739 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 740 if (!ret) 741 cpu->epp_cached = epp; 742 743 return ret; 744 } 745 746 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 747 int pref_index, bool use_raw, 748 u32 raw_epp) 749 { 750 int epp = -EINVAL; 751 int ret; 752 753 if (!pref_index) 754 epp = cpu_data->epp_default; 755 756 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 757 if (use_raw) 758 epp = raw_epp; 759 else if (epp == -EINVAL) 760 epp = epp_values[pref_index - 1]; 761 762 /* 763 * To avoid confusion, refuse to set EPP to any values different 764 * from 0 (performance) if the current policy is "performance", 765 * because those values would be overridden. 766 */ 767 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 768 return -EBUSY; 769 770 ret = intel_pstate_set_epp(cpu_data, epp); 771 } else { 772 if (epp == -EINVAL) 773 epp = (pref_index - 1) << 2; 774 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 775 } 776 777 return ret; 778 } 779 780 static ssize_t show_energy_performance_available_preferences( 781 struct cpufreq_policy *policy, char *buf) 782 { 783 int i = 0; 784 int ret = 0; 785 786 while (energy_perf_strings[i] != NULL) 787 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 788 789 ret += sprintf(&buf[ret], "\n"); 790 791 return ret; 792 } 793 794 cpufreq_freq_attr_ro(energy_performance_available_preferences); 795 796 static struct cpufreq_driver intel_pstate; 797 798 static ssize_t store_energy_performance_preference( 799 struct cpufreq_policy *policy, const char *buf, size_t count) 800 { 801 struct cpudata *cpu = all_cpu_data[policy->cpu]; 802 char str_preference[21]; 803 bool raw = false; 804 ssize_t ret; 805 u32 epp = 0; 806 807 ret = sscanf(buf, "%20s", str_preference); 808 if (ret != 1) 809 return -EINVAL; 810 811 ret = match_string(energy_perf_strings, -1, str_preference); 812 if (ret < 0) { 813 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 814 return ret; 815 816 ret = kstrtouint(buf, 10, &epp); 817 if (ret) 818 return ret; 819 820 if (epp > 255) 821 return -EINVAL; 822 823 raw = true; 824 } 825 826 /* 827 * This function runs with the policy R/W semaphore held, which 828 * guarantees that the driver pointer will not change while it is 829 * running. 830 */ 831 if (!intel_pstate_driver) 832 return -EAGAIN; 833 834 mutex_lock(&intel_pstate_limits_lock); 835 836 if (intel_pstate_driver == &intel_pstate) { 837 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 838 } else { 839 /* 840 * In the passive mode the governor needs to be stopped on the 841 * target CPU before the EPP update and restarted after it, 842 * which is super-heavy-weight, so make sure it is worth doing 843 * upfront. 844 */ 845 if (!raw) 846 epp = ret ? epp_values[ret - 1] : cpu->epp_default; 847 848 if (cpu->epp_cached != epp) { 849 int err; 850 851 cpufreq_stop_governor(policy); 852 ret = intel_pstate_set_epp(cpu, epp); 853 err = cpufreq_start_governor(policy); 854 if (!ret) 855 ret = err; 856 } 857 } 858 859 mutex_unlock(&intel_pstate_limits_lock); 860 861 return ret ?: count; 862 } 863 864 static ssize_t show_energy_performance_preference( 865 struct cpufreq_policy *policy, char *buf) 866 { 867 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 868 int preference, raw_epp; 869 870 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 871 if (preference < 0) 872 return preference; 873 874 if (raw_epp) 875 return sprintf(buf, "%d\n", raw_epp); 876 else 877 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 878 } 879 880 cpufreq_freq_attr_rw(energy_performance_preference); 881 882 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 883 { 884 struct cpudata *cpu = all_cpu_data[policy->cpu]; 885 int ratio, freq; 886 887 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 888 if (ratio <= 0) { 889 u64 cap; 890 891 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 892 ratio = HWP_GUARANTEED_PERF(cap); 893 } 894 895 freq = ratio * cpu->pstate.scaling; 896 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 897 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 898 899 return sprintf(buf, "%d\n", freq); 900 } 901 902 cpufreq_freq_attr_ro(base_frequency); 903 904 static struct freq_attr *hwp_cpufreq_attrs[] = { 905 &energy_performance_preference, 906 &energy_performance_available_preferences, 907 &base_frequency, 908 NULL, 909 }; 910 911 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 912 { 913 u64 cap; 914 915 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 916 WRITE_ONCE(cpu->hwp_cap_cached, cap); 917 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 918 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 919 } 920 921 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 922 { 923 int scaling = cpu->pstate.scaling; 924 925 __intel_pstate_get_hwp_cap(cpu); 926 927 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 928 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 929 if (scaling != cpu->pstate.perf_ctl_scaling) { 930 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 931 932 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 933 perf_ctl_scaling); 934 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 935 perf_ctl_scaling); 936 } 937 } 938 939 static void intel_pstate_hwp_set(unsigned int cpu) 940 { 941 struct cpudata *cpu_data = all_cpu_data[cpu]; 942 int max, min; 943 u64 value; 944 s16 epp; 945 946 max = cpu_data->max_perf_ratio; 947 min = cpu_data->min_perf_ratio; 948 949 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 950 min = max; 951 952 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 953 954 value &= ~HWP_MIN_PERF(~0L); 955 value |= HWP_MIN_PERF(min); 956 957 value &= ~HWP_MAX_PERF(~0L); 958 value |= HWP_MAX_PERF(max); 959 960 if (cpu_data->epp_policy == cpu_data->policy) 961 goto skip_epp; 962 963 cpu_data->epp_policy = cpu_data->policy; 964 965 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 966 epp = intel_pstate_get_epp(cpu_data, value); 967 cpu_data->epp_powersave = epp; 968 /* If EPP read was failed, then don't try to write */ 969 if (epp < 0) 970 goto skip_epp; 971 972 epp = 0; 973 } else { 974 /* skip setting EPP, when saved value is invalid */ 975 if (cpu_data->epp_powersave < 0) 976 goto skip_epp; 977 978 /* 979 * No need to restore EPP when it is not zero. This 980 * means: 981 * - Policy is not changed 982 * - user has manually changed 983 * - Error reading EPB 984 */ 985 epp = intel_pstate_get_epp(cpu_data, value); 986 if (epp) 987 goto skip_epp; 988 989 epp = cpu_data->epp_powersave; 990 } 991 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 992 value &= ~GENMASK_ULL(31, 24); 993 value |= (u64)epp << 24; 994 } else { 995 intel_pstate_set_epb(cpu, epp); 996 } 997 skip_epp: 998 WRITE_ONCE(cpu_data->hwp_req_cached, value); 999 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1000 } 1001 1002 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1003 1004 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1005 { 1006 u64 value = READ_ONCE(cpu->hwp_req_cached); 1007 int min_perf; 1008 1009 intel_pstate_disable_hwp_interrupt(cpu); 1010 1011 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1012 /* 1013 * In case the EPP has been set to "performance" by the 1014 * active mode "performance" scaling algorithm, replace that 1015 * temporary value with the cached EPP one. 1016 */ 1017 value &= ~GENMASK_ULL(31, 24); 1018 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1019 /* 1020 * However, make sure that EPP will be set to "performance" when 1021 * the CPU is brought back online again and the "performance" 1022 * scaling algorithm is still in effect. 1023 */ 1024 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1025 } 1026 1027 /* 1028 * Clear the desired perf field in the cached HWP request value to 1029 * prevent nonzero desired values from being leaked into the active 1030 * mode. 1031 */ 1032 value &= ~HWP_DESIRED_PERF(~0L); 1033 WRITE_ONCE(cpu->hwp_req_cached, value); 1034 1035 value &= ~GENMASK_ULL(31, 0); 1036 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1037 1038 /* Set hwp_max = hwp_min */ 1039 value |= HWP_MAX_PERF(min_perf); 1040 value |= HWP_MIN_PERF(min_perf); 1041 1042 /* Set EPP to min */ 1043 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1044 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1045 1046 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1047 } 1048 1049 #define POWER_CTL_EE_ENABLE 1 1050 #define POWER_CTL_EE_DISABLE 2 1051 1052 static int power_ctl_ee_state; 1053 1054 static void set_power_ctl_ee_state(bool input) 1055 { 1056 u64 power_ctl; 1057 1058 mutex_lock(&intel_pstate_driver_lock); 1059 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1060 if (input) { 1061 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1062 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1063 } else { 1064 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1065 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1066 } 1067 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1068 mutex_unlock(&intel_pstate_driver_lock); 1069 } 1070 1071 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1072 1073 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1074 { 1075 intel_pstate_hwp_enable(cpu); 1076 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1077 } 1078 1079 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1080 { 1081 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1082 1083 pr_debug("CPU %d suspending\n", cpu->cpu); 1084 1085 cpu->suspended = true; 1086 1087 /* disable HWP interrupt and cancel any pending work */ 1088 intel_pstate_disable_hwp_interrupt(cpu); 1089 1090 return 0; 1091 } 1092 1093 static int intel_pstate_resume(struct cpufreq_policy *policy) 1094 { 1095 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1096 1097 pr_debug("CPU %d resuming\n", cpu->cpu); 1098 1099 /* Only restore if the system default is changed */ 1100 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1101 set_power_ctl_ee_state(true); 1102 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1103 set_power_ctl_ee_state(false); 1104 1105 if (cpu->suspended && hwp_active) { 1106 mutex_lock(&intel_pstate_limits_lock); 1107 1108 /* Re-enable HWP, because "online" has not done that. */ 1109 intel_pstate_hwp_reenable(cpu); 1110 1111 mutex_unlock(&intel_pstate_limits_lock); 1112 } 1113 1114 cpu->suspended = false; 1115 1116 return 0; 1117 } 1118 1119 static void intel_pstate_update_policies(void) 1120 { 1121 int cpu; 1122 1123 for_each_possible_cpu(cpu) 1124 cpufreq_update_policy(cpu); 1125 } 1126 1127 static void intel_pstate_update_max_freq(unsigned int cpu) 1128 { 1129 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1130 struct cpudata *cpudata; 1131 1132 if (!policy) 1133 return; 1134 1135 cpudata = all_cpu_data[cpu]; 1136 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 1137 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1138 1139 refresh_frequency_limits(policy); 1140 1141 cpufreq_cpu_release(policy); 1142 } 1143 1144 static void intel_pstate_update_limits(unsigned int cpu) 1145 { 1146 mutex_lock(&intel_pstate_driver_lock); 1147 1148 update_turbo_state(); 1149 /* 1150 * If turbo has been turned on or off globally, policy limits for 1151 * all CPUs need to be updated to reflect that. 1152 */ 1153 if (global.turbo_disabled_mf != global.turbo_disabled) { 1154 global.turbo_disabled_mf = global.turbo_disabled; 1155 arch_set_max_freq_ratio(global.turbo_disabled); 1156 for_each_possible_cpu(cpu) 1157 intel_pstate_update_max_freq(cpu); 1158 } else { 1159 cpufreq_update_policy(cpu); 1160 } 1161 1162 mutex_unlock(&intel_pstate_driver_lock); 1163 } 1164 1165 /************************** sysfs begin ************************/ 1166 #define show_one(file_name, object) \ 1167 static ssize_t show_##file_name \ 1168 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1169 { \ 1170 return sprintf(buf, "%u\n", global.object); \ 1171 } 1172 1173 static ssize_t intel_pstate_show_status(char *buf); 1174 static int intel_pstate_update_status(const char *buf, size_t size); 1175 1176 static ssize_t show_status(struct kobject *kobj, 1177 struct kobj_attribute *attr, char *buf) 1178 { 1179 ssize_t ret; 1180 1181 mutex_lock(&intel_pstate_driver_lock); 1182 ret = intel_pstate_show_status(buf); 1183 mutex_unlock(&intel_pstate_driver_lock); 1184 1185 return ret; 1186 } 1187 1188 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1189 const char *buf, size_t count) 1190 { 1191 char *p = memchr(buf, '\n', count); 1192 int ret; 1193 1194 mutex_lock(&intel_pstate_driver_lock); 1195 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1196 mutex_unlock(&intel_pstate_driver_lock); 1197 1198 return ret < 0 ? ret : count; 1199 } 1200 1201 static ssize_t show_turbo_pct(struct kobject *kobj, 1202 struct kobj_attribute *attr, char *buf) 1203 { 1204 struct cpudata *cpu; 1205 int total, no_turbo, turbo_pct; 1206 uint32_t turbo_fp; 1207 1208 mutex_lock(&intel_pstate_driver_lock); 1209 1210 if (!intel_pstate_driver) { 1211 mutex_unlock(&intel_pstate_driver_lock); 1212 return -EAGAIN; 1213 } 1214 1215 cpu = all_cpu_data[0]; 1216 1217 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1218 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1219 turbo_fp = div_fp(no_turbo, total); 1220 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1221 1222 mutex_unlock(&intel_pstate_driver_lock); 1223 1224 return sprintf(buf, "%u\n", turbo_pct); 1225 } 1226 1227 static ssize_t show_num_pstates(struct kobject *kobj, 1228 struct kobj_attribute *attr, char *buf) 1229 { 1230 struct cpudata *cpu; 1231 int total; 1232 1233 mutex_lock(&intel_pstate_driver_lock); 1234 1235 if (!intel_pstate_driver) { 1236 mutex_unlock(&intel_pstate_driver_lock); 1237 return -EAGAIN; 1238 } 1239 1240 cpu = all_cpu_data[0]; 1241 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1242 1243 mutex_unlock(&intel_pstate_driver_lock); 1244 1245 return sprintf(buf, "%u\n", total); 1246 } 1247 1248 static ssize_t show_no_turbo(struct kobject *kobj, 1249 struct kobj_attribute *attr, char *buf) 1250 { 1251 ssize_t ret; 1252 1253 mutex_lock(&intel_pstate_driver_lock); 1254 1255 if (!intel_pstate_driver) { 1256 mutex_unlock(&intel_pstate_driver_lock); 1257 return -EAGAIN; 1258 } 1259 1260 update_turbo_state(); 1261 if (global.turbo_disabled) 1262 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1263 else 1264 ret = sprintf(buf, "%u\n", global.no_turbo); 1265 1266 mutex_unlock(&intel_pstate_driver_lock); 1267 1268 return ret; 1269 } 1270 1271 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1272 const char *buf, size_t count) 1273 { 1274 unsigned int input; 1275 int ret; 1276 1277 ret = sscanf(buf, "%u", &input); 1278 if (ret != 1) 1279 return -EINVAL; 1280 1281 mutex_lock(&intel_pstate_driver_lock); 1282 1283 if (!intel_pstate_driver) { 1284 mutex_unlock(&intel_pstate_driver_lock); 1285 return -EAGAIN; 1286 } 1287 1288 mutex_lock(&intel_pstate_limits_lock); 1289 1290 update_turbo_state(); 1291 if (global.turbo_disabled) { 1292 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1293 mutex_unlock(&intel_pstate_limits_lock); 1294 mutex_unlock(&intel_pstate_driver_lock); 1295 return -EPERM; 1296 } 1297 1298 global.no_turbo = clamp_t(int, input, 0, 1); 1299 1300 if (global.no_turbo) { 1301 struct cpudata *cpu = all_cpu_data[0]; 1302 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1303 1304 /* Squash the global minimum into the permitted range. */ 1305 if (global.min_perf_pct > pct) 1306 global.min_perf_pct = pct; 1307 } 1308 1309 mutex_unlock(&intel_pstate_limits_lock); 1310 1311 intel_pstate_update_policies(); 1312 1313 mutex_unlock(&intel_pstate_driver_lock); 1314 1315 return count; 1316 } 1317 1318 static void update_qos_request(enum freq_qos_req_type type) 1319 { 1320 struct freq_qos_request *req; 1321 struct cpufreq_policy *policy; 1322 int i; 1323 1324 for_each_possible_cpu(i) { 1325 struct cpudata *cpu = all_cpu_data[i]; 1326 unsigned int freq, perf_pct; 1327 1328 policy = cpufreq_cpu_get(i); 1329 if (!policy) 1330 continue; 1331 1332 req = policy->driver_data; 1333 cpufreq_cpu_put(policy); 1334 1335 if (!req) 1336 continue; 1337 1338 if (hwp_active) 1339 intel_pstate_get_hwp_cap(cpu); 1340 1341 if (type == FREQ_QOS_MIN) { 1342 perf_pct = global.min_perf_pct; 1343 } else { 1344 req++; 1345 perf_pct = global.max_perf_pct; 1346 } 1347 1348 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1349 1350 if (freq_qos_update_request(req, freq) < 0) 1351 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1352 } 1353 } 1354 1355 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1356 const char *buf, size_t count) 1357 { 1358 unsigned int input; 1359 int ret; 1360 1361 ret = sscanf(buf, "%u", &input); 1362 if (ret != 1) 1363 return -EINVAL; 1364 1365 mutex_lock(&intel_pstate_driver_lock); 1366 1367 if (!intel_pstate_driver) { 1368 mutex_unlock(&intel_pstate_driver_lock); 1369 return -EAGAIN; 1370 } 1371 1372 mutex_lock(&intel_pstate_limits_lock); 1373 1374 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1375 1376 mutex_unlock(&intel_pstate_limits_lock); 1377 1378 if (intel_pstate_driver == &intel_pstate) 1379 intel_pstate_update_policies(); 1380 else 1381 update_qos_request(FREQ_QOS_MAX); 1382 1383 mutex_unlock(&intel_pstate_driver_lock); 1384 1385 return count; 1386 } 1387 1388 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1389 const char *buf, size_t count) 1390 { 1391 unsigned int input; 1392 int ret; 1393 1394 ret = sscanf(buf, "%u", &input); 1395 if (ret != 1) 1396 return -EINVAL; 1397 1398 mutex_lock(&intel_pstate_driver_lock); 1399 1400 if (!intel_pstate_driver) { 1401 mutex_unlock(&intel_pstate_driver_lock); 1402 return -EAGAIN; 1403 } 1404 1405 mutex_lock(&intel_pstate_limits_lock); 1406 1407 global.min_perf_pct = clamp_t(int, input, 1408 min_perf_pct_min(), global.max_perf_pct); 1409 1410 mutex_unlock(&intel_pstate_limits_lock); 1411 1412 if (intel_pstate_driver == &intel_pstate) 1413 intel_pstate_update_policies(); 1414 else 1415 update_qos_request(FREQ_QOS_MIN); 1416 1417 mutex_unlock(&intel_pstate_driver_lock); 1418 1419 return count; 1420 } 1421 1422 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1423 struct kobj_attribute *attr, char *buf) 1424 { 1425 return sprintf(buf, "%u\n", hwp_boost); 1426 } 1427 1428 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1429 struct kobj_attribute *b, 1430 const char *buf, size_t count) 1431 { 1432 unsigned int input; 1433 int ret; 1434 1435 ret = kstrtouint(buf, 10, &input); 1436 if (ret) 1437 return ret; 1438 1439 mutex_lock(&intel_pstate_driver_lock); 1440 hwp_boost = !!input; 1441 intel_pstate_update_policies(); 1442 mutex_unlock(&intel_pstate_driver_lock); 1443 1444 return count; 1445 } 1446 1447 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1448 char *buf) 1449 { 1450 u64 power_ctl; 1451 int enable; 1452 1453 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1454 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1455 return sprintf(buf, "%d\n", !enable); 1456 } 1457 1458 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1459 const char *buf, size_t count) 1460 { 1461 bool input; 1462 int ret; 1463 1464 ret = kstrtobool(buf, &input); 1465 if (ret) 1466 return ret; 1467 1468 set_power_ctl_ee_state(input); 1469 1470 return count; 1471 } 1472 1473 show_one(max_perf_pct, max_perf_pct); 1474 show_one(min_perf_pct, min_perf_pct); 1475 1476 define_one_global_rw(status); 1477 define_one_global_rw(no_turbo); 1478 define_one_global_rw(max_perf_pct); 1479 define_one_global_rw(min_perf_pct); 1480 define_one_global_ro(turbo_pct); 1481 define_one_global_ro(num_pstates); 1482 define_one_global_rw(hwp_dynamic_boost); 1483 define_one_global_rw(energy_efficiency); 1484 1485 static struct attribute *intel_pstate_attributes[] = { 1486 &status.attr, 1487 &no_turbo.attr, 1488 NULL 1489 }; 1490 1491 static const struct attribute_group intel_pstate_attr_group = { 1492 .attrs = intel_pstate_attributes, 1493 }; 1494 1495 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1496 1497 static struct kobject *intel_pstate_kobject; 1498 1499 static void __init intel_pstate_sysfs_expose_params(void) 1500 { 1501 int rc; 1502 1503 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1504 &cpu_subsys.dev_root->kobj); 1505 if (WARN_ON(!intel_pstate_kobject)) 1506 return; 1507 1508 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1509 if (WARN_ON(rc)) 1510 return; 1511 1512 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1513 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1514 WARN_ON(rc); 1515 1516 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1517 WARN_ON(rc); 1518 } 1519 1520 /* 1521 * If per cpu limits are enforced there are no global limits, so 1522 * return without creating max/min_perf_pct attributes 1523 */ 1524 if (per_cpu_limits) 1525 return; 1526 1527 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1528 WARN_ON(rc); 1529 1530 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1531 WARN_ON(rc); 1532 1533 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1534 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1535 WARN_ON(rc); 1536 } 1537 } 1538 1539 static void __init intel_pstate_sysfs_remove(void) 1540 { 1541 if (!intel_pstate_kobject) 1542 return; 1543 1544 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1545 1546 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1547 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1548 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1549 } 1550 1551 if (!per_cpu_limits) { 1552 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1553 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1554 1555 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1556 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1557 } 1558 1559 kobject_put(intel_pstate_kobject); 1560 } 1561 1562 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1563 { 1564 int rc; 1565 1566 if (!hwp_active) 1567 return; 1568 1569 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1570 WARN_ON_ONCE(rc); 1571 } 1572 1573 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1574 { 1575 if (!hwp_active) 1576 return; 1577 1578 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1579 } 1580 1581 /************************** sysfs end ************************/ 1582 1583 static void intel_pstate_notify_work(struct work_struct *work) 1584 { 1585 struct cpudata *cpudata = 1586 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1587 1588 cpufreq_update_policy(cpudata->cpu); 1589 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1590 } 1591 1592 static DEFINE_SPINLOCK(hwp_notify_lock); 1593 static cpumask_t hwp_intr_enable_mask; 1594 1595 void notify_hwp_interrupt(void) 1596 { 1597 unsigned int this_cpu = smp_processor_id(); 1598 struct cpudata *cpudata; 1599 unsigned long flags; 1600 u64 value; 1601 1602 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1603 return; 1604 1605 rdmsrl_safe(MSR_HWP_STATUS, &value); 1606 if (!(value & 0x01)) 1607 return; 1608 1609 spin_lock_irqsave(&hwp_notify_lock, flags); 1610 1611 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1612 goto ack_intr; 1613 1614 /* 1615 * Currently we never free all_cpu_data. And we can't reach here 1616 * without this allocated. But for safety for future changes, added 1617 * check. 1618 */ 1619 if (unlikely(!READ_ONCE(all_cpu_data))) 1620 goto ack_intr; 1621 1622 /* 1623 * The free is done during cleanup, when cpufreq registry is failed. 1624 * We wouldn't be here if it fails on init or switch status. But for 1625 * future changes, added check. 1626 */ 1627 cpudata = READ_ONCE(all_cpu_data[this_cpu]); 1628 if (unlikely(!cpudata)) 1629 goto ack_intr; 1630 1631 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10)); 1632 1633 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1634 1635 return; 1636 1637 ack_intr: 1638 wrmsrl_safe(MSR_HWP_STATUS, 0); 1639 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1640 } 1641 1642 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1643 { 1644 unsigned long flags; 1645 1646 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1647 return; 1648 1649 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1650 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1651 1652 spin_lock_irqsave(&hwp_notify_lock, flags); 1653 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask)) 1654 cancel_delayed_work(&cpudata->hwp_notify_work); 1655 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1656 } 1657 1658 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1659 { 1660 /* Enable HWP notification interrupt for guaranteed performance change */ 1661 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1662 unsigned long flags; 1663 1664 spin_lock_irqsave(&hwp_notify_lock, flags); 1665 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1666 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1667 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1668 1669 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1670 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1671 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1672 } 1673 } 1674 1675 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1676 { 1677 /* First disable HWP notification interrupt till we activate again */ 1678 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1679 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1680 1681 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1682 if (cpudata->epp_default == -EINVAL) 1683 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1684 1685 intel_pstate_enable_hwp_interrupt(cpudata); 1686 } 1687 1688 static int atom_get_min_pstate(void) 1689 { 1690 u64 value; 1691 1692 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1693 return (value >> 8) & 0x7F; 1694 } 1695 1696 static int atom_get_max_pstate(void) 1697 { 1698 u64 value; 1699 1700 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1701 return (value >> 16) & 0x7F; 1702 } 1703 1704 static int atom_get_turbo_pstate(void) 1705 { 1706 u64 value; 1707 1708 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1709 return value & 0x7F; 1710 } 1711 1712 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1713 { 1714 u64 val; 1715 int32_t vid_fp; 1716 u32 vid; 1717 1718 val = (u64)pstate << 8; 1719 if (global.no_turbo && !global.turbo_disabled) 1720 val |= (u64)1 << 32; 1721 1722 vid_fp = cpudata->vid.min + mul_fp( 1723 int_tofp(pstate - cpudata->pstate.min_pstate), 1724 cpudata->vid.ratio); 1725 1726 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1727 vid = ceiling_fp(vid_fp); 1728 1729 if (pstate > cpudata->pstate.max_pstate) 1730 vid = cpudata->vid.turbo; 1731 1732 return val | vid; 1733 } 1734 1735 static int silvermont_get_scaling(void) 1736 { 1737 u64 value; 1738 int i; 1739 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1740 static int silvermont_freq_table[] = { 1741 83300, 100000, 133300, 116700, 80000}; 1742 1743 rdmsrl(MSR_FSB_FREQ, value); 1744 i = value & 0x7; 1745 WARN_ON(i > 4); 1746 1747 return silvermont_freq_table[i]; 1748 } 1749 1750 static int airmont_get_scaling(void) 1751 { 1752 u64 value; 1753 int i; 1754 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1755 static int airmont_freq_table[] = { 1756 83300, 100000, 133300, 116700, 80000, 1757 93300, 90000, 88900, 87500}; 1758 1759 rdmsrl(MSR_FSB_FREQ, value); 1760 i = value & 0xF; 1761 WARN_ON(i > 8); 1762 1763 return airmont_freq_table[i]; 1764 } 1765 1766 static void atom_get_vid(struct cpudata *cpudata) 1767 { 1768 u64 value; 1769 1770 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1771 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1772 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1773 cpudata->vid.ratio = div_fp( 1774 cpudata->vid.max - cpudata->vid.min, 1775 int_tofp(cpudata->pstate.max_pstate - 1776 cpudata->pstate.min_pstate)); 1777 1778 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1779 cpudata->vid.turbo = value & 0x7f; 1780 } 1781 1782 static int core_get_min_pstate(void) 1783 { 1784 u64 value; 1785 1786 rdmsrl(MSR_PLATFORM_INFO, value); 1787 return (value >> 40) & 0xFF; 1788 } 1789 1790 static int core_get_max_pstate_physical(void) 1791 { 1792 u64 value; 1793 1794 rdmsrl(MSR_PLATFORM_INFO, value); 1795 return (value >> 8) & 0xFF; 1796 } 1797 1798 static int core_get_tdp_ratio(u64 plat_info) 1799 { 1800 /* Check how many TDP levels present */ 1801 if (plat_info & 0x600000000) { 1802 u64 tdp_ctrl; 1803 u64 tdp_ratio; 1804 int tdp_msr; 1805 int err; 1806 1807 /* Get the TDP level (0, 1, 2) to get ratios */ 1808 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1809 if (err) 1810 return err; 1811 1812 /* TDP MSR are continuous starting at 0x648 */ 1813 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1814 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1815 if (err) 1816 return err; 1817 1818 /* For level 1 and 2, bits[23:16] contain the ratio */ 1819 if (tdp_ctrl & 0x03) 1820 tdp_ratio >>= 16; 1821 1822 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1823 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1824 1825 return (int)tdp_ratio; 1826 } 1827 1828 return -ENXIO; 1829 } 1830 1831 static int core_get_max_pstate(void) 1832 { 1833 u64 tar; 1834 u64 plat_info; 1835 int max_pstate; 1836 int tdp_ratio; 1837 int err; 1838 1839 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1840 max_pstate = (plat_info >> 8) & 0xFF; 1841 1842 tdp_ratio = core_get_tdp_ratio(plat_info); 1843 if (tdp_ratio <= 0) 1844 return max_pstate; 1845 1846 if (hwp_active) { 1847 /* Turbo activation ratio is not used on HWP platforms */ 1848 return tdp_ratio; 1849 } 1850 1851 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1852 if (!err) { 1853 int tar_levels; 1854 1855 /* Do some sanity checking for safety */ 1856 tar_levels = tar & 0xff; 1857 if (tdp_ratio - 1 == tar_levels) { 1858 max_pstate = tar_levels; 1859 pr_debug("max_pstate=TAC %x\n", max_pstate); 1860 } 1861 } 1862 1863 return max_pstate; 1864 } 1865 1866 static int core_get_turbo_pstate(void) 1867 { 1868 u64 value; 1869 int nont, ret; 1870 1871 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1872 nont = core_get_max_pstate(); 1873 ret = (value) & 255; 1874 if (ret <= nont) 1875 ret = nont; 1876 return ret; 1877 } 1878 1879 static inline int core_get_scaling(void) 1880 { 1881 return 100000; 1882 } 1883 1884 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1885 { 1886 u64 val; 1887 1888 val = (u64)pstate << 8; 1889 if (global.no_turbo && !global.turbo_disabled) 1890 val |= (u64)1 << 32; 1891 1892 return val; 1893 } 1894 1895 static int knl_get_aperf_mperf_shift(void) 1896 { 1897 return 10; 1898 } 1899 1900 static int knl_get_turbo_pstate(void) 1901 { 1902 u64 value; 1903 int nont, ret; 1904 1905 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1906 nont = core_get_max_pstate(); 1907 ret = (((value) >> 8) & 0xFF); 1908 if (ret <= nont) 1909 ret = nont; 1910 return ret; 1911 } 1912 1913 #ifdef CONFIG_ACPI_CPPC_LIB 1914 static u32 hybrid_ref_perf; 1915 1916 static int hybrid_get_cpu_scaling(int cpu) 1917 { 1918 return DIV_ROUND_UP(core_get_scaling() * hybrid_ref_perf, 1919 intel_pstate_cppc_nominal(cpu)); 1920 } 1921 1922 static void intel_pstate_cppc_set_cpu_scaling(void) 1923 { 1924 u32 min_nominal_perf = U32_MAX; 1925 int cpu; 1926 1927 for_each_present_cpu(cpu) { 1928 u32 nominal_perf = intel_pstate_cppc_nominal(cpu); 1929 1930 if (nominal_perf && nominal_perf < min_nominal_perf) 1931 min_nominal_perf = nominal_perf; 1932 } 1933 1934 if (min_nominal_perf < U32_MAX) { 1935 hybrid_ref_perf = min_nominal_perf; 1936 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling; 1937 } 1938 } 1939 #else 1940 static inline void intel_pstate_cppc_set_cpu_scaling(void) 1941 { 1942 } 1943 #endif /* CONFIG_ACPI_CPPC_LIB */ 1944 1945 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1946 { 1947 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1948 cpu->pstate.current_pstate = pstate; 1949 /* 1950 * Generally, there is no guarantee that this code will always run on 1951 * the CPU being updated, so force the register update to run on the 1952 * right CPU. 1953 */ 1954 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1955 pstate_funcs.get_val(cpu, pstate)); 1956 } 1957 1958 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1959 { 1960 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1961 } 1962 1963 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1964 { 1965 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1966 1967 update_turbo_state(); 1968 intel_pstate_set_pstate(cpu, pstate); 1969 } 1970 1971 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1972 { 1973 int perf_ctl_max_phys = pstate_funcs.get_max_physical(); 1974 int perf_ctl_scaling = pstate_funcs.get_scaling(); 1975 1976 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1977 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 1978 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 1979 1980 if (hwp_active && !hwp_mode_bdw) { 1981 __intel_pstate_get_hwp_cap(cpu); 1982 1983 if (pstate_funcs.get_cpu_scaling) { 1984 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 1985 if (cpu->pstate.scaling != perf_ctl_scaling) 1986 intel_pstate_hybrid_hwp_adjust(cpu); 1987 } else { 1988 cpu->pstate.scaling = perf_ctl_scaling; 1989 } 1990 } else { 1991 cpu->pstate.scaling = perf_ctl_scaling; 1992 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1993 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1994 } 1995 1996 if (cpu->pstate.scaling == perf_ctl_scaling) { 1997 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 1998 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 1999 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2000 } 2001 2002 if (pstate_funcs.get_aperf_mperf_shift) 2003 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2004 2005 if (pstate_funcs.get_vid) 2006 pstate_funcs.get_vid(cpu); 2007 2008 intel_pstate_set_min_pstate(cpu); 2009 } 2010 2011 /* 2012 * Long hold time will keep high perf limits for long time, 2013 * which negatively impacts perf/watt for some workloads, 2014 * like specpower. 3ms is based on experiements on some 2015 * workoads. 2016 */ 2017 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2018 2019 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2020 { 2021 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2022 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2023 u32 max_limit = (hwp_req & 0xff00) >> 8; 2024 u32 min_limit = (hwp_req & 0xff); 2025 u32 boost_level1; 2026 2027 /* 2028 * Cases to consider (User changes via sysfs or boot time): 2029 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2030 * No boost, return. 2031 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2032 * Should result in one level boost only for P0. 2033 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2034 * Should result in two level boost: 2035 * (min + p1)/2 and P1. 2036 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2037 * Should result in three level boost: 2038 * (min + p1)/2, P1 and P0. 2039 */ 2040 2041 /* If max and min are equal or already at max, nothing to boost */ 2042 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2043 return; 2044 2045 if (!cpu->hwp_boost_min) 2046 cpu->hwp_boost_min = min_limit; 2047 2048 /* level at half way mark between min and guranteed */ 2049 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2050 2051 if (cpu->hwp_boost_min < boost_level1) 2052 cpu->hwp_boost_min = boost_level1; 2053 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2054 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2055 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2056 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2057 cpu->hwp_boost_min = max_limit; 2058 else 2059 return; 2060 2061 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2062 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2063 cpu->last_update = cpu->sample.time; 2064 } 2065 2066 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2067 { 2068 if (cpu->hwp_boost_min) { 2069 bool expired; 2070 2071 /* Check if we are idle for hold time to boost down */ 2072 expired = time_after64(cpu->sample.time, cpu->last_update + 2073 hwp_boost_hold_time_ns); 2074 if (expired) { 2075 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2076 cpu->hwp_boost_min = 0; 2077 } 2078 } 2079 cpu->last_update = cpu->sample.time; 2080 } 2081 2082 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2083 u64 time) 2084 { 2085 cpu->sample.time = time; 2086 2087 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2088 bool do_io = false; 2089 2090 cpu->sched_flags = 0; 2091 /* 2092 * Set iowait_boost flag and update time. Since IO WAIT flag 2093 * is set all the time, we can't just conclude that there is 2094 * some IO bound activity is scheduled on this CPU with just 2095 * one occurrence. If we receive at least two in two 2096 * consecutive ticks, then we treat as boost candidate. 2097 */ 2098 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2099 do_io = true; 2100 2101 cpu->last_io_update = time; 2102 2103 if (do_io) 2104 intel_pstate_hwp_boost_up(cpu); 2105 2106 } else { 2107 intel_pstate_hwp_boost_down(cpu); 2108 } 2109 } 2110 2111 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2112 u64 time, unsigned int flags) 2113 { 2114 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2115 2116 cpu->sched_flags |= flags; 2117 2118 if (smp_processor_id() == cpu->cpu) 2119 intel_pstate_update_util_hwp_local(cpu, time); 2120 } 2121 2122 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2123 { 2124 struct sample *sample = &cpu->sample; 2125 2126 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2127 } 2128 2129 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2130 { 2131 u64 aperf, mperf; 2132 unsigned long flags; 2133 u64 tsc; 2134 2135 local_irq_save(flags); 2136 rdmsrl(MSR_IA32_APERF, aperf); 2137 rdmsrl(MSR_IA32_MPERF, mperf); 2138 tsc = rdtsc(); 2139 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2140 local_irq_restore(flags); 2141 return false; 2142 } 2143 local_irq_restore(flags); 2144 2145 cpu->last_sample_time = cpu->sample.time; 2146 cpu->sample.time = time; 2147 cpu->sample.aperf = aperf; 2148 cpu->sample.mperf = mperf; 2149 cpu->sample.tsc = tsc; 2150 cpu->sample.aperf -= cpu->prev_aperf; 2151 cpu->sample.mperf -= cpu->prev_mperf; 2152 cpu->sample.tsc -= cpu->prev_tsc; 2153 2154 cpu->prev_aperf = aperf; 2155 cpu->prev_mperf = mperf; 2156 cpu->prev_tsc = tsc; 2157 /* 2158 * First time this function is invoked in a given cycle, all of the 2159 * previous sample data fields are equal to zero or stale and they must 2160 * be populated with meaningful numbers for things to work, so assume 2161 * that sample.time will always be reset before setting the utilization 2162 * update hook and make the caller skip the sample then. 2163 */ 2164 if (cpu->last_sample_time) { 2165 intel_pstate_calc_avg_perf(cpu); 2166 return true; 2167 } 2168 return false; 2169 } 2170 2171 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2172 { 2173 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2174 } 2175 2176 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2177 { 2178 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2179 cpu->sample.core_avg_perf); 2180 } 2181 2182 static inline int32_t get_target_pstate(struct cpudata *cpu) 2183 { 2184 struct sample *sample = &cpu->sample; 2185 int32_t busy_frac; 2186 int target, avg_pstate; 2187 2188 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2189 sample->tsc); 2190 2191 if (busy_frac < cpu->iowait_boost) 2192 busy_frac = cpu->iowait_boost; 2193 2194 sample->busy_scaled = busy_frac * 100; 2195 2196 target = global.no_turbo || global.turbo_disabled ? 2197 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2198 target += target >> 2; 2199 target = mul_fp(target, busy_frac); 2200 if (target < cpu->pstate.min_pstate) 2201 target = cpu->pstate.min_pstate; 2202 2203 /* 2204 * If the average P-state during the previous cycle was higher than the 2205 * current target, add 50% of the difference to the target to reduce 2206 * possible performance oscillations and offset possible performance 2207 * loss related to moving the workload from one CPU to another within 2208 * a package/module. 2209 */ 2210 avg_pstate = get_avg_pstate(cpu); 2211 if (avg_pstate > target) 2212 target += (avg_pstate - target) >> 1; 2213 2214 return target; 2215 } 2216 2217 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2218 { 2219 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2220 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2221 2222 return clamp_t(int, pstate, min_pstate, max_pstate); 2223 } 2224 2225 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2226 { 2227 if (pstate == cpu->pstate.current_pstate) 2228 return; 2229 2230 cpu->pstate.current_pstate = pstate; 2231 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2232 } 2233 2234 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2235 { 2236 int from = cpu->pstate.current_pstate; 2237 struct sample *sample; 2238 int target_pstate; 2239 2240 update_turbo_state(); 2241 2242 target_pstate = get_target_pstate(cpu); 2243 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2244 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2245 intel_pstate_update_pstate(cpu, target_pstate); 2246 2247 sample = &cpu->sample; 2248 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2249 fp_toint(sample->busy_scaled), 2250 from, 2251 cpu->pstate.current_pstate, 2252 sample->mperf, 2253 sample->aperf, 2254 sample->tsc, 2255 get_avg_frequency(cpu), 2256 fp_toint(cpu->iowait_boost * 100)); 2257 } 2258 2259 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2260 unsigned int flags) 2261 { 2262 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2263 u64 delta_ns; 2264 2265 /* Don't allow remote callbacks */ 2266 if (smp_processor_id() != cpu->cpu) 2267 return; 2268 2269 delta_ns = time - cpu->last_update; 2270 if (flags & SCHED_CPUFREQ_IOWAIT) { 2271 /* Start over if the CPU may have been idle. */ 2272 if (delta_ns > TICK_NSEC) { 2273 cpu->iowait_boost = ONE_EIGHTH_FP; 2274 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2275 cpu->iowait_boost <<= 1; 2276 if (cpu->iowait_boost > int_tofp(1)) 2277 cpu->iowait_boost = int_tofp(1); 2278 } else { 2279 cpu->iowait_boost = ONE_EIGHTH_FP; 2280 } 2281 } else if (cpu->iowait_boost) { 2282 /* Clear iowait_boost if the CPU may have been idle. */ 2283 if (delta_ns > TICK_NSEC) 2284 cpu->iowait_boost = 0; 2285 else 2286 cpu->iowait_boost >>= 1; 2287 } 2288 cpu->last_update = time; 2289 delta_ns = time - cpu->sample.time; 2290 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2291 return; 2292 2293 if (intel_pstate_sample(cpu, time)) 2294 intel_pstate_adjust_pstate(cpu); 2295 } 2296 2297 static struct pstate_funcs core_funcs = { 2298 .get_max = core_get_max_pstate, 2299 .get_max_physical = core_get_max_pstate_physical, 2300 .get_min = core_get_min_pstate, 2301 .get_turbo = core_get_turbo_pstate, 2302 .get_scaling = core_get_scaling, 2303 .get_val = core_get_val, 2304 }; 2305 2306 static const struct pstate_funcs silvermont_funcs = { 2307 .get_max = atom_get_max_pstate, 2308 .get_max_physical = atom_get_max_pstate, 2309 .get_min = atom_get_min_pstate, 2310 .get_turbo = atom_get_turbo_pstate, 2311 .get_val = atom_get_val, 2312 .get_scaling = silvermont_get_scaling, 2313 .get_vid = atom_get_vid, 2314 }; 2315 2316 static const struct pstate_funcs airmont_funcs = { 2317 .get_max = atom_get_max_pstate, 2318 .get_max_physical = atom_get_max_pstate, 2319 .get_min = atom_get_min_pstate, 2320 .get_turbo = atom_get_turbo_pstate, 2321 .get_val = atom_get_val, 2322 .get_scaling = airmont_get_scaling, 2323 .get_vid = atom_get_vid, 2324 }; 2325 2326 static const struct pstate_funcs knl_funcs = { 2327 .get_max = core_get_max_pstate, 2328 .get_max_physical = core_get_max_pstate_physical, 2329 .get_min = core_get_min_pstate, 2330 .get_turbo = knl_get_turbo_pstate, 2331 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2332 .get_scaling = core_get_scaling, 2333 .get_val = core_get_val, 2334 }; 2335 2336 #define X86_MATCH(model, policy) \ 2337 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2338 X86_FEATURE_APERFMPERF, &policy) 2339 2340 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2341 X86_MATCH(SANDYBRIDGE, core_funcs), 2342 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2343 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2344 X86_MATCH(IVYBRIDGE, core_funcs), 2345 X86_MATCH(HASWELL, core_funcs), 2346 X86_MATCH(BROADWELL, core_funcs), 2347 X86_MATCH(IVYBRIDGE_X, core_funcs), 2348 X86_MATCH(HASWELL_X, core_funcs), 2349 X86_MATCH(HASWELL_L, core_funcs), 2350 X86_MATCH(HASWELL_G, core_funcs), 2351 X86_MATCH(BROADWELL_G, core_funcs), 2352 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2353 X86_MATCH(SKYLAKE_L, core_funcs), 2354 X86_MATCH(BROADWELL_X, core_funcs), 2355 X86_MATCH(SKYLAKE, core_funcs), 2356 X86_MATCH(BROADWELL_D, core_funcs), 2357 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2358 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2359 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2360 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2361 X86_MATCH(SKYLAKE_X, core_funcs), 2362 X86_MATCH(COMETLAKE, core_funcs), 2363 X86_MATCH(ICELAKE_X, core_funcs), 2364 {} 2365 }; 2366 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2367 2368 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2369 X86_MATCH(BROADWELL_D, core_funcs), 2370 X86_MATCH(BROADWELL_X, core_funcs), 2371 X86_MATCH(SKYLAKE_X, core_funcs), 2372 X86_MATCH(ICELAKE_X, core_funcs), 2373 {} 2374 }; 2375 2376 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2377 X86_MATCH(KABYLAKE, core_funcs), 2378 {} 2379 }; 2380 2381 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = { 2382 X86_MATCH(SKYLAKE_X, core_funcs), 2383 X86_MATCH(SKYLAKE, core_funcs), 2384 {} 2385 }; 2386 2387 static int intel_pstate_init_cpu(unsigned int cpunum) 2388 { 2389 struct cpudata *cpu; 2390 2391 cpu = all_cpu_data[cpunum]; 2392 2393 if (!cpu) { 2394 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2395 if (!cpu) 2396 return -ENOMEM; 2397 2398 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2399 2400 cpu->cpu = cpunum; 2401 2402 cpu->epp_default = -EINVAL; 2403 2404 if (hwp_active) { 2405 const struct x86_cpu_id *id; 2406 2407 intel_pstate_hwp_enable(cpu); 2408 2409 id = x86_match_cpu(intel_pstate_hwp_boost_ids); 2410 if (id && intel_pstate_acpi_pm_profile_server()) 2411 hwp_boost = true; 2412 } 2413 } else if (hwp_active) { 2414 /* 2415 * Re-enable HWP in case this happens after a resume from ACPI 2416 * S3 if the CPU was offline during the whole system/resume 2417 * cycle. 2418 */ 2419 intel_pstate_hwp_reenable(cpu); 2420 } 2421 2422 cpu->epp_powersave = -EINVAL; 2423 cpu->epp_policy = 0; 2424 2425 intel_pstate_get_cpu_pstates(cpu); 2426 2427 pr_debug("controlling: cpu %d\n", cpunum); 2428 2429 return 0; 2430 } 2431 2432 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2433 { 2434 struct cpudata *cpu = all_cpu_data[cpu_num]; 2435 2436 if (hwp_active && !hwp_boost) 2437 return; 2438 2439 if (cpu->update_util_set) 2440 return; 2441 2442 /* Prevent intel_pstate_update_util() from using stale data. */ 2443 cpu->sample.time = 0; 2444 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2445 (hwp_active ? 2446 intel_pstate_update_util_hwp : 2447 intel_pstate_update_util)); 2448 cpu->update_util_set = true; 2449 } 2450 2451 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2452 { 2453 struct cpudata *cpu_data = all_cpu_data[cpu]; 2454 2455 if (!cpu_data->update_util_set) 2456 return; 2457 2458 cpufreq_remove_update_util_hook(cpu); 2459 cpu_data->update_util_set = false; 2460 synchronize_rcu(); 2461 } 2462 2463 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2464 { 2465 return global.turbo_disabled || global.no_turbo ? 2466 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2467 } 2468 2469 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2470 unsigned int policy_min, 2471 unsigned int policy_max) 2472 { 2473 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2474 int32_t max_policy_perf, min_policy_perf; 2475 2476 max_policy_perf = policy_max / perf_ctl_scaling; 2477 if (policy_max == policy_min) { 2478 min_policy_perf = max_policy_perf; 2479 } else { 2480 min_policy_perf = policy_min / perf_ctl_scaling; 2481 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2482 0, max_policy_perf); 2483 } 2484 2485 /* 2486 * HWP needs some special consideration, because HWP_REQUEST uses 2487 * abstract values to represent performance rather than pure ratios. 2488 */ 2489 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2490 int scaling = cpu->pstate.scaling; 2491 int freq; 2492 2493 freq = max_policy_perf * perf_ctl_scaling; 2494 max_policy_perf = DIV_ROUND_UP(freq, scaling); 2495 freq = min_policy_perf * perf_ctl_scaling; 2496 min_policy_perf = DIV_ROUND_UP(freq, scaling); 2497 } 2498 2499 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2500 cpu->cpu, min_policy_perf, max_policy_perf); 2501 2502 /* Normalize user input to [min_perf, max_perf] */ 2503 if (per_cpu_limits) { 2504 cpu->min_perf_ratio = min_policy_perf; 2505 cpu->max_perf_ratio = max_policy_perf; 2506 } else { 2507 int turbo_max = cpu->pstate.turbo_pstate; 2508 int32_t global_min, global_max; 2509 2510 /* Global limits are in percent of the maximum turbo P-state. */ 2511 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2512 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2513 global_min = clamp_t(int32_t, global_min, 0, global_max); 2514 2515 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2516 global_min, global_max); 2517 2518 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2519 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2520 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2521 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2522 2523 /* Make sure min_perf <= max_perf */ 2524 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2525 cpu->max_perf_ratio); 2526 2527 } 2528 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2529 cpu->max_perf_ratio, 2530 cpu->min_perf_ratio); 2531 } 2532 2533 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2534 { 2535 struct cpudata *cpu; 2536 2537 if (!policy->cpuinfo.max_freq) 2538 return -ENODEV; 2539 2540 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2541 policy->cpuinfo.max_freq, policy->max); 2542 2543 cpu = all_cpu_data[policy->cpu]; 2544 cpu->policy = policy->policy; 2545 2546 mutex_lock(&intel_pstate_limits_lock); 2547 2548 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2549 2550 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2551 /* 2552 * NOHZ_FULL CPUs need this as the governor callback may not 2553 * be invoked on them. 2554 */ 2555 intel_pstate_clear_update_util_hook(policy->cpu); 2556 intel_pstate_max_within_limits(cpu); 2557 } else { 2558 intel_pstate_set_update_util_hook(policy->cpu); 2559 } 2560 2561 if (hwp_active) { 2562 /* 2563 * When hwp_boost was active before and dynamically it 2564 * was turned off, in that case we need to clear the 2565 * update util hook. 2566 */ 2567 if (!hwp_boost) 2568 intel_pstate_clear_update_util_hook(policy->cpu); 2569 intel_pstate_hwp_set(policy->cpu); 2570 } 2571 2572 mutex_unlock(&intel_pstate_limits_lock); 2573 2574 return 0; 2575 } 2576 2577 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2578 struct cpufreq_policy_data *policy) 2579 { 2580 if (!hwp_active && 2581 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2582 policy->max < policy->cpuinfo.max_freq && 2583 policy->max > cpu->pstate.max_freq) { 2584 pr_debug("policy->max > max non turbo frequency\n"); 2585 policy->max = policy->cpuinfo.max_freq; 2586 } 2587 } 2588 2589 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2590 struct cpufreq_policy_data *policy) 2591 { 2592 int max_freq; 2593 2594 update_turbo_state(); 2595 if (hwp_active) { 2596 intel_pstate_get_hwp_cap(cpu); 2597 max_freq = global.no_turbo || global.turbo_disabled ? 2598 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2599 } else { 2600 max_freq = intel_pstate_get_max_freq(cpu); 2601 } 2602 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2603 2604 intel_pstate_adjust_policy_max(cpu, policy); 2605 } 2606 2607 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2608 { 2609 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2610 2611 return 0; 2612 } 2613 2614 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2615 { 2616 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2617 2618 pr_debug("CPU %d going offline\n", cpu->cpu); 2619 2620 if (cpu->suspended) 2621 return 0; 2622 2623 /* 2624 * If the CPU is an SMT thread and it goes offline with the performance 2625 * settings different from the minimum, it will prevent its sibling 2626 * from getting to lower performance levels, so force the minimum 2627 * performance on CPU offline to prevent that from happening. 2628 */ 2629 if (hwp_active) 2630 intel_pstate_hwp_offline(cpu); 2631 else 2632 intel_pstate_set_min_pstate(cpu); 2633 2634 intel_pstate_exit_perf_limits(policy); 2635 2636 return 0; 2637 } 2638 2639 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2640 { 2641 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2642 2643 pr_debug("CPU %d going online\n", cpu->cpu); 2644 2645 intel_pstate_init_acpi_perf_limits(policy); 2646 2647 if (hwp_active) { 2648 /* 2649 * Re-enable HWP and clear the "suspended" flag to let "resume" 2650 * know that it need not do that. 2651 */ 2652 intel_pstate_hwp_reenable(cpu); 2653 cpu->suspended = false; 2654 } 2655 2656 return 0; 2657 } 2658 2659 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2660 { 2661 intel_pstate_clear_update_util_hook(policy->cpu); 2662 2663 return intel_cpufreq_cpu_offline(policy); 2664 } 2665 2666 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2667 { 2668 pr_debug("CPU %d exiting\n", policy->cpu); 2669 2670 policy->fast_switch_possible = false; 2671 2672 return 0; 2673 } 2674 2675 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2676 { 2677 struct cpudata *cpu; 2678 int rc; 2679 2680 rc = intel_pstate_init_cpu(policy->cpu); 2681 if (rc) 2682 return rc; 2683 2684 cpu = all_cpu_data[policy->cpu]; 2685 2686 cpu->max_perf_ratio = 0xFF; 2687 cpu->min_perf_ratio = 0; 2688 2689 /* cpuinfo and default policy values */ 2690 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2691 update_turbo_state(); 2692 global.turbo_disabled_mf = global.turbo_disabled; 2693 policy->cpuinfo.max_freq = global.turbo_disabled ? 2694 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2695 2696 policy->min = policy->cpuinfo.min_freq; 2697 policy->max = policy->cpuinfo.max_freq; 2698 2699 intel_pstate_init_acpi_perf_limits(policy); 2700 2701 policy->fast_switch_possible = true; 2702 2703 return 0; 2704 } 2705 2706 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2707 { 2708 int ret = __intel_pstate_cpu_init(policy); 2709 2710 if (ret) 2711 return ret; 2712 2713 /* 2714 * Set the policy to powersave to provide a valid fallback value in case 2715 * the default cpufreq governor is neither powersave nor performance. 2716 */ 2717 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2718 2719 if (hwp_active) { 2720 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2721 2722 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2723 } 2724 2725 return 0; 2726 } 2727 2728 static struct cpufreq_driver intel_pstate = { 2729 .flags = CPUFREQ_CONST_LOOPS, 2730 .verify = intel_pstate_verify_policy, 2731 .setpolicy = intel_pstate_set_policy, 2732 .suspend = intel_pstate_suspend, 2733 .resume = intel_pstate_resume, 2734 .init = intel_pstate_cpu_init, 2735 .exit = intel_pstate_cpu_exit, 2736 .offline = intel_pstate_cpu_offline, 2737 .online = intel_pstate_cpu_online, 2738 .update_limits = intel_pstate_update_limits, 2739 .name = "intel_pstate", 2740 }; 2741 2742 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2743 { 2744 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2745 2746 intel_pstate_verify_cpu_policy(cpu, policy); 2747 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2748 2749 return 0; 2750 } 2751 2752 /* Use of trace in passive mode: 2753 * 2754 * In passive mode the trace core_busy field (also known as the 2755 * performance field, and lablelled as such on the graphs; also known as 2756 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2757 * driver call was via the normal or fast switch path. Various graphs 2758 * output from the intel_pstate_tracer.py utility that include core_busy 2759 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2760 * so we use 10 to indicate the normal path through the driver, and 2761 * 90 to indicate the fast switch path through the driver. 2762 * The scaled_busy field is not used, and is set to 0. 2763 */ 2764 2765 #define INTEL_PSTATE_TRACE_TARGET 10 2766 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2767 2768 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2769 { 2770 struct sample *sample; 2771 2772 if (!trace_pstate_sample_enabled()) 2773 return; 2774 2775 if (!intel_pstate_sample(cpu, ktime_get())) 2776 return; 2777 2778 sample = &cpu->sample; 2779 trace_pstate_sample(trace_type, 2780 0, 2781 old_pstate, 2782 cpu->pstate.current_pstate, 2783 sample->mperf, 2784 sample->aperf, 2785 sample->tsc, 2786 get_avg_frequency(cpu), 2787 fp_toint(cpu->iowait_boost * 100)); 2788 } 2789 2790 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2791 u32 desired, bool fast_switch) 2792 { 2793 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2794 2795 value &= ~HWP_MIN_PERF(~0L); 2796 value |= HWP_MIN_PERF(min); 2797 2798 value &= ~HWP_MAX_PERF(~0L); 2799 value |= HWP_MAX_PERF(max); 2800 2801 value &= ~HWP_DESIRED_PERF(~0L); 2802 value |= HWP_DESIRED_PERF(desired); 2803 2804 if (value == prev) 2805 return; 2806 2807 WRITE_ONCE(cpu->hwp_req_cached, value); 2808 if (fast_switch) 2809 wrmsrl(MSR_HWP_REQUEST, value); 2810 else 2811 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2812 } 2813 2814 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2815 u32 target_pstate, bool fast_switch) 2816 { 2817 if (fast_switch) 2818 wrmsrl(MSR_IA32_PERF_CTL, 2819 pstate_funcs.get_val(cpu, target_pstate)); 2820 else 2821 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2822 pstate_funcs.get_val(cpu, target_pstate)); 2823 } 2824 2825 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2826 int target_pstate, bool fast_switch) 2827 { 2828 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2829 int old_pstate = cpu->pstate.current_pstate; 2830 2831 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2832 if (hwp_active) { 2833 int max_pstate = policy->strict_target ? 2834 target_pstate : cpu->max_perf_ratio; 2835 2836 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2837 fast_switch); 2838 } else if (target_pstate != old_pstate) { 2839 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2840 } 2841 2842 cpu->pstate.current_pstate = target_pstate; 2843 2844 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2845 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2846 2847 return target_pstate; 2848 } 2849 2850 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2851 unsigned int target_freq, 2852 unsigned int relation) 2853 { 2854 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2855 struct cpufreq_freqs freqs; 2856 int target_pstate; 2857 2858 update_turbo_state(); 2859 2860 freqs.old = policy->cur; 2861 freqs.new = target_freq; 2862 2863 cpufreq_freq_transition_begin(policy, &freqs); 2864 2865 switch (relation) { 2866 case CPUFREQ_RELATION_L: 2867 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2868 break; 2869 case CPUFREQ_RELATION_H: 2870 target_pstate = freqs.new / cpu->pstate.scaling; 2871 break; 2872 default: 2873 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2874 break; 2875 } 2876 2877 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2878 2879 freqs.new = target_pstate * cpu->pstate.scaling; 2880 2881 cpufreq_freq_transition_end(policy, &freqs, false); 2882 2883 return 0; 2884 } 2885 2886 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2887 unsigned int target_freq) 2888 { 2889 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2890 int target_pstate; 2891 2892 update_turbo_state(); 2893 2894 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2895 2896 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2897 2898 return target_pstate * cpu->pstate.scaling; 2899 } 2900 2901 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2902 unsigned long min_perf, 2903 unsigned long target_perf, 2904 unsigned long capacity) 2905 { 2906 struct cpudata *cpu = all_cpu_data[cpunum]; 2907 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2908 int old_pstate = cpu->pstate.current_pstate; 2909 int cap_pstate, min_pstate, max_pstate, target_pstate; 2910 2911 update_turbo_state(); 2912 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) : 2913 HWP_HIGHEST_PERF(hwp_cap); 2914 2915 /* Optimization: Avoid unnecessary divisions. */ 2916 2917 target_pstate = cap_pstate; 2918 if (target_perf < capacity) 2919 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2920 2921 min_pstate = cap_pstate; 2922 if (min_perf < capacity) 2923 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2924 2925 if (min_pstate < cpu->pstate.min_pstate) 2926 min_pstate = cpu->pstate.min_pstate; 2927 2928 if (min_pstate < cpu->min_perf_ratio) 2929 min_pstate = cpu->min_perf_ratio; 2930 2931 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2932 if (max_pstate < min_pstate) 2933 max_pstate = min_pstate; 2934 2935 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2936 2937 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2938 2939 cpu->pstate.current_pstate = target_pstate; 2940 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2941 } 2942 2943 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2944 { 2945 struct freq_qos_request *req; 2946 struct cpudata *cpu; 2947 struct device *dev; 2948 int ret, freq; 2949 2950 dev = get_cpu_device(policy->cpu); 2951 if (!dev) 2952 return -ENODEV; 2953 2954 ret = __intel_pstate_cpu_init(policy); 2955 if (ret) 2956 return ret; 2957 2958 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2959 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2960 policy->cur = policy->cpuinfo.min_freq; 2961 2962 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2963 if (!req) { 2964 ret = -ENOMEM; 2965 goto pstate_exit; 2966 } 2967 2968 cpu = all_cpu_data[policy->cpu]; 2969 2970 if (hwp_active) { 2971 u64 value; 2972 2973 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2974 2975 intel_pstate_get_hwp_cap(cpu); 2976 2977 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 2978 WRITE_ONCE(cpu->hwp_req_cached, value); 2979 2980 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 2981 } else { 2982 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2983 } 2984 2985 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 2986 2987 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 2988 freq); 2989 if (ret < 0) { 2990 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 2991 goto free_req; 2992 } 2993 2994 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 2995 2996 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 2997 freq); 2998 if (ret < 0) { 2999 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3000 goto remove_min_req; 3001 } 3002 3003 policy->driver_data = req; 3004 3005 return 0; 3006 3007 remove_min_req: 3008 freq_qos_remove_request(req); 3009 free_req: 3010 kfree(req); 3011 pstate_exit: 3012 intel_pstate_exit_perf_limits(policy); 3013 3014 return ret; 3015 } 3016 3017 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3018 { 3019 struct freq_qos_request *req; 3020 3021 req = policy->driver_data; 3022 3023 freq_qos_remove_request(req + 1); 3024 freq_qos_remove_request(req); 3025 kfree(req); 3026 3027 return intel_pstate_cpu_exit(policy); 3028 } 3029 3030 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3031 { 3032 intel_pstate_suspend(policy); 3033 3034 if (hwp_active) { 3035 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3036 u64 value = READ_ONCE(cpu->hwp_req_cached); 3037 3038 /* 3039 * Clear the desired perf field in MSR_HWP_REQUEST in case 3040 * intel_cpufreq_adjust_perf() is in use and the last value 3041 * written by it may not be suitable. 3042 */ 3043 value &= ~HWP_DESIRED_PERF(~0L); 3044 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3045 WRITE_ONCE(cpu->hwp_req_cached, value); 3046 } 3047 3048 return 0; 3049 } 3050 3051 static struct cpufreq_driver intel_cpufreq = { 3052 .flags = CPUFREQ_CONST_LOOPS, 3053 .verify = intel_cpufreq_verify_policy, 3054 .target = intel_cpufreq_target, 3055 .fast_switch = intel_cpufreq_fast_switch, 3056 .init = intel_cpufreq_cpu_init, 3057 .exit = intel_cpufreq_cpu_exit, 3058 .offline = intel_cpufreq_cpu_offline, 3059 .online = intel_pstate_cpu_online, 3060 .suspend = intel_cpufreq_suspend, 3061 .resume = intel_pstate_resume, 3062 .update_limits = intel_pstate_update_limits, 3063 .name = "intel_cpufreq", 3064 }; 3065 3066 static struct cpufreq_driver *default_driver; 3067 3068 static void intel_pstate_driver_cleanup(void) 3069 { 3070 unsigned int cpu; 3071 3072 cpus_read_lock(); 3073 for_each_online_cpu(cpu) { 3074 if (all_cpu_data[cpu]) { 3075 if (intel_pstate_driver == &intel_pstate) 3076 intel_pstate_clear_update_util_hook(cpu); 3077 3078 spin_lock(&hwp_notify_lock); 3079 kfree(all_cpu_data[cpu]); 3080 WRITE_ONCE(all_cpu_data[cpu], NULL); 3081 spin_unlock(&hwp_notify_lock); 3082 } 3083 } 3084 cpus_read_unlock(); 3085 3086 intel_pstate_driver = NULL; 3087 } 3088 3089 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3090 { 3091 int ret; 3092 3093 if (driver == &intel_pstate) 3094 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3095 3096 memset(&global, 0, sizeof(global)); 3097 global.max_perf_pct = 100; 3098 3099 intel_pstate_driver = driver; 3100 ret = cpufreq_register_driver(intel_pstate_driver); 3101 if (ret) { 3102 intel_pstate_driver_cleanup(); 3103 return ret; 3104 } 3105 3106 global.min_perf_pct = min_perf_pct_min(); 3107 3108 return 0; 3109 } 3110 3111 static ssize_t intel_pstate_show_status(char *buf) 3112 { 3113 if (!intel_pstate_driver) 3114 return sprintf(buf, "off\n"); 3115 3116 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3117 "active" : "passive"); 3118 } 3119 3120 static int intel_pstate_update_status(const char *buf, size_t size) 3121 { 3122 if (size == 3 && !strncmp(buf, "off", size)) { 3123 if (!intel_pstate_driver) 3124 return -EINVAL; 3125 3126 if (hwp_active) 3127 return -EBUSY; 3128 3129 cpufreq_unregister_driver(intel_pstate_driver); 3130 intel_pstate_driver_cleanup(); 3131 return 0; 3132 } 3133 3134 if (size == 6 && !strncmp(buf, "active", size)) { 3135 if (intel_pstate_driver) { 3136 if (intel_pstate_driver == &intel_pstate) 3137 return 0; 3138 3139 cpufreq_unregister_driver(intel_pstate_driver); 3140 } 3141 3142 return intel_pstate_register_driver(&intel_pstate); 3143 } 3144 3145 if (size == 7 && !strncmp(buf, "passive", size)) { 3146 if (intel_pstate_driver) { 3147 if (intel_pstate_driver == &intel_cpufreq) 3148 return 0; 3149 3150 cpufreq_unregister_driver(intel_pstate_driver); 3151 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3152 } 3153 3154 return intel_pstate_register_driver(&intel_cpufreq); 3155 } 3156 3157 return -EINVAL; 3158 } 3159 3160 static int no_load __initdata; 3161 static int no_hwp __initdata; 3162 static int hwp_only __initdata; 3163 static unsigned int force_load __initdata; 3164 3165 static int __init intel_pstate_msrs_not_valid(void) 3166 { 3167 if (!pstate_funcs.get_max() || 3168 !pstate_funcs.get_min() || 3169 !pstate_funcs.get_turbo()) 3170 return -ENODEV; 3171 3172 return 0; 3173 } 3174 3175 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3176 { 3177 pstate_funcs.get_max = funcs->get_max; 3178 pstate_funcs.get_max_physical = funcs->get_max_physical; 3179 pstate_funcs.get_min = funcs->get_min; 3180 pstate_funcs.get_turbo = funcs->get_turbo; 3181 pstate_funcs.get_scaling = funcs->get_scaling; 3182 pstate_funcs.get_val = funcs->get_val; 3183 pstate_funcs.get_vid = funcs->get_vid; 3184 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3185 } 3186 3187 #ifdef CONFIG_ACPI 3188 3189 static bool __init intel_pstate_no_acpi_pss(void) 3190 { 3191 int i; 3192 3193 for_each_possible_cpu(i) { 3194 acpi_status status; 3195 union acpi_object *pss; 3196 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3197 struct acpi_processor *pr = per_cpu(processors, i); 3198 3199 if (!pr) 3200 continue; 3201 3202 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3203 if (ACPI_FAILURE(status)) 3204 continue; 3205 3206 pss = buffer.pointer; 3207 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3208 kfree(pss); 3209 return false; 3210 } 3211 3212 kfree(pss); 3213 } 3214 3215 pr_debug("ACPI _PSS not found\n"); 3216 return true; 3217 } 3218 3219 static bool __init intel_pstate_no_acpi_pcch(void) 3220 { 3221 acpi_status status; 3222 acpi_handle handle; 3223 3224 status = acpi_get_handle(NULL, "\\_SB", &handle); 3225 if (ACPI_FAILURE(status)) 3226 goto not_found; 3227 3228 if (acpi_has_method(handle, "PCCH")) 3229 return false; 3230 3231 not_found: 3232 pr_debug("ACPI PCCH not found\n"); 3233 return true; 3234 } 3235 3236 static bool __init intel_pstate_has_acpi_ppc(void) 3237 { 3238 int i; 3239 3240 for_each_possible_cpu(i) { 3241 struct acpi_processor *pr = per_cpu(processors, i); 3242 3243 if (!pr) 3244 continue; 3245 if (acpi_has_method(pr->handle, "_PPC")) 3246 return true; 3247 } 3248 pr_debug("ACPI _PPC not found\n"); 3249 return false; 3250 } 3251 3252 enum { 3253 PSS, 3254 PPC, 3255 }; 3256 3257 /* Hardware vendor-specific info that has its own power management modes */ 3258 static struct acpi_platform_list plat_info[] __initdata = { 3259 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3260 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3261 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3262 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3263 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3264 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3265 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3266 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3267 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3268 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3269 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3270 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3271 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3272 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3273 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3274 { } /* End */ 3275 }; 3276 3277 #define BITMASK_OOB (BIT(8) | BIT(18)) 3278 3279 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3280 { 3281 const struct x86_cpu_id *id; 3282 u64 misc_pwr; 3283 int idx; 3284 3285 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3286 if (id) { 3287 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3288 if (misc_pwr & BITMASK_OOB) { 3289 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3290 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3291 return true; 3292 } 3293 } 3294 3295 idx = acpi_match_platform_list(plat_info); 3296 if (idx < 0) 3297 return false; 3298 3299 switch (plat_info[idx].data) { 3300 case PSS: 3301 if (!intel_pstate_no_acpi_pss()) 3302 return false; 3303 3304 return intel_pstate_no_acpi_pcch(); 3305 case PPC: 3306 return intel_pstate_has_acpi_ppc() && !force_load; 3307 } 3308 3309 return false; 3310 } 3311 3312 static void intel_pstate_request_control_from_smm(void) 3313 { 3314 /* 3315 * It may be unsafe to request P-states control from SMM if _PPC support 3316 * has not been enabled. 3317 */ 3318 if (acpi_ppc) 3319 acpi_processor_pstate_control(); 3320 } 3321 #else /* CONFIG_ACPI not enabled */ 3322 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3323 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3324 static inline void intel_pstate_request_control_from_smm(void) {} 3325 #endif /* CONFIG_ACPI */ 3326 3327 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3328 3329 #define X86_MATCH_HWP(model, hwp_mode) \ 3330 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3331 X86_FEATURE_HWP, hwp_mode) 3332 3333 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3334 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3335 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3336 X86_MATCH_HWP(ANY, 0), 3337 {} 3338 }; 3339 3340 static bool intel_pstate_hwp_is_enabled(void) 3341 { 3342 u64 value; 3343 3344 rdmsrl(MSR_PM_ENABLE, value); 3345 return !!(value & 0x1); 3346 } 3347 3348 static int __init intel_pstate_init(void) 3349 { 3350 static struct cpudata **_all_cpu_data; 3351 const struct x86_cpu_id *id; 3352 int rc; 3353 3354 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3355 return -ENODEV; 3356 3357 id = x86_match_cpu(hwp_support_ids); 3358 if (id) { 3359 bool hwp_forced = intel_pstate_hwp_is_enabled(); 3360 3361 if (hwp_forced) 3362 pr_info("HWP enabled by BIOS\n"); 3363 else if (no_load) 3364 return -ENODEV; 3365 3366 copy_cpu_funcs(&core_funcs); 3367 /* 3368 * Avoid enabling HWP for processors without EPP support, 3369 * because that means incomplete HWP implementation which is a 3370 * corner case and supporting it is generally problematic. 3371 * 3372 * If HWP is enabled already, though, there is no choice but to 3373 * deal with it. 3374 */ 3375 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3376 WRITE_ONCE(hwp_active, 1); 3377 hwp_mode_bdw = id->driver_data; 3378 intel_pstate.attr = hwp_cpufreq_attrs; 3379 intel_cpufreq.attr = hwp_cpufreq_attrs; 3380 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3381 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3382 if (!default_driver) 3383 default_driver = &intel_pstate; 3384 3385 if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) 3386 intel_pstate_cppc_set_cpu_scaling(); 3387 3388 goto hwp_cpu_matched; 3389 } 3390 pr_info("HWP not enabled\n"); 3391 } else { 3392 if (no_load) 3393 return -ENODEV; 3394 3395 id = x86_match_cpu(intel_pstate_cpu_ids); 3396 if (!id) { 3397 pr_info("CPU model not supported\n"); 3398 return -ENODEV; 3399 } 3400 3401 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3402 } 3403 3404 if (intel_pstate_msrs_not_valid()) { 3405 pr_info("Invalid MSRs\n"); 3406 return -ENODEV; 3407 } 3408 /* Without HWP start in the passive mode. */ 3409 if (!default_driver) 3410 default_driver = &intel_cpufreq; 3411 3412 hwp_cpu_matched: 3413 /* 3414 * The Intel pstate driver will be ignored if the platform 3415 * firmware has its own power management modes. 3416 */ 3417 if (intel_pstate_platform_pwr_mgmt_exists()) { 3418 pr_info("P-states controlled by the platform\n"); 3419 return -ENODEV; 3420 } 3421 3422 if (!hwp_active && hwp_only) 3423 return -ENOTSUPP; 3424 3425 pr_info("Intel P-state driver initializing\n"); 3426 3427 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3428 if (!_all_cpu_data) 3429 return -ENOMEM; 3430 3431 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3432 3433 intel_pstate_request_control_from_smm(); 3434 3435 intel_pstate_sysfs_expose_params(); 3436 3437 mutex_lock(&intel_pstate_driver_lock); 3438 rc = intel_pstate_register_driver(default_driver); 3439 mutex_unlock(&intel_pstate_driver_lock); 3440 if (rc) { 3441 intel_pstate_sysfs_remove(); 3442 return rc; 3443 } 3444 3445 if (hwp_active) { 3446 const struct x86_cpu_id *id; 3447 3448 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3449 if (id) { 3450 set_power_ctl_ee_state(false); 3451 pr_info("Disabling energy efficiency optimization\n"); 3452 } 3453 3454 pr_info("HWP enabled\n"); 3455 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3456 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3457 } 3458 3459 return 0; 3460 } 3461 device_initcall(intel_pstate_init); 3462 3463 static int __init intel_pstate_setup(char *str) 3464 { 3465 if (!str) 3466 return -EINVAL; 3467 3468 if (!strcmp(str, "disable")) 3469 no_load = 1; 3470 else if (!strcmp(str, "active")) 3471 default_driver = &intel_pstate; 3472 else if (!strcmp(str, "passive")) 3473 default_driver = &intel_cpufreq; 3474 3475 if (!strcmp(str, "no_hwp")) 3476 no_hwp = 1; 3477 3478 if (!strcmp(str, "force")) 3479 force_load = 1; 3480 if (!strcmp(str, "hwp_only")) 3481 hwp_only = 1; 3482 if (!strcmp(str, "per_cpu_perf_limits")) 3483 per_cpu_limits = true; 3484 3485 #ifdef CONFIG_ACPI 3486 if (!strcmp(str, "support_acpi_ppc")) 3487 acpi_ppc = true; 3488 #endif 3489 3490 return 0; 3491 } 3492 early_param("intel_pstate", intel_pstate_setup); 3493 3494 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3495 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3496 MODULE_LICENSE("GPL"); 3497