1 /* 2 * intel_pstate.c: Native P state management for Intel processors 3 * 4 * (C) Copyright 2012 Intel Corporation 5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/kernel.h> 16 #include <linux/kernel_stat.h> 17 #include <linux/module.h> 18 #include <linux/ktime.h> 19 #include <linux/hrtimer.h> 20 #include <linux/tick.h> 21 #include <linux/slab.h> 22 #include <linux/sched.h> 23 #include <linux/list.h> 24 #include <linux/cpu.h> 25 #include <linux/cpufreq.h> 26 #include <linux/sysfs.h> 27 #include <linux/types.h> 28 #include <linux/fs.h> 29 #include <linux/debugfs.h> 30 #include <linux/acpi.h> 31 #include <linux/vmalloc.h> 32 #include <trace/events/power.h> 33 34 #include <asm/div64.h> 35 #include <asm/msr.h> 36 #include <asm/cpu_device_id.h> 37 #include <asm/cpufeature.h> 38 #include <asm/intel-family.h> 39 40 #define ATOM_RATIOS 0x66a 41 #define ATOM_VIDS 0x66b 42 #define ATOM_TURBO_RATIOS 0x66c 43 #define ATOM_TURBO_VIDS 0x66d 44 45 #ifdef CONFIG_ACPI 46 #include <acpi/processor.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define EXT_BITS 6 54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 55 56 static inline int32_t mul_fp(int32_t x, int32_t y) 57 { 58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 59 } 60 61 static inline int32_t div_fp(s64 x, s64 y) 62 { 63 return div64_s64((int64_t)x << FRAC_BITS, y); 64 } 65 66 static inline int ceiling_fp(int32_t x) 67 { 68 int mask, ret; 69 70 ret = fp_toint(x); 71 mask = (1 << FRAC_BITS) - 1; 72 if (x & mask) 73 ret += 1; 74 return ret; 75 } 76 77 static inline u64 mul_ext_fp(u64 x, u64 y) 78 { 79 return (x * y) >> EXT_FRAC_BITS; 80 } 81 82 static inline u64 div_ext_fp(u64 x, u64 y) 83 { 84 return div64_u64(x << EXT_FRAC_BITS, y); 85 } 86 87 /** 88 * struct sample - Store performance sample 89 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 90 * performance during last sample period 91 * @busy_scaled: Scaled busy value which is used to calculate next 92 * P state. This can be different than core_avg_perf 93 * to account for cpu idle period 94 * @aperf: Difference of actual performance frequency clock count 95 * read from APERF MSR between last and current sample 96 * @mperf: Difference of maximum performance frequency clock count 97 * read from MPERF MSR between last and current sample 98 * @tsc: Difference of time stamp counter between last and 99 * current sample 100 * @time: Current time from scheduler 101 * 102 * This structure is used in the cpudata structure to store performance sample 103 * data for choosing next P State. 104 */ 105 struct sample { 106 int32_t core_avg_perf; 107 int32_t busy_scaled; 108 u64 aperf; 109 u64 mperf; 110 u64 tsc; 111 u64 time; 112 }; 113 114 /** 115 * struct pstate_data - Store P state data 116 * @current_pstate: Current requested P state 117 * @min_pstate: Min P state possible for this platform 118 * @max_pstate: Max P state possible for this platform 119 * @max_pstate_physical:This is physical Max P state for a processor 120 * This can be higher than the max_pstate which can 121 * be limited by platform thermal design power limits 122 * @scaling: Scaling factor to convert frequency to cpufreq 123 * frequency units 124 * @turbo_pstate: Max Turbo P state possible for this platform 125 * 126 * Stores the per cpu model P state limits and current P state. 127 */ 128 struct pstate_data { 129 int current_pstate; 130 int min_pstate; 131 int max_pstate; 132 int max_pstate_physical; 133 int scaling; 134 int turbo_pstate; 135 }; 136 137 /** 138 * struct vid_data - Stores voltage information data 139 * @min: VID data for this platform corresponding to 140 * the lowest P state 141 * @max: VID data corresponding to the highest P State. 142 * @turbo: VID data for turbo P state 143 * @ratio: Ratio of (vid max - vid min) / 144 * (max P state - Min P State) 145 * 146 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 147 * This data is used in Atom platforms, where in addition to target P state, 148 * the voltage data needs to be specified to select next P State. 149 */ 150 struct vid_data { 151 int min; 152 int max; 153 int turbo; 154 int32_t ratio; 155 }; 156 157 /** 158 * struct _pid - Stores PID data 159 * @setpoint: Target set point for busyness or performance 160 * @integral: Storage for accumulated error values 161 * @p_gain: PID proportional gain 162 * @i_gain: PID integral gain 163 * @d_gain: PID derivative gain 164 * @deadband: PID deadband 165 * @last_err: Last error storage for integral part of PID calculation 166 * 167 * Stores PID coefficients and last error for PID controller. 168 */ 169 struct _pid { 170 int setpoint; 171 int32_t integral; 172 int32_t p_gain; 173 int32_t i_gain; 174 int32_t d_gain; 175 int deadband; 176 int32_t last_err; 177 }; 178 179 /** 180 * struct cpudata - Per CPU instance data storage 181 * @cpu: CPU number for this instance data 182 * @update_util: CPUFreq utility callback information 183 * @update_util_set: CPUFreq utility callback is set 184 * @pstate: Stores P state limits for this CPU 185 * @vid: Stores VID limits for this CPU 186 * @pid: Stores PID parameters for this CPU 187 * @last_sample_time: Last Sample time 188 * @prev_aperf: Last APERF value read from APERF MSR 189 * @prev_mperf: Last MPERF value read from MPERF MSR 190 * @prev_tsc: Last timestamp counter (TSC) value 191 * @prev_cummulative_iowait: IO Wait time difference from last and 192 * current sample 193 * @sample: Storage for storing last Sample data 194 * @acpi_perf_data: Stores ACPI perf information read from _PSS 195 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 196 * 197 * This structure stores per CPU instance data for all CPUs. 198 */ 199 struct cpudata { 200 int cpu; 201 202 struct update_util_data update_util; 203 bool update_util_set; 204 205 struct pstate_data pstate; 206 struct vid_data vid; 207 struct _pid pid; 208 209 u64 last_sample_time; 210 u64 prev_aperf; 211 u64 prev_mperf; 212 u64 prev_tsc; 213 u64 prev_cummulative_iowait; 214 struct sample sample; 215 #ifdef CONFIG_ACPI 216 struct acpi_processor_performance acpi_perf_data; 217 bool valid_pss_table; 218 #endif 219 }; 220 221 static struct cpudata **all_cpu_data; 222 223 /** 224 * struct pid_adjust_policy - Stores static PID configuration data 225 * @sample_rate_ms: PID calculation sample rate in ms 226 * @sample_rate_ns: Sample rate calculation in ns 227 * @deadband: PID deadband 228 * @setpoint: PID Setpoint 229 * @p_gain_pct: PID proportional gain 230 * @i_gain_pct: PID integral gain 231 * @d_gain_pct: PID derivative gain 232 * 233 * Stores per CPU model static PID configuration data. 234 */ 235 struct pstate_adjust_policy { 236 int sample_rate_ms; 237 s64 sample_rate_ns; 238 int deadband; 239 int setpoint; 240 int p_gain_pct; 241 int d_gain_pct; 242 int i_gain_pct; 243 }; 244 245 /** 246 * struct pstate_funcs - Per CPU model specific callbacks 247 * @get_max: Callback to get maximum non turbo effective P state 248 * @get_max_physical: Callback to get maximum non turbo physical P state 249 * @get_min: Callback to get minimum P state 250 * @get_turbo: Callback to get turbo P state 251 * @get_scaling: Callback to get frequency scaling factor 252 * @get_val: Callback to convert P state to actual MSR write value 253 * @get_vid: Callback to get VID data for Atom platforms 254 * @get_target_pstate: Callback to a function to calculate next P state to use 255 * 256 * Core and Atom CPU models have different way to get P State limits. This 257 * structure is used to store those callbacks. 258 */ 259 struct pstate_funcs { 260 int (*get_max)(void); 261 int (*get_max_physical)(void); 262 int (*get_min)(void); 263 int (*get_turbo)(void); 264 int (*get_scaling)(void); 265 u64 (*get_val)(struct cpudata*, int pstate); 266 void (*get_vid)(struct cpudata *); 267 int32_t (*get_target_pstate)(struct cpudata *); 268 }; 269 270 /** 271 * struct cpu_defaults- Per CPU model default config data 272 * @pid_policy: PID config data 273 * @funcs: Callback function data 274 */ 275 struct cpu_defaults { 276 struct pstate_adjust_policy pid_policy; 277 struct pstate_funcs funcs; 278 }; 279 280 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); 281 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); 282 283 static struct pstate_adjust_policy pid_params __read_mostly; 284 static struct pstate_funcs pstate_funcs __read_mostly; 285 static int hwp_active __read_mostly; 286 287 #ifdef CONFIG_ACPI 288 static bool acpi_ppc; 289 #endif 290 291 /** 292 * struct perf_limits - Store user and policy limits 293 * @no_turbo: User requested turbo state from intel_pstate sysfs 294 * @turbo_disabled: Platform turbo status either from msr 295 * MSR_IA32_MISC_ENABLE or when maximum available pstate 296 * matches the maximum turbo pstate 297 * @max_perf_pct: Effective maximum performance limit in percentage, this 298 * is minimum of either limits enforced by cpufreq policy 299 * or limits from user set limits via intel_pstate sysfs 300 * @min_perf_pct: Effective minimum performance limit in percentage, this 301 * is maximum of either limits enforced by cpufreq policy 302 * or limits from user set limits via intel_pstate sysfs 303 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct 304 * This value is used to limit max pstate 305 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct 306 * This value is used to limit min pstate 307 * @max_policy_pct: The maximum performance in percentage enforced by 308 * cpufreq setpolicy interface 309 * @max_sysfs_pct: The maximum performance in percentage enforced by 310 * intel pstate sysfs interface 311 * @min_policy_pct: The minimum performance in percentage enforced by 312 * cpufreq setpolicy interface 313 * @min_sysfs_pct: The minimum performance in percentage enforced by 314 * intel pstate sysfs interface 315 * 316 * Storage for user and policy defined limits. 317 */ 318 struct perf_limits { 319 int no_turbo; 320 int turbo_disabled; 321 int max_perf_pct; 322 int min_perf_pct; 323 int32_t max_perf; 324 int32_t min_perf; 325 int max_policy_pct; 326 int max_sysfs_pct; 327 int min_policy_pct; 328 int min_sysfs_pct; 329 }; 330 331 static struct perf_limits performance_limits = { 332 .no_turbo = 0, 333 .turbo_disabled = 0, 334 .max_perf_pct = 100, 335 .max_perf = int_tofp(1), 336 .min_perf_pct = 100, 337 .min_perf = int_tofp(1), 338 .max_policy_pct = 100, 339 .max_sysfs_pct = 100, 340 .min_policy_pct = 0, 341 .min_sysfs_pct = 0, 342 }; 343 344 static struct perf_limits powersave_limits = { 345 .no_turbo = 0, 346 .turbo_disabled = 0, 347 .max_perf_pct = 100, 348 .max_perf = int_tofp(1), 349 .min_perf_pct = 0, 350 .min_perf = 0, 351 .max_policy_pct = 100, 352 .max_sysfs_pct = 100, 353 .min_policy_pct = 0, 354 .min_sysfs_pct = 0, 355 }; 356 357 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE 358 static struct perf_limits *limits = &performance_limits; 359 #else 360 static struct perf_limits *limits = &powersave_limits; 361 #endif 362 363 #ifdef CONFIG_ACPI 364 365 static bool intel_pstate_get_ppc_enable_status(void) 366 { 367 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 368 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 369 return true; 370 371 return acpi_ppc; 372 } 373 374 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 375 { 376 struct cpudata *cpu; 377 int ret; 378 int i; 379 380 if (hwp_active) 381 return; 382 383 if (!intel_pstate_get_ppc_enable_status()) 384 return; 385 386 cpu = all_cpu_data[policy->cpu]; 387 388 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 389 policy->cpu); 390 if (ret) 391 return; 392 393 /* 394 * Check if the control value in _PSS is for PERF_CTL MSR, which should 395 * guarantee that the states returned by it map to the states in our 396 * list directly. 397 */ 398 if (cpu->acpi_perf_data.control_register.space_id != 399 ACPI_ADR_SPACE_FIXED_HARDWARE) 400 goto err; 401 402 /* 403 * If there is only one entry _PSS, simply ignore _PSS and continue as 404 * usual without taking _PSS into account 405 */ 406 if (cpu->acpi_perf_data.state_count < 2) 407 goto err; 408 409 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 410 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 411 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 412 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 413 (u32) cpu->acpi_perf_data.states[i].core_frequency, 414 (u32) cpu->acpi_perf_data.states[i].power, 415 (u32) cpu->acpi_perf_data.states[i].control); 416 } 417 418 /* 419 * The _PSS table doesn't contain whole turbo frequency range. 420 * This just contains +1 MHZ above the max non turbo frequency, 421 * with control value corresponding to max turbo ratio. But 422 * when cpufreq set policy is called, it will call with this 423 * max frequency, which will cause a reduced performance as 424 * this driver uses real max turbo frequency as the max 425 * frequency. So correct this frequency in _PSS table to 426 * correct max turbo frequency based on the turbo state. 427 * Also need to convert to MHz as _PSS freq is in MHz. 428 */ 429 if (!limits->turbo_disabled) 430 cpu->acpi_perf_data.states[0].core_frequency = 431 policy->cpuinfo.max_freq / 1000; 432 cpu->valid_pss_table = true; 433 pr_debug("_PPC limits will be enforced\n"); 434 435 return; 436 437 err: 438 cpu->valid_pss_table = false; 439 acpi_processor_unregister_performance(policy->cpu); 440 } 441 442 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 443 { 444 struct cpudata *cpu; 445 446 cpu = all_cpu_data[policy->cpu]; 447 if (!cpu->valid_pss_table) 448 return; 449 450 acpi_processor_unregister_performance(policy->cpu); 451 } 452 453 #else 454 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 455 { 456 } 457 458 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 459 { 460 } 461 #endif 462 463 static inline void pid_reset(struct _pid *pid, int setpoint, int busy, 464 int deadband, int integral) { 465 pid->setpoint = int_tofp(setpoint); 466 pid->deadband = int_tofp(deadband); 467 pid->integral = int_tofp(integral); 468 pid->last_err = int_tofp(setpoint) - int_tofp(busy); 469 } 470 471 static inline void pid_p_gain_set(struct _pid *pid, int percent) 472 { 473 pid->p_gain = div_fp(percent, 100); 474 } 475 476 static inline void pid_i_gain_set(struct _pid *pid, int percent) 477 { 478 pid->i_gain = div_fp(percent, 100); 479 } 480 481 static inline void pid_d_gain_set(struct _pid *pid, int percent) 482 { 483 pid->d_gain = div_fp(percent, 100); 484 } 485 486 static signed int pid_calc(struct _pid *pid, int32_t busy) 487 { 488 signed int result; 489 int32_t pterm, dterm, fp_error; 490 int32_t integral_limit; 491 492 fp_error = pid->setpoint - busy; 493 494 if (abs(fp_error) <= pid->deadband) 495 return 0; 496 497 pterm = mul_fp(pid->p_gain, fp_error); 498 499 pid->integral += fp_error; 500 501 /* 502 * We limit the integral here so that it will never 503 * get higher than 30. This prevents it from becoming 504 * too large an input over long periods of time and allows 505 * it to get factored out sooner. 506 * 507 * The value of 30 was chosen through experimentation. 508 */ 509 integral_limit = int_tofp(30); 510 if (pid->integral > integral_limit) 511 pid->integral = integral_limit; 512 if (pid->integral < -integral_limit) 513 pid->integral = -integral_limit; 514 515 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); 516 pid->last_err = fp_error; 517 518 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; 519 result = result + (1 << (FRAC_BITS-1)); 520 return (signed int)fp_toint(result); 521 } 522 523 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) 524 { 525 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); 526 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); 527 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); 528 529 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); 530 } 531 532 static inline void intel_pstate_reset_all_pid(void) 533 { 534 unsigned int cpu; 535 536 for_each_online_cpu(cpu) { 537 if (all_cpu_data[cpu]) 538 intel_pstate_busy_pid_reset(all_cpu_data[cpu]); 539 } 540 } 541 542 static inline void update_turbo_state(void) 543 { 544 u64 misc_en; 545 struct cpudata *cpu; 546 547 cpu = all_cpu_data[0]; 548 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 549 limits->turbo_disabled = 550 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 551 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 552 } 553 554 static void intel_pstate_hwp_set(const struct cpumask *cpumask) 555 { 556 int min, hw_min, max, hw_max, cpu, range, adj_range; 557 u64 value, cap; 558 559 rdmsrl(MSR_HWP_CAPABILITIES, cap); 560 hw_min = HWP_LOWEST_PERF(cap); 561 hw_max = HWP_HIGHEST_PERF(cap); 562 range = hw_max - hw_min; 563 564 for_each_cpu(cpu, cpumask) { 565 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 566 adj_range = limits->min_perf_pct * range / 100; 567 min = hw_min + adj_range; 568 value &= ~HWP_MIN_PERF(~0L); 569 value |= HWP_MIN_PERF(min); 570 571 adj_range = limits->max_perf_pct * range / 100; 572 max = hw_min + adj_range; 573 if (limits->no_turbo) { 574 hw_max = HWP_GUARANTEED_PERF(cap); 575 if (hw_max < max) 576 max = hw_max; 577 } 578 579 value &= ~HWP_MAX_PERF(~0L); 580 value |= HWP_MAX_PERF(max); 581 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 582 } 583 } 584 585 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) 586 { 587 if (hwp_active) 588 intel_pstate_hwp_set(policy->cpus); 589 590 return 0; 591 } 592 593 static void intel_pstate_hwp_set_online_cpus(void) 594 { 595 get_online_cpus(); 596 intel_pstate_hwp_set(cpu_online_mask); 597 put_online_cpus(); 598 } 599 600 /************************** debugfs begin ************************/ 601 static int pid_param_set(void *data, u64 val) 602 { 603 *(u32 *)data = val; 604 intel_pstate_reset_all_pid(); 605 return 0; 606 } 607 608 static int pid_param_get(void *data, u64 *val) 609 { 610 *val = *(u32 *)data; 611 return 0; 612 } 613 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); 614 615 struct pid_param { 616 char *name; 617 void *value; 618 }; 619 620 static struct pid_param pid_files[] = { 621 {"sample_rate_ms", &pid_params.sample_rate_ms}, 622 {"d_gain_pct", &pid_params.d_gain_pct}, 623 {"i_gain_pct", &pid_params.i_gain_pct}, 624 {"deadband", &pid_params.deadband}, 625 {"setpoint", &pid_params.setpoint}, 626 {"p_gain_pct", &pid_params.p_gain_pct}, 627 {NULL, NULL} 628 }; 629 630 static void __init intel_pstate_debug_expose_params(void) 631 { 632 struct dentry *debugfs_parent; 633 int i = 0; 634 635 if (hwp_active) 636 return; 637 debugfs_parent = debugfs_create_dir("pstate_snb", NULL); 638 if (IS_ERR_OR_NULL(debugfs_parent)) 639 return; 640 while (pid_files[i].name) { 641 debugfs_create_file(pid_files[i].name, 0660, 642 debugfs_parent, pid_files[i].value, 643 &fops_pid_param); 644 i++; 645 } 646 } 647 648 /************************** debugfs end ************************/ 649 650 /************************** sysfs begin ************************/ 651 #define show_one(file_name, object) \ 652 static ssize_t show_##file_name \ 653 (struct kobject *kobj, struct attribute *attr, char *buf) \ 654 { \ 655 return sprintf(buf, "%u\n", limits->object); \ 656 } 657 658 static ssize_t show_turbo_pct(struct kobject *kobj, 659 struct attribute *attr, char *buf) 660 { 661 struct cpudata *cpu; 662 int total, no_turbo, turbo_pct; 663 uint32_t turbo_fp; 664 665 cpu = all_cpu_data[0]; 666 667 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 668 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 669 turbo_fp = div_fp(no_turbo, total); 670 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 671 return sprintf(buf, "%u\n", turbo_pct); 672 } 673 674 static ssize_t show_num_pstates(struct kobject *kobj, 675 struct attribute *attr, char *buf) 676 { 677 struct cpudata *cpu; 678 int total; 679 680 cpu = all_cpu_data[0]; 681 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 682 return sprintf(buf, "%u\n", total); 683 } 684 685 static ssize_t show_no_turbo(struct kobject *kobj, 686 struct attribute *attr, char *buf) 687 { 688 ssize_t ret; 689 690 update_turbo_state(); 691 if (limits->turbo_disabled) 692 ret = sprintf(buf, "%u\n", limits->turbo_disabled); 693 else 694 ret = sprintf(buf, "%u\n", limits->no_turbo); 695 696 return ret; 697 } 698 699 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, 700 const char *buf, size_t count) 701 { 702 unsigned int input; 703 int ret; 704 705 ret = sscanf(buf, "%u", &input); 706 if (ret != 1) 707 return -EINVAL; 708 709 update_turbo_state(); 710 if (limits->turbo_disabled) { 711 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 712 return -EPERM; 713 } 714 715 limits->no_turbo = clamp_t(int, input, 0, 1); 716 717 if (hwp_active) 718 intel_pstate_hwp_set_online_cpus(); 719 720 return count; 721 } 722 723 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, 724 const char *buf, size_t count) 725 { 726 unsigned int input; 727 int ret; 728 729 ret = sscanf(buf, "%u", &input); 730 if (ret != 1) 731 return -EINVAL; 732 733 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); 734 limits->max_perf_pct = min(limits->max_policy_pct, 735 limits->max_sysfs_pct); 736 limits->max_perf_pct = max(limits->min_policy_pct, 737 limits->max_perf_pct); 738 limits->max_perf_pct = max(limits->min_perf_pct, 739 limits->max_perf_pct); 740 limits->max_perf = div_fp(limits->max_perf_pct, 100); 741 742 if (hwp_active) 743 intel_pstate_hwp_set_online_cpus(); 744 return count; 745 } 746 747 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, 748 const char *buf, size_t count) 749 { 750 unsigned int input; 751 int ret; 752 753 ret = sscanf(buf, "%u", &input); 754 if (ret != 1) 755 return -EINVAL; 756 757 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); 758 limits->min_perf_pct = max(limits->min_policy_pct, 759 limits->min_sysfs_pct); 760 limits->min_perf_pct = min(limits->max_policy_pct, 761 limits->min_perf_pct); 762 limits->min_perf_pct = min(limits->max_perf_pct, 763 limits->min_perf_pct); 764 limits->min_perf = div_fp(limits->min_perf_pct, 100); 765 766 if (hwp_active) 767 intel_pstate_hwp_set_online_cpus(); 768 return count; 769 } 770 771 show_one(max_perf_pct, max_perf_pct); 772 show_one(min_perf_pct, min_perf_pct); 773 774 define_one_global_rw(no_turbo); 775 define_one_global_rw(max_perf_pct); 776 define_one_global_rw(min_perf_pct); 777 define_one_global_ro(turbo_pct); 778 define_one_global_ro(num_pstates); 779 780 static struct attribute *intel_pstate_attributes[] = { 781 &no_turbo.attr, 782 &max_perf_pct.attr, 783 &min_perf_pct.attr, 784 &turbo_pct.attr, 785 &num_pstates.attr, 786 NULL 787 }; 788 789 static struct attribute_group intel_pstate_attr_group = { 790 .attrs = intel_pstate_attributes, 791 }; 792 793 static void __init intel_pstate_sysfs_expose_params(void) 794 { 795 struct kobject *intel_pstate_kobject; 796 int rc; 797 798 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 799 &cpu_subsys.dev_root->kobj); 800 BUG_ON(!intel_pstate_kobject); 801 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 802 BUG_ON(rc); 803 } 804 /************************** sysfs end ************************/ 805 806 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 807 { 808 /* First disable HWP notification interrupt as we don't process them */ 809 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 810 811 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 812 } 813 814 static int atom_get_min_pstate(void) 815 { 816 u64 value; 817 818 rdmsrl(ATOM_RATIOS, value); 819 return (value >> 8) & 0x7F; 820 } 821 822 static int atom_get_max_pstate(void) 823 { 824 u64 value; 825 826 rdmsrl(ATOM_RATIOS, value); 827 return (value >> 16) & 0x7F; 828 } 829 830 static int atom_get_turbo_pstate(void) 831 { 832 u64 value; 833 834 rdmsrl(ATOM_TURBO_RATIOS, value); 835 return value & 0x7F; 836 } 837 838 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 839 { 840 u64 val; 841 int32_t vid_fp; 842 u32 vid; 843 844 val = (u64)pstate << 8; 845 if (limits->no_turbo && !limits->turbo_disabled) 846 val |= (u64)1 << 32; 847 848 vid_fp = cpudata->vid.min + mul_fp( 849 int_tofp(pstate - cpudata->pstate.min_pstate), 850 cpudata->vid.ratio); 851 852 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 853 vid = ceiling_fp(vid_fp); 854 855 if (pstate > cpudata->pstate.max_pstate) 856 vid = cpudata->vid.turbo; 857 858 return val | vid; 859 } 860 861 static int silvermont_get_scaling(void) 862 { 863 u64 value; 864 int i; 865 /* Defined in Table 35-6 from SDM (Sept 2015) */ 866 static int silvermont_freq_table[] = { 867 83300, 100000, 133300, 116700, 80000}; 868 869 rdmsrl(MSR_FSB_FREQ, value); 870 i = value & 0x7; 871 WARN_ON(i > 4); 872 873 return silvermont_freq_table[i]; 874 } 875 876 static int airmont_get_scaling(void) 877 { 878 u64 value; 879 int i; 880 /* Defined in Table 35-10 from SDM (Sept 2015) */ 881 static int airmont_freq_table[] = { 882 83300, 100000, 133300, 116700, 80000, 883 93300, 90000, 88900, 87500}; 884 885 rdmsrl(MSR_FSB_FREQ, value); 886 i = value & 0xF; 887 WARN_ON(i > 8); 888 889 return airmont_freq_table[i]; 890 } 891 892 static void atom_get_vid(struct cpudata *cpudata) 893 { 894 u64 value; 895 896 rdmsrl(ATOM_VIDS, value); 897 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 898 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 899 cpudata->vid.ratio = div_fp( 900 cpudata->vid.max - cpudata->vid.min, 901 int_tofp(cpudata->pstate.max_pstate - 902 cpudata->pstate.min_pstate)); 903 904 rdmsrl(ATOM_TURBO_VIDS, value); 905 cpudata->vid.turbo = value & 0x7f; 906 } 907 908 static int core_get_min_pstate(void) 909 { 910 u64 value; 911 912 rdmsrl(MSR_PLATFORM_INFO, value); 913 return (value >> 40) & 0xFF; 914 } 915 916 static int core_get_max_pstate_physical(void) 917 { 918 u64 value; 919 920 rdmsrl(MSR_PLATFORM_INFO, value); 921 return (value >> 8) & 0xFF; 922 } 923 924 static int core_get_max_pstate(void) 925 { 926 u64 tar; 927 u64 plat_info; 928 int max_pstate; 929 int err; 930 931 rdmsrl(MSR_PLATFORM_INFO, plat_info); 932 max_pstate = (plat_info >> 8) & 0xFF; 933 934 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 935 if (!err) { 936 /* Do some sanity checking for safety */ 937 if (plat_info & 0x600000000) { 938 u64 tdp_ctrl; 939 u64 tdp_ratio; 940 int tdp_msr; 941 942 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 943 if (err) 944 goto skip_tar; 945 946 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3); 947 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 948 if (err) 949 goto skip_tar; 950 951 /* For level 1 and 2, bits[23:16] contain the ratio */ 952 if (tdp_ctrl) 953 tdp_ratio >>= 16; 954 955 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 956 if (tdp_ratio - 1 == tar) { 957 max_pstate = tar; 958 pr_debug("max_pstate=TAC %x\n", max_pstate); 959 } else { 960 goto skip_tar; 961 } 962 } 963 } 964 965 skip_tar: 966 return max_pstate; 967 } 968 969 static int core_get_turbo_pstate(void) 970 { 971 u64 value; 972 int nont, ret; 973 974 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 975 nont = core_get_max_pstate(); 976 ret = (value) & 255; 977 if (ret <= nont) 978 ret = nont; 979 return ret; 980 } 981 982 static inline int core_get_scaling(void) 983 { 984 return 100000; 985 } 986 987 static u64 core_get_val(struct cpudata *cpudata, int pstate) 988 { 989 u64 val; 990 991 val = (u64)pstate << 8; 992 if (limits->no_turbo && !limits->turbo_disabled) 993 val |= (u64)1 << 32; 994 995 return val; 996 } 997 998 static int knl_get_turbo_pstate(void) 999 { 1000 u64 value; 1001 int nont, ret; 1002 1003 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); 1004 nont = core_get_max_pstate(); 1005 ret = (((value) >> 8) & 0xFF); 1006 if (ret <= nont) 1007 ret = nont; 1008 return ret; 1009 } 1010 1011 static struct cpu_defaults core_params = { 1012 .pid_policy = { 1013 .sample_rate_ms = 10, 1014 .deadband = 0, 1015 .setpoint = 97, 1016 .p_gain_pct = 20, 1017 .d_gain_pct = 0, 1018 .i_gain_pct = 0, 1019 }, 1020 .funcs = { 1021 .get_max = core_get_max_pstate, 1022 .get_max_physical = core_get_max_pstate_physical, 1023 .get_min = core_get_min_pstate, 1024 .get_turbo = core_get_turbo_pstate, 1025 .get_scaling = core_get_scaling, 1026 .get_val = core_get_val, 1027 .get_target_pstate = get_target_pstate_use_performance, 1028 }, 1029 }; 1030 1031 static struct cpu_defaults silvermont_params = { 1032 .pid_policy = { 1033 .sample_rate_ms = 10, 1034 .deadband = 0, 1035 .setpoint = 60, 1036 .p_gain_pct = 14, 1037 .d_gain_pct = 0, 1038 .i_gain_pct = 4, 1039 }, 1040 .funcs = { 1041 .get_max = atom_get_max_pstate, 1042 .get_max_physical = atom_get_max_pstate, 1043 .get_min = atom_get_min_pstate, 1044 .get_turbo = atom_get_turbo_pstate, 1045 .get_val = atom_get_val, 1046 .get_scaling = silvermont_get_scaling, 1047 .get_vid = atom_get_vid, 1048 .get_target_pstate = get_target_pstate_use_cpu_load, 1049 }, 1050 }; 1051 1052 static struct cpu_defaults airmont_params = { 1053 .pid_policy = { 1054 .sample_rate_ms = 10, 1055 .deadband = 0, 1056 .setpoint = 60, 1057 .p_gain_pct = 14, 1058 .d_gain_pct = 0, 1059 .i_gain_pct = 4, 1060 }, 1061 .funcs = { 1062 .get_max = atom_get_max_pstate, 1063 .get_max_physical = atom_get_max_pstate, 1064 .get_min = atom_get_min_pstate, 1065 .get_turbo = atom_get_turbo_pstate, 1066 .get_val = atom_get_val, 1067 .get_scaling = airmont_get_scaling, 1068 .get_vid = atom_get_vid, 1069 .get_target_pstate = get_target_pstate_use_cpu_load, 1070 }, 1071 }; 1072 1073 static struct cpu_defaults knl_params = { 1074 .pid_policy = { 1075 .sample_rate_ms = 10, 1076 .deadband = 0, 1077 .setpoint = 97, 1078 .p_gain_pct = 20, 1079 .d_gain_pct = 0, 1080 .i_gain_pct = 0, 1081 }, 1082 .funcs = { 1083 .get_max = core_get_max_pstate, 1084 .get_max_physical = core_get_max_pstate_physical, 1085 .get_min = core_get_min_pstate, 1086 .get_turbo = knl_get_turbo_pstate, 1087 .get_scaling = core_get_scaling, 1088 .get_val = core_get_val, 1089 .get_target_pstate = get_target_pstate_use_performance, 1090 }, 1091 }; 1092 1093 static struct cpu_defaults bxt_params = { 1094 .pid_policy = { 1095 .sample_rate_ms = 10, 1096 .deadband = 0, 1097 .setpoint = 60, 1098 .p_gain_pct = 14, 1099 .d_gain_pct = 0, 1100 .i_gain_pct = 4, 1101 }, 1102 .funcs = { 1103 .get_max = core_get_max_pstate, 1104 .get_max_physical = core_get_max_pstate_physical, 1105 .get_min = core_get_min_pstate, 1106 .get_turbo = core_get_turbo_pstate, 1107 .get_scaling = core_get_scaling, 1108 .get_val = core_get_val, 1109 .get_target_pstate = get_target_pstate_use_cpu_load, 1110 }, 1111 }; 1112 1113 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) 1114 { 1115 int max_perf = cpu->pstate.turbo_pstate; 1116 int max_perf_adj; 1117 int min_perf; 1118 1119 if (limits->no_turbo || limits->turbo_disabled) 1120 max_perf = cpu->pstate.max_pstate; 1121 1122 /* 1123 * performance can be limited by user through sysfs, by cpufreq 1124 * policy, or by cpu specific default values determined through 1125 * experimentation. 1126 */ 1127 max_perf_adj = fp_toint(max_perf * limits->max_perf); 1128 *max = clamp_t(int, max_perf_adj, 1129 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); 1130 1131 min_perf = fp_toint(max_perf * limits->min_perf); 1132 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); 1133 } 1134 1135 static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate) 1136 { 1137 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1138 cpu->pstate.current_pstate = pstate; 1139 } 1140 1141 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1142 { 1143 int pstate = cpu->pstate.min_pstate; 1144 1145 intel_pstate_record_pstate(cpu, pstate); 1146 /* 1147 * Generally, there is no guarantee that this code will always run on 1148 * the CPU being updated, so force the register update to run on the 1149 * right CPU. 1150 */ 1151 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1152 pstate_funcs.get_val(cpu, pstate)); 1153 } 1154 1155 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1156 { 1157 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1158 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1159 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1160 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1161 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1162 1163 if (pstate_funcs.get_vid) 1164 pstate_funcs.get_vid(cpu); 1165 1166 intel_pstate_set_min_pstate(cpu); 1167 } 1168 1169 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1170 { 1171 struct sample *sample = &cpu->sample; 1172 1173 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1174 } 1175 1176 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1177 { 1178 u64 aperf, mperf; 1179 unsigned long flags; 1180 u64 tsc; 1181 1182 local_irq_save(flags); 1183 rdmsrl(MSR_IA32_APERF, aperf); 1184 rdmsrl(MSR_IA32_MPERF, mperf); 1185 tsc = rdtsc(); 1186 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1187 local_irq_restore(flags); 1188 return false; 1189 } 1190 local_irq_restore(flags); 1191 1192 cpu->last_sample_time = cpu->sample.time; 1193 cpu->sample.time = time; 1194 cpu->sample.aperf = aperf; 1195 cpu->sample.mperf = mperf; 1196 cpu->sample.tsc = tsc; 1197 cpu->sample.aperf -= cpu->prev_aperf; 1198 cpu->sample.mperf -= cpu->prev_mperf; 1199 cpu->sample.tsc -= cpu->prev_tsc; 1200 1201 cpu->prev_aperf = aperf; 1202 cpu->prev_mperf = mperf; 1203 cpu->prev_tsc = tsc; 1204 /* 1205 * First time this function is invoked in a given cycle, all of the 1206 * previous sample data fields are equal to zero or stale and they must 1207 * be populated with meaningful numbers for things to work, so assume 1208 * that sample.time will always be reset before setting the utilization 1209 * update hook and make the caller skip the sample then. 1210 */ 1211 return !!cpu->last_sample_time; 1212 } 1213 1214 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1215 { 1216 return mul_ext_fp(cpu->sample.core_avg_perf, 1217 cpu->pstate.max_pstate_physical * cpu->pstate.scaling); 1218 } 1219 1220 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1221 { 1222 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1223 cpu->sample.core_avg_perf); 1224 } 1225 1226 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) 1227 { 1228 struct sample *sample = &cpu->sample; 1229 u64 cummulative_iowait, delta_iowait_us; 1230 u64 delta_iowait_mperf; 1231 u64 mperf, now; 1232 int32_t cpu_load; 1233 1234 cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now); 1235 1236 /* 1237 * Convert iowait time into number of IO cycles spent at max_freq. 1238 * IO is considered as busy only for the cpu_load algorithm. For 1239 * performance this is not needed since we always try to reach the 1240 * maximum P-State, so we are already boosting the IOs. 1241 */ 1242 delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait; 1243 delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling * 1244 cpu->pstate.max_pstate, MSEC_PER_SEC); 1245 1246 mperf = cpu->sample.mperf + delta_iowait_mperf; 1247 cpu->prev_cummulative_iowait = cummulative_iowait; 1248 1249 /* 1250 * The load can be estimated as the ratio of the mperf counter 1251 * running at a constant frequency during active periods 1252 * (C0) and the time stamp counter running at the same frequency 1253 * also during C-states. 1254 */ 1255 cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc); 1256 cpu->sample.busy_scaled = cpu_load; 1257 1258 return get_avg_pstate(cpu) - pid_calc(&cpu->pid, cpu_load); 1259 } 1260 1261 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) 1262 { 1263 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; 1264 u64 duration_ns; 1265 1266 /* 1267 * perf_scaled is the average performance during the last sampling 1268 * period scaled by the ratio of the maximum P-state to the P-state 1269 * requested last time (in percent). That measures the system's 1270 * response to the previous P-state selection. 1271 */ 1272 max_pstate = cpu->pstate.max_pstate_physical; 1273 current_pstate = cpu->pstate.current_pstate; 1274 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, 1275 div_fp(100 * max_pstate, current_pstate)); 1276 1277 /* 1278 * Since our utilization update callback will not run unless we are 1279 * in C0, check if the actual elapsed time is significantly greater (3x) 1280 * than our sample interval. If it is, then we were idle for a long 1281 * enough period of time to adjust our performance metric. 1282 */ 1283 duration_ns = cpu->sample.time - cpu->last_sample_time; 1284 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { 1285 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); 1286 perf_scaled = mul_fp(perf_scaled, sample_ratio); 1287 } else { 1288 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); 1289 if (sample_ratio < int_tofp(1)) 1290 perf_scaled = 0; 1291 } 1292 1293 cpu->sample.busy_scaled = perf_scaled; 1294 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); 1295 } 1296 1297 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1298 { 1299 int max_perf, min_perf; 1300 1301 update_turbo_state(); 1302 1303 intel_pstate_get_min_max(cpu, &min_perf, &max_perf); 1304 pstate = clamp_t(int, pstate, min_perf, max_perf); 1305 if (pstate == cpu->pstate.current_pstate) 1306 return; 1307 1308 intel_pstate_record_pstate(cpu, pstate); 1309 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1310 } 1311 1312 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) 1313 { 1314 int from, target_pstate; 1315 struct sample *sample; 1316 1317 from = cpu->pstate.current_pstate; 1318 1319 target_pstate = pstate_funcs.get_target_pstate(cpu); 1320 1321 intel_pstate_update_pstate(cpu, target_pstate); 1322 1323 sample = &cpu->sample; 1324 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1325 fp_toint(sample->busy_scaled), 1326 from, 1327 cpu->pstate.current_pstate, 1328 sample->mperf, 1329 sample->aperf, 1330 sample->tsc, 1331 get_avg_frequency(cpu)); 1332 } 1333 1334 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1335 unsigned long util, unsigned long max) 1336 { 1337 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1338 u64 delta_ns = time - cpu->sample.time; 1339 1340 if ((s64)delta_ns >= pid_params.sample_rate_ns) { 1341 bool sample_taken = intel_pstate_sample(cpu, time); 1342 1343 if (sample_taken) { 1344 intel_pstate_calc_avg_perf(cpu); 1345 if (!hwp_active) 1346 intel_pstate_adjust_busy_pstate(cpu); 1347 } 1348 } 1349 } 1350 1351 #define ICPU(model, policy) \ 1352 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ 1353 (unsigned long)&policy } 1354 1355 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1356 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), 1357 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), 1358 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), 1359 ICPU(INTEL_FAM6_IVYBRIDGE, core_params), 1360 ICPU(INTEL_FAM6_HASWELL_CORE, core_params), 1361 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), 1362 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), 1363 ICPU(INTEL_FAM6_HASWELL_X, core_params), 1364 ICPU(INTEL_FAM6_HASWELL_ULT, core_params), 1365 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), 1366 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), 1367 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), 1368 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), 1369 ICPU(INTEL_FAM6_BROADWELL_X, core_params), 1370 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), 1371 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1372 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), 1373 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), 1374 {} 1375 }; 1376 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1377 1378 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1379 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), 1380 {} 1381 }; 1382 1383 static int intel_pstate_init_cpu(unsigned int cpunum) 1384 { 1385 struct cpudata *cpu; 1386 1387 if (!all_cpu_data[cpunum]) 1388 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), 1389 GFP_KERNEL); 1390 if (!all_cpu_data[cpunum]) 1391 return -ENOMEM; 1392 1393 cpu = all_cpu_data[cpunum]; 1394 1395 cpu->cpu = cpunum; 1396 1397 if (hwp_active) { 1398 intel_pstate_hwp_enable(cpu); 1399 pid_params.sample_rate_ms = 50; 1400 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; 1401 } 1402 1403 intel_pstate_get_cpu_pstates(cpu); 1404 1405 intel_pstate_busy_pid_reset(cpu); 1406 1407 pr_debug("controlling: cpu %d\n", cpunum); 1408 1409 return 0; 1410 } 1411 1412 static unsigned int intel_pstate_get(unsigned int cpu_num) 1413 { 1414 struct cpudata *cpu = all_cpu_data[cpu_num]; 1415 1416 return cpu ? get_avg_frequency(cpu) : 0; 1417 } 1418 1419 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 1420 { 1421 struct cpudata *cpu = all_cpu_data[cpu_num]; 1422 1423 if (cpu->update_util_set) 1424 return; 1425 1426 /* Prevent intel_pstate_update_util() from using stale data. */ 1427 cpu->sample.time = 0; 1428 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 1429 intel_pstate_update_util); 1430 cpu->update_util_set = true; 1431 } 1432 1433 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 1434 { 1435 struct cpudata *cpu_data = all_cpu_data[cpu]; 1436 1437 if (!cpu_data->update_util_set) 1438 return; 1439 1440 cpufreq_remove_update_util_hook(cpu); 1441 cpu_data->update_util_set = false; 1442 synchronize_sched(); 1443 } 1444 1445 static void intel_pstate_set_performance_limits(struct perf_limits *limits) 1446 { 1447 limits->no_turbo = 0; 1448 limits->turbo_disabled = 0; 1449 limits->max_perf_pct = 100; 1450 limits->max_perf = int_tofp(1); 1451 limits->min_perf_pct = 100; 1452 limits->min_perf = int_tofp(1); 1453 limits->max_policy_pct = 100; 1454 limits->max_sysfs_pct = 100; 1455 limits->min_policy_pct = 0; 1456 limits->min_sysfs_pct = 0; 1457 } 1458 1459 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 1460 { 1461 struct cpudata *cpu; 1462 1463 if (!policy->cpuinfo.max_freq) 1464 return -ENODEV; 1465 1466 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 1467 policy->cpuinfo.max_freq, policy->max); 1468 1469 cpu = all_cpu_data[0]; 1470 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 1471 policy->max < policy->cpuinfo.max_freq && 1472 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { 1473 pr_debug("policy->max > max non turbo frequency\n"); 1474 policy->max = policy->cpuinfo.max_freq; 1475 } 1476 1477 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 1478 limits = &performance_limits; 1479 if (policy->max >= policy->cpuinfo.max_freq) { 1480 pr_debug("set performance\n"); 1481 intel_pstate_set_performance_limits(limits); 1482 goto out; 1483 } 1484 } else { 1485 pr_debug("set powersave\n"); 1486 limits = &powersave_limits; 1487 } 1488 1489 limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; 1490 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); 1491 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, 1492 policy->cpuinfo.max_freq); 1493 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); 1494 1495 /* Normalize user input to [min_policy_pct, max_policy_pct] */ 1496 limits->min_perf_pct = max(limits->min_policy_pct, 1497 limits->min_sysfs_pct); 1498 limits->min_perf_pct = min(limits->max_policy_pct, 1499 limits->min_perf_pct); 1500 limits->max_perf_pct = min(limits->max_policy_pct, 1501 limits->max_sysfs_pct); 1502 limits->max_perf_pct = max(limits->min_policy_pct, 1503 limits->max_perf_pct); 1504 1505 /* Make sure min_perf_pct <= max_perf_pct */ 1506 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); 1507 1508 limits->min_perf = div_fp(limits->min_perf_pct, 100); 1509 limits->max_perf = div_fp(limits->max_perf_pct, 100); 1510 limits->max_perf = round_up(limits->max_perf, FRAC_BITS); 1511 1512 out: 1513 intel_pstate_set_update_util_hook(policy->cpu); 1514 1515 intel_pstate_hwp_set_policy(policy); 1516 1517 return 0; 1518 } 1519 1520 static int intel_pstate_verify_policy(struct cpufreq_policy *policy) 1521 { 1522 cpufreq_verify_within_cpu_limits(policy); 1523 1524 if (policy->policy != CPUFREQ_POLICY_POWERSAVE && 1525 policy->policy != CPUFREQ_POLICY_PERFORMANCE) 1526 return -EINVAL; 1527 1528 return 0; 1529 } 1530 1531 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 1532 { 1533 int cpu_num = policy->cpu; 1534 struct cpudata *cpu = all_cpu_data[cpu_num]; 1535 1536 pr_debug("CPU %d exiting\n", cpu_num); 1537 1538 intel_pstate_clear_update_util_hook(cpu_num); 1539 1540 if (hwp_active) 1541 return; 1542 1543 intel_pstate_set_min_pstate(cpu); 1544 } 1545 1546 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 1547 { 1548 struct cpudata *cpu; 1549 int rc; 1550 1551 rc = intel_pstate_init_cpu(policy->cpu); 1552 if (rc) 1553 return rc; 1554 1555 cpu = all_cpu_data[policy->cpu]; 1556 1557 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) 1558 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1559 else 1560 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1561 1562 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 1563 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1564 1565 /* cpuinfo and default policy values */ 1566 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 1567 update_turbo_state(); 1568 policy->cpuinfo.max_freq = limits->turbo_disabled ? 1569 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1570 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 1571 1572 intel_pstate_init_acpi_perf_limits(policy); 1573 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 1574 cpumask_set_cpu(policy->cpu, policy->cpus); 1575 1576 return 0; 1577 } 1578 1579 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 1580 { 1581 intel_pstate_exit_perf_limits(policy); 1582 1583 return 0; 1584 } 1585 1586 static struct cpufreq_driver intel_pstate_driver = { 1587 .flags = CPUFREQ_CONST_LOOPS, 1588 .verify = intel_pstate_verify_policy, 1589 .setpolicy = intel_pstate_set_policy, 1590 .resume = intel_pstate_hwp_set_policy, 1591 .get = intel_pstate_get, 1592 .init = intel_pstate_cpu_init, 1593 .exit = intel_pstate_cpu_exit, 1594 .stop_cpu = intel_pstate_stop_cpu, 1595 .name = "intel_pstate", 1596 }; 1597 1598 static int no_load __initdata; 1599 static int no_hwp __initdata; 1600 static int hwp_only __initdata; 1601 static unsigned int force_load __initdata; 1602 1603 static int __init intel_pstate_msrs_not_valid(void) 1604 { 1605 if (!pstate_funcs.get_max() || 1606 !pstate_funcs.get_min() || 1607 !pstate_funcs.get_turbo()) 1608 return -ENODEV; 1609 1610 return 0; 1611 } 1612 1613 static void __init copy_pid_params(struct pstate_adjust_policy *policy) 1614 { 1615 pid_params.sample_rate_ms = policy->sample_rate_ms; 1616 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; 1617 pid_params.p_gain_pct = policy->p_gain_pct; 1618 pid_params.i_gain_pct = policy->i_gain_pct; 1619 pid_params.d_gain_pct = policy->d_gain_pct; 1620 pid_params.deadband = policy->deadband; 1621 pid_params.setpoint = policy->setpoint; 1622 } 1623 1624 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 1625 { 1626 pstate_funcs.get_max = funcs->get_max; 1627 pstate_funcs.get_max_physical = funcs->get_max_physical; 1628 pstate_funcs.get_min = funcs->get_min; 1629 pstate_funcs.get_turbo = funcs->get_turbo; 1630 pstate_funcs.get_scaling = funcs->get_scaling; 1631 pstate_funcs.get_val = funcs->get_val; 1632 pstate_funcs.get_vid = funcs->get_vid; 1633 pstate_funcs.get_target_pstate = funcs->get_target_pstate; 1634 1635 } 1636 1637 #ifdef CONFIG_ACPI 1638 1639 static bool __init intel_pstate_no_acpi_pss(void) 1640 { 1641 int i; 1642 1643 for_each_possible_cpu(i) { 1644 acpi_status status; 1645 union acpi_object *pss; 1646 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1647 struct acpi_processor *pr = per_cpu(processors, i); 1648 1649 if (!pr) 1650 continue; 1651 1652 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 1653 if (ACPI_FAILURE(status)) 1654 continue; 1655 1656 pss = buffer.pointer; 1657 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 1658 kfree(pss); 1659 return false; 1660 } 1661 1662 kfree(pss); 1663 } 1664 1665 return true; 1666 } 1667 1668 static bool __init intel_pstate_has_acpi_ppc(void) 1669 { 1670 int i; 1671 1672 for_each_possible_cpu(i) { 1673 struct acpi_processor *pr = per_cpu(processors, i); 1674 1675 if (!pr) 1676 continue; 1677 if (acpi_has_method(pr->handle, "_PPC")) 1678 return true; 1679 } 1680 return false; 1681 } 1682 1683 enum { 1684 PSS, 1685 PPC, 1686 }; 1687 1688 struct hw_vendor_info { 1689 u16 valid; 1690 char oem_id[ACPI_OEM_ID_SIZE]; 1691 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; 1692 int oem_pwr_table; 1693 }; 1694 1695 /* Hardware vendor-specific info that has its own power management modes */ 1696 static struct hw_vendor_info vendor_info[] __initdata = { 1697 {1, "HP ", "ProLiant", PSS}, 1698 {1, "ORACLE", "X4-2 ", PPC}, 1699 {1, "ORACLE", "X4-2L ", PPC}, 1700 {1, "ORACLE", "X4-2B ", PPC}, 1701 {1, "ORACLE", "X3-2 ", PPC}, 1702 {1, "ORACLE", "X3-2L ", PPC}, 1703 {1, "ORACLE", "X3-2B ", PPC}, 1704 {1, "ORACLE", "X4470M2 ", PPC}, 1705 {1, "ORACLE", "X4270M3 ", PPC}, 1706 {1, "ORACLE", "X4270M2 ", PPC}, 1707 {1, "ORACLE", "X4170M2 ", PPC}, 1708 {1, "ORACLE", "X4170 M3", PPC}, 1709 {1, "ORACLE", "X4275 M3", PPC}, 1710 {1, "ORACLE", "X6-2 ", PPC}, 1711 {1, "ORACLE", "Sudbury ", PPC}, 1712 {0, "", ""}, 1713 }; 1714 1715 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 1716 { 1717 struct acpi_table_header hdr; 1718 struct hw_vendor_info *v_info; 1719 const struct x86_cpu_id *id; 1720 u64 misc_pwr; 1721 1722 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 1723 if (id) { 1724 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 1725 if ( misc_pwr & (1 << 8)) 1726 return true; 1727 } 1728 1729 if (acpi_disabled || 1730 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) 1731 return false; 1732 1733 for (v_info = vendor_info; v_info->valid; v_info++) { 1734 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && 1735 !strncmp(hdr.oem_table_id, v_info->oem_table_id, 1736 ACPI_OEM_TABLE_ID_SIZE)) 1737 switch (v_info->oem_pwr_table) { 1738 case PSS: 1739 return intel_pstate_no_acpi_pss(); 1740 case PPC: 1741 return intel_pstate_has_acpi_ppc() && 1742 (!force_load); 1743 } 1744 } 1745 1746 return false; 1747 } 1748 #else /* CONFIG_ACPI not enabled */ 1749 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 1750 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 1751 #endif /* CONFIG_ACPI */ 1752 1753 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 1754 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, 1755 {} 1756 }; 1757 1758 static int __init intel_pstate_init(void) 1759 { 1760 int cpu, rc = 0; 1761 const struct x86_cpu_id *id; 1762 struct cpu_defaults *cpu_def; 1763 1764 if (no_load) 1765 return -ENODEV; 1766 1767 if (x86_match_cpu(hwp_support_ids) && !no_hwp) { 1768 copy_cpu_funcs(&core_params.funcs); 1769 hwp_active++; 1770 goto hwp_cpu_matched; 1771 } 1772 1773 id = x86_match_cpu(intel_pstate_cpu_ids); 1774 if (!id) 1775 return -ENODEV; 1776 1777 cpu_def = (struct cpu_defaults *)id->driver_data; 1778 1779 copy_pid_params(&cpu_def->pid_policy); 1780 copy_cpu_funcs(&cpu_def->funcs); 1781 1782 if (intel_pstate_msrs_not_valid()) 1783 return -ENODEV; 1784 1785 hwp_cpu_matched: 1786 /* 1787 * The Intel pstate driver will be ignored if the platform 1788 * firmware has its own power management modes. 1789 */ 1790 if (intel_pstate_platform_pwr_mgmt_exists()) 1791 return -ENODEV; 1792 1793 pr_info("Intel P-state driver initializing\n"); 1794 1795 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); 1796 if (!all_cpu_data) 1797 return -ENOMEM; 1798 1799 if (!hwp_active && hwp_only) 1800 goto out; 1801 1802 rc = cpufreq_register_driver(&intel_pstate_driver); 1803 if (rc) 1804 goto out; 1805 1806 intel_pstate_debug_expose_params(); 1807 intel_pstate_sysfs_expose_params(); 1808 1809 if (hwp_active) 1810 pr_info("HWP enabled\n"); 1811 1812 return rc; 1813 out: 1814 get_online_cpus(); 1815 for_each_online_cpu(cpu) { 1816 if (all_cpu_data[cpu]) { 1817 intel_pstate_clear_update_util_hook(cpu); 1818 kfree(all_cpu_data[cpu]); 1819 } 1820 } 1821 1822 put_online_cpus(); 1823 vfree(all_cpu_data); 1824 return -ENODEV; 1825 } 1826 device_initcall(intel_pstate_init); 1827 1828 static int __init intel_pstate_setup(char *str) 1829 { 1830 if (!str) 1831 return -EINVAL; 1832 1833 if (!strcmp(str, "disable")) 1834 no_load = 1; 1835 if (!strcmp(str, "no_hwp")) { 1836 pr_info("HWP disabled\n"); 1837 no_hwp = 1; 1838 } 1839 if (!strcmp(str, "force")) 1840 force_load = 1; 1841 if (!strcmp(str, "hwp_only")) 1842 hwp_only = 1; 1843 1844 #ifdef CONFIG_ACPI 1845 if (!strcmp(str, "support_acpi_ppc")) 1846 acpi_ppc = true; 1847 #endif 1848 1849 return 0; 1850 } 1851 early_param("intel_pstate", intel_pstate_setup); 1852 1853 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 1854 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 1855 MODULE_LICENSE("GPL"); 1856