1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/cpu.h> 31 #include <asm/div64.h> 32 #include <asm/msr.h> 33 #include <asm/cpu_device_id.h> 34 #include <asm/cpufeature.h> 35 #include <asm/intel-family.h> 36 #include "../drivers/thermal/intel/thermal_interrupt.h" 37 38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 39 40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #include <acpi/cppc_acpi.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 54 55 #define EXT_BITS 6 56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 59 60 static inline int32_t mul_fp(int32_t x, int32_t y) 61 { 62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 63 } 64 65 static inline int32_t div_fp(s64 x, s64 y) 66 { 67 return div64_s64((int64_t)x << FRAC_BITS, y); 68 } 69 70 static inline int ceiling_fp(int32_t x) 71 { 72 int mask, ret; 73 74 ret = fp_toint(x); 75 mask = (1 << FRAC_BITS) - 1; 76 if (x & mask) 77 ret += 1; 78 return ret; 79 } 80 81 static inline u64 mul_ext_fp(u64 x, u64 y) 82 { 83 return (x * y) >> EXT_FRAC_BITS; 84 } 85 86 static inline u64 div_ext_fp(u64 x, u64 y) 87 { 88 return div64_u64(x << EXT_FRAC_BITS, y); 89 } 90 91 /** 92 * struct sample - Store performance sample 93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 94 * performance during last sample period 95 * @busy_scaled: Scaled busy value which is used to calculate next 96 * P state. This can be different than core_avg_perf 97 * to account for cpu idle period 98 * @aperf: Difference of actual performance frequency clock count 99 * read from APERF MSR between last and current sample 100 * @mperf: Difference of maximum performance frequency clock count 101 * read from MPERF MSR between last and current sample 102 * @tsc: Difference of time stamp counter between last and 103 * current sample 104 * @time: Current time from scheduler 105 * 106 * This structure is used in the cpudata structure to store performance sample 107 * data for choosing next P State. 108 */ 109 struct sample { 110 int32_t core_avg_perf; 111 int32_t busy_scaled; 112 u64 aperf; 113 u64 mperf; 114 u64 tsc; 115 u64 time; 116 }; 117 118 /** 119 * struct pstate_data - Store P state data 120 * @current_pstate: Current requested P state 121 * @min_pstate: Min P state possible for this platform 122 * @max_pstate: Max P state possible for this platform 123 * @max_pstate_physical:This is physical Max P state for a processor 124 * This can be higher than the max_pstate which can 125 * be limited by platform thermal design power limits 126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 127 * @scaling: Scaling factor between performance and frequency 128 * @turbo_pstate: Max Turbo P state possible for this platform 129 * @min_freq: @min_pstate frequency in cpufreq units 130 * @max_freq: @max_pstate frequency in cpufreq units 131 * @turbo_freq: @turbo_pstate frequency in cpufreq units 132 * 133 * Stores the per cpu model P state limits and current P state. 134 */ 135 struct pstate_data { 136 int current_pstate; 137 int min_pstate; 138 int max_pstate; 139 int max_pstate_physical; 140 int perf_ctl_scaling; 141 int scaling; 142 int turbo_pstate; 143 unsigned int min_freq; 144 unsigned int max_freq; 145 unsigned int turbo_freq; 146 }; 147 148 /** 149 * struct vid_data - Stores voltage information data 150 * @min: VID data for this platform corresponding to 151 * the lowest P state 152 * @max: VID data corresponding to the highest P State. 153 * @turbo: VID data for turbo P state 154 * @ratio: Ratio of (vid max - vid min) / 155 * (max P state - Min P State) 156 * 157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 158 * This data is used in Atom platforms, where in addition to target P state, 159 * the voltage data needs to be specified to select next P State. 160 */ 161 struct vid_data { 162 int min; 163 int max; 164 int turbo; 165 int32_t ratio; 166 }; 167 168 /** 169 * struct global_params - Global parameters, mostly tunable via sysfs. 170 * @no_turbo: Whether or not to use turbo P-states. 171 * @turbo_disabled: Whether or not turbo P-states are available at all, 172 * based on the MSR_IA32_MISC_ENABLE value and whether or 173 * not the maximum reported turbo P-state is different from 174 * the maximum reported non-turbo one. 175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 177 * P-state capacity. 178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 */ 181 struct global_params { 182 bool no_turbo; 183 bool turbo_disabled; 184 bool turbo_disabled_mf; 185 int max_perf_pct; 186 int min_perf_pct; 187 }; 188 189 /** 190 * struct cpudata - Per CPU instance data storage 191 * @cpu: CPU number for this instance data 192 * @policy: CPUFreq policy value 193 * @update_util: CPUFreq utility callback information 194 * @update_util_set: CPUFreq utility callback is set 195 * @iowait_boost: iowait-related boost fraction 196 * @last_update: Time of the last update. 197 * @pstate: Stores P state limits for this CPU 198 * @vid: Stores VID limits for this CPU 199 * @last_sample_time: Last Sample time 200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 201 * @prev_aperf: Last APERF value read from APERF MSR 202 * @prev_mperf: Last MPERF value read from MPERF MSR 203 * @prev_tsc: Last timestamp counter (TSC) value 204 * @prev_cummulative_iowait: IO Wait time difference from last and 205 * current sample 206 * @sample: Storage for storing last Sample data 207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 209 * @acpi_perf_data: Stores ACPI perf information read from _PSS 210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 211 * @epp_powersave: Last saved HWP energy performance preference 212 * (EPP) or energy performance bias (EPB), 213 * when policy switched to performance 214 * @epp_policy: Last saved policy used to set EPP/EPB 215 * @epp_default: Power on default HWP energy performance 216 * preference/bias 217 * @epp_cached Cached HWP energy-performance preference value 218 * @hwp_req_cached: Cached value of the last HWP Request MSR 219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 220 * @last_io_update: Last time when IO wake flag was set 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @hwp_notify_work: workqueue for HWP notifications. 225 * 226 * This structure stores per CPU instance data for all CPUs. 227 */ 228 struct cpudata { 229 int cpu; 230 231 unsigned int policy; 232 struct update_util_data update_util; 233 bool update_util_set; 234 235 struct pstate_data pstate; 236 struct vid_data vid; 237 238 u64 last_update; 239 u64 last_sample_time; 240 u64 aperf_mperf_shift; 241 u64 prev_aperf; 242 u64 prev_mperf; 243 u64 prev_tsc; 244 u64 prev_cummulative_iowait; 245 struct sample sample; 246 int32_t min_perf_ratio; 247 int32_t max_perf_ratio; 248 #ifdef CONFIG_ACPI 249 struct acpi_processor_performance acpi_perf_data; 250 bool valid_pss_table; 251 #endif 252 unsigned int iowait_boost; 253 s16 epp_powersave; 254 s16 epp_policy; 255 s16 epp_default; 256 s16 epp_cached; 257 u64 hwp_req_cached; 258 u64 hwp_cap_cached; 259 u64 last_io_update; 260 unsigned int sched_flags; 261 u32 hwp_boost_min; 262 bool suspended; 263 struct delayed_work hwp_notify_work; 264 }; 265 266 static struct cpudata **all_cpu_data; 267 268 /** 269 * struct pstate_funcs - Per CPU model specific callbacks 270 * @get_max: Callback to get maximum non turbo effective P state 271 * @get_max_physical: Callback to get maximum non turbo physical P state 272 * @get_min: Callback to get minimum P state 273 * @get_turbo: Callback to get turbo P state 274 * @get_scaling: Callback to get frequency scaling factor 275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(int cpu); 285 int (*get_max_physical)(int cpu); 286 int (*get_min)(int cpu); 287 int (*get_turbo)(int cpu); 288 int (*get_scaling)(void); 289 int (*get_cpu_scaling)(int cpu); 290 int (*get_aperf_mperf_shift)(void); 291 u64 (*get_val)(struct cpudata*, int pstate); 292 void (*get_vid)(struct cpudata *); 293 }; 294 295 static struct pstate_funcs pstate_funcs __read_mostly; 296 297 static int hwp_active __read_mostly; 298 static int hwp_mode_bdw __read_mostly; 299 static bool per_cpu_limits __read_mostly; 300 static bool hwp_boost __read_mostly; 301 static bool hwp_forced __read_mostly; 302 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 304 305 #define HYBRID_SCALING_FACTOR 78741 306 307 static inline int core_get_scaling(void) 308 { 309 return 100000; 310 } 311 312 #ifdef CONFIG_ACPI 313 static bool acpi_ppc; 314 #endif 315 316 static struct global_params global; 317 318 static DEFINE_MUTEX(intel_pstate_driver_lock); 319 static DEFINE_MUTEX(intel_pstate_limits_lock); 320 321 #ifdef CONFIG_ACPI 322 323 static bool intel_pstate_acpi_pm_profile_server(void) 324 { 325 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 326 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 327 return true; 328 329 return false; 330 } 331 332 static bool intel_pstate_get_ppc_enable_status(void) 333 { 334 if (intel_pstate_acpi_pm_profile_server()) 335 return true; 336 337 return acpi_ppc; 338 } 339 340 #ifdef CONFIG_ACPI_CPPC_LIB 341 342 /* The work item is needed to avoid CPU hotplug locking issues */ 343 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 344 { 345 sched_set_itmt_support(); 346 } 347 348 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 349 350 #define CPPC_MAX_PERF U8_MAX 351 352 static void intel_pstate_set_itmt_prio(int cpu) 353 { 354 struct cppc_perf_caps cppc_perf; 355 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 356 int ret; 357 358 ret = cppc_get_perf_caps(cpu, &cppc_perf); 359 if (ret) 360 return; 361 362 /* 363 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. 364 * In this case we can't use CPPC.highest_perf to enable ITMT. 365 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. 366 */ 367 if (cppc_perf.highest_perf == CPPC_MAX_PERF) 368 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 369 370 /* 371 * The priorities can be set regardless of whether or not 372 * sched_set_itmt_support(true) has been called and it is valid to 373 * update them at any time after it has been called. 374 */ 375 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 376 377 if (max_highest_perf <= min_highest_perf) { 378 if (cppc_perf.highest_perf > max_highest_perf) 379 max_highest_perf = cppc_perf.highest_perf; 380 381 if (cppc_perf.highest_perf < min_highest_perf) 382 min_highest_perf = cppc_perf.highest_perf; 383 384 if (max_highest_perf > min_highest_perf) { 385 /* 386 * This code can be run during CPU online under the 387 * CPU hotplug locks, so sched_set_itmt_support() 388 * cannot be called from here. Queue up a work item 389 * to invoke it. 390 */ 391 schedule_work(&sched_itmt_work); 392 } 393 } 394 } 395 396 static int intel_pstate_get_cppc_guaranteed(int cpu) 397 { 398 struct cppc_perf_caps cppc_perf; 399 int ret; 400 401 ret = cppc_get_perf_caps(cpu, &cppc_perf); 402 if (ret) 403 return ret; 404 405 if (cppc_perf.guaranteed_perf) 406 return cppc_perf.guaranteed_perf; 407 408 return cppc_perf.nominal_perf; 409 } 410 411 static int intel_pstate_cppc_get_scaling(int cpu) 412 { 413 struct cppc_perf_caps cppc_perf; 414 int ret; 415 416 ret = cppc_get_perf_caps(cpu, &cppc_perf); 417 418 /* 419 * If the nominal frequency and the nominal performance are not 420 * zero and the ratio between them is not 100, return the hybrid 421 * scaling factor. 422 */ 423 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq && 424 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq) 425 return HYBRID_SCALING_FACTOR; 426 427 return core_get_scaling(); 428 } 429 430 #else /* CONFIG_ACPI_CPPC_LIB */ 431 static inline void intel_pstate_set_itmt_prio(int cpu) 432 { 433 } 434 #endif /* CONFIG_ACPI_CPPC_LIB */ 435 436 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 437 { 438 struct cpudata *cpu; 439 int ret; 440 int i; 441 442 if (hwp_active) { 443 intel_pstate_set_itmt_prio(policy->cpu); 444 return; 445 } 446 447 if (!intel_pstate_get_ppc_enable_status()) 448 return; 449 450 cpu = all_cpu_data[policy->cpu]; 451 452 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 453 policy->cpu); 454 if (ret) 455 return; 456 457 /* 458 * Check if the control value in _PSS is for PERF_CTL MSR, which should 459 * guarantee that the states returned by it map to the states in our 460 * list directly. 461 */ 462 if (cpu->acpi_perf_data.control_register.space_id != 463 ACPI_ADR_SPACE_FIXED_HARDWARE) 464 goto err; 465 466 /* 467 * If there is only one entry _PSS, simply ignore _PSS and continue as 468 * usual without taking _PSS into account 469 */ 470 if (cpu->acpi_perf_data.state_count < 2) 471 goto err; 472 473 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 474 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 475 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 476 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 477 (u32) cpu->acpi_perf_data.states[i].core_frequency, 478 (u32) cpu->acpi_perf_data.states[i].power, 479 (u32) cpu->acpi_perf_data.states[i].control); 480 } 481 482 cpu->valid_pss_table = true; 483 pr_debug("_PPC limits will be enforced\n"); 484 485 return; 486 487 err: 488 cpu->valid_pss_table = false; 489 acpi_processor_unregister_performance(policy->cpu); 490 } 491 492 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 493 { 494 struct cpudata *cpu; 495 496 cpu = all_cpu_data[policy->cpu]; 497 if (!cpu->valid_pss_table) 498 return; 499 500 acpi_processor_unregister_performance(policy->cpu); 501 } 502 #else /* CONFIG_ACPI */ 503 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 504 { 505 } 506 507 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 508 { 509 } 510 511 static inline bool intel_pstate_acpi_pm_profile_server(void) 512 { 513 return false; 514 } 515 #endif /* CONFIG_ACPI */ 516 517 #ifndef CONFIG_ACPI_CPPC_LIB 518 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 519 { 520 return -ENOTSUPP; 521 } 522 523 static int intel_pstate_cppc_get_scaling(int cpu) 524 { 525 return core_get_scaling(); 526 } 527 #endif /* CONFIG_ACPI_CPPC_LIB */ 528 529 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq, 530 unsigned int relation) 531 { 532 if (freq == cpu->pstate.turbo_freq) 533 return cpu->pstate.turbo_pstate; 534 535 if (freq == cpu->pstate.max_freq) 536 return cpu->pstate.max_pstate; 537 538 switch (relation) { 539 case CPUFREQ_RELATION_H: 540 return freq / cpu->pstate.scaling; 541 case CPUFREQ_RELATION_C: 542 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling); 543 } 544 545 return DIV_ROUND_UP(freq, cpu->pstate.scaling); 546 } 547 548 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq) 549 { 550 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L); 551 } 552 553 /** 554 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 555 * @cpu: Target CPU. 556 * 557 * On hybrid processors, HWP may expose more performance levels than there are 558 * P-states accessible through the PERF_CTL interface. If that happens, the 559 * scaling factor between HWP performance levels and CPU frequency will be less 560 * than the scaling factor between P-state values and CPU frequency. 561 * 562 * In that case, adjust the CPU parameters used in computations accordingly. 563 */ 564 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 565 { 566 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 567 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 568 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 569 int scaling = cpu->pstate.scaling; 570 int freq; 571 572 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 573 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 574 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 575 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 576 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 577 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 578 579 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 580 perf_ctl_scaling); 581 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 582 perf_ctl_scaling); 583 584 freq = perf_ctl_max_phys * perf_ctl_scaling; 585 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq); 586 587 freq = cpu->pstate.min_pstate * perf_ctl_scaling; 588 cpu->pstate.min_freq = freq; 589 /* 590 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 591 * the effective range of HWP performance levels. 592 */ 593 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq); 594 } 595 596 static inline void update_turbo_state(void) 597 { 598 u64 misc_en; 599 struct cpudata *cpu; 600 601 cpu = all_cpu_data[0]; 602 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 603 global.turbo_disabled = 604 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 605 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 606 } 607 608 static int min_perf_pct_min(void) 609 { 610 struct cpudata *cpu = all_cpu_data[0]; 611 int turbo_pstate = cpu->pstate.turbo_pstate; 612 613 return turbo_pstate ? 614 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 615 } 616 617 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 618 { 619 u64 epb; 620 int ret; 621 622 if (!boot_cpu_has(X86_FEATURE_EPB)) 623 return -ENXIO; 624 625 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 626 if (ret) 627 return (s16)ret; 628 629 return (s16)(epb & 0x0f); 630 } 631 632 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 633 { 634 s16 epp; 635 636 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 637 /* 638 * When hwp_req_data is 0, means that caller didn't read 639 * MSR_HWP_REQUEST, so need to read and get EPP. 640 */ 641 if (!hwp_req_data) { 642 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 643 &hwp_req_data); 644 if (epp) 645 return epp; 646 } 647 epp = (hwp_req_data >> 24) & 0xff; 648 } else { 649 /* When there is no EPP present, HWP uses EPB settings */ 650 epp = intel_pstate_get_epb(cpu_data); 651 } 652 653 return epp; 654 } 655 656 static int intel_pstate_set_epb(int cpu, s16 pref) 657 { 658 u64 epb; 659 int ret; 660 661 if (!boot_cpu_has(X86_FEATURE_EPB)) 662 return -ENXIO; 663 664 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 665 if (ret) 666 return ret; 667 668 epb = (epb & ~0x0f) | pref; 669 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 670 671 return 0; 672 } 673 674 /* 675 * EPP/EPB display strings corresponding to EPP index in the 676 * energy_perf_strings[] 677 * index String 678 *------------------------------------- 679 * 0 default 680 * 1 performance 681 * 2 balance_performance 682 * 3 balance_power 683 * 4 power 684 */ 685 686 enum energy_perf_value_index { 687 EPP_INDEX_DEFAULT = 0, 688 EPP_INDEX_PERFORMANCE, 689 EPP_INDEX_BALANCE_PERFORMANCE, 690 EPP_INDEX_BALANCE_POWERSAVE, 691 EPP_INDEX_POWERSAVE, 692 }; 693 694 static const char * const energy_perf_strings[] = { 695 [EPP_INDEX_DEFAULT] = "default", 696 [EPP_INDEX_PERFORMANCE] = "performance", 697 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 698 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 699 [EPP_INDEX_POWERSAVE] = "power", 700 NULL 701 }; 702 static unsigned int epp_values[] = { 703 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 704 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 705 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 706 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 707 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 708 }; 709 710 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 711 { 712 s16 epp; 713 int index = -EINVAL; 714 715 *raw_epp = 0; 716 epp = intel_pstate_get_epp(cpu_data, 0); 717 if (epp < 0) 718 return epp; 719 720 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 721 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 722 return EPP_INDEX_PERFORMANCE; 723 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 724 return EPP_INDEX_BALANCE_PERFORMANCE; 725 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 726 return EPP_INDEX_BALANCE_POWERSAVE; 727 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 728 return EPP_INDEX_POWERSAVE; 729 *raw_epp = epp; 730 return 0; 731 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 732 /* 733 * Range: 734 * 0x00-0x03 : Performance 735 * 0x04-0x07 : Balance performance 736 * 0x08-0x0B : Balance power 737 * 0x0C-0x0F : Power 738 * The EPB is a 4 bit value, but our ranges restrict the 739 * value which can be set. Here only using top two bits 740 * effectively. 741 */ 742 index = (epp >> 2) + 1; 743 } 744 745 return index; 746 } 747 748 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 749 { 750 int ret; 751 752 /* 753 * Use the cached HWP Request MSR value, because in the active mode the 754 * register itself may be updated by intel_pstate_hwp_boost_up() or 755 * intel_pstate_hwp_boost_down() at any time. 756 */ 757 u64 value = READ_ONCE(cpu->hwp_req_cached); 758 759 value &= ~GENMASK_ULL(31, 24); 760 value |= (u64)epp << 24; 761 /* 762 * The only other updater of hwp_req_cached in the active mode, 763 * intel_pstate_hwp_set(), is called under the same lock as this 764 * function, so it cannot run in parallel with the update below. 765 */ 766 WRITE_ONCE(cpu->hwp_req_cached, value); 767 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 768 if (!ret) 769 cpu->epp_cached = epp; 770 771 return ret; 772 } 773 774 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 775 int pref_index, bool use_raw, 776 u32 raw_epp) 777 { 778 int epp = -EINVAL; 779 int ret; 780 781 if (!pref_index) 782 epp = cpu_data->epp_default; 783 784 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 785 if (use_raw) 786 epp = raw_epp; 787 else if (epp == -EINVAL) 788 epp = epp_values[pref_index]; 789 790 /* 791 * To avoid confusion, refuse to set EPP to any values different 792 * from 0 (performance) if the current policy is "performance", 793 * because those values would be overridden. 794 */ 795 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 796 return -EBUSY; 797 798 ret = intel_pstate_set_epp(cpu_data, epp); 799 } else { 800 if (epp == -EINVAL) 801 epp = (pref_index - 1) << 2; 802 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 803 } 804 805 return ret; 806 } 807 808 static ssize_t show_energy_performance_available_preferences( 809 struct cpufreq_policy *policy, char *buf) 810 { 811 int i = 0; 812 int ret = 0; 813 814 while (energy_perf_strings[i] != NULL) 815 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 816 817 ret += sprintf(&buf[ret], "\n"); 818 819 return ret; 820 } 821 822 cpufreq_freq_attr_ro(energy_performance_available_preferences); 823 824 static struct cpufreq_driver intel_pstate; 825 826 static ssize_t store_energy_performance_preference( 827 struct cpufreq_policy *policy, const char *buf, size_t count) 828 { 829 struct cpudata *cpu = all_cpu_data[policy->cpu]; 830 char str_preference[21]; 831 bool raw = false; 832 ssize_t ret; 833 u32 epp = 0; 834 835 ret = sscanf(buf, "%20s", str_preference); 836 if (ret != 1) 837 return -EINVAL; 838 839 ret = match_string(energy_perf_strings, -1, str_preference); 840 if (ret < 0) { 841 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 842 return ret; 843 844 ret = kstrtouint(buf, 10, &epp); 845 if (ret) 846 return ret; 847 848 if (epp > 255) 849 return -EINVAL; 850 851 raw = true; 852 } 853 854 /* 855 * This function runs with the policy R/W semaphore held, which 856 * guarantees that the driver pointer will not change while it is 857 * running. 858 */ 859 if (!intel_pstate_driver) 860 return -EAGAIN; 861 862 mutex_lock(&intel_pstate_limits_lock); 863 864 if (intel_pstate_driver == &intel_pstate) { 865 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 866 } else { 867 /* 868 * In the passive mode the governor needs to be stopped on the 869 * target CPU before the EPP update and restarted after it, 870 * which is super-heavy-weight, so make sure it is worth doing 871 * upfront. 872 */ 873 if (!raw) 874 epp = ret ? epp_values[ret] : cpu->epp_default; 875 876 if (cpu->epp_cached != epp) { 877 int err; 878 879 cpufreq_stop_governor(policy); 880 ret = intel_pstate_set_epp(cpu, epp); 881 err = cpufreq_start_governor(policy); 882 if (!ret) 883 ret = err; 884 } else { 885 ret = 0; 886 } 887 } 888 889 mutex_unlock(&intel_pstate_limits_lock); 890 891 return ret ?: count; 892 } 893 894 static ssize_t show_energy_performance_preference( 895 struct cpufreq_policy *policy, char *buf) 896 { 897 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 898 int preference, raw_epp; 899 900 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 901 if (preference < 0) 902 return preference; 903 904 if (raw_epp) 905 return sprintf(buf, "%d\n", raw_epp); 906 else 907 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 908 } 909 910 cpufreq_freq_attr_rw(energy_performance_preference); 911 912 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 913 { 914 struct cpudata *cpu = all_cpu_data[policy->cpu]; 915 int ratio, freq; 916 917 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 918 if (ratio <= 0) { 919 u64 cap; 920 921 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 922 ratio = HWP_GUARANTEED_PERF(cap); 923 } 924 925 freq = ratio * cpu->pstate.scaling; 926 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 927 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 928 929 return sprintf(buf, "%d\n", freq); 930 } 931 932 cpufreq_freq_attr_ro(base_frequency); 933 934 static struct freq_attr *hwp_cpufreq_attrs[] = { 935 &energy_performance_preference, 936 &energy_performance_available_preferences, 937 &base_frequency, 938 NULL, 939 }; 940 941 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 942 { 943 u64 cap; 944 945 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 946 WRITE_ONCE(cpu->hwp_cap_cached, cap); 947 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 948 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 949 } 950 951 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 952 { 953 int scaling = cpu->pstate.scaling; 954 955 __intel_pstate_get_hwp_cap(cpu); 956 957 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 958 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 959 if (scaling != cpu->pstate.perf_ctl_scaling) { 960 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 961 962 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 963 perf_ctl_scaling); 964 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 965 perf_ctl_scaling); 966 } 967 } 968 969 static void intel_pstate_hwp_set(unsigned int cpu) 970 { 971 struct cpudata *cpu_data = all_cpu_data[cpu]; 972 int max, min; 973 u64 value; 974 s16 epp; 975 976 max = cpu_data->max_perf_ratio; 977 min = cpu_data->min_perf_ratio; 978 979 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 980 min = max; 981 982 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 983 984 value &= ~HWP_MIN_PERF(~0L); 985 value |= HWP_MIN_PERF(min); 986 987 value &= ~HWP_MAX_PERF(~0L); 988 value |= HWP_MAX_PERF(max); 989 990 if (cpu_data->epp_policy == cpu_data->policy) 991 goto skip_epp; 992 993 cpu_data->epp_policy = cpu_data->policy; 994 995 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 996 epp = intel_pstate_get_epp(cpu_data, value); 997 cpu_data->epp_powersave = epp; 998 /* If EPP read was failed, then don't try to write */ 999 if (epp < 0) 1000 goto skip_epp; 1001 1002 epp = 0; 1003 } else { 1004 /* skip setting EPP, when saved value is invalid */ 1005 if (cpu_data->epp_powersave < 0) 1006 goto skip_epp; 1007 1008 /* 1009 * No need to restore EPP when it is not zero. This 1010 * means: 1011 * - Policy is not changed 1012 * - user has manually changed 1013 * - Error reading EPB 1014 */ 1015 epp = intel_pstate_get_epp(cpu_data, value); 1016 if (epp) 1017 goto skip_epp; 1018 1019 epp = cpu_data->epp_powersave; 1020 } 1021 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1022 value &= ~GENMASK_ULL(31, 24); 1023 value |= (u64)epp << 24; 1024 } else { 1025 intel_pstate_set_epb(cpu, epp); 1026 } 1027 skip_epp: 1028 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1029 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1030 } 1031 1032 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 1033 1034 static void intel_pstate_hwp_offline(struct cpudata *cpu) 1035 { 1036 u64 value = READ_ONCE(cpu->hwp_req_cached); 1037 int min_perf; 1038 1039 intel_pstate_disable_hwp_interrupt(cpu); 1040 1041 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1042 /* 1043 * In case the EPP has been set to "performance" by the 1044 * active mode "performance" scaling algorithm, replace that 1045 * temporary value with the cached EPP one. 1046 */ 1047 value &= ~GENMASK_ULL(31, 24); 1048 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1049 /* 1050 * However, make sure that EPP will be set to "performance" when 1051 * the CPU is brought back online again and the "performance" 1052 * scaling algorithm is still in effect. 1053 */ 1054 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 1055 } 1056 1057 /* 1058 * Clear the desired perf field in the cached HWP request value to 1059 * prevent nonzero desired values from being leaked into the active 1060 * mode. 1061 */ 1062 value &= ~HWP_DESIRED_PERF(~0L); 1063 WRITE_ONCE(cpu->hwp_req_cached, value); 1064 1065 value &= ~GENMASK_ULL(31, 0); 1066 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1067 1068 /* Set hwp_max = hwp_min */ 1069 value |= HWP_MAX_PERF(min_perf); 1070 value |= HWP_MIN_PERF(min_perf); 1071 1072 /* Set EPP to min */ 1073 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1074 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1075 1076 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1077 } 1078 1079 #define POWER_CTL_EE_ENABLE 1 1080 #define POWER_CTL_EE_DISABLE 2 1081 1082 static int power_ctl_ee_state; 1083 1084 static void set_power_ctl_ee_state(bool input) 1085 { 1086 u64 power_ctl; 1087 1088 mutex_lock(&intel_pstate_driver_lock); 1089 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1090 if (input) { 1091 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1092 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1093 } else { 1094 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1095 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1096 } 1097 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1098 mutex_unlock(&intel_pstate_driver_lock); 1099 } 1100 1101 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1102 1103 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1104 { 1105 intel_pstate_hwp_enable(cpu); 1106 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1107 } 1108 1109 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1110 { 1111 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1112 1113 pr_debug("CPU %d suspending\n", cpu->cpu); 1114 1115 cpu->suspended = true; 1116 1117 /* disable HWP interrupt and cancel any pending work */ 1118 intel_pstate_disable_hwp_interrupt(cpu); 1119 1120 return 0; 1121 } 1122 1123 static int intel_pstate_resume(struct cpufreq_policy *policy) 1124 { 1125 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1126 1127 pr_debug("CPU %d resuming\n", cpu->cpu); 1128 1129 /* Only restore if the system default is changed */ 1130 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1131 set_power_ctl_ee_state(true); 1132 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1133 set_power_ctl_ee_state(false); 1134 1135 if (cpu->suspended && hwp_active) { 1136 mutex_lock(&intel_pstate_limits_lock); 1137 1138 /* Re-enable HWP, because "online" has not done that. */ 1139 intel_pstate_hwp_reenable(cpu); 1140 1141 mutex_unlock(&intel_pstate_limits_lock); 1142 } 1143 1144 cpu->suspended = false; 1145 1146 return 0; 1147 } 1148 1149 static void intel_pstate_update_policies(void) 1150 { 1151 int cpu; 1152 1153 for_each_possible_cpu(cpu) 1154 cpufreq_update_policy(cpu); 1155 } 1156 1157 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1158 struct cpufreq_policy *policy) 1159 { 1160 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 1161 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1162 refresh_frequency_limits(policy); 1163 } 1164 1165 static void intel_pstate_update_max_freq(unsigned int cpu) 1166 { 1167 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1168 1169 if (!policy) 1170 return; 1171 1172 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1173 1174 cpufreq_cpu_release(policy); 1175 } 1176 1177 static void intel_pstate_update_limits(unsigned int cpu) 1178 { 1179 mutex_lock(&intel_pstate_driver_lock); 1180 1181 update_turbo_state(); 1182 /* 1183 * If turbo has been turned on or off globally, policy limits for 1184 * all CPUs need to be updated to reflect that. 1185 */ 1186 if (global.turbo_disabled_mf != global.turbo_disabled) { 1187 global.turbo_disabled_mf = global.turbo_disabled; 1188 arch_set_max_freq_ratio(global.turbo_disabled); 1189 for_each_possible_cpu(cpu) 1190 intel_pstate_update_max_freq(cpu); 1191 } else { 1192 cpufreq_update_policy(cpu); 1193 } 1194 1195 mutex_unlock(&intel_pstate_driver_lock); 1196 } 1197 1198 /************************** sysfs begin ************************/ 1199 #define show_one(file_name, object) \ 1200 static ssize_t show_##file_name \ 1201 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1202 { \ 1203 return sprintf(buf, "%u\n", global.object); \ 1204 } 1205 1206 static ssize_t intel_pstate_show_status(char *buf); 1207 static int intel_pstate_update_status(const char *buf, size_t size); 1208 1209 static ssize_t show_status(struct kobject *kobj, 1210 struct kobj_attribute *attr, char *buf) 1211 { 1212 ssize_t ret; 1213 1214 mutex_lock(&intel_pstate_driver_lock); 1215 ret = intel_pstate_show_status(buf); 1216 mutex_unlock(&intel_pstate_driver_lock); 1217 1218 return ret; 1219 } 1220 1221 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1222 const char *buf, size_t count) 1223 { 1224 char *p = memchr(buf, '\n', count); 1225 int ret; 1226 1227 mutex_lock(&intel_pstate_driver_lock); 1228 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1229 mutex_unlock(&intel_pstate_driver_lock); 1230 1231 return ret < 0 ? ret : count; 1232 } 1233 1234 static ssize_t show_turbo_pct(struct kobject *kobj, 1235 struct kobj_attribute *attr, char *buf) 1236 { 1237 struct cpudata *cpu; 1238 int total, no_turbo, turbo_pct; 1239 uint32_t turbo_fp; 1240 1241 mutex_lock(&intel_pstate_driver_lock); 1242 1243 if (!intel_pstate_driver) { 1244 mutex_unlock(&intel_pstate_driver_lock); 1245 return -EAGAIN; 1246 } 1247 1248 cpu = all_cpu_data[0]; 1249 1250 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1251 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1252 turbo_fp = div_fp(no_turbo, total); 1253 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1254 1255 mutex_unlock(&intel_pstate_driver_lock); 1256 1257 return sprintf(buf, "%u\n", turbo_pct); 1258 } 1259 1260 static ssize_t show_num_pstates(struct kobject *kobj, 1261 struct kobj_attribute *attr, char *buf) 1262 { 1263 struct cpudata *cpu; 1264 int total; 1265 1266 mutex_lock(&intel_pstate_driver_lock); 1267 1268 if (!intel_pstate_driver) { 1269 mutex_unlock(&intel_pstate_driver_lock); 1270 return -EAGAIN; 1271 } 1272 1273 cpu = all_cpu_data[0]; 1274 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1275 1276 mutex_unlock(&intel_pstate_driver_lock); 1277 1278 return sprintf(buf, "%u\n", total); 1279 } 1280 1281 static ssize_t show_no_turbo(struct kobject *kobj, 1282 struct kobj_attribute *attr, char *buf) 1283 { 1284 ssize_t ret; 1285 1286 mutex_lock(&intel_pstate_driver_lock); 1287 1288 if (!intel_pstate_driver) { 1289 mutex_unlock(&intel_pstate_driver_lock); 1290 return -EAGAIN; 1291 } 1292 1293 update_turbo_state(); 1294 if (global.turbo_disabled) 1295 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1296 else 1297 ret = sprintf(buf, "%u\n", global.no_turbo); 1298 1299 mutex_unlock(&intel_pstate_driver_lock); 1300 1301 return ret; 1302 } 1303 1304 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1305 const char *buf, size_t count) 1306 { 1307 unsigned int input; 1308 int ret; 1309 1310 ret = sscanf(buf, "%u", &input); 1311 if (ret != 1) 1312 return -EINVAL; 1313 1314 mutex_lock(&intel_pstate_driver_lock); 1315 1316 if (!intel_pstate_driver) { 1317 mutex_unlock(&intel_pstate_driver_lock); 1318 return -EAGAIN; 1319 } 1320 1321 mutex_lock(&intel_pstate_limits_lock); 1322 1323 update_turbo_state(); 1324 if (global.turbo_disabled) { 1325 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1326 mutex_unlock(&intel_pstate_limits_lock); 1327 mutex_unlock(&intel_pstate_driver_lock); 1328 return -EPERM; 1329 } 1330 1331 global.no_turbo = clamp_t(int, input, 0, 1); 1332 1333 if (global.no_turbo) { 1334 struct cpudata *cpu = all_cpu_data[0]; 1335 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1336 1337 /* Squash the global minimum into the permitted range. */ 1338 if (global.min_perf_pct > pct) 1339 global.min_perf_pct = pct; 1340 } 1341 1342 mutex_unlock(&intel_pstate_limits_lock); 1343 1344 intel_pstate_update_policies(); 1345 arch_set_max_freq_ratio(global.no_turbo); 1346 1347 mutex_unlock(&intel_pstate_driver_lock); 1348 1349 return count; 1350 } 1351 1352 static void update_qos_request(enum freq_qos_req_type type) 1353 { 1354 struct freq_qos_request *req; 1355 struct cpufreq_policy *policy; 1356 int i; 1357 1358 for_each_possible_cpu(i) { 1359 struct cpudata *cpu = all_cpu_data[i]; 1360 unsigned int freq, perf_pct; 1361 1362 policy = cpufreq_cpu_get(i); 1363 if (!policy) 1364 continue; 1365 1366 req = policy->driver_data; 1367 cpufreq_cpu_put(policy); 1368 1369 if (!req) 1370 continue; 1371 1372 if (hwp_active) 1373 intel_pstate_get_hwp_cap(cpu); 1374 1375 if (type == FREQ_QOS_MIN) { 1376 perf_pct = global.min_perf_pct; 1377 } else { 1378 req++; 1379 perf_pct = global.max_perf_pct; 1380 } 1381 1382 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1383 1384 if (freq_qos_update_request(req, freq) < 0) 1385 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1386 } 1387 } 1388 1389 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1390 const char *buf, size_t count) 1391 { 1392 unsigned int input; 1393 int ret; 1394 1395 ret = sscanf(buf, "%u", &input); 1396 if (ret != 1) 1397 return -EINVAL; 1398 1399 mutex_lock(&intel_pstate_driver_lock); 1400 1401 if (!intel_pstate_driver) { 1402 mutex_unlock(&intel_pstate_driver_lock); 1403 return -EAGAIN; 1404 } 1405 1406 mutex_lock(&intel_pstate_limits_lock); 1407 1408 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1409 1410 mutex_unlock(&intel_pstate_limits_lock); 1411 1412 if (intel_pstate_driver == &intel_pstate) 1413 intel_pstate_update_policies(); 1414 else 1415 update_qos_request(FREQ_QOS_MAX); 1416 1417 mutex_unlock(&intel_pstate_driver_lock); 1418 1419 return count; 1420 } 1421 1422 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1423 const char *buf, size_t count) 1424 { 1425 unsigned int input; 1426 int ret; 1427 1428 ret = sscanf(buf, "%u", &input); 1429 if (ret != 1) 1430 return -EINVAL; 1431 1432 mutex_lock(&intel_pstate_driver_lock); 1433 1434 if (!intel_pstate_driver) { 1435 mutex_unlock(&intel_pstate_driver_lock); 1436 return -EAGAIN; 1437 } 1438 1439 mutex_lock(&intel_pstate_limits_lock); 1440 1441 global.min_perf_pct = clamp_t(int, input, 1442 min_perf_pct_min(), global.max_perf_pct); 1443 1444 mutex_unlock(&intel_pstate_limits_lock); 1445 1446 if (intel_pstate_driver == &intel_pstate) 1447 intel_pstate_update_policies(); 1448 else 1449 update_qos_request(FREQ_QOS_MIN); 1450 1451 mutex_unlock(&intel_pstate_driver_lock); 1452 1453 return count; 1454 } 1455 1456 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1457 struct kobj_attribute *attr, char *buf) 1458 { 1459 return sprintf(buf, "%u\n", hwp_boost); 1460 } 1461 1462 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1463 struct kobj_attribute *b, 1464 const char *buf, size_t count) 1465 { 1466 unsigned int input; 1467 int ret; 1468 1469 ret = kstrtouint(buf, 10, &input); 1470 if (ret) 1471 return ret; 1472 1473 mutex_lock(&intel_pstate_driver_lock); 1474 hwp_boost = !!input; 1475 intel_pstate_update_policies(); 1476 mutex_unlock(&intel_pstate_driver_lock); 1477 1478 return count; 1479 } 1480 1481 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1482 char *buf) 1483 { 1484 u64 power_ctl; 1485 int enable; 1486 1487 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1488 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1489 return sprintf(buf, "%d\n", !enable); 1490 } 1491 1492 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1493 const char *buf, size_t count) 1494 { 1495 bool input; 1496 int ret; 1497 1498 ret = kstrtobool(buf, &input); 1499 if (ret) 1500 return ret; 1501 1502 set_power_ctl_ee_state(input); 1503 1504 return count; 1505 } 1506 1507 show_one(max_perf_pct, max_perf_pct); 1508 show_one(min_perf_pct, min_perf_pct); 1509 1510 define_one_global_rw(status); 1511 define_one_global_rw(no_turbo); 1512 define_one_global_rw(max_perf_pct); 1513 define_one_global_rw(min_perf_pct); 1514 define_one_global_ro(turbo_pct); 1515 define_one_global_ro(num_pstates); 1516 define_one_global_rw(hwp_dynamic_boost); 1517 define_one_global_rw(energy_efficiency); 1518 1519 static struct attribute *intel_pstate_attributes[] = { 1520 &status.attr, 1521 &no_turbo.attr, 1522 NULL 1523 }; 1524 1525 static const struct attribute_group intel_pstate_attr_group = { 1526 .attrs = intel_pstate_attributes, 1527 }; 1528 1529 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1530 1531 static struct kobject *intel_pstate_kobject; 1532 1533 static void __init intel_pstate_sysfs_expose_params(void) 1534 { 1535 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1536 int rc; 1537 1538 if (dev_root) { 1539 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1540 put_device(dev_root); 1541 } 1542 if (WARN_ON(!intel_pstate_kobject)) 1543 return; 1544 1545 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1546 if (WARN_ON(rc)) 1547 return; 1548 1549 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1550 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1551 WARN_ON(rc); 1552 1553 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1554 WARN_ON(rc); 1555 } 1556 1557 /* 1558 * If per cpu limits are enforced there are no global limits, so 1559 * return without creating max/min_perf_pct attributes 1560 */ 1561 if (per_cpu_limits) 1562 return; 1563 1564 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1565 WARN_ON(rc); 1566 1567 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1568 WARN_ON(rc); 1569 1570 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1571 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1572 WARN_ON(rc); 1573 } 1574 } 1575 1576 static void __init intel_pstate_sysfs_remove(void) 1577 { 1578 if (!intel_pstate_kobject) 1579 return; 1580 1581 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1582 1583 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1584 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1585 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1586 } 1587 1588 if (!per_cpu_limits) { 1589 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1590 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1591 1592 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1593 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1594 } 1595 1596 kobject_put(intel_pstate_kobject); 1597 } 1598 1599 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1600 { 1601 int rc; 1602 1603 if (!hwp_active) 1604 return; 1605 1606 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1607 WARN_ON_ONCE(rc); 1608 } 1609 1610 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1611 { 1612 if (!hwp_active) 1613 return; 1614 1615 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1616 } 1617 1618 /************************** sysfs end ************************/ 1619 1620 static void intel_pstate_notify_work(struct work_struct *work) 1621 { 1622 struct cpudata *cpudata = 1623 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1624 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1625 1626 if (policy) { 1627 intel_pstate_get_hwp_cap(cpudata); 1628 __intel_pstate_update_max_freq(cpudata, policy); 1629 1630 cpufreq_cpu_release(policy); 1631 } 1632 1633 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1634 } 1635 1636 static DEFINE_SPINLOCK(hwp_notify_lock); 1637 static cpumask_t hwp_intr_enable_mask; 1638 1639 void notify_hwp_interrupt(void) 1640 { 1641 unsigned int this_cpu = smp_processor_id(); 1642 struct cpudata *cpudata; 1643 unsigned long flags; 1644 u64 value; 1645 1646 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1647 return; 1648 1649 rdmsrl_safe(MSR_HWP_STATUS, &value); 1650 if (!(value & 0x01)) 1651 return; 1652 1653 spin_lock_irqsave(&hwp_notify_lock, flags); 1654 1655 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1656 goto ack_intr; 1657 1658 /* 1659 * Currently we never free all_cpu_data. And we can't reach here 1660 * without this allocated. But for safety for future changes, added 1661 * check. 1662 */ 1663 if (unlikely(!READ_ONCE(all_cpu_data))) 1664 goto ack_intr; 1665 1666 /* 1667 * The free is done during cleanup, when cpufreq registry is failed. 1668 * We wouldn't be here if it fails on init or switch status. But for 1669 * future changes, added check. 1670 */ 1671 cpudata = READ_ONCE(all_cpu_data[this_cpu]); 1672 if (unlikely(!cpudata)) 1673 goto ack_intr; 1674 1675 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10)); 1676 1677 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1678 1679 return; 1680 1681 ack_intr: 1682 wrmsrl_safe(MSR_HWP_STATUS, 0); 1683 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1684 } 1685 1686 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1687 { 1688 unsigned long flags; 1689 1690 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1691 return; 1692 1693 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1694 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1695 1696 spin_lock_irqsave(&hwp_notify_lock, flags); 1697 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask)) 1698 cancel_delayed_work(&cpudata->hwp_notify_work); 1699 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1700 } 1701 1702 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1703 { 1704 /* Enable HWP notification interrupt for guaranteed performance change */ 1705 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1706 unsigned long flags; 1707 1708 spin_lock_irqsave(&hwp_notify_lock, flags); 1709 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1710 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1711 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1712 1713 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1714 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1715 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1716 } 1717 } 1718 1719 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1720 { 1721 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1722 1723 /* 1724 * If this CPU gen doesn't call for change in balance_perf 1725 * EPP return. 1726 */ 1727 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1728 return; 1729 1730 /* 1731 * If the EPP is set by firmware, which means that firmware enabled HWP 1732 * - Is equal or less than 0x80 (default balance_perf EPP) 1733 * - But less performance oriented than performance EPP 1734 * then use this as new balance_perf EPP. 1735 */ 1736 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1737 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1738 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1739 return; 1740 } 1741 1742 /* 1743 * Use hard coded value per gen to update the balance_perf 1744 * and default EPP. 1745 */ 1746 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1747 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1748 } 1749 1750 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1751 { 1752 /* First disable HWP notification interrupt till we activate again */ 1753 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1754 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1755 1756 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1757 1758 intel_pstate_enable_hwp_interrupt(cpudata); 1759 1760 if (cpudata->epp_default >= 0) 1761 return; 1762 1763 intel_pstate_update_epp_defaults(cpudata); 1764 } 1765 1766 static int atom_get_min_pstate(int not_used) 1767 { 1768 u64 value; 1769 1770 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1771 return (value >> 8) & 0x7F; 1772 } 1773 1774 static int atom_get_max_pstate(int not_used) 1775 { 1776 u64 value; 1777 1778 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1779 return (value >> 16) & 0x7F; 1780 } 1781 1782 static int atom_get_turbo_pstate(int not_used) 1783 { 1784 u64 value; 1785 1786 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1787 return value & 0x7F; 1788 } 1789 1790 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1791 { 1792 u64 val; 1793 int32_t vid_fp; 1794 u32 vid; 1795 1796 val = (u64)pstate << 8; 1797 if (global.no_turbo && !global.turbo_disabled) 1798 val |= (u64)1 << 32; 1799 1800 vid_fp = cpudata->vid.min + mul_fp( 1801 int_tofp(pstate - cpudata->pstate.min_pstate), 1802 cpudata->vid.ratio); 1803 1804 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1805 vid = ceiling_fp(vid_fp); 1806 1807 if (pstate > cpudata->pstate.max_pstate) 1808 vid = cpudata->vid.turbo; 1809 1810 return val | vid; 1811 } 1812 1813 static int silvermont_get_scaling(void) 1814 { 1815 u64 value; 1816 int i; 1817 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1818 static int silvermont_freq_table[] = { 1819 83300, 100000, 133300, 116700, 80000}; 1820 1821 rdmsrl(MSR_FSB_FREQ, value); 1822 i = value & 0x7; 1823 WARN_ON(i > 4); 1824 1825 return silvermont_freq_table[i]; 1826 } 1827 1828 static int airmont_get_scaling(void) 1829 { 1830 u64 value; 1831 int i; 1832 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1833 static int airmont_freq_table[] = { 1834 83300, 100000, 133300, 116700, 80000, 1835 93300, 90000, 88900, 87500}; 1836 1837 rdmsrl(MSR_FSB_FREQ, value); 1838 i = value & 0xF; 1839 WARN_ON(i > 8); 1840 1841 return airmont_freq_table[i]; 1842 } 1843 1844 static void atom_get_vid(struct cpudata *cpudata) 1845 { 1846 u64 value; 1847 1848 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1849 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1850 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1851 cpudata->vid.ratio = div_fp( 1852 cpudata->vid.max - cpudata->vid.min, 1853 int_tofp(cpudata->pstate.max_pstate - 1854 cpudata->pstate.min_pstate)); 1855 1856 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1857 cpudata->vid.turbo = value & 0x7f; 1858 } 1859 1860 static int core_get_min_pstate(int cpu) 1861 { 1862 u64 value; 1863 1864 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1865 return (value >> 40) & 0xFF; 1866 } 1867 1868 static int core_get_max_pstate_physical(int cpu) 1869 { 1870 u64 value; 1871 1872 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1873 return (value >> 8) & 0xFF; 1874 } 1875 1876 static int core_get_tdp_ratio(int cpu, u64 plat_info) 1877 { 1878 /* Check how many TDP levels present */ 1879 if (plat_info & 0x600000000) { 1880 u64 tdp_ctrl; 1881 u64 tdp_ratio; 1882 int tdp_msr; 1883 int err; 1884 1885 /* Get the TDP level (0, 1, 2) to get ratios */ 1886 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1887 if (err) 1888 return err; 1889 1890 /* TDP MSR are continuous starting at 0x648 */ 1891 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1892 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 1893 if (err) 1894 return err; 1895 1896 /* For level 1 and 2, bits[23:16] contain the ratio */ 1897 if (tdp_ctrl & 0x03) 1898 tdp_ratio >>= 16; 1899 1900 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1901 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1902 1903 return (int)tdp_ratio; 1904 } 1905 1906 return -ENXIO; 1907 } 1908 1909 static int core_get_max_pstate(int cpu) 1910 { 1911 u64 tar; 1912 u64 plat_info; 1913 int max_pstate; 1914 int tdp_ratio; 1915 int err; 1916 1917 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 1918 max_pstate = (plat_info >> 8) & 0xFF; 1919 1920 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 1921 if (tdp_ratio <= 0) 1922 return max_pstate; 1923 1924 if (hwp_active) { 1925 /* Turbo activation ratio is not used on HWP platforms */ 1926 return tdp_ratio; 1927 } 1928 1929 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 1930 if (!err) { 1931 int tar_levels; 1932 1933 /* Do some sanity checking for safety */ 1934 tar_levels = tar & 0xff; 1935 if (tdp_ratio - 1 == tar_levels) { 1936 max_pstate = tar_levels; 1937 pr_debug("max_pstate=TAC %x\n", max_pstate); 1938 } 1939 } 1940 1941 return max_pstate; 1942 } 1943 1944 static int core_get_turbo_pstate(int cpu) 1945 { 1946 u64 value; 1947 int nont, ret; 1948 1949 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1950 nont = core_get_max_pstate(cpu); 1951 ret = (value) & 255; 1952 if (ret <= nont) 1953 ret = nont; 1954 return ret; 1955 } 1956 1957 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1958 { 1959 u64 val; 1960 1961 val = (u64)pstate << 8; 1962 if (global.no_turbo && !global.turbo_disabled) 1963 val |= (u64)1 << 32; 1964 1965 return val; 1966 } 1967 1968 static int knl_get_aperf_mperf_shift(void) 1969 { 1970 return 10; 1971 } 1972 1973 static int knl_get_turbo_pstate(int cpu) 1974 { 1975 u64 value; 1976 int nont, ret; 1977 1978 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1979 nont = core_get_max_pstate(cpu); 1980 ret = (((value) >> 8) & 0xFF); 1981 if (ret <= nont) 1982 ret = nont; 1983 return ret; 1984 } 1985 1986 static void hybrid_get_type(void *data) 1987 { 1988 u8 *cpu_type = data; 1989 1990 *cpu_type = get_this_hybrid_cpu_type(); 1991 } 1992 1993 static int hwp_get_cpu_scaling(int cpu) 1994 { 1995 u8 cpu_type = 0; 1996 1997 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 1998 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 1999 if (cpu_type == 0x40) 2000 return HYBRID_SCALING_FACTOR; 2001 2002 /* Use default core scaling for E-cores */ 2003 if (cpu_type == 0x20) 2004 return core_get_scaling(); 2005 2006 /* 2007 * If reached here, this system is either non-hybrid (like Tiger 2008 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with 2009 * no E cores (in which case CPUID for hybrid support is 0). 2010 * 2011 * The CPPC nominal_frequency field is 0 for non-hybrid systems, 2012 * so the default core scaling will be used for them. 2013 */ 2014 return intel_pstate_cppc_get_scaling(cpu); 2015 } 2016 2017 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 2018 { 2019 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 2020 cpu->pstate.current_pstate = pstate; 2021 /* 2022 * Generally, there is no guarantee that this code will always run on 2023 * the CPU being updated, so force the register update to run on the 2024 * right CPU. 2025 */ 2026 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2027 pstate_funcs.get_val(cpu, pstate)); 2028 } 2029 2030 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 2031 { 2032 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 2033 } 2034 2035 static void intel_pstate_max_within_limits(struct cpudata *cpu) 2036 { 2037 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 2038 2039 update_turbo_state(); 2040 intel_pstate_set_pstate(cpu, pstate); 2041 } 2042 2043 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2044 { 2045 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2046 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2047 2048 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2049 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2050 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2051 2052 if (hwp_active && !hwp_mode_bdw) { 2053 __intel_pstate_get_hwp_cap(cpu); 2054 2055 if (pstate_funcs.get_cpu_scaling) { 2056 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2057 if (cpu->pstate.scaling != perf_ctl_scaling) 2058 intel_pstate_hybrid_hwp_adjust(cpu); 2059 } else { 2060 cpu->pstate.scaling = perf_ctl_scaling; 2061 } 2062 } else { 2063 cpu->pstate.scaling = perf_ctl_scaling; 2064 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2065 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2066 } 2067 2068 if (cpu->pstate.scaling == perf_ctl_scaling) { 2069 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2070 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2071 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2072 } 2073 2074 if (pstate_funcs.get_aperf_mperf_shift) 2075 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2076 2077 if (pstate_funcs.get_vid) 2078 pstate_funcs.get_vid(cpu); 2079 2080 intel_pstate_set_min_pstate(cpu); 2081 } 2082 2083 /* 2084 * Long hold time will keep high perf limits for long time, 2085 * which negatively impacts perf/watt for some workloads, 2086 * like specpower. 3ms is based on experiements on some 2087 * workoads. 2088 */ 2089 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2090 2091 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2092 { 2093 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2094 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2095 u32 max_limit = (hwp_req & 0xff00) >> 8; 2096 u32 min_limit = (hwp_req & 0xff); 2097 u32 boost_level1; 2098 2099 /* 2100 * Cases to consider (User changes via sysfs or boot time): 2101 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2102 * No boost, return. 2103 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2104 * Should result in one level boost only for P0. 2105 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2106 * Should result in two level boost: 2107 * (min + p1)/2 and P1. 2108 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2109 * Should result in three level boost: 2110 * (min + p1)/2, P1 and P0. 2111 */ 2112 2113 /* If max and min are equal or already at max, nothing to boost */ 2114 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2115 return; 2116 2117 if (!cpu->hwp_boost_min) 2118 cpu->hwp_boost_min = min_limit; 2119 2120 /* level at half way mark between min and guranteed */ 2121 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2122 2123 if (cpu->hwp_boost_min < boost_level1) 2124 cpu->hwp_boost_min = boost_level1; 2125 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2126 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2127 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2128 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2129 cpu->hwp_boost_min = max_limit; 2130 else 2131 return; 2132 2133 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2134 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2135 cpu->last_update = cpu->sample.time; 2136 } 2137 2138 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2139 { 2140 if (cpu->hwp_boost_min) { 2141 bool expired; 2142 2143 /* Check if we are idle for hold time to boost down */ 2144 expired = time_after64(cpu->sample.time, cpu->last_update + 2145 hwp_boost_hold_time_ns); 2146 if (expired) { 2147 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2148 cpu->hwp_boost_min = 0; 2149 } 2150 } 2151 cpu->last_update = cpu->sample.time; 2152 } 2153 2154 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2155 u64 time) 2156 { 2157 cpu->sample.time = time; 2158 2159 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2160 bool do_io = false; 2161 2162 cpu->sched_flags = 0; 2163 /* 2164 * Set iowait_boost flag and update time. Since IO WAIT flag 2165 * is set all the time, we can't just conclude that there is 2166 * some IO bound activity is scheduled on this CPU with just 2167 * one occurrence. If we receive at least two in two 2168 * consecutive ticks, then we treat as boost candidate. 2169 */ 2170 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2171 do_io = true; 2172 2173 cpu->last_io_update = time; 2174 2175 if (do_io) 2176 intel_pstate_hwp_boost_up(cpu); 2177 2178 } else { 2179 intel_pstate_hwp_boost_down(cpu); 2180 } 2181 } 2182 2183 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2184 u64 time, unsigned int flags) 2185 { 2186 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2187 2188 cpu->sched_flags |= flags; 2189 2190 if (smp_processor_id() == cpu->cpu) 2191 intel_pstate_update_util_hwp_local(cpu, time); 2192 } 2193 2194 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2195 { 2196 struct sample *sample = &cpu->sample; 2197 2198 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2199 } 2200 2201 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2202 { 2203 u64 aperf, mperf; 2204 unsigned long flags; 2205 u64 tsc; 2206 2207 local_irq_save(flags); 2208 rdmsrl(MSR_IA32_APERF, aperf); 2209 rdmsrl(MSR_IA32_MPERF, mperf); 2210 tsc = rdtsc(); 2211 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2212 local_irq_restore(flags); 2213 return false; 2214 } 2215 local_irq_restore(flags); 2216 2217 cpu->last_sample_time = cpu->sample.time; 2218 cpu->sample.time = time; 2219 cpu->sample.aperf = aperf; 2220 cpu->sample.mperf = mperf; 2221 cpu->sample.tsc = tsc; 2222 cpu->sample.aperf -= cpu->prev_aperf; 2223 cpu->sample.mperf -= cpu->prev_mperf; 2224 cpu->sample.tsc -= cpu->prev_tsc; 2225 2226 cpu->prev_aperf = aperf; 2227 cpu->prev_mperf = mperf; 2228 cpu->prev_tsc = tsc; 2229 /* 2230 * First time this function is invoked in a given cycle, all of the 2231 * previous sample data fields are equal to zero or stale and they must 2232 * be populated with meaningful numbers for things to work, so assume 2233 * that sample.time will always be reset before setting the utilization 2234 * update hook and make the caller skip the sample then. 2235 */ 2236 if (cpu->last_sample_time) { 2237 intel_pstate_calc_avg_perf(cpu); 2238 return true; 2239 } 2240 return false; 2241 } 2242 2243 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2244 { 2245 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2246 } 2247 2248 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2249 { 2250 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2251 cpu->sample.core_avg_perf); 2252 } 2253 2254 static inline int32_t get_target_pstate(struct cpudata *cpu) 2255 { 2256 struct sample *sample = &cpu->sample; 2257 int32_t busy_frac; 2258 int target, avg_pstate; 2259 2260 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2261 sample->tsc); 2262 2263 if (busy_frac < cpu->iowait_boost) 2264 busy_frac = cpu->iowait_boost; 2265 2266 sample->busy_scaled = busy_frac * 100; 2267 2268 target = global.no_turbo || global.turbo_disabled ? 2269 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2270 target += target >> 2; 2271 target = mul_fp(target, busy_frac); 2272 if (target < cpu->pstate.min_pstate) 2273 target = cpu->pstate.min_pstate; 2274 2275 /* 2276 * If the average P-state during the previous cycle was higher than the 2277 * current target, add 50% of the difference to the target to reduce 2278 * possible performance oscillations and offset possible performance 2279 * loss related to moving the workload from one CPU to another within 2280 * a package/module. 2281 */ 2282 avg_pstate = get_avg_pstate(cpu); 2283 if (avg_pstate > target) 2284 target += (avg_pstate - target) >> 1; 2285 2286 return target; 2287 } 2288 2289 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2290 { 2291 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2292 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2293 2294 return clamp_t(int, pstate, min_pstate, max_pstate); 2295 } 2296 2297 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2298 { 2299 if (pstate == cpu->pstate.current_pstate) 2300 return; 2301 2302 cpu->pstate.current_pstate = pstate; 2303 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2304 } 2305 2306 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2307 { 2308 int from = cpu->pstate.current_pstate; 2309 struct sample *sample; 2310 int target_pstate; 2311 2312 update_turbo_state(); 2313 2314 target_pstate = get_target_pstate(cpu); 2315 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2316 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2317 intel_pstate_update_pstate(cpu, target_pstate); 2318 2319 sample = &cpu->sample; 2320 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2321 fp_toint(sample->busy_scaled), 2322 from, 2323 cpu->pstate.current_pstate, 2324 sample->mperf, 2325 sample->aperf, 2326 sample->tsc, 2327 get_avg_frequency(cpu), 2328 fp_toint(cpu->iowait_boost * 100)); 2329 } 2330 2331 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2332 unsigned int flags) 2333 { 2334 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2335 u64 delta_ns; 2336 2337 /* Don't allow remote callbacks */ 2338 if (smp_processor_id() != cpu->cpu) 2339 return; 2340 2341 delta_ns = time - cpu->last_update; 2342 if (flags & SCHED_CPUFREQ_IOWAIT) { 2343 /* Start over if the CPU may have been idle. */ 2344 if (delta_ns > TICK_NSEC) { 2345 cpu->iowait_boost = ONE_EIGHTH_FP; 2346 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2347 cpu->iowait_boost <<= 1; 2348 if (cpu->iowait_boost > int_tofp(1)) 2349 cpu->iowait_boost = int_tofp(1); 2350 } else { 2351 cpu->iowait_boost = ONE_EIGHTH_FP; 2352 } 2353 } else if (cpu->iowait_boost) { 2354 /* Clear iowait_boost if the CPU may have been idle. */ 2355 if (delta_ns > TICK_NSEC) 2356 cpu->iowait_boost = 0; 2357 else 2358 cpu->iowait_boost >>= 1; 2359 } 2360 cpu->last_update = time; 2361 delta_ns = time - cpu->sample.time; 2362 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2363 return; 2364 2365 if (intel_pstate_sample(cpu, time)) 2366 intel_pstate_adjust_pstate(cpu); 2367 } 2368 2369 static struct pstate_funcs core_funcs = { 2370 .get_max = core_get_max_pstate, 2371 .get_max_physical = core_get_max_pstate_physical, 2372 .get_min = core_get_min_pstate, 2373 .get_turbo = core_get_turbo_pstate, 2374 .get_scaling = core_get_scaling, 2375 .get_val = core_get_val, 2376 }; 2377 2378 static const struct pstate_funcs silvermont_funcs = { 2379 .get_max = atom_get_max_pstate, 2380 .get_max_physical = atom_get_max_pstate, 2381 .get_min = atom_get_min_pstate, 2382 .get_turbo = atom_get_turbo_pstate, 2383 .get_val = atom_get_val, 2384 .get_scaling = silvermont_get_scaling, 2385 .get_vid = atom_get_vid, 2386 }; 2387 2388 static const struct pstate_funcs airmont_funcs = { 2389 .get_max = atom_get_max_pstate, 2390 .get_max_physical = atom_get_max_pstate, 2391 .get_min = atom_get_min_pstate, 2392 .get_turbo = atom_get_turbo_pstate, 2393 .get_val = atom_get_val, 2394 .get_scaling = airmont_get_scaling, 2395 .get_vid = atom_get_vid, 2396 }; 2397 2398 static const struct pstate_funcs knl_funcs = { 2399 .get_max = core_get_max_pstate, 2400 .get_max_physical = core_get_max_pstate_physical, 2401 .get_min = core_get_min_pstate, 2402 .get_turbo = knl_get_turbo_pstate, 2403 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2404 .get_scaling = core_get_scaling, 2405 .get_val = core_get_val, 2406 }; 2407 2408 #define X86_MATCH(model, policy) \ 2409 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2410 X86_FEATURE_APERFMPERF, &policy) 2411 2412 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2413 X86_MATCH(SANDYBRIDGE, core_funcs), 2414 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2415 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2416 X86_MATCH(IVYBRIDGE, core_funcs), 2417 X86_MATCH(HASWELL, core_funcs), 2418 X86_MATCH(BROADWELL, core_funcs), 2419 X86_MATCH(IVYBRIDGE_X, core_funcs), 2420 X86_MATCH(HASWELL_X, core_funcs), 2421 X86_MATCH(HASWELL_L, core_funcs), 2422 X86_MATCH(HASWELL_G, core_funcs), 2423 X86_MATCH(BROADWELL_G, core_funcs), 2424 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2425 X86_MATCH(SKYLAKE_L, core_funcs), 2426 X86_MATCH(BROADWELL_X, core_funcs), 2427 X86_MATCH(SKYLAKE, core_funcs), 2428 X86_MATCH(BROADWELL_D, core_funcs), 2429 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2430 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2431 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2432 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2433 X86_MATCH(SKYLAKE_X, core_funcs), 2434 X86_MATCH(COMETLAKE, core_funcs), 2435 X86_MATCH(ICELAKE_X, core_funcs), 2436 X86_MATCH(TIGERLAKE, core_funcs), 2437 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2438 {} 2439 }; 2440 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2441 2442 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2443 X86_MATCH(BROADWELL_D, core_funcs), 2444 X86_MATCH(BROADWELL_X, core_funcs), 2445 X86_MATCH(SKYLAKE_X, core_funcs), 2446 X86_MATCH(ICELAKE_X, core_funcs), 2447 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2448 {} 2449 }; 2450 2451 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2452 X86_MATCH(KABYLAKE, core_funcs), 2453 {} 2454 }; 2455 2456 static int intel_pstate_init_cpu(unsigned int cpunum) 2457 { 2458 struct cpudata *cpu; 2459 2460 cpu = all_cpu_data[cpunum]; 2461 2462 if (!cpu) { 2463 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2464 if (!cpu) 2465 return -ENOMEM; 2466 2467 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2468 2469 cpu->cpu = cpunum; 2470 2471 cpu->epp_default = -EINVAL; 2472 2473 if (hwp_active) { 2474 intel_pstate_hwp_enable(cpu); 2475 2476 if (intel_pstate_acpi_pm_profile_server()) 2477 hwp_boost = true; 2478 } 2479 } else if (hwp_active) { 2480 /* 2481 * Re-enable HWP in case this happens after a resume from ACPI 2482 * S3 if the CPU was offline during the whole system/resume 2483 * cycle. 2484 */ 2485 intel_pstate_hwp_reenable(cpu); 2486 } 2487 2488 cpu->epp_powersave = -EINVAL; 2489 cpu->epp_policy = 0; 2490 2491 intel_pstate_get_cpu_pstates(cpu); 2492 2493 pr_debug("controlling: cpu %d\n", cpunum); 2494 2495 return 0; 2496 } 2497 2498 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2499 { 2500 struct cpudata *cpu = all_cpu_data[cpu_num]; 2501 2502 if (hwp_active && !hwp_boost) 2503 return; 2504 2505 if (cpu->update_util_set) 2506 return; 2507 2508 /* Prevent intel_pstate_update_util() from using stale data. */ 2509 cpu->sample.time = 0; 2510 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2511 (hwp_active ? 2512 intel_pstate_update_util_hwp : 2513 intel_pstate_update_util)); 2514 cpu->update_util_set = true; 2515 } 2516 2517 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2518 { 2519 struct cpudata *cpu_data = all_cpu_data[cpu]; 2520 2521 if (!cpu_data->update_util_set) 2522 return; 2523 2524 cpufreq_remove_update_util_hook(cpu); 2525 cpu_data->update_util_set = false; 2526 synchronize_rcu(); 2527 } 2528 2529 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2530 { 2531 return global.turbo_disabled || global.no_turbo ? 2532 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2533 } 2534 2535 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2536 unsigned int policy_min, 2537 unsigned int policy_max) 2538 { 2539 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2540 int32_t max_policy_perf, min_policy_perf; 2541 2542 max_policy_perf = policy_max / perf_ctl_scaling; 2543 if (policy_max == policy_min) { 2544 min_policy_perf = max_policy_perf; 2545 } else { 2546 min_policy_perf = policy_min / perf_ctl_scaling; 2547 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2548 0, max_policy_perf); 2549 } 2550 2551 /* 2552 * HWP needs some special consideration, because HWP_REQUEST uses 2553 * abstract values to represent performance rather than pure ratios. 2554 */ 2555 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2556 int freq; 2557 2558 freq = max_policy_perf * perf_ctl_scaling; 2559 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2560 freq = min_policy_perf * perf_ctl_scaling; 2561 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq); 2562 } 2563 2564 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2565 cpu->cpu, min_policy_perf, max_policy_perf); 2566 2567 /* Normalize user input to [min_perf, max_perf] */ 2568 if (per_cpu_limits) { 2569 cpu->min_perf_ratio = min_policy_perf; 2570 cpu->max_perf_ratio = max_policy_perf; 2571 } else { 2572 int turbo_max = cpu->pstate.turbo_pstate; 2573 int32_t global_min, global_max; 2574 2575 /* Global limits are in percent of the maximum turbo P-state. */ 2576 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2577 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2578 global_min = clamp_t(int32_t, global_min, 0, global_max); 2579 2580 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2581 global_min, global_max); 2582 2583 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2584 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2585 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2586 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2587 2588 /* Make sure min_perf <= max_perf */ 2589 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2590 cpu->max_perf_ratio); 2591 2592 } 2593 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2594 cpu->max_perf_ratio, 2595 cpu->min_perf_ratio); 2596 } 2597 2598 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2599 { 2600 struct cpudata *cpu; 2601 2602 if (!policy->cpuinfo.max_freq) 2603 return -ENODEV; 2604 2605 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2606 policy->cpuinfo.max_freq, policy->max); 2607 2608 cpu = all_cpu_data[policy->cpu]; 2609 cpu->policy = policy->policy; 2610 2611 mutex_lock(&intel_pstate_limits_lock); 2612 2613 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2614 2615 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2616 /* 2617 * NOHZ_FULL CPUs need this as the governor callback may not 2618 * be invoked on them. 2619 */ 2620 intel_pstate_clear_update_util_hook(policy->cpu); 2621 intel_pstate_max_within_limits(cpu); 2622 } else { 2623 intel_pstate_set_update_util_hook(policy->cpu); 2624 } 2625 2626 if (hwp_active) { 2627 /* 2628 * When hwp_boost was active before and dynamically it 2629 * was turned off, in that case we need to clear the 2630 * update util hook. 2631 */ 2632 if (!hwp_boost) 2633 intel_pstate_clear_update_util_hook(policy->cpu); 2634 intel_pstate_hwp_set(policy->cpu); 2635 } 2636 /* 2637 * policy->cur is never updated with the intel_pstate driver, but it 2638 * is used as a stale frequency value. So, keep it within limits. 2639 */ 2640 policy->cur = policy->min; 2641 2642 mutex_unlock(&intel_pstate_limits_lock); 2643 2644 return 0; 2645 } 2646 2647 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2648 struct cpufreq_policy_data *policy) 2649 { 2650 if (!hwp_active && 2651 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2652 policy->max < policy->cpuinfo.max_freq && 2653 policy->max > cpu->pstate.max_freq) { 2654 pr_debug("policy->max > max non turbo frequency\n"); 2655 policy->max = policy->cpuinfo.max_freq; 2656 } 2657 } 2658 2659 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2660 struct cpufreq_policy_data *policy) 2661 { 2662 int max_freq; 2663 2664 update_turbo_state(); 2665 if (hwp_active) { 2666 intel_pstate_get_hwp_cap(cpu); 2667 max_freq = global.no_turbo || global.turbo_disabled ? 2668 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2669 } else { 2670 max_freq = intel_pstate_get_max_freq(cpu); 2671 } 2672 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2673 2674 intel_pstate_adjust_policy_max(cpu, policy); 2675 } 2676 2677 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2678 { 2679 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2680 2681 return 0; 2682 } 2683 2684 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2685 { 2686 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2687 2688 pr_debug("CPU %d going offline\n", cpu->cpu); 2689 2690 if (cpu->suspended) 2691 return 0; 2692 2693 /* 2694 * If the CPU is an SMT thread and it goes offline with the performance 2695 * settings different from the minimum, it will prevent its sibling 2696 * from getting to lower performance levels, so force the minimum 2697 * performance on CPU offline to prevent that from happening. 2698 */ 2699 if (hwp_active) 2700 intel_pstate_hwp_offline(cpu); 2701 else 2702 intel_pstate_set_min_pstate(cpu); 2703 2704 intel_pstate_exit_perf_limits(policy); 2705 2706 return 0; 2707 } 2708 2709 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2710 { 2711 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2712 2713 pr_debug("CPU %d going online\n", cpu->cpu); 2714 2715 intel_pstate_init_acpi_perf_limits(policy); 2716 2717 if (hwp_active) { 2718 /* 2719 * Re-enable HWP and clear the "suspended" flag to let "resume" 2720 * know that it need not do that. 2721 */ 2722 intel_pstate_hwp_reenable(cpu); 2723 cpu->suspended = false; 2724 } 2725 2726 return 0; 2727 } 2728 2729 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2730 { 2731 intel_pstate_clear_update_util_hook(policy->cpu); 2732 2733 return intel_cpufreq_cpu_offline(policy); 2734 } 2735 2736 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2737 { 2738 pr_debug("CPU %d exiting\n", policy->cpu); 2739 2740 policy->fast_switch_possible = false; 2741 2742 return 0; 2743 } 2744 2745 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2746 { 2747 struct cpudata *cpu; 2748 int rc; 2749 2750 rc = intel_pstate_init_cpu(policy->cpu); 2751 if (rc) 2752 return rc; 2753 2754 cpu = all_cpu_data[policy->cpu]; 2755 2756 cpu->max_perf_ratio = 0xFF; 2757 cpu->min_perf_ratio = 0; 2758 2759 /* cpuinfo and default policy values */ 2760 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2761 update_turbo_state(); 2762 global.turbo_disabled_mf = global.turbo_disabled; 2763 policy->cpuinfo.max_freq = global.turbo_disabled ? 2764 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2765 2766 policy->min = policy->cpuinfo.min_freq; 2767 policy->max = policy->cpuinfo.max_freq; 2768 2769 intel_pstate_init_acpi_perf_limits(policy); 2770 2771 policy->fast_switch_possible = true; 2772 2773 return 0; 2774 } 2775 2776 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2777 { 2778 int ret = __intel_pstate_cpu_init(policy); 2779 2780 if (ret) 2781 return ret; 2782 2783 /* 2784 * Set the policy to powersave to provide a valid fallback value in case 2785 * the default cpufreq governor is neither powersave nor performance. 2786 */ 2787 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2788 2789 if (hwp_active) { 2790 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2791 2792 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2793 } 2794 2795 return 0; 2796 } 2797 2798 static struct cpufreq_driver intel_pstate = { 2799 .flags = CPUFREQ_CONST_LOOPS, 2800 .verify = intel_pstate_verify_policy, 2801 .setpolicy = intel_pstate_set_policy, 2802 .suspend = intel_pstate_suspend, 2803 .resume = intel_pstate_resume, 2804 .init = intel_pstate_cpu_init, 2805 .exit = intel_pstate_cpu_exit, 2806 .offline = intel_pstate_cpu_offline, 2807 .online = intel_pstate_cpu_online, 2808 .update_limits = intel_pstate_update_limits, 2809 .name = "intel_pstate", 2810 }; 2811 2812 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2813 { 2814 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2815 2816 intel_pstate_verify_cpu_policy(cpu, policy); 2817 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2818 2819 return 0; 2820 } 2821 2822 /* Use of trace in passive mode: 2823 * 2824 * In passive mode the trace core_busy field (also known as the 2825 * performance field, and lablelled as such on the graphs; also known as 2826 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2827 * driver call was via the normal or fast switch path. Various graphs 2828 * output from the intel_pstate_tracer.py utility that include core_busy 2829 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2830 * so we use 10 to indicate the normal path through the driver, and 2831 * 90 to indicate the fast switch path through the driver. 2832 * The scaled_busy field is not used, and is set to 0. 2833 */ 2834 2835 #define INTEL_PSTATE_TRACE_TARGET 10 2836 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2837 2838 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2839 { 2840 struct sample *sample; 2841 2842 if (!trace_pstate_sample_enabled()) 2843 return; 2844 2845 if (!intel_pstate_sample(cpu, ktime_get())) 2846 return; 2847 2848 sample = &cpu->sample; 2849 trace_pstate_sample(trace_type, 2850 0, 2851 old_pstate, 2852 cpu->pstate.current_pstate, 2853 sample->mperf, 2854 sample->aperf, 2855 sample->tsc, 2856 get_avg_frequency(cpu), 2857 fp_toint(cpu->iowait_boost * 100)); 2858 } 2859 2860 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2861 u32 desired, bool fast_switch) 2862 { 2863 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2864 2865 value &= ~HWP_MIN_PERF(~0L); 2866 value |= HWP_MIN_PERF(min); 2867 2868 value &= ~HWP_MAX_PERF(~0L); 2869 value |= HWP_MAX_PERF(max); 2870 2871 value &= ~HWP_DESIRED_PERF(~0L); 2872 value |= HWP_DESIRED_PERF(desired); 2873 2874 if (value == prev) 2875 return; 2876 2877 WRITE_ONCE(cpu->hwp_req_cached, value); 2878 if (fast_switch) 2879 wrmsrl(MSR_HWP_REQUEST, value); 2880 else 2881 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2882 } 2883 2884 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2885 u32 target_pstate, bool fast_switch) 2886 { 2887 if (fast_switch) 2888 wrmsrl(MSR_IA32_PERF_CTL, 2889 pstate_funcs.get_val(cpu, target_pstate)); 2890 else 2891 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2892 pstate_funcs.get_val(cpu, target_pstate)); 2893 } 2894 2895 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2896 int target_pstate, bool fast_switch) 2897 { 2898 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2899 int old_pstate = cpu->pstate.current_pstate; 2900 2901 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2902 if (hwp_active) { 2903 int max_pstate = policy->strict_target ? 2904 target_pstate : cpu->max_perf_ratio; 2905 2906 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2907 fast_switch); 2908 } else if (target_pstate != old_pstate) { 2909 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2910 } 2911 2912 cpu->pstate.current_pstate = target_pstate; 2913 2914 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2915 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2916 2917 return target_pstate; 2918 } 2919 2920 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2921 unsigned int target_freq, 2922 unsigned int relation) 2923 { 2924 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2925 struct cpufreq_freqs freqs; 2926 int target_pstate; 2927 2928 update_turbo_state(); 2929 2930 freqs.old = policy->cur; 2931 freqs.new = target_freq; 2932 2933 cpufreq_freq_transition_begin(policy, &freqs); 2934 2935 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation); 2936 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2937 2938 freqs.new = target_pstate * cpu->pstate.scaling; 2939 2940 cpufreq_freq_transition_end(policy, &freqs, false); 2941 2942 return 0; 2943 } 2944 2945 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2946 unsigned int target_freq) 2947 { 2948 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2949 int target_pstate; 2950 2951 update_turbo_state(); 2952 2953 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq); 2954 2955 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2956 2957 return target_pstate * cpu->pstate.scaling; 2958 } 2959 2960 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2961 unsigned long min_perf, 2962 unsigned long target_perf, 2963 unsigned long capacity) 2964 { 2965 struct cpudata *cpu = all_cpu_data[cpunum]; 2966 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2967 int old_pstate = cpu->pstate.current_pstate; 2968 int cap_pstate, min_pstate, max_pstate, target_pstate; 2969 2970 update_turbo_state(); 2971 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) : 2972 HWP_HIGHEST_PERF(hwp_cap); 2973 2974 /* Optimization: Avoid unnecessary divisions. */ 2975 2976 target_pstate = cap_pstate; 2977 if (target_perf < capacity) 2978 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2979 2980 min_pstate = cap_pstate; 2981 if (min_perf < capacity) 2982 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2983 2984 if (min_pstate < cpu->pstate.min_pstate) 2985 min_pstate = cpu->pstate.min_pstate; 2986 2987 if (min_pstate < cpu->min_perf_ratio) 2988 min_pstate = cpu->min_perf_ratio; 2989 2990 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2991 if (max_pstate < min_pstate) 2992 max_pstate = min_pstate; 2993 2994 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2995 2996 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2997 2998 cpu->pstate.current_pstate = target_pstate; 2999 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 3000 } 3001 3002 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 3003 { 3004 struct freq_qos_request *req; 3005 struct cpudata *cpu; 3006 struct device *dev; 3007 int ret, freq; 3008 3009 dev = get_cpu_device(policy->cpu); 3010 if (!dev) 3011 return -ENODEV; 3012 3013 ret = __intel_pstate_cpu_init(policy); 3014 if (ret) 3015 return ret; 3016 3017 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 3018 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 3019 policy->cur = policy->cpuinfo.min_freq; 3020 3021 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 3022 if (!req) { 3023 ret = -ENOMEM; 3024 goto pstate_exit; 3025 } 3026 3027 cpu = all_cpu_data[policy->cpu]; 3028 3029 if (hwp_active) { 3030 u64 value; 3031 3032 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 3033 3034 intel_pstate_get_hwp_cap(cpu); 3035 3036 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3037 WRITE_ONCE(cpu->hwp_req_cached, value); 3038 3039 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 3040 } else { 3041 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 3042 } 3043 3044 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 3045 3046 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 3047 freq); 3048 if (ret < 0) { 3049 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 3050 goto free_req; 3051 } 3052 3053 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 3054 3055 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 3056 freq); 3057 if (ret < 0) { 3058 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3059 goto remove_min_req; 3060 } 3061 3062 policy->driver_data = req; 3063 3064 return 0; 3065 3066 remove_min_req: 3067 freq_qos_remove_request(req); 3068 free_req: 3069 kfree(req); 3070 pstate_exit: 3071 intel_pstate_exit_perf_limits(policy); 3072 3073 return ret; 3074 } 3075 3076 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3077 { 3078 struct freq_qos_request *req; 3079 3080 req = policy->driver_data; 3081 3082 freq_qos_remove_request(req + 1); 3083 freq_qos_remove_request(req); 3084 kfree(req); 3085 3086 return intel_pstate_cpu_exit(policy); 3087 } 3088 3089 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3090 { 3091 intel_pstate_suspend(policy); 3092 3093 if (hwp_active) { 3094 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3095 u64 value = READ_ONCE(cpu->hwp_req_cached); 3096 3097 /* 3098 * Clear the desired perf field in MSR_HWP_REQUEST in case 3099 * intel_cpufreq_adjust_perf() is in use and the last value 3100 * written by it may not be suitable. 3101 */ 3102 value &= ~HWP_DESIRED_PERF(~0L); 3103 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3104 WRITE_ONCE(cpu->hwp_req_cached, value); 3105 } 3106 3107 return 0; 3108 } 3109 3110 static struct cpufreq_driver intel_cpufreq = { 3111 .flags = CPUFREQ_CONST_LOOPS, 3112 .verify = intel_cpufreq_verify_policy, 3113 .target = intel_cpufreq_target, 3114 .fast_switch = intel_cpufreq_fast_switch, 3115 .init = intel_cpufreq_cpu_init, 3116 .exit = intel_cpufreq_cpu_exit, 3117 .offline = intel_cpufreq_cpu_offline, 3118 .online = intel_pstate_cpu_online, 3119 .suspend = intel_cpufreq_suspend, 3120 .resume = intel_pstate_resume, 3121 .update_limits = intel_pstate_update_limits, 3122 .name = "intel_cpufreq", 3123 }; 3124 3125 static struct cpufreq_driver *default_driver; 3126 3127 static void intel_pstate_driver_cleanup(void) 3128 { 3129 unsigned int cpu; 3130 3131 cpus_read_lock(); 3132 for_each_online_cpu(cpu) { 3133 if (all_cpu_data[cpu]) { 3134 if (intel_pstate_driver == &intel_pstate) 3135 intel_pstate_clear_update_util_hook(cpu); 3136 3137 spin_lock(&hwp_notify_lock); 3138 kfree(all_cpu_data[cpu]); 3139 WRITE_ONCE(all_cpu_data[cpu], NULL); 3140 spin_unlock(&hwp_notify_lock); 3141 } 3142 } 3143 cpus_read_unlock(); 3144 3145 intel_pstate_driver = NULL; 3146 } 3147 3148 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3149 { 3150 int ret; 3151 3152 if (driver == &intel_pstate) 3153 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3154 3155 memset(&global, 0, sizeof(global)); 3156 global.max_perf_pct = 100; 3157 3158 intel_pstate_driver = driver; 3159 ret = cpufreq_register_driver(intel_pstate_driver); 3160 if (ret) { 3161 intel_pstate_driver_cleanup(); 3162 return ret; 3163 } 3164 3165 global.min_perf_pct = min_perf_pct_min(); 3166 3167 return 0; 3168 } 3169 3170 static ssize_t intel_pstate_show_status(char *buf) 3171 { 3172 if (!intel_pstate_driver) 3173 return sprintf(buf, "off\n"); 3174 3175 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3176 "active" : "passive"); 3177 } 3178 3179 static int intel_pstate_update_status(const char *buf, size_t size) 3180 { 3181 if (size == 3 && !strncmp(buf, "off", size)) { 3182 if (!intel_pstate_driver) 3183 return -EINVAL; 3184 3185 if (hwp_active) 3186 return -EBUSY; 3187 3188 cpufreq_unregister_driver(intel_pstate_driver); 3189 intel_pstate_driver_cleanup(); 3190 return 0; 3191 } 3192 3193 if (size == 6 && !strncmp(buf, "active", size)) { 3194 if (intel_pstate_driver) { 3195 if (intel_pstate_driver == &intel_pstate) 3196 return 0; 3197 3198 cpufreq_unregister_driver(intel_pstate_driver); 3199 } 3200 3201 return intel_pstate_register_driver(&intel_pstate); 3202 } 3203 3204 if (size == 7 && !strncmp(buf, "passive", size)) { 3205 if (intel_pstate_driver) { 3206 if (intel_pstate_driver == &intel_cpufreq) 3207 return 0; 3208 3209 cpufreq_unregister_driver(intel_pstate_driver); 3210 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3211 } 3212 3213 return intel_pstate_register_driver(&intel_cpufreq); 3214 } 3215 3216 return -EINVAL; 3217 } 3218 3219 static int no_load __initdata; 3220 static int no_hwp __initdata; 3221 static int hwp_only __initdata; 3222 static unsigned int force_load __initdata; 3223 3224 static int __init intel_pstate_msrs_not_valid(void) 3225 { 3226 if (!pstate_funcs.get_max(0) || 3227 !pstate_funcs.get_min(0) || 3228 !pstate_funcs.get_turbo(0)) 3229 return -ENODEV; 3230 3231 return 0; 3232 } 3233 3234 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3235 { 3236 pstate_funcs.get_max = funcs->get_max; 3237 pstate_funcs.get_max_physical = funcs->get_max_physical; 3238 pstate_funcs.get_min = funcs->get_min; 3239 pstate_funcs.get_turbo = funcs->get_turbo; 3240 pstate_funcs.get_scaling = funcs->get_scaling; 3241 pstate_funcs.get_val = funcs->get_val; 3242 pstate_funcs.get_vid = funcs->get_vid; 3243 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3244 } 3245 3246 #ifdef CONFIG_ACPI 3247 3248 static bool __init intel_pstate_no_acpi_pss(void) 3249 { 3250 int i; 3251 3252 for_each_possible_cpu(i) { 3253 acpi_status status; 3254 union acpi_object *pss; 3255 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3256 struct acpi_processor *pr = per_cpu(processors, i); 3257 3258 if (!pr) 3259 continue; 3260 3261 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3262 if (ACPI_FAILURE(status)) 3263 continue; 3264 3265 pss = buffer.pointer; 3266 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3267 kfree(pss); 3268 return false; 3269 } 3270 3271 kfree(pss); 3272 } 3273 3274 pr_debug("ACPI _PSS not found\n"); 3275 return true; 3276 } 3277 3278 static bool __init intel_pstate_no_acpi_pcch(void) 3279 { 3280 acpi_status status; 3281 acpi_handle handle; 3282 3283 status = acpi_get_handle(NULL, "\\_SB", &handle); 3284 if (ACPI_FAILURE(status)) 3285 goto not_found; 3286 3287 if (acpi_has_method(handle, "PCCH")) 3288 return false; 3289 3290 not_found: 3291 pr_debug("ACPI PCCH not found\n"); 3292 return true; 3293 } 3294 3295 static bool __init intel_pstate_has_acpi_ppc(void) 3296 { 3297 int i; 3298 3299 for_each_possible_cpu(i) { 3300 struct acpi_processor *pr = per_cpu(processors, i); 3301 3302 if (!pr) 3303 continue; 3304 if (acpi_has_method(pr->handle, "_PPC")) 3305 return true; 3306 } 3307 pr_debug("ACPI _PPC not found\n"); 3308 return false; 3309 } 3310 3311 enum { 3312 PSS, 3313 PPC, 3314 }; 3315 3316 /* Hardware vendor-specific info that has its own power management modes */ 3317 static struct acpi_platform_list plat_info[] __initdata = { 3318 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3319 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3320 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3321 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3322 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3323 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3324 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3325 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3326 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3327 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3328 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3329 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3330 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3331 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3332 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3333 { } /* End */ 3334 }; 3335 3336 #define BITMASK_OOB (BIT(8) | BIT(18)) 3337 3338 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3339 { 3340 const struct x86_cpu_id *id; 3341 u64 misc_pwr; 3342 int idx; 3343 3344 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3345 if (id) { 3346 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3347 if (misc_pwr & BITMASK_OOB) { 3348 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3349 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3350 return true; 3351 } 3352 } 3353 3354 idx = acpi_match_platform_list(plat_info); 3355 if (idx < 0) 3356 return false; 3357 3358 switch (plat_info[idx].data) { 3359 case PSS: 3360 if (!intel_pstate_no_acpi_pss()) 3361 return false; 3362 3363 return intel_pstate_no_acpi_pcch(); 3364 case PPC: 3365 return intel_pstate_has_acpi_ppc() && !force_load; 3366 } 3367 3368 return false; 3369 } 3370 3371 static void intel_pstate_request_control_from_smm(void) 3372 { 3373 /* 3374 * It may be unsafe to request P-states control from SMM if _PPC support 3375 * has not been enabled. 3376 */ 3377 if (acpi_ppc) 3378 acpi_processor_pstate_control(); 3379 } 3380 #else /* CONFIG_ACPI not enabled */ 3381 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3382 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3383 static inline void intel_pstate_request_control_from_smm(void) {} 3384 #endif /* CONFIG_ACPI */ 3385 3386 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3387 3388 #define X86_MATCH_HWP(model, hwp_mode) \ 3389 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3390 X86_FEATURE_HWP, hwp_mode) 3391 3392 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3393 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3394 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3395 X86_MATCH_HWP(ANY, 0), 3396 {} 3397 }; 3398 3399 static bool intel_pstate_hwp_is_enabled(void) 3400 { 3401 u64 value; 3402 3403 rdmsrl(MSR_PM_ENABLE, value); 3404 return !!(value & 0x1); 3405 } 3406 3407 static const struct x86_cpu_id intel_epp_balance_perf[] = { 3408 /* 3409 * Set EPP value as 102, this is the max suggested EPP 3410 * which can result in one core turbo frequency for 3411 * AlderLake Mobile CPUs. 3412 */ 3413 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102), 3414 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32), 3415 {} 3416 }; 3417 3418 static int __init intel_pstate_init(void) 3419 { 3420 static struct cpudata **_all_cpu_data; 3421 const struct x86_cpu_id *id; 3422 int rc; 3423 3424 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3425 return -ENODEV; 3426 3427 id = x86_match_cpu(hwp_support_ids); 3428 if (id) { 3429 hwp_forced = intel_pstate_hwp_is_enabled(); 3430 3431 if (hwp_forced) 3432 pr_info("HWP enabled by BIOS\n"); 3433 else if (no_load) 3434 return -ENODEV; 3435 3436 copy_cpu_funcs(&core_funcs); 3437 /* 3438 * Avoid enabling HWP for processors without EPP support, 3439 * because that means incomplete HWP implementation which is a 3440 * corner case and supporting it is generally problematic. 3441 * 3442 * If HWP is enabled already, though, there is no choice but to 3443 * deal with it. 3444 */ 3445 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3446 WRITE_ONCE(hwp_active, 1); 3447 hwp_mode_bdw = id->driver_data; 3448 intel_pstate.attr = hwp_cpufreq_attrs; 3449 intel_cpufreq.attr = hwp_cpufreq_attrs; 3450 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3451 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3452 if (!default_driver) 3453 default_driver = &intel_pstate; 3454 3455 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling; 3456 3457 goto hwp_cpu_matched; 3458 } 3459 pr_info("HWP not enabled\n"); 3460 } else { 3461 if (no_load) 3462 return -ENODEV; 3463 3464 id = x86_match_cpu(intel_pstate_cpu_ids); 3465 if (!id) { 3466 pr_info("CPU model not supported\n"); 3467 return -ENODEV; 3468 } 3469 3470 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3471 } 3472 3473 if (intel_pstate_msrs_not_valid()) { 3474 pr_info("Invalid MSRs\n"); 3475 return -ENODEV; 3476 } 3477 /* Without HWP start in the passive mode. */ 3478 if (!default_driver) 3479 default_driver = &intel_cpufreq; 3480 3481 hwp_cpu_matched: 3482 /* 3483 * The Intel pstate driver will be ignored if the platform 3484 * firmware has its own power management modes. 3485 */ 3486 if (intel_pstate_platform_pwr_mgmt_exists()) { 3487 pr_info("P-states controlled by the platform\n"); 3488 return -ENODEV; 3489 } 3490 3491 if (!hwp_active && hwp_only) 3492 return -ENOTSUPP; 3493 3494 pr_info("Intel P-state driver initializing\n"); 3495 3496 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3497 if (!_all_cpu_data) 3498 return -ENOMEM; 3499 3500 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3501 3502 intel_pstate_request_control_from_smm(); 3503 3504 intel_pstate_sysfs_expose_params(); 3505 3506 if (hwp_active) { 3507 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf); 3508 3509 if (id) 3510 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data; 3511 } 3512 3513 mutex_lock(&intel_pstate_driver_lock); 3514 rc = intel_pstate_register_driver(default_driver); 3515 mutex_unlock(&intel_pstate_driver_lock); 3516 if (rc) { 3517 intel_pstate_sysfs_remove(); 3518 return rc; 3519 } 3520 3521 if (hwp_active) { 3522 const struct x86_cpu_id *id; 3523 3524 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3525 if (id) { 3526 set_power_ctl_ee_state(false); 3527 pr_info("Disabling energy efficiency optimization\n"); 3528 } 3529 3530 pr_info("HWP enabled\n"); 3531 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3532 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3533 } 3534 3535 return 0; 3536 } 3537 device_initcall(intel_pstate_init); 3538 3539 static int __init intel_pstate_setup(char *str) 3540 { 3541 if (!str) 3542 return -EINVAL; 3543 3544 if (!strcmp(str, "disable")) 3545 no_load = 1; 3546 else if (!strcmp(str, "active")) 3547 default_driver = &intel_pstate; 3548 else if (!strcmp(str, "passive")) 3549 default_driver = &intel_cpufreq; 3550 3551 if (!strcmp(str, "no_hwp")) 3552 no_hwp = 1; 3553 3554 if (!strcmp(str, "force")) 3555 force_load = 1; 3556 if (!strcmp(str, "hwp_only")) 3557 hwp_only = 1; 3558 if (!strcmp(str, "per_cpu_perf_limits")) 3559 per_cpu_limits = true; 3560 3561 #ifdef CONFIG_ACPI 3562 if (!strcmp(str, "support_acpi_ppc")) 3563 acpi_ppc = true; 3564 #endif 3565 3566 return 0; 3567 } 3568 early_param("intel_pstate", intel_pstate_setup); 3569 3570 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3571 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3572