1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/div64.h> 31 #include <asm/msr.h> 32 #include <asm/cpu_device_id.h> 33 #include <asm/cpufeature.h> 34 #include <asm/intel-family.h> 35 #include "../drivers/thermal/intel/thermal_interrupt.h" 36 37 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 38 39 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 40 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 41 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 42 43 #ifdef CONFIG_ACPI 44 #include <acpi/processor.h> 45 #include <acpi/cppc_acpi.h> 46 #endif 47 48 #define FRAC_BITS 8 49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 50 #define fp_toint(X) ((X) >> FRAC_BITS) 51 52 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 53 54 #define EXT_BITS 6 55 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 56 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 57 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 58 59 static inline int32_t mul_fp(int32_t x, int32_t y) 60 { 61 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 62 } 63 64 static inline int32_t div_fp(s64 x, s64 y) 65 { 66 return div64_s64((int64_t)x << FRAC_BITS, y); 67 } 68 69 static inline int ceiling_fp(int32_t x) 70 { 71 int mask, ret; 72 73 ret = fp_toint(x); 74 mask = (1 << FRAC_BITS) - 1; 75 if (x & mask) 76 ret += 1; 77 return ret; 78 } 79 80 static inline u64 mul_ext_fp(u64 x, u64 y) 81 { 82 return (x * y) >> EXT_FRAC_BITS; 83 } 84 85 static inline u64 div_ext_fp(u64 x, u64 y) 86 { 87 return div64_u64(x << EXT_FRAC_BITS, y); 88 } 89 90 /** 91 * struct sample - Store performance sample 92 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 93 * performance during last sample period 94 * @busy_scaled: Scaled busy value which is used to calculate next 95 * P state. This can be different than core_avg_perf 96 * to account for cpu idle period 97 * @aperf: Difference of actual performance frequency clock count 98 * read from APERF MSR between last and current sample 99 * @mperf: Difference of maximum performance frequency clock count 100 * read from MPERF MSR between last and current sample 101 * @tsc: Difference of time stamp counter between last and 102 * current sample 103 * @time: Current time from scheduler 104 * 105 * This structure is used in the cpudata structure to store performance sample 106 * data for choosing next P State. 107 */ 108 struct sample { 109 int32_t core_avg_perf; 110 int32_t busy_scaled; 111 u64 aperf; 112 u64 mperf; 113 u64 tsc; 114 u64 time; 115 }; 116 117 /** 118 * struct pstate_data - Store P state data 119 * @current_pstate: Current requested P state 120 * @min_pstate: Min P state possible for this platform 121 * @max_pstate: Max P state possible for this platform 122 * @max_pstate_physical:This is physical Max P state for a processor 123 * This can be higher than the max_pstate which can 124 * be limited by platform thermal design power limits 125 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 126 * @scaling: Scaling factor between performance and frequency 127 * @turbo_pstate: Max Turbo P state possible for this platform 128 * @min_freq: @min_pstate frequency in cpufreq units 129 * @max_freq: @max_pstate frequency in cpufreq units 130 * @turbo_freq: @turbo_pstate frequency in cpufreq units 131 * 132 * Stores the per cpu model P state limits and current P state. 133 */ 134 struct pstate_data { 135 int current_pstate; 136 int min_pstate; 137 int max_pstate; 138 int max_pstate_physical; 139 int perf_ctl_scaling; 140 int scaling; 141 int turbo_pstate; 142 unsigned int min_freq; 143 unsigned int max_freq; 144 unsigned int turbo_freq; 145 }; 146 147 /** 148 * struct vid_data - Stores voltage information data 149 * @min: VID data for this platform corresponding to 150 * the lowest P state 151 * @max: VID data corresponding to the highest P State. 152 * @turbo: VID data for turbo P state 153 * @ratio: Ratio of (vid max - vid min) / 154 * (max P state - Min P State) 155 * 156 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 157 * This data is used in Atom platforms, where in addition to target P state, 158 * the voltage data needs to be specified to select next P State. 159 */ 160 struct vid_data { 161 int min; 162 int max; 163 int turbo; 164 int32_t ratio; 165 }; 166 167 /** 168 * struct global_params - Global parameters, mostly tunable via sysfs. 169 * @no_turbo: Whether or not to use turbo P-states. 170 * @turbo_disabled: Whether or not turbo P-states are available at all, 171 * based on the MSR_IA32_MISC_ENABLE value and whether or 172 * not the maximum reported turbo P-state is different from 173 * the maximum reported non-turbo one. 174 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 175 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 176 * P-state capacity. 177 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 178 * P-state capacity. 179 */ 180 struct global_params { 181 bool no_turbo; 182 bool turbo_disabled; 183 bool turbo_disabled_mf; 184 int max_perf_pct; 185 int min_perf_pct; 186 }; 187 188 /** 189 * struct cpudata - Per CPU instance data storage 190 * @cpu: CPU number for this instance data 191 * @policy: CPUFreq policy value 192 * @update_util: CPUFreq utility callback information 193 * @update_util_set: CPUFreq utility callback is set 194 * @iowait_boost: iowait-related boost fraction 195 * @last_update: Time of the last update. 196 * @pstate: Stores P state limits for this CPU 197 * @vid: Stores VID limits for this CPU 198 * @last_sample_time: Last Sample time 199 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 200 * @prev_aperf: Last APERF value read from APERF MSR 201 * @prev_mperf: Last MPERF value read from MPERF MSR 202 * @prev_tsc: Last timestamp counter (TSC) value 203 * @prev_cummulative_iowait: IO Wait time difference from last and 204 * current sample 205 * @sample: Storage for storing last Sample data 206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 208 * @acpi_perf_data: Stores ACPI perf information read from _PSS 209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 210 * @epp_powersave: Last saved HWP energy performance preference 211 * (EPP) or energy performance bias (EPB), 212 * when policy switched to performance 213 * @epp_policy: Last saved policy used to set EPP/EPB 214 * @epp_default: Power on default HWP energy performance 215 * preference/bias 216 * @epp_cached Cached HWP energy-performance preference value 217 * @hwp_req_cached: Cached value of the last HWP Request MSR 218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 219 * @last_io_update: Last time when IO wake flag was set 220 * @sched_flags: Store scheduler flags for possible cross CPU update 221 * @hwp_boost_min: Last HWP boosted min performance 222 * @suspended: Whether or not the driver has been suspended. 223 * @hwp_notify_work: workqueue for HWP notifications. 224 * 225 * This structure stores per CPU instance data for all CPUs. 226 */ 227 struct cpudata { 228 int cpu; 229 230 unsigned int policy; 231 struct update_util_data update_util; 232 bool update_util_set; 233 234 struct pstate_data pstate; 235 struct vid_data vid; 236 237 u64 last_update; 238 u64 last_sample_time; 239 u64 aperf_mperf_shift; 240 u64 prev_aperf; 241 u64 prev_mperf; 242 u64 prev_tsc; 243 u64 prev_cummulative_iowait; 244 struct sample sample; 245 int32_t min_perf_ratio; 246 int32_t max_perf_ratio; 247 #ifdef CONFIG_ACPI 248 struct acpi_processor_performance acpi_perf_data; 249 bool valid_pss_table; 250 #endif 251 unsigned int iowait_boost; 252 s16 epp_powersave; 253 s16 epp_policy; 254 s16 epp_default; 255 s16 epp_cached; 256 u64 hwp_req_cached; 257 u64 hwp_cap_cached; 258 u64 last_io_update; 259 unsigned int sched_flags; 260 u32 hwp_boost_min; 261 bool suspended; 262 struct delayed_work hwp_notify_work; 263 }; 264 265 static struct cpudata **all_cpu_data; 266 267 /** 268 * struct pstate_funcs - Per CPU model specific callbacks 269 * @get_max: Callback to get maximum non turbo effective P state 270 * @get_max_physical: Callback to get maximum non turbo physical P state 271 * @get_min: Callback to get minimum P state 272 * @get_turbo: Callback to get turbo P state 273 * @get_scaling: Callback to get frequency scaling factor 274 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 275 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 276 * @get_val: Callback to convert P state to actual MSR write value 277 * @get_vid: Callback to get VID data for Atom platforms 278 * 279 * Core and Atom CPU models have different way to get P State limits. This 280 * structure is used to store those callbacks. 281 */ 282 struct pstate_funcs { 283 int (*get_max)(void); 284 int (*get_max_physical)(void); 285 int (*get_min)(void); 286 int (*get_turbo)(void); 287 int (*get_scaling)(void); 288 int (*get_cpu_scaling)(int cpu); 289 int (*get_aperf_mperf_shift)(void); 290 u64 (*get_val)(struct cpudata*, int pstate); 291 void (*get_vid)(struct cpudata *); 292 }; 293 294 static struct pstate_funcs pstate_funcs __read_mostly; 295 296 static int hwp_active __read_mostly; 297 static int hwp_mode_bdw __read_mostly; 298 static bool per_cpu_limits __read_mostly; 299 static bool hwp_boost __read_mostly; 300 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 302 303 #ifdef CONFIG_ACPI 304 static bool acpi_ppc; 305 #endif 306 307 static struct global_params global; 308 309 static DEFINE_MUTEX(intel_pstate_driver_lock); 310 static DEFINE_MUTEX(intel_pstate_limits_lock); 311 312 #ifdef CONFIG_ACPI 313 314 static bool intel_pstate_acpi_pm_profile_server(void) 315 { 316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 318 return true; 319 320 return false; 321 } 322 323 static bool intel_pstate_get_ppc_enable_status(void) 324 { 325 if (intel_pstate_acpi_pm_profile_server()) 326 return true; 327 328 return acpi_ppc; 329 } 330 331 #ifdef CONFIG_ACPI_CPPC_LIB 332 333 /* The work item is needed to avoid CPU hotplug locking issues */ 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 335 { 336 sched_set_itmt_support(); 337 } 338 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 340 341 static void intel_pstate_set_itmt_prio(int cpu) 342 { 343 struct cppc_perf_caps cppc_perf; 344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 345 int ret; 346 347 ret = cppc_get_perf_caps(cpu, &cppc_perf); 348 if (ret) 349 return; 350 351 /* 352 * The priorities can be set regardless of whether or not 353 * sched_set_itmt_support(true) has been called and it is valid to 354 * update them at any time after it has been called. 355 */ 356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 357 358 if (max_highest_perf <= min_highest_perf) { 359 if (cppc_perf.highest_perf > max_highest_perf) 360 max_highest_perf = cppc_perf.highest_perf; 361 362 if (cppc_perf.highest_perf < min_highest_perf) 363 min_highest_perf = cppc_perf.highest_perf; 364 365 if (max_highest_perf > min_highest_perf) { 366 /* 367 * This code can be run during CPU online under the 368 * CPU hotplug locks, so sched_set_itmt_support() 369 * cannot be called from here. Queue up a work item 370 * to invoke it. 371 */ 372 schedule_work(&sched_itmt_work); 373 } 374 } 375 } 376 377 static int intel_pstate_get_cppc_guaranteed(int cpu) 378 { 379 struct cppc_perf_caps cppc_perf; 380 int ret; 381 382 ret = cppc_get_perf_caps(cpu, &cppc_perf); 383 if (ret) 384 return ret; 385 386 if (cppc_perf.guaranteed_perf) 387 return cppc_perf.guaranteed_perf; 388 389 return cppc_perf.nominal_perf; 390 } 391 392 static u32 intel_pstate_cppc_nominal(int cpu) 393 { 394 u64 nominal_perf; 395 396 if (cppc_get_nominal_perf(cpu, &nominal_perf)) 397 return 0; 398 399 return nominal_perf; 400 } 401 #else /* CONFIG_ACPI_CPPC_LIB */ 402 static inline void intel_pstate_set_itmt_prio(int cpu) 403 { 404 } 405 #endif /* CONFIG_ACPI_CPPC_LIB */ 406 407 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 408 { 409 struct cpudata *cpu; 410 int ret; 411 int i; 412 413 if (hwp_active) { 414 intel_pstate_set_itmt_prio(policy->cpu); 415 return; 416 } 417 418 if (!intel_pstate_get_ppc_enable_status()) 419 return; 420 421 cpu = all_cpu_data[policy->cpu]; 422 423 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 424 policy->cpu); 425 if (ret) 426 return; 427 428 /* 429 * Check if the control value in _PSS is for PERF_CTL MSR, which should 430 * guarantee that the states returned by it map to the states in our 431 * list directly. 432 */ 433 if (cpu->acpi_perf_data.control_register.space_id != 434 ACPI_ADR_SPACE_FIXED_HARDWARE) 435 goto err; 436 437 /* 438 * If there is only one entry _PSS, simply ignore _PSS and continue as 439 * usual without taking _PSS into account 440 */ 441 if (cpu->acpi_perf_data.state_count < 2) 442 goto err; 443 444 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 445 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 446 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 447 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 448 (u32) cpu->acpi_perf_data.states[i].core_frequency, 449 (u32) cpu->acpi_perf_data.states[i].power, 450 (u32) cpu->acpi_perf_data.states[i].control); 451 } 452 453 /* 454 * The _PSS table doesn't contain whole turbo frequency range. 455 * This just contains +1 MHZ above the max non turbo frequency, 456 * with control value corresponding to max turbo ratio. But 457 * when cpufreq set policy is called, it will call with this 458 * max frequency, which will cause a reduced performance as 459 * this driver uses real max turbo frequency as the max 460 * frequency. So correct this frequency in _PSS table to 461 * correct max turbo frequency based on the turbo state. 462 * Also need to convert to MHz as _PSS freq is in MHz. 463 */ 464 if (!global.turbo_disabled) 465 cpu->acpi_perf_data.states[0].core_frequency = 466 policy->cpuinfo.max_freq / 1000; 467 cpu->valid_pss_table = true; 468 pr_debug("_PPC limits will be enforced\n"); 469 470 return; 471 472 err: 473 cpu->valid_pss_table = false; 474 acpi_processor_unregister_performance(policy->cpu); 475 } 476 477 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 478 { 479 struct cpudata *cpu; 480 481 cpu = all_cpu_data[policy->cpu]; 482 if (!cpu->valid_pss_table) 483 return; 484 485 acpi_processor_unregister_performance(policy->cpu); 486 } 487 #else /* CONFIG_ACPI */ 488 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 489 { 490 } 491 492 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 493 { 494 } 495 496 static inline bool intel_pstate_acpi_pm_profile_server(void) 497 { 498 return false; 499 } 500 #endif /* CONFIG_ACPI */ 501 502 #ifndef CONFIG_ACPI_CPPC_LIB 503 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 504 { 505 return -ENOTSUPP; 506 } 507 #endif /* CONFIG_ACPI_CPPC_LIB */ 508 509 /** 510 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 511 * @cpu: Target CPU. 512 * 513 * On hybrid processors, HWP may expose more performance levels than there are 514 * P-states accessible through the PERF_CTL interface. If that happens, the 515 * scaling factor between HWP performance levels and CPU frequency will be less 516 * than the scaling factor between P-state values and CPU frequency. 517 * 518 * In that case, adjust the CPU parameters used in computations accordingly. 519 */ 520 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 521 { 522 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 523 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 524 int perf_ctl_turbo = pstate_funcs.get_turbo(); 525 int turbo_freq = perf_ctl_turbo * perf_ctl_scaling; 526 int scaling = cpu->pstate.scaling; 527 528 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 529 pr_debug("CPU%d: perf_ctl_max = %d\n", cpu->cpu, pstate_funcs.get_max()); 530 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 531 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 532 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 533 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 534 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 535 536 /* 537 * If the product of the HWP performance scaling factor and the HWP_CAP 538 * highest performance is greater than the maximum turbo frequency 539 * corresponding to the pstate_funcs.get_turbo() return value, the 540 * scaling factor is too high, so recompute it to make the HWP_CAP 541 * highest performance correspond to the maximum turbo frequency. 542 */ 543 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 544 if (turbo_freq < cpu->pstate.turbo_freq) { 545 cpu->pstate.turbo_freq = turbo_freq; 546 scaling = DIV_ROUND_UP(turbo_freq, cpu->pstate.turbo_pstate); 547 cpu->pstate.scaling = scaling; 548 549 pr_debug("CPU%d: refined HWP-to-frequency scaling factor: %d\n", 550 cpu->cpu, scaling); 551 } 552 553 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 554 perf_ctl_scaling); 555 556 cpu->pstate.max_pstate_physical = 557 DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling, 558 scaling); 559 560 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 561 /* 562 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 563 * the effective range of HWP performance levels. 564 */ 565 cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling); 566 } 567 568 static inline void update_turbo_state(void) 569 { 570 u64 misc_en; 571 struct cpudata *cpu; 572 573 cpu = all_cpu_data[0]; 574 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 575 global.turbo_disabled = 576 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 577 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 578 } 579 580 static int min_perf_pct_min(void) 581 { 582 struct cpudata *cpu = all_cpu_data[0]; 583 int turbo_pstate = cpu->pstate.turbo_pstate; 584 585 return turbo_pstate ? 586 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 587 } 588 589 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 590 { 591 u64 epb; 592 int ret; 593 594 if (!boot_cpu_has(X86_FEATURE_EPB)) 595 return -ENXIO; 596 597 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 598 if (ret) 599 return (s16)ret; 600 601 return (s16)(epb & 0x0f); 602 } 603 604 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 605 { 606 s16 epp; 607 608 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 609 /* 610 * When hwp_req_data is 0, means that caller didn't read 611 * MSR_HWP_REQUEST, so need to read and get EPP. 612 */ 613 if (!hwp_req_data) { 614 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 615 &hwp_req_data); 616 if (epp) 617 return epp; 618 } 619 epp = (hwp_req_data >> 24) & 0xff; 620 } else { 621 /* When there is no EPP present, HWP uses EPB settings */ 622 epp = intel_pstate_get_epb(cpu_data); 623 } 624 625 return epp; 626 } 627 628 static int intel_pstate_set_epb(int cpu, s16 pref) 629 { 630 u64 epb; 631 int ret; 632 633 if (!boot_cpu_has(X86_FEATURE_EPB)) 634 return -ENXIO; 635 636 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 637 if (ret) 638 return ret; 639 640 epb = (epb & ~0x0f) | pref; 641 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 642 643 return 0; 644 } 645 646 /* 647 * EPP/EPB display strings corresponding to EPP index in the 648 * energy_perf_strings[] 649 * index String 650 *------------------------------------- 651 * 0 default 652 * 1 performance 653 * 2 balance_performance 654 * 3 balance_power 655 * 4 power 656 */ 657 static const char * const energy_perf_strings[] = { 658 "default", 659 "performance", 660 "balance_performance", 661 "balance_power", 662 "power", 663 NULL 664 }; 665 static const unsigned int epp_values[] = { 666 HWP_EPP_PERFORMANCE, 667 HWP_EPP_BALANCE_PERFORMANCE, 668 HWP_EPP_BALANCE_POWERSAVE, 669 HWP_EPP_POWERSAVE 670 }; 671 672 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 673 { 674 s16 epp; 675 int index = -EINVAL; 676 677 *raw_epp = 0; 678 epp = intel_pstate_get_epp(cpu_data, 0); 679 if (epp < 0) 680 return epp; 681 682 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 683 if (epp == HWP_EPP_PERFORMANCE) 684 return 1; 685 if (epp == HWP_EPP_BALANCE_PERFORMANCE) 686 return 2; 687 if (epp == HWP_EPP_BALANCE_POWERSAVE) 688 return 3; 689 if (epp == HWP_EPP_POWERSAVE) 690 return 4; 691 *raw_epp = epp; 692 return 0; 693 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 694 /* 695 * Range: 696 * 0x00-0x03 : Performance 697 * 0x04-0x07 : Balance performance 698 * 0x08-0x0B : Balance power 699 * 0x0C-0x0F : Power 700 * The EPB is a 4 bit value, but our ranges restrict the 701 * value which can be set. Here only using top two bits 702 * effectively. 703 */ 704 index = (epp >> 2) + 1; 705 } 706 707 return index; 708 } 709 710 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 711 { 712 int ret; 713 714 /* 715 * Use the cached HWP Request MSR value, because in the active mode the 716 * register itself may be updated by intel_pstate_hwp_boost_up() or 717 * intel_pstate_hwp_boost_down() at any time. 718 */ 719 u64 value = READ_ONCE(cpu->hwp_req_cached); 720 721 value &= ~GENMASK_ULL(31, 24); 722 value |= (u64)epp << 24; 723 /* 724 * The only other updater of hwp_req_cached in the active mode, 725 * intel_pstate_hwp_set(), is called under the same lock as this 726 * function, so it cannot run in parallel with the update below. 727 */ 728 WRITE_ONCE(cpu->hwp_req_cached, value); 729 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 730 if (!ret) 731 cpu->epp_cached = epp; 732 733 return ret; 734 } 735 736 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 737 int pref_index, bool use_raw, 738 u32 raw_epp) 739 { 740 int epp = -EINVAL; 741 int ret; 742 743 if (!pref_index) 744 epp = cpu_data->epp_default; 745 746 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 747 if (use_raw) 748 epp = raw_epp; 749 else if (epp == -EINVAL) 750 epp = epp_values[pref_index - 1]; 751 752 /* 753 * To avoid confusion, refuse to set EPP to any values different 754 * from 0 (performance) if the current policy is "performance", 755 * because those values would be overridden. 756 */ 757 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 758 return -EBUSY; 759 760 ret = intel_pstate_set_epp(cpu_data, epp); 761 } else { 762 if (epp == -EINVAL) 763 epp = (pref_index - 1) << 2; 764 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 765 } 766 767 return ret; 768 } 769 770 static ssize_t show_energy_performance_available_preferences( 771 struct cpufreq_policy *policy, char *buf) 772 { 773 int i = 0; 774 int ret = 0; 775 776 while (energy_perf_strings[i] != NULL) 777 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 778 779 ret += sprintf(&buf[ret], "\n"); 780 781 return ret; 782 } 783 784 cpufreq_freq_attr_ro(energy_performance_available_preferences); 785 786 static struct cpufreq_driver intel_pstate; 787 788 static ssize_t store_energy_performance_preference( 789 struct cpufreq_policy *policy, const char *buf, size_t count) 790 { 791 struct cpudata *cpu = all_cpu_data[policy->cpu]; 792 char str_preference[21]; 793 bool raw = false; 794 ssize_t ret; 795 u32 epp = 0; 796 797 ret = sscanf(buf, "%20s", str_preference); 798 if (ret != 1) 799 return -EINVAL; 800 801 ret = match_string(energy_perf_strings, -1, str_preference); 802 if (ret < 0) { 803 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 804 return ret; 805 806 ret = kstrtouint(buf, 10, &epp); 807 if (ret) 808 return ret; 809 810 if (epp > 255) 811 return -EINVAL; 812 813 raw = true; 814 } 815 816 /* 817 * This function runs with the policy R/W semaphore held, which 818 * guarantees that the driver pointer will not change while it is 819 * running. 820 */ 821 if (!intel_pstate_driver) 822 return -EAGAIN; 823 824 mutex_lock(&intel_pstate_limits_lock); 825 826 if (intel_pstate_driver == &intel_pstate) { 827 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 828 } else { 829 /* 830 * In the passive mode the governor needs to be stopped on the 831 * target CPU before the EPP update and restarted after it, 832 * which is super-heavy-weight, so make sure it is worth doing 833 * upfront. 834 */ 835 if (!raw) 836 epp = ret ? epp_values[ret - 1] : cpu->epp_default; 837 838 if (cpu->epp_cached != epp) { 839 int err; 840 841 cpufreq_stop_governor(policy); 842 ret = intel_pstate_set_epp(cpu, epp); 843 err = cpufreq_start_governor(policy); 844 if (!ret) 845 ret = err; 846 } 847 } 848 849 mutex_unlock(&intel_pstate_limits_lock); 850 851 return ret ?: count; 852 } 853 854 static ssize_t show_energy_performance_preference( 855 struct cpufreq_policy *policy, char *buf) 856 { 857 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 858 int preference, raw_epp; 859 860 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 861 if (preference < 0) 862 return preference; 863 864 if (raw_epp) 865 return sprintf(buf, "%d\n", raw_epp); 866 else 867 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 868 } 869 870 cpufreq_freq_attr_rw(energy_performance_preference); 871 872 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 873 { 874 struct cpudata *cpu = all_cpu_data[policy->cpu]; 875 int ratio, freq; 876 877 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 878 if (ratio <= 0) { 879 u64 cap; 880 881 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 882 ratio = HWP_GUARANTEED_PERF(cap); 883 } 884 885 freq = ratio * cpu->pstate.scaling; 886 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 887 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 888 889 return sprintf(buf, "%d\n", freq); 890 } 891 892 cpufreq_freq_attr_ro(base_frequency); 893 894 static struct freq_attr *hwp_cpufreq_attrs[] = { 895 &energy_performance_preference, 896 &energy_performance_available_preferences, 897 &base_frequency, 898 NULL, 899 }; 900 901 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 902 { 903 u64 cap; 904 905 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 906 WRITE_ONCE(cpu->hwp_cap_cached, cap); 907 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 908 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 909 } 910 911 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 912 { 913 int scaling = cpu->pstate.scaling; 914 915 __intel_pstate_get_hwp_cap(cpu); 916 917 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 918 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 919 if (scaling != cpu->pstate.perf_ctl_scaling) { 920 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 921 922 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 923 perf_ctl_scaling); 924 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 925 perf_ctl_scaling); 926 } 927 } 928 929 static void intel_pstate_hwp_set(unsigned int cpu) 930 { 931 struct cpudata *cpu_data = all_cpu_data[cpu]; 932 int max, min; 933 u64 value; 934 s16 epp; 935 936 max = cpu_data->max_perf_ratio; 937 min = cpu_data->min_perf_ratio; 938 939 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 940 min = max; 941 942 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 943 944 value &= ~HWP_MIN_PERF(~0L); 945 value |= HWP_MIN_PERF(min); 946 947 value &= ~HWP_MAX_PERF(~0L); 948 value |= HWP_MAX_PERF(max); 949 950 if (cpu_data->epp_policy == cpu_data->policy) 951 goto skip_epp; 952 953 cpu_data->epp_policy = cpu_data->policy; 954 955 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 956 epp = intel_pstate_get_epp(cpu_data, value); 957 cpu_data->epp_powersave = epp; 958 /* If EPP read was failed, then don't try to write */ 959 if (epp < 0) 960 goto skip_epp; 961 962 epp = 0; 963 } else { 964 /* skip setting EPP, when saved value is invalid */ 965 if (cpu_data->epp_powersave < 0) 966 goto skip_epp; 967 968 /* 969 * No need to restore EPP when it is not zero. This 970 * means: 971 * - Policy is not changed 972 * - user has manually changed 973 * - Error reading EPB 974 */ 975 epp = intel_pstate_get_epp(cpu_data, value); 976 if (epp) 977 goto skip_epp; 978 979 epp = cpu_data->epp_powersave; 980 } 981 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 982 value &= ~GENMASK_ULL(31, 24); 983 value |= (u64)epp << 24; 984 } else { 985 intel_pstate_set_epb(cpu, epp); 986 } 987 skip_epp: 988 WRITE_ONCE(cpu_data->hwp_req_cached, value); 989 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 990 } 991 992 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 993 994 static void intel_pstate_hwp_offline(struct cpudata *cpu) 995 { 996 u64 value = READ_ONCE(cpu->hwp_req_cached); 997 int min_perf; 998 999 intel_pstate_disable_hwp_interrupt(cpu); 1000 1001 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 1002 /* 1003 * In case the EPP has been set to "performance" by the 1004 * active mode "performance" scaling algorithm, replace that 1005 * temporary value with the cached EPP one. 1006 */ 1007 value &= ~GENMASK_ULL(31, 24); 1008 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 1009 } 1010 1011 /* 1012 * Clear the desired perf field in the cached HWP request value to 1013 * prevent nonzero desired values from being leaked into the active 1014 * mode. 1015 */ 1016 value &= ~HWP_DESIRED_PERF(~0L); 1017 WRITE_ONCE(cpu->hwp_req_cached, value); 1018 1019 value &= ~GENMASK_ULL(31, 0); 1020 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1021 1022 /* Set hwp_max = hwp_min */ 1023 value |= HWP_MAX_PERF(min_perf); 1024 value |= HWP_MIN_PERF(min_perf); 1025 1026 /* Set EPP to min */ 1027 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1028 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1029 1030 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1031 } 1032 1033 #define POWER_CTL_EE_ENABLE 1 1034 #define POWER_CTL_EE_DISABLE 2 1035 1036 static int power_ctl_ee_state; 1037 1038 static void set_power_ctl_ee_state(bool input) 1039 { 1040 u64 power_ctl; 1041 1042 mutex_lock(&intel_pstate_driver_lock); 1043 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1044 if (input) { 1045 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1046 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1047 } else { 1048 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1049 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1050 } 1051 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1052 mutex_unlock(&intel_pstate_driver_lock); 1053 } 1054 1055 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1056 1057 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1058 { 1059 intel_pstate_hwp_enable(cpu); 1060 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1061 } 1062 1063 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1064 { 1065 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1066 1067 pr_debug("CPU %d suspending\n", cpu->cpu); 1068 1069 cpu->suspended = true; 1070 1071 /* disable HWP interrupt and cancel any pending work */ 1072 intel_pstate_disable_hwp_interrupt(cpu); 1073 1074 return 0; 1075 } 1076 1077 static int intel_pstate_resume(struct cpufreq_policy *policy) 1078 { 1079 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1080 1081 pr_debug("CPU %d resuming\n", cpu->cpu); 1082 1083 /* Only restore if the system default is changed */ 1084 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1085 set_power_ctl_ee_state(true); 1086 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1087 set_power_ctl_ee_state(false); 1088 1089 if (cpu->suspended && hwp_active) { 1090 mutex_lock(&intel_pstate_limits_lock); 1091 1092 /* Re-enable HWP, because "online" has not done that. */ 1093 intel_pstate_hwp_reenable(cpu); 1094 1095 mutex_unlock(&intel_pstate_limits_lock); 1096 } 1097 1098 cpu->suspended = false; 1099 1100 return 0; 1101 } 1102 1103 static void intel_pstate_update_policies(void) 1104 { 1105 int cpu; 1106 1107 for_each_possible_cpu(cpu) 1108 cpufreq_update_policy(cpu); 1109 } 1110 1111 static void intel_pstate_update_max_freq(unsigned int cpu) 1112 { 1113 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1114 struct cpudata *cpudata; 1115 1116 if (!policy) 1117 return; 1118 1119 cpudata = all_cpu_data[cpu]; 1120 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 1121 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1122 1123 refresh_frequency_limits(policy); 1124 1125 cpufreq_cpu_release(policy); 1126 } 1127 1128 static void intel_pstate_update_limits(unsigned int cpu) 1129 { 1130 mutex_lock(&intel_pstate_driver_lock); 1131 1132 update_turbo_state(); 1133 /* 1134 * If turbo has been turned on or off globally, policy limits for 1135 * all CPUs need to be updated to reflect that. 1136 */ 1137 if (global.turbo_disabled_mf != global.turbo_disabled) { 1138 global.turbo_disabled_mf = global.turbo_disabled; 1139 arch_set_max_freq_ratio(global.turbo_disabled); 1140 for_each_possible_cpu(cpu) 1141 intel_pstate_update_max_freq(cpu); 1142 } else { 1143 cpufreq_update_policy(cpu); 1144 } 1145 1146 mutex_unlock(&intel_pstate_driver_lock); 1147 } 1148 1149 /************************** sysfs begin ************************/ 1150 #define show_one(file_name, object) \ 1151 static ssize_t show_##file_name \ 1152 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1153 { \ 1154 return sprintf(buf, "%u\n", global.object); \ 1155 } 1156 1157 static ssize_t intel_pstate_show_status(char *buf); 1158 static int intel_pstate_update_status(const char *buf, size_t size); 1159 1160 static ssize_t show_status(struct kobject *kobj, 1161 struct kobj_attribute *attr, char *buf) 1162 { 1163 ssize_t ret; 1164 1165 mutex_lock(&intel_pstate_driver_lock); 1166 ret = intel_pstate_show_status(buf); 1167 mutex_unlock(&intel_pstate_driver_lock); 1168 1169 return ret; 1170 } 1171 1172 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1173 const char *buf, size_t count) 1174 { 1175 char *p = memchr(buf, '\n', count); 1176 int ret; 1177 1178 mutex_lock(&intel_pstate_driver_lock); 1179 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1180 mutex_unlock(&intel_pstate_driver_lock); 1181 1182 return ret < 0 ? ret : count; 1183 } 1184 1185 static ssize_t show_turbo_pct(struct kobject *kobj, 1186 struct kobj_attribute *attr, char *buf) 1187 { 1188 struct cpudata *cpu; 1189 int total, no_turbo, turbo_pct; 1190 uint32_t turbo_fp; 1191 1192 mutex_lock(&intel_pstate_driver_lock); 1193 1194 if (!intel_pstate_driver) { 1195 mutex_unlock(&intel_pstate_driver_lock); 1196 return -EAGAIN; 1197 } 1198 1199 cpu = all_cpu_data[0]; 1200 1201 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1202 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1203 turbo_fp = div_fp(no_turbo, total); 1204 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1205 1206 mutex_unlock(&intel_pstate_driver_lock); 1207 1208 return sprintf(buf, "%u\n", turbo_pct); 1209 } 1210 1211 static ssize_t show_num_pstates(struct kobject *kobj, 1212 struct kobj_attribute *attr, char *buf) 1213 { 1214 struct cpudata *cpu; 1215 int total; 1216 1217 mutex_lock(&intel_pstate_driver_lock); 1218 1219 if (!intel_pstate_driver) { 1220 mutex_unlock(&intel_pstate_driver_lock); 1221 return -EAGAIN; 1222 } 1223 1224 cpu = all_cpu_data[0]; 1225 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1226 1227 mutex_unlock(&intel_pstate_driver_lock); 1228 1229 return sprintf(buf, "%u\n", total); 1230 } 1231 1232 static ssize_t show_no_turbo(struct kobject *kobj, 1233 struct kobj_attribute *attr, char *buf) 1234 { 1235 ssize_t ret; 1236 1237 mutex_lock(&intel_pstate_driver_lock); 1238 1239 if (!intel_pstate_driver) { 1240 mutex_unlock(&intel_pstate_driver_lock); 1241 return -EAGAIN; 1242 } 1243 1244 update_turbo_state(); 1245 if (global.turbo_disabled) 1246 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1247 else 1248 ret = sprintf(buf, "%u\n", global.no_turbo); 1249 1250 mutex_unlock(&intel_pstate_driver_lock); 1251 1252 return ret; 1253 } 1254 1255 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1256 const char *buf, size_t count) 1257 { 1258 unsigned int input; 1259 int ret; 1260 1261 ret = sscanf(buf, "%u", &input); 1262 if (ret != 1) 1263 return -EINVAL; 1264 1265 mutex_lock(&intel_pstate_driver_lock); 1266 1267 if (!intel_pstate_driver) { 1268 mutex_unlock(&intel_pstate_driver_lock); 1269 return -EAGAIN; 1270 } 1271 1272 mutex_lock(&intel_pstate_limits_lock); 1273 1274 update_turbo_state(); 1275 if (global.turbo_disabled) { 1276 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1277 mutex_unlock(&intel_pstate_limits_lock); 1278 mutex_unlock(&intel_pstate_driver_lock); 1279 return -EPERM; 1280 } 1281 1282 global.no_turbo = clamp_t(int, input, 0, 1); 1283 1284 if (global.no_turbo) { 1285 struct cpudata *cpu = all_cpu_data[0]; 1286 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1287 1288 /* Squash the global minimum into the permitted range. */ 1289 if (global.min_perf_pct > pct) 1290 global.min_perf_pct = pct; 1291 } 1292 1293 mutex_unlock(&intel_pstate_limits_lock); 1294 1295 intel_pstate_update_policies(); 1296 1297 mutex_unlock(&intel_pstate_driver_lock); 1298 1299 return count; 1300 } 1301 1302 static void update_qos_request(enum freq_qos_req_type type) 1303 { 1304 struct freq_qos_request *req; 1305 struct cpufreq_policy *policy; 1306 int i; 1307 1308 for_each_possible_cpu(i) { 1309 struct cpudata *cpu = all_cpu_data[i]; 1310 unsigned int freq, perf_pct; 1311 1312 policy = cpufreq_cpu_get(i); 1313 if (!policy) 1314 continue; 1315 1316 req = policy->driver_data; 1317 cpufreq_cpu_put(policy); 1318 1319 if (!req) 1320 continue; 1321 1322 if (hwp_active) 1323 intel_pstate_get_hwp_cap(cpu); 1324 1325 if (type == FREQ_QOS_MIN) { 1326 perf_pct = global.min_perf_pct; 1327 } else { 1328 req++; 1329 perf_pct = global.max_perf_pct; 1330 } 1331 1332 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1333 1334 if (freq_qos_update_request(req, freq) < 0) 1335 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1336 } 1337 } 1338 1339 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1340 const char *buf, size_t count) 1341 { 1342 unsigned int input; 1343 int ret; 1344 1345 ret = sscanf(buf, "%u", &input); 1346 if (ret != 1) 1347 return -EINVAL; 1348 1349 mutex_lock(&intel_pstate_driver_lock); 1350 1351 if (!intel_pstate_driver) { 1352 mutex_unlock(&intel_pstate_driver_lock); 1353 return -EAGAIN; 1354 } 1355 1356 mutex_lock(&intel_pstate_limits_lock); 1357 1358 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1359 1360 mutex_unlock(&intel_pstate_limits_lock); 1361 1362 if (intel_pstate_driver == &intel_pstate) 1363 intel_pstate_update_policies(); 1364 else 1365 update_qos_request(FREQ_QOS_MAX); 1366 1367 mutex_unlock(&intel_pstate_driver_lock); 1368 1369 return count; 1370 } 1371 1372 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1373 const char *buf, size_t count) 1374 { 1375 unsigned int input; 1376 int ret; 1377 1378 ret = sscanf(buf, "%u", &input); 1379 if (ret != 1) 1380 return -EINVAL; 1381 1382 mutex_lock(&intel_pstate_driver_lock); 1383 1384 if (!intel_pstate_driver) { 1385 mutex_unlock(&intel_pstate_driver_lock); 1386 return -EAGAIN; 1387 } 1388 1389 mutex_lock(&intel_pstate_limits_lock); 1390 1391 global.min_perf_pct = clamp_t(int, input, 1392 min_perf_pct_min(), global.max_perf_pct); 1393 1394 mutex_unlock(&intel_pstate_limits_lock); 1395 1396 if (intel_pstate_driver == &intel_pstate) 1397 intel_pstate_update_policies(); 1398 else 1399 update_qos_request(FREQ_QOS_MIN); 1400 1401 mutex_unlock(&intel_pstate_driver_lock); 1402 1403 return count; 1404 } 1405 1406 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1407 struct kobj_attribute *attr, char *buf) 1408 { 1409 return sprintf(buf, "%u\n", hwp_boost); 1410 } 1411 1412 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1413 struct kobj_attribute *b, 1414 const char *buf, size_t count) 1415 { 1416 unsigned int input; 1417 int ret; 1418 1419 ret = kstrtouint(buf, 10, &input); 1420 if (ret) 1421 return ret; 1422 1423 mutex_lock(&intel_pstate_driver_lock); 1424 hwp_boost = !!input; 1425 intel_pstate_update_policies(); 1426 mutex_unlock(&intel_pstate_driver_lock); 1427 1428 return count; 1429 } 1430 1431 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1432 char *buf) 1433 { 1434 u64 power_ctl; 1435 int enable; 1436 1437 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1438 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1439 return sprintf(buf, "%d\n", !enable); 1440 } 1441 1442 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1443 const char *buf, size_t count) 1444 { 1445 bool input; 1446 int ret; 1447 1448 ret = kstrtobool(buf, &input); 1449 if (ret) 1450 return ret; 1451 1452 set_power_ctl_ee_state(input); 1453 1454 return count; 1455 } 1456 1457 show_one(max_perf_pct, max_perf_pct); 1458 show_one(min_perf_pct, min_perf_pct); 1459 1460 define_one_global_rw(status); 1461 define_one_global_rw(no_turbo); 1462 define_one_global_rw(max_perf_pct); 1463 define_one_global_rw(min_perf_pct); 1464 define_one_global_ro(turbo_pct); 1465 define_one_global_ro(num_pstates); 1466 define_one_global_rw(hwp_dynamic_boost); 1467 define_one_global_rw(energy_efficiency); 1468 1469 static struct attribute *intel_pstate_attributes[] = { 1470 &status.attr, 1471 &no_turbo.attr, 1472 NULL 1473 }; 1474 1475 static const struct attribute_group intel_pstate_attr_group = { 1476 .attrs = intel_pstate_attributes, 1477 }; 1478 1479 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1480 1481 static struct kobject *intel_pstate_kobject; 1482 1483 static void __init intel_pstate_sysfs_expose_params(void) 1484 { 1485 int rc; 1486 1487 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1488 &cpu_subsys.dev_root->kobj); 1489 if (WARN_ON(!intel_pstate_kobject)) 1490 return; 1491 1492 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1493 if (WARN_ON(rc)) 1494 return; 1495 1496 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1497 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1498 WARN_ON(rc); 1499 1500 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1501 WARN_ON(rc); 1502 } 1503 1504 /* 1505 * If per cpu limits are enforced there are no global limits, so 1506 * return without creating max/min_perf_pct attributes 1507 */ 1508 if (per_cpu_limits) 1509 return; 1510 1511 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1512 WARN_ON(rc); 1513 1514 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1515 WARN_ON(rc); 1516 1517 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1518 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1519 WARN_ON(rc); 1520 } 1521 } 1522 1523 static void __init intel_pstate_sysfs_remove(void) 1524 { 1525 if (!intel_pstate_kobject) 1526 return; 1527 1528 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1529 1530 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1531 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1532 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1533 } 1534 1535 if (!per_cpu_limits) { 1536 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1537 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1538 1539 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1540 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1541 } 1542 1543 kobject_put(intel_pstate_kobject); 1544 } 1545 1546 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1547 { 1548 int rc; 1549 1550 if (!hwp_active) 1551 return; 1552 1553 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1554 WARN_ON_ONCE(rc); 1555 } 1556 1557 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1558 { 1559 if (!hwp_active) 1560 return; 1561 1562 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1563 } 1564 1565 /************************** sysfs end ************************/ 1566 1567 static void intel_pstate_notify_work(struct work_struct *work) 1568 { 1569 struct cpudata *cpudata = 1570 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1571 1572 cpufreq_update_policy(cpudata->cpu); 1573 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1574 } 1575 1576 static DEFINE_SPINLOCK(hwp_notify_lock); 1577 static cpumask_t hwp_intr_enable_mask; 1578 1579 void notify_hwp_interrupt(void) 1580 { 1581 unsigned int this_cpu = smp_processor_id(); 1582 struct cpudata *cpudata; 1583 unsigned long flags; 1584 u64 value; 1585 1586 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1587 return; 1588 1589 rdmsrl_safe(MSR_HWP_STATUS, &value); 1590 if (!(value & 0x01)) 1591 return; 1592 1593 spin_lock_irqsave(&hwp_notify_lock, flags); 1594 1595 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1596 goto ack_intr; 1597 1598 /* 1599 * Currently we never free all_cpu_data. And we can't reach here 1600 * without this allocated. But for safety for future changes, added 1601 * check. 1602 */ 1603 if (unlikely(!READ_ONCE(all_cpu_data))) 1604 goto ack_intr; 1605 1606 /* 1607 * The free is done during cleanup, when cpufreq registry is failed. 1608 * We wouldn't be here if it fails on init or switch status. But for 1609 * future changes, added check. 1610 */ 1611 cpudata = READ_ONCE(all_cpu_data[this_cpu]); 1612 if (unlikely(!cpudata)) 1613 goto ack_intr; 1614 1615 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10)); 1616 1617 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1618 1619 return; 1620 1621 ack_intr: 1622 wrmsrl_safe(MSR_HWP_STATUS, 0); 1623 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1624 } 1625 1626 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1627 { 1628 unsigned long flags; 1629 1630 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1631 return; 1632 1633 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1634 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1635 1636 spin_lock_irqsave(&hwp_notify_lock, flags); 1637 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask)) 1638 cancel_delayed_work(&cpudata->hwp_notify_work); 1639 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1640 } 1641 1642 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1643 { 1644 /* Enable HWP notification interrupt for guaranteed performance change */ 1645 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1646 unsigned long flags; 1647 1648 spin_lock_irqsave(&hwp_notify_lock, flags); 1649 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1650 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1651 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1652 1653 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1654 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1655 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1656 } 1657 } 1658 1659 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1660 { 1661 /* First disable HWP notification interrupt till we activate again */ 1662 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1663 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1664 1665 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1666 if (cpudata->epp_default == -EINVAL) 1667 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1668 1669 intel_pstate_enable_hwp_interrupt(cpudata); 1670 } 1671 1672 static int atom_get_min_pstate(void) 1673 { 1674 u64 value; 1675 1676 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1677 return (value >> 8) & 0x7F; 1678 } 1679 1680 static int atom_get_max_pstate(void) 1681 { 1682 u64 value; 1683 1684 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1685 return (value >> 16) & 0x7F; 1686 } 1687 1688 static int atom_get_turbo_pstate(void) 1689 { 1690 u64 value; 1691 1692 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1693 return value & 0x7F; 1694 } 1695 1696 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1697 { 1698 u64 val; 1699 int32_t vid_fp; 1700 u32 vid; 1701 1702 val = (u64)pstate << 8; 1703 if (global.no_turbo && !global.turbo_disabled) 1704 val |= (u64)1 << 32; 1705 1706 vid_fp = cpudata->vid.min + mul_fp( 1707 int_tofp(pstate - cpudata->pstate.min_pstate), 1708 cpudata->vid.ratio); 1709 1710 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1711 vid = ceiling_fp(vid_fp); 1712 1713 if (pstate > cpudata->pstate.max_pstate) 1714 vid = cpudata->vid.turbo; 1715 1716 return val | vid; 1717 } 1718 1719 static int silvermont_get_scaling(void) 1720 { 1721 u64 value; 1722 int i; 1723 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1724 static int silvermont_freq_table[] = { 1725 83300, 100000, 133300, 116700, 80000}; 1726 1727 rdmsrl(MSR_FSB_FREQ, value); 1728 i = value & 0x7; 1729 WARN_ON(i > 4); 1730 1731 return silvermont_freq_table[i]; 1732 } 1733 1734 static int airmont_get_scaling(void) 1735 { 1736 u64 value; 1737 int i; 1738 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1739 static int airmont_freq_table[] = { 1740 83300, 100000, 133300, 116700, 80000, 1741 93300, 90000, 88900, 87500}; 1742 1743 rdmsrl(MSR_FSB_FREQ, value); 1744 i = value & 0xF; 1745 WARN_ON(i > 8); 1746 1747 return airmont_freq_table[i]; 1748 } 1749 1750 static void atom_get_vid(struct cpudata *cpudata) 1751 { 1752 u64 value; 1753 1754 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1755 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1756 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1757 cpudata->vid.ratio = div_fp( 1758 cpudata->vid.max - cpudata->vid.min, 1759 int_tofp(cpudata->pstate.max_pstate - 1760 cpudata->pstate.min_pstate)); 1761 1762 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1763 cpudata->vid.turbo = value & 0x7f; 1764 } 1765 1766 static int core_get_min_pstate(void) 1767 { 1768 u64 value; 1769 1770 rdmsrl(MSR_PLATFORM_INFO, value); 1771 return (value >> 40) & 0xFF; 1772 } 1773 1774 static int core_get_max_pstate_physical(void) 1775 { 1776 u64 value; 1777 1778 rdmsrl(MSR_PLATFORM_INFO, value); 1779 return (value >> 8) & 0xFF; 1780 } 1781 1782 static int core_get_tdp_ratio(u64 plat_info) 1783 { 1784 /* Check how many TDP levels present */ 1785 if (plat_info & 0x600000000) { 1786 u64 tdp_ctrl; 1787 u64 tdp_ratio; 1788 int tdp_msr; 1789 int err; 1790 1791 /* Get the TDP level (0, 1, 2) to get ratios */ 1792 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1793 if (err) 1794 return err; 1795 1796 /* TDP MSR are continuous starting at 0x648 */ 1797 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1798 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1799 if (err) 1800 return err; 1801 1802 /* For level 1 and 2, bits[23:16] contain the ratio */ 1803 if (tdp_ctrl & 0x03) 1804 tdp_ratio >>= 16; 1805 1806 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1807 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1808 1809 return (int)tdp_ratio; 1810 } 1811 1812 return -ENXIO; 1813 } 1814 1815 static int core_get_max_pstate(void) 1816 { 1817 u64 tar; 1818 u64 plat_info; 1819 int max_pstate; 1820 int tdp_ratio; 1821 int err; 1822 1823 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1824 max_pstate = (plat_info >> 8) & 0xFF; 1825 1826 tdp_ratio = core_get_tdp_ratio(plat_info); 1827 if (tdp_ratio <= 0) 1828 return max_pstate; 1829 1830 if (hwp_active) { 1831 /* Turbo activation ratio is not used on HWP platforms */ 1832 return tdp_ratio; 1833 } 1834 1835 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1836 if (!err) { 1837 int tar_levels; 1838 1839 /* Do some sanity checking for safety */ 1840 tar_levels = tar & 0xff; 1841 if (tdp_ratio - 1 == tar_levels) { 1842 max_pstate = tar_levels; 1843 pr_debug("max_pstate=TAC %x\n", max_pstate); 1844 } 1845 } 1846 1847 return max_pstate; 1848 } 1849 1850 static int core_get_turbo_pstate(void) 1851 { 1852 u64 value; 1853 int nont, ret; 1854 1855 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1856 nont = core_get_max_pstate(); 1857 ret = (value) & 255; 1858 if (ret <= nont) 1859 ret = nont; 1860 return ret; 1861 } 1862 1863 static inline int core_get_scaling(void) 1864 { 1865 return 100000; 1866 } 1867 1868 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1869 { 1870 u64 val; 1871 1872 val = (u64)pstate << 8; 1873 if (global.no_turbo && !global.turbo_disabled) 1874 val |= (u64)1 << 32; 1875 1876 return val; 1877 } 1878 1879 static int knl_get_aperf_mperf_shift(void) 1880 { 1881 return 10; 1882 } 1883 1884 static int knl_get_turbo_pstate(void) 1885 { 1886 u64 value; 1887 int nont, ret; 1888 1889 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1890 nont = core_get_max_pstate(); 1891 ret = (((value) >> 8) & 0xFF); 1892 if (ret <= nont) 1893 ret = nont; 1894 return ret; 1895 } 1896 1897 #ifdef CONFIG_ACPI_CPPC_LIB 1898 static u32 hybrid_ref_perf; 1899 1900 static int hybrid_get_cpu_scaling(int cpu) 1901 { 1902 return DIV_ROUND_UP(core_get_scaling() * hybrid_ref_perf, 1903 intel_pstate_cppc_nominal(cpu)); 1904 } 1905 1906 static void intel_pstate_cppc_set_cpu_scaling(void) 1907 { 1908 u32 min_nominal_perf = U32_MAX; 1909 int cpu; 1910 1911 for_each_present_cpu(cpu) { 1912 u32 nominal_perf = intel_pstate_cppc_nominal(cpu); 1913 1914 if (nominal_perf && nominal_perf < min_nominal_perf) 1915 min_nominal_perf = nominal_perf; 1916 } 1917 1918 if (min_nominal_perf < U32_MAX) { 1919 hybrid_ref_perf = min_nominal_perf; 1920 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling; 1921 } 1922 } 1923 #else 1924 static inline void intel_pstate_cppc_set_cpu_scaling(void) 1925 { 1926 } 1927 #endif /* CONFIG_ACPI_CPPC_LIB */ 1928 1929 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1930 { 1931 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1932 cpu->pstate.current_pstate = pstate; 1933 /* 1934 * Generally, there is no guarantee that this code will always run on 1935 * the CPU being updated, so force the register update to run on the 1936 * right CPU. 1937 */ 1938 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1939 pstate_funcs.get_val(cpu, pstate)); 1940 } 1941 1942 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1943 { 1944 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1945 } 1946 1947 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1948 { 1949 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1950 1951 update_turbo_state(); 1952 intel_pstate_set_pstate(cpu, pstate); 1953 } 1954 1955 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1956 { 1957 int perf_ctl_max_phys = pstate_funcs.get_max_physical(); 1958 int perf_ctl_scaling = pstate_funcs.get_scaling(); 1959 1960 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1961 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 1962 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 1963 1964 if (hwp_active && !hwp_mode_bdw) { 1965 __intel_pstate_get_hwp_cap(cpu); 1966 1967 if (pstate_funcs.get_cpu_scaling) { 1968 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 1969 if (cpu->pstate.scaling != perf_ctl_scaling) 1970 intel_pstate_hybrid_hwp_adjust(cpu); 1971 } else { 1972 cpu->pstate.scaling = perf_ctl_scaling; 1973 } 1974 } else { 1975 cpu->pstate.scaling = perf_ctl_scaling; 1976 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1977 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1978 } 1979 1980 if (cpu->pstate.scaling == perf_ctl_scaling) { 1981 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 1982 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 1983 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 1984 } 1985 1986 if (pstate_funcs.get_aperf_mperf_shift) 1987 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 1988 1989 if (pstate_funcs.get_vid) 1990 pstate_funcs.get_vid(cpu); 1991 1992 intel_pstate_set_min_pstate(cpu); 1993 } 1994 1995 /* 1996 * Long hold time will keep high perf limits for long time, 1997 * which negatively impacts perf/watt for some workloads, 1998 * like specpower. 3ms is based on experiements on some 1999 * workoads. 2000 */ 2001 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2002 2003 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2004 { 2005 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2006 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2007 u32 max_limit = (hwp_req & 0xff00) >> 8; 2008 u32 min_limit = (hwp_req & 0xff); 2009 u32 boost_level1; 2010 2011 /* 2012 * Cases to consider (User changes via sysfs or boot time): 2013 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2014 * No boost, return. 2015 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2016 * Should result in one level boost only for P0. 2017 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2018 * Should result in two level boost: 2019 * (min + p1)/2 and P1. 2020 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2021 * Should result in three level boost: 2022 * (min + p1)/2, P1 and P0. 2023 */ 2024 2025 /* If max and min are equal or already at max, nothing to boost */ 2026 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2027 return; 2028 2029 if (!cpu->hwp_boost_min) 2030 cpu->hwp_boost_min = min_limit; 2031 2032 /* level at half way mark between min and guranteed */ 2033 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2034 2035 if (cpu->hwp_boost_min < boost_level1) 2036 cpu->hwp_boost_min = boost_level1; 2037 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2038 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2039 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2040 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2041 cpu->hwp_boost_min = max_limit; 2042 else 2043 return; 2044 2045 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2046 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2047 cpu->last_update = cpu->sample.time; 2048 } 2049 2050 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2051 { 2052 if (cpu->hwp_boost_min) { 2053 bool expired; 2054 2055 /* Check if we are idle for hold time to boost down */ 2056 expired = time_after64(cpu->sample.time, cpu->last_update + 2057 hwp_boost_hold_time_ns); 2058 if (expired) { 2059 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2060 cpu->hwp_boost_min = 0; 2061 } 2062 } 2063 cpu->last_update = cpu->sample.time; 2064 } 2065 2066 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2067 u64 time) 2068 { 2069 cpu->sample.time = time; 2070 2071 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2072 bool do_io = false; 2073 2074 cpu->sched_flags = 0; 2075 /* 2076 * Set iowait_boost flag and update time. Since IO WAIT flag 2077 * is set all the time, we can't just conclude that there is 2078 * some IO bound activity is scheduled on this CPU with just 2079 * one occurrence. If we receive at least two in two 2080 * consecutive ticks, then we treat as boost candidate. 2081 */ 2082 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2083 do_io = true; 2084 2085 cpu->last_io_update = time; 2086 2087 if (do_io) 2088 intel_pstate_hwp_boost_up(cpu); 2089 2090 } else { 2091 intel_pstate_hwp_boost_down(cpu); 2092 } 2093 } 2094 2095 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2096 u64 time, unsigned int flags) 2097 { 2098 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2099 2100 cpu->sched_flags |= flags; 2101 2102 if (smp_processor_id() == cpu->cpu) 2103 intel_pstate_update_util_hwp_local(cpu, time); 2104 } 2105 2106 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2107 { 2108 struct sample *sample = &cpu->sample; 2109 2110 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2111 } 2112 2113 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2114 { 2115 u64 aperf, mperf; 2116 unsigned long flags; 2117 u64 tsc; 2118 2119 local_irq_save(flags); 2120 rdmsrl(MSR_IA32_APERF, aperf); 2121 rdmsrl(MSR_IA32_MPERF, mperf); 2122 tsc = rdtsc(); 2123 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2124 local_irq_restore(flags); 2125 return false; 2126 } 2127 local_irq_restore(flags); 2128 2129 cpu->last_sample_time = cpu->sample.time; 2130 cpu->sample.time = time; 2131 cpu->sample.aperf = aperf; 2132 cpu->sample.mperf = mperf; 2133 cpu->sample.tsc = tsc; 2134 cpu->sample.aperf -= cpu->prev_aperf; 2135 cpu->sample.mperf -= cpu->prev_mperf; 2136 cpu->sample.tsc -= cpu->prev_tsc; 2137 2138 cpu->prev_aperf = aperf; 2139 cpu->prev_mperf = mperf; 2140 cpu->prev_tsc = tsc; 2141 /* 2142 * First time this function is invoked in a given cycle, all of the 2143 * previous sample data fields are equal to zero or stale and they must 2144 * be populated with meaningful numbers for things to work, so assume 2145 * that sample.time will always be reset before setting the utilization 2146 * update hook and make the caller skip the sample then. 2147 */ 2148 if (cpu->last_sample_time) { 2149 intel_pstate_calc_avg_perf(cpu); 2150 return true; 2151 } 2152 return false; 2153 } 2154 2155 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2156 { 2157 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2158 } 2159 2160 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2161 { 2162 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2163 cpu->sample.core_avg_perf); 2164 } 2165 2166 static inline int32_t get_target_pstate(struct cpudata *cpu) 2167 { 2168 struct sample *sample = &cpu->sample; 2169 int32_t busy_frac; 2170 int target, avg_pstate; 2171 2172 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2173 sample->tsc); 2174 2175 if (busy_frac < cpu->iowait_boost) 2176 busy_frac = cpu->iowait_boost; 2177 2178 sample->busy_scaled = busy_frac * 100; 2179 2180 target = global.no_turbo || global.turbo_disabled ? 2181 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2182 target += target >> 2; 2183 target = mul_fp(target, busy_frac); 2184 if (target < cpu->pstate.min_pstate) 2185 target = cpu->pstate.min_pstate; 2186 2187 /* 2188 * If the average P-state during the previous cycle was higher than the 2189 * current target, add 50% of the difference to the target to reduce 2190 * possible performance oscillations and offset possible performance 2191 * loss related to moving the workload from one CPU to another within 2192 * a package/module. 2193 */ 2194 avg_pstate = get_avg_pstate(cpu); 2195 if (avg_pstate > target) 2196 target += (avg_pstate - target) >> 1; 2197 2198 return target; 2199 } 2200 2201 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2202 { 2203 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2204 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2205 2206 return clamp_t(int, pstate, min_pstate, max_pstate); 2207 } 2208 2209 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2210 { 2211 if (pstate == cpu->pstate.current_pstate) 2212 return; 2213 2214 cpu->pstate.current_pstate = pstate; 2215 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2216 } 2217 2218 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2219 { 2220 int from = cpu->pstate.current_pstate; 2221 struct sample *sample; 2222 int target_pstate; 2223 2224 update_turbo_state(); 2225 2226 target_pstate = get_target_pstate(cpu); 2227 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2228 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2229 intel_pstate_update_pstate(cpu, target_pstate); 2230 2231 sample = &cpu->sample; 2232 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2233 fp_toint(sample->busy_scaled), 2234 from, 2235 cpu->pstate.current_pstate, 2236 sample->mperf, 2237 sample->aperf, 2238 sample->tsc, 2239 get_avg_frequency(cpu), 2240 fp_toint(cpu->iowait_boost * 100)); 2241 } 2242 2243 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2244 unsigned int flags) 2245 { 2246 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2247 u64 delta_ns; 2248 2249 /* Don't allow remote callbacks */ 2250 if (smp_processor_id() != cpu->cpu) 2251 return; 2252 2253 delta_ns = time - cpu->last_update; 2254 if (flags & SCHED_CPUFREQ_IOWAIT) { 2255 /* Start over if the CPU may have been idle. */ 2256 if (delta_ns > TICK_NSEC) { 2257 cpu->iowait_boost = ONE_EIGHTH_FP; 2258 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2259 cpu->iowait_boost <<= 1; 2260 if (cpu->iowait_boost > int_tofp(1)) 2261 cpu->iowait_boost = int_tofp(1); 2262 } else { 2263 cpu->iowait_boost = ONE_EIGHTH_FP; 2264 } 2265 } else if (cpu->iowait_boost) { 2266 /* Clear iowait_boost if the CPU may have been idle. */ 2267 if (delta_ns > TICK_NSEC) 2268 cpu->iowait_boost = 0; 2269 else 2270 cpu->iowait_boost >>= 1; 2271 } 2272 cpu->last_update = time; 2273 delta_ns = time - cpu->sample.time; 2274 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2275 return; 2276 2277 if (intel_pstate_sample(cpu, time)) 2278 intel_pstate_adjust_pstate(cpu); 2279 } 2280 2281 static struct pstate_funcs core_funcs = { 2282 .get_max = core_get_max_pstate, 2283 .get_max_physical = core_get_max_pstate_physical, 2284 .get_min = core_get_min_pstate, 2285 .get_turbo = core_get_turbo_pstate, 2286 .get_scaling = core_get_scaling, 2287 .get_val = core_get_val, 2288 }; 2289 2290 static const struct pstate_funcs silvermont_funcs = { 2291 .get_max = atom_get_max_pstate, 2292 .get_max_physical = atom_get_max_pstate, 2293 .get_min = atom_get_min_pstate, 2294 .get_turbo = atom_get_turbo_pstate, 2295 .get_val = atom_get_val, 2296 .get_scaling = silvermont_get_scaling, 2297 .get_vid = atom_get_vid, 2298 }; 2299 2300 static const struct pstate_funcs airmont_funcs = { 2301 .get_max = atom_get_max_pstate, 2302 .get_max_physical = atom_get_max_pstate, 2303 .get_min = atom_get_min_pstate, 2304 .get_turbo = atom_get_turbo_pstate, 2305 .get_val = atom_get_val, 2306 .get_scaling = airmont_get_scaling, 2307 .get_vid = atom_get_vid, 2308 }; 2309 2310 static const struct pstate_funcs knl_funcs = { 2311 .get_max = core_get_max_pstate, 2312 .get_max_physical = core_get_max_pstate_physical, 2313 .get_min = core_get_min_pstate, 2314 .get_turbo = knl_get_turbo_pstate, 2315 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2316 .get_scaling = core_get_scaling, 2317 .get_val = core_get_val, 2318 }; 2319 2320 #define X86_MATCH(model, policy) \ 2321 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2322 X86_FEATURE_APERFMPERF, &policy) 2323 2324 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2325 X86_MATCH(SANDYBRIDGE, core_funcs), 2326 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2327 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2328 X86_MATCH(IVYBRIDGE, core_funcs), 2329 X86_MATCH(HASWELL, core_funcs), 2330 X86_MATCH(BROADWELL, core_funcs), 2331 X86_MATCH(IVYBRIDGE_X, core_funcs), 2332 X86_MATCH(HASWELL_X, core_funcs), 2333 X86_MATCH(HASWELL_L, core_funcs), 2334 X86_MATCH(HASWELL_G, core_funcs), 2335 X86_MATCH(BROADWELL_G, core_funcs), 2336 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2337 X86_MATCH(SKYLAKE_L, core_funcs), 2338 X86_MATCH(BROADWELL_X, core_funcs), 2339 X86_MATCH(SKYLAKE, core_funcs), 2340 X86_MATCH(BROADWELL_D, core_funcs), 2341 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2342 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2343 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2344 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2345 X86_MATCH(SKYLAKE_X, core_funcs), 2346 X86_MATCH(COMETLAKE, core_funcs), 2347 X86_MATCH(ICELAKE_X, core_funcs), 2348 {} 2349 }; 2350 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2351 2352 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2353 X86_MATCH(BROADWELL_D, core_funcs), 2354 X86_MATCH(BROADWELL_X, core_funcs), 2355 X86_MATCH(SKYLAKE_X, core_funcs), 2356 {} 2357 }; 2358 2359 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2360 X86_MATCH(KABYLAKE, core_funcs), 2361 {} 2362 }; 2363 2364 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = { 2365 X86_MATCH(SKYLAKE_X, core_funcs), 2366 X86_MATCH(SKYLAKE, core_funcs), 2367 {} 2368 }; 2369 2370 static int intel_pstate_init_cpu(unsigned int cpunum) 2371 { 2372 struct cpudata *cpu; 2373 2374 cpu = all_cpu_data[cpunum]; 2375 2376 if (!cpu) { 2377 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2378 if (!cpu) 2379 return -ENOMEM; 2380 2381 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2382 2383 cpu->cpu = cpunum; 2384 2385 cpu->epp_default = -EINVAL; 2386 2387 if (hwp_active) { 2388 const struct x86_cpu_id *id; 2389 2390 intel_pstate_hwp_enable(cpu); 2391 2392 id = x86_match_cpu(intel_pstate_hwp_boost_ids); 2393 if (id && intel_pstate_acpi_pm_profile_server()) 2394 hwp_boost = true; 2395 } 2396 } else if (hwp_active) { 2397 /* 2398 * Re-enable HWP in case this happens after a resume from ACPI 2399 * S3 if the CPU was offline during the whole system/resume 2400 * cycle. 2401 */ 2402 intel_pstate_hwp_reenable(cpu); 2403 } 2404 2405 cpu->epp_powersave = -EINVAL; 2406 cpu->epp_policy = 0; 2407 2408 intel_pstate_get_cpu_pstates(cpu); 2409 2410 pr_debug("controlling: cpu %d\n", cpunum); 2411 2412 return 0; 2413 } 2414 2415 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2416 { 2417 struct cpudata *cpu = all_cpu_data[cpu_num]; 2418 2419 if (hwp_active && !hwp_boost) 2420 return; 2421 2422 if (cpu->update_util_set) 2423 return; 2424 2425 /* Prevent intel_pstate_update_util() from using stale data. */ 2426 cpu->sample.time = 0; 2427 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2428 (hwp_active ? 2429 intel_pstate_update_util_hwp : 2430 intel_pstate_update_util)); 2431 cpu->update_util_set = true; 2432 } 2433 2434 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2435 { 2436 struct cpudata *cpu_data = all_cpu_data[cpu]; 2437 2438 if (!cpu_data->update_util_set) 2439 return; 2440 2441 cpufreq_remove_update_util_hook(cpu); 2442 cpu_data->update_util_set = false; 2443 synchronize_rcu(); 2444 } 2445 2446 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2447 { 2448 return global.turbo_disabled || global.no_turbo ? 2449 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2450 } 2451 2452 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2453 unsigned int policy_min, 2454 unsigned int policy_max) 2455 { 2456 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2457 int32_t max_policy_perf, min_policy_perf; 2458 2459 max_policy_perf = policy_max / perf_ctl_scaling; 2460 if (policy_max == policy_min) { 2461 min_policy_perf = max_policy_perf; 2462 } else { 2463 min_policy_perf = policy_min / perf_ctl_scaling; 2464 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2465 0, max_policy_perf); 2466 } 2467 2468 /* 2469 * HWP needs some special consideration, because HWP_REQUEST uses 2470 * abstract values to represent performance rather than pure ratios. 2471 */ 2472 if (hwp_active) { 2473 intel_pstate_get_hwp_cap(cpu); 2474 2475 if (cpu->pstate.scaling != perf_ctl_scaling) { 2476 int scaling = cpu->pstate.scaling; 2477 int freq; 2478 2479 freq = max_policy_perf * perf_ctl_scaling; 2480 max_policy_perf = DIV_ROUND_UP(freq, scaling); 2481 freq = min_policy_perf * perf_ctl_scaling; 2482 min_policy_perf = DIV_ROUND_UP(freq, scaling); 2483 } 2484 } 2485 2486 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2487 cpu->cpu, min_policy_perf, max_policy_perf); 2488 2489 /* Normalize user input to [min_perf, max_perf] */ 2490 if (per_cpu_limits) { 2491 cpu->min_perf_ratio = min_policy_perf; 2492 cpu->max_perf_ratio = max_policy_perf; 2493 } else { 2494 int turbo_max = cpu->pstate.turbo_pstate; 2495 int32_t global_min, global_max; 2496 2497 /* Global limits are in percent of the maximum turbo P-state. */ 2498 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2499 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2500 global_min = clamp_t(int32_t, global_min, 0, global_max); 2501 2502 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2503 global_min, global_max); 2504 2505 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2506 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2507 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2508 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2509 2510 /* Make sure min_perf <= max_perf */ 2511 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2512 cpu->max_perf_ratio); 2513 2514 } 2515 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2516 cpu->max_perf_ratio, 2517 cpu->min_perf_ratio); 2518 } 2519 2520 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2521 { 2522 struct cpudata *cpu; 2523 2524 if (!policy->cpuinfo.max_freq) 2525 return -ENODEV; 2526 2527 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2528 policy->cpuinfo.max_freq, policy->max); 2529 2530 cpu = all_cpu_data[policy->cpu]; 2531 cpu->policy = policy->policy; 2532 2533 mutex_lock(&intel_pstate_limits_lock); 2534 2535 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2536 2537 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2538 /* 2539 * NOHZ_FULL CPUs need this as the governor callback may not 2540 * be invoked on them. 2541 */ 2542 intel_pstate_clear_update_util_hook(policy->cpu); 2543 intel_pstate_max_within_limits(cpu); 2544 } else { 2545 intel_pstate_set_update_util_hook(policy->cpu); 2546 } 2547 2548 if (hwp_active) { 2549 /* 2550 * When hwp_boost was active before and dynamically it 2551 * was turned off, in that case we need to clear the 2552 * update util hook. 2553 */ 2554 if (!hwp_boost) 2555 intel_pstate_clear_update_util_hook(policy->cpu); 2556 intel_pstate_hwp_set(policy->cpu); 2557 } 2558 2559 mutex_unlock(&intel_pstate_limits_lock); 2560 2561 return 0; 2562 } 2563 2564 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2565 struct cpufreq_policy_data *policy) 2566 { 2567 if (!hwp_active && 2568 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2569 policy->max < policy->cpuinfo.max_freq && 2570 policy->max > cpu->pstate.max_freq) { 2571 pr_debug("policy->max > max non turbo frequency\n"); 2572 policy->max = policy->cpuinfo.max_freq; 2573 } 2574 } 2575 2576 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2577 struct cpufreq_policy_data *policy) 2578 { 2579 int max_freq; 2580 2581 update_turbo_state(); 2582 if (hwp_active) { 2583 intel_pstate_get_hwp_cap(cpu); 2584 max_freq = global.no_turbo || global.turbo_disabled ? 2585 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2586 } else { 2587 max_freq = intel_pstate_get_max_freq(cpu); 2588 } 2589 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2590 2591 intel_pstate_adjust_policy_max(cpu, policy); 2592 } 2593 2594 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2595 { 2596 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2597 2598 return 0; 2599 } 2600 2601 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2602 { 2603 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2604 2605 pr_debug("CPU %d going offline\n", cpu->cpu); 2606 2607 if (cpu->suspended) 2608 return 0; 2609 2610 /* 2611 * If the CPU is an SMT thread and it goes offline with the performance 2612 * settings different from the minimum, it will prevent its sibling 2613 * from getting to lower performance levels, so force the minimum 2614 * performance on CPU offline to prevent that from happening. 2615 */ 2616 if (hwp_active) 2617 intel_pstate_hwp_offline(cpu); 2618 else 2619 intel_pstate_set_min_pstate(cpu); 2620 2621 intel_pstate_exit_perf_limits(policy); 2622 2623 return 0; 2624 } 2625 2626 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2627 { 2628 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2629 2630 pr_debug("CPU %d going online\n", cpu->cpu); 2631 2632 intel_pstate_init_acpi_perf_limits(policy); 2633 2634 if (hwp_active) { 2635 /* 2636 * Re-enable HWP and clear the "suspended" flag to let "resume" 2637 * know that it need not do that. 2638 */ 2639 intel_pstate_hwp_reenable(cpu); 2640 cpu->suspended = false; 2641 } 2642 2643 return 0; 2644 } 2645 2646 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2647 { 2648 intel_pstate_clear_update_util_hook(policy->cpu); 2649 2650 return intel_cpufreq_cpu_offline(policy); 2651 } 2652 2653 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2654 { 2655 pr_debug("CPU %d exiting\n", policy->cpu); 2656 2657 policy->fast_switch_possible = false; 2658 2659 return 0; 2660 } 2661 2662 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2663 { 2664 struct cpudata *cpu; 2665 int rc; 2666 2667 rc = intel_pstate_init_cpu(policy->cpu); 2668 if (rc) 2669 return rc; 2670 2671 cpu = all_cpu_data[policy->cpu]; 2672 2673 cpu->max_perf_ratio = 0xFF; 2674 cpu->min_perf_ratio = 0; 2675 2676 /* cpuinfo and default policy values */ 2677 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2678 update_turbo_state(); 2679 global.turbo_disabled_mf = global.turbo_disabled; 2680 policy->cpuinfo.max_freq = global.turbo_disabled ? 2681 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2682 2683 policy->min = policy->cpuinfo.min_freq; 2684 policy->max = policy->cpuinfo.max_freq; 2685 2686 intel_pstate_init_acpi_perf_limits(policy); 2687 2688 policy->fast_switch_possible = true; 2689 2690 return 0; 2691 } 2692 2693 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2694 { 2695 int ret = __intel_pstate_cpu_init(policy); 2696 2697 if (ret) 2698 return ret; 2699 2700 /* 2701 * Set the policy to powersave to provide a valid fallback value in case 2702 * the default cpufreq governor is neither powersave nor performance. 2703 */ 2704 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2705 2706 if (hwp_active) { 2707 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2708 2709 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2710 } 2711 2712 return 0; 2713 } 2714 2715 static struct cpufreq_driver intel_pstate = { 2716 .flags = CPUFREQ_CONST_LOOPS, 2717 .verify = intel_pstate_verify_policy, 2718 .setpolicy = intel_pstate_set_policy, 2719 .suspend = intel_pstate_suspend, 2720 .resume = intel_pstate_resume, 2721 .init = intel_pstate_cpu_init, 2722 .exit = intel_pstate_cpu_exit, 2723 .offline = intel_pstate_cpu_offline, 2724 .online = intel_pstate_cpu_online, 2725 .update_limits = intel_pstate_update_limits, 2726 .name = "intel_pstate", 2727 }; 2728 2729 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2730 { 2731 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2732 2733 intel_pstate_verify_cpu_policy(cpu, policy); 2734 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2735 2736 return 0; 2737 } 2738 2739 /* Use of trace in passive mode: 2740 * 2741 * In passive mode the trace core_busy field (also known as the 2742 * performance field, and lablelled as such on the graphs; also known as 2743 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2744 * driver call was via the normal or fast switch path. Various graphs 2745 * output from the intel_pstate_tracer.py utility that include core_busy 2746 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2747 * so we use 10 to indicate the normal path through the driver, and 2748 * 90 to indicate the fast switch path through the driver. 2749 * The scaled_busy field is not used, and is set to 0. 2750 */ 2751 2752 #define INTEL_PSTATE_TRACE_TARGET 10 2753 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2754 2755 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2756 { 2757 struct sample *sample; 2758 2759 if (!trace_pstate_sample_enabled()) 2760 return; 2761 2762 if (!intel_pstate_sample(cpu, ktime_get())) 2763 return; 2764 2765 sample = &cpu->sample; 2766 trace_pstate_sample(trace_type, 2767 0, 2768 old_pstate, 2769 cpu->pstate.current_pstate, 2770 sample->mperf, 2771 sample->aperf, 2772 sample->tsc, 2773 get_avg_frequency(cpu), 2774 fp_toint(cpu->iowait_boost * 100)); 2775 } 2776 2777 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2778 u32 desired, bool fast_switch) 2779 { 2780 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2781 2782 value &= ~HWP_MIN_PERF(~0L); 2783 value |= HWP_MIN_PERF(min); 2784 2785 value &= ~HWP_MAX_PERF(~0L); 2786 value |= HWP_MAX_PERF(max); 2787 2788 value &= ~HWP_DESIRED_PERF(~0L); 2789 value |= HWP_DESIRED_PERF(desired); 2790 2791 if (value == prev) 2792 return; 2793 2794 WRITE_ONCE(cpu->hwp_req_cached, value); 2795 if (fast_switch) 2796 wrmsrl(MSR_HWP_REQUEST, value); 2797 else 2798 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2799 } 2800 2801 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2802 u32 target_pstate, bool fast_switch) 2803 { 2804 if (fast_switch) 2805 wrmsrl(MSR_IA32_PERF_CTL, 2806 pstate_funcs.get_val(cpu, target_pstate)); 2807 else 2808 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2809 pstate_funcs.get_val(cpu, target_pstate)); 2810 } 2811 2812 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2813 int target_pstate, bool fast_switch) 2814 { 2815 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2816 int old_pstate = cpu->pstate.current_pstate; 2817 2818 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2819 if (hwp_active) { 2820 int max_pstate = policy->strict_target ? 2821 target_pstate : cpu->max_perf_ratio; 2822 2823 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2824 fast_switch); 2825 } else if (target_pstate != old_pstate) { 2826 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2827 } 2828 2829 cpu->pstate.current_pstate = target_pstate; 2830 2831 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2832 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2833 2834 return target_pstate; 2835 } 2836 2837 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2838 unsigned int target_freq, 2839 unsigned int relation) 2840 { 2841 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2842 struct cpufreq_freqs freqs; 2843 int target_pstate; 2844 2845 update_turbo_state(); 2846 2847 freqs.old = policy->cur; 2848 freqs.new = target_freq; 2849 2850 cpufreq_freq_transition_begin(policy, &freqs); 2851 2852 switch (relation) { 2853 case CPUFREQ_RELATION_L: 2854 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2855 break; 2856 case CPUFREQ_RELATION_H: 2857 target_pstate = freqs.new / cpu->pstate.scaling; 2858 break; 2859 default: 2860 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2861 break; 2862 } 2863 2864 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2865 2866 freqs.new = target_pstate * cpu->pstate.scaling; 2867 2868 cpufreq_freq_transition_end(policy, &freqs, false); 2869 2870 return 0; 2871 } 2872 2873 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2874 unsigned int target_freq) 2875 { 2876 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2877 int target_pstate; 2878 2879 update_turbo_state(); 2880 2881 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2882 2883 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2884 2885 return target_pstate * cpu->pstate.scaling; 2886 } 2887 2888 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2889 unsigned long min_perf, 2890 unsigned long target_perf, 2891 unsigned long capacity) 2892 { 2893 struct cpudata *cpu = all_cpu_data[cpunum]; 2894 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2895 int old_pstate = cpu->pstate.current_pstate; 2896 int cap_pstate, min_pstate, max_pstate, target_pstate; 2897 2898 update_turbo_state(); 2899 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) : 2900 HWP_HIGHEST_PERF(hwp_cap); 2901 2902 /* Optimization: Avoid unnecessary divisions. */ 2903 2904 target_pstate = cap_pstate; 2905 if (target_perf < capacity) 2906 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2907 2908 min_pstate = cap_pstate; 2909 if (min_perf < capacity) 2910 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2911 2912 if (min_pstate < cpu->pstate.min_pstate) 2913 min_pstate = cpu->pstate.min_pstate; 2914 2915 if (min_pstate < cpu->min_perf_ratio) 2916 min_pstate = cpu->min_perf_ratio; 2917 2918 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2919 if (max_pstate < min_pstate) 2920 max_pstate = min_pstate; 2921 2922 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2923 2924 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2925 2926 cpu->pstate.current_pstate = target_pstate; 2927 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2928 } 2929 2930 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2931 { 2932 struct freq_qos_request *req; 2933 struct cpudata *cpu; 2934 struct device *dev; 2935 int ret, freq; 2936 2937 dev = get_cpu_device(policy->cpu); 2938 if (!dev) 2939 return -ENODEV; 2940 2941 ret = __intel_pstate_cpu_init(policy); 2942 if (ret) 2943 return ret; 2944 2945 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2946 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2947 policy->cur = policy->cpuinfo.min_freq; 2948 2949 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2950 if (!req) { 2951 ret = -ENOMEM; 2952 goto pstate_exit; 2953 } 2954 2955 cpu = all_cpu_data[policy->cpu]; 2956 2957 if (hwp_active) { 2958 u64 value; 2959 2960 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2961 2962 intel_pstate_get_hwp_cap(cpu); 2963 2964 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 2965 WRITE_ONCE(cpu->hwp_req_cached, value); 2966 2967 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 2968 } else { 2969 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2970 } 2971 2972 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 2973 2974 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 2975 freq); 2976 if (ret < 0) { 2977 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 2978 goto free_req; 2979 } 2980 2981 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 2982 2983 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 2984 freq); 2985 if (ret < 0) { 2986 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 2987 goto remove_min_req; 2988 } 2989 2990 policy->driver_data = req; 2991 2992 return 0; 2993 2994 remove_min_req: 2995 freq_qos_remove_request(req); 2996 free_req: 2997 kfree(req); 2998 pstate_exit: 2999 intel_pstate_exit_perf_limits(policy); 3000 3001 return ret; 3002 } 3003 3004 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3005 { 3006 struct freq_qos_request *req; 3007 3008 req = policy->driver_data; 3009 3010 freq_qos_remove_request(req + 1); 3011 freq_qos_remove_request(req); 3012 kfree(req); 3013 3014 return intel_pstate_cpu_exit(policy); 3015 } 3016 3017 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3018 { 3019 intel_pstate_suspend(policy); 3020 3021 if (hwp_active) { 3022 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3023 u64 value = READ_ONCE(cpu->hwp_req_cached); 3024 3025 /* 3026 * Clear the desired perf field in MSR_HWP_REQUEST in case 3027 * intel_cpufreq_adjust_perf() is in use and the last value 3028 * written by it may not be suitable. 3029 */ 3030 value &= ~HWP_DESIRED_PERF(~0L); 3031 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3032 WRITE_ONCE(cpu->hwp_req_cached, value); 3033 } 3034 3035 return 0; 3036 } 3037 3038 static struct cpufreq_driver intel_cpufreq = { 3039 .flags = CPUFREQ_CONST_LOOPS, 3040 .verify = intel_cpufreq_verify_policy, 3041 .target = intel_cpufreq_target, 3042 .fast_switch = intel_cpufreq_fast_switch, 3043 .init = intel_cpufreq_cpu_init, 3044 .exit = intel_cpufreq_cpu_exit, 3045 .offline = intel_cpufreq_cpu_offline, 3046 .online = intel_pstate_cpu_online, 3047 .suspend = intel_cpufreq_suspend, 3048 .resume = intel_pstate_resume, 3049 .update_limits = intel_pstate_update_limits, 3050 .name = "intel_cpufreq", 3051 }; 3052 3053 static struct cpufreq_driver *default_driver; 3054 3055 static void intel_pstate_driver_cleanup(void) 3056 { 3057 unsigned int cpu; 3058 3059 cpus_read_lock(); 3060 for_each_online_cpu(cpu) { 3061 if (all_cpu_data[cpu]) { 3062 if (intel_pstate_driver == &intel_pstate) 3063 intel_pstate_clear_update_util_hook(cpu); 3064 3065 spin_lock(&hwp_notify_lock); 3066 kfree(all_cpu_data[cpu]); 3067 WRITE_ONCE(all_cpu_data[cpu], NULL); 3068 spin_unlock(&hwp_notify_lock); 3069 } 3070 } 3071 cpus_read_unlock(); 3072 3073 intel_pstate_driver = NULL; 3074 } 3075 3076 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3077 { 3078 int ret; 3079 3080 if (driver == &intel_pstate) 3081 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3082 3083 memset(&global, 0, sizeof(global)); 3084 global.max_perf_pct = 100; 3085 3086 intel_pstate_driver = driver; 3087 ret = cpufreq_register_driver(intel_pstate_driver); 3088 if (ret) { 3089 intel_pstate_driver_cleanup(); 3090 return ret; 3091 } 3092 3093 global.min_perf_pct = min_perf_pct_min(); 3094 3095 return 0; 3096 } 3097 3098 static ssize_t intel_pstate_show_status(char *buf) 3099 { 3100 if (!intel_pstate_driver) 3101 return sprintf(buf, "off\n"); 3102 3103 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3104 "active" : "passive"); 3105 } 3106 3107 static int intel_pstate_update_status(const char *buf, size_t size) 3108 { 3109 if (size == 3 && !strncmp(buf, "off", size)) { 3110 if (!intel_pstate_driver) 3111 return -EINVAL; 3112 3113 if (hwp_active) 3114 return -EBUSY; 3115 3116 cpufreq_unregister_driver(intel_pstate_driver); 3117 intel_pstate_driver_cleanup(); 3118 return 0; 3119 } 3120 3121 if (size == 6 && !strncmp(buf, "active", size)) { 3122 if (intel_pstate_driver) { 3123 if (intel_pstate_driver == &intel_pstate) 3124 return 0; 3125 3126 cpufreq_unregister_driver(intel_pstate_driver); 3127 } 3128 3129 return intel_pstate_register_driver(&intel_pstate); 3130 } 3131 3132 if (size == 7 && !strncmp(buf, "passive", size)) { 3133 if (intel_pstate_driver) { 3134 if (intel_pstate_driver == &intel_cpufreq) 3135 return 0; 3136 3137 cpufreq_unregister_driver(intel_pstate_driver); 3138 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3139 } 3140 3141 return intel_pstate_register_driver(&intel_cpufreq); 3142 } 3143 3144 return -EINVAL; 3145 } 3146 3147 static int no_load __initdata; 3148 static int no_hwp __initdata; 3149 static int hwp_only __initdata; 3150 static unsigned int force_load __initdata; 3151 3152 static int __init intel_pstate_msrs_not_valid(void) 3153 { 3154 if (!pstate_funcs.get_max() || 3155 !pstate_funcs.get_min() || 3156 !pstate_funcs.get_turbo()) 3157 return -ENODEV; 3158 3159 return 0; 3160 } 3161 3162 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3163 { 3164 pstate_funcs.get_max = funcs->get_max; 3165 pstate_funcs.get_max_physical = funcs->get_max_physical; 3166 pstate_funcs.get_min = funcs->get_min; 3167 pstate_funcs.get_turbo = funcs->get_turbo; 3168 pstate_funcs.get_scaling = funcs->get_scaling; 3169 pstate_funcs.get_val = funcs->get_val; 3170 pstate_funcs.get_vid = funcs->get_vid; 3171 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3172 } 3173 3174 #ifdef CONFIG_ACPI 3175 3176 static bool __init intel_pstate_no_acpi_pss(void) 3177 { 3178 int i; 3179 3180 for_each_possible_cpu(i) { 3181 acpi_status status; 3182 union acpi_object *pss; 3183 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3184 struct acpi_processor *pr = per_cpu(processors, i); 3185 3186 if (!pr) 3187 continue; 3188 3189 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3190 if (ACPI_FAILURE(status)) 3191 continue; 3192 3193 pss = buffer.pointer; 3194 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3195 kfree(pss); 3196 return false; 3197 } 3198 3199 kfree(pss); 3200 } 3201 3202 pr_debug("ACPI _PSS not found\n"); 3203 return true; 3204 } 3205 3206 static bool __init intel_pstate_no_acpi_pcch(void) 3207 { 3208 acpi_status status; 3209 acpi_handle handle; 3210 3211 status = acpi_get_handle(NULL, "\\_SB", &handle); 3212 if (ACPI_FAILURE(status)) 3213 goto not_found; 3214 3215 if (acpi_has_method(handle, "PCCH")) 3216 return false; 3217 3218 not_found: 3219 pr_debug("ACPI PCCH not found\n"); 3220 return true; 3221 } 3222 3223 static bool __init intel_pstate_has_acpi_ppc(void) 3224 { 3225 int i; 3226 3227 for_each_possible_cpu(i) { 3228 struct acpi_processor *pr = per_cpu(processors, i); 3229 3230 if (!pr) 3231 continue; 3232 if (acpi_has_method(pr->handle, "_PPC")) 3233 return true; 3234 } 3235 pr_debug("ACPI _PPC not found\n"); 3236 return false; 3237 } 3238 3239 enum { 3240 PSS, 3241 PPC, 3242 }; 3243 3244 /* Hardware vendor-specific info that has its own power management modes */ 3245 static struct acpi_platform_list plat_info[] __initdata = { 3246 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3247 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3248 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3249 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3250 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3251 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3252 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3253 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3254 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3255 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3256 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3257 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3258 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3259 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3260 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3261 { } /* End */ 3262 }; 3263 3264 #define BITMASK_OOB (BIT(8) | BIT(18)) 3265 3266 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3267 { 3268 const struct x86_cpu_id *id; 3269 u64 misc_pwr; 3270 int idx; 3271 3272 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3273 if (id) { 3274 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3275 if (misc_pwr & BITMASK_OOB) { 3276 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3277 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3278 return true; 3279 } 3280 } 3281 3282 idx = acpi_match_platform_list(plat_info); 3283 if (idx < 0) 3284 return false; 3285 3286 switch (plat_info[idx].data) { 3287 case PSS: 3288 if (!intel_pstate_no_acpi_pss()) 3289 return false; 3290 3291 return intel_pstate_no_acpi_pcch(); 3292 case PPC: 3293 return intel_pstate_has_acpi_ppc() && !force_load; 3294 } 3295 3296 return false; 3297 } 3298 3299 static void intel_pstate_request_control_from_smm(void) 3300 { 3301 /* 3302 * It may be unsafe to request P-states control from SMM if _PPC support 3303 * has not been enabled. 3304 */ 3305 if (acpi_ppc) 3306 acpi_processor_pstate_control(); 3307 } 3308 #else /* CONFIG_ACPI not enabled */ 3309 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3310 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3311 static inline void intel_pstate_request_control_from_smm(void) {} 3312 #endif /* CONFIG_ACPI */ 3313 3314 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3315 3316 #define X86_MATCH_HWP(model, hwp_mode) \ 3317 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3318 X86_FEATURE_HWP, hwp_mode) 3319 3320 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3321 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3322 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3323 X86_MATCH_HWP(ANY, 0), 3324 {} 3325 }; 3326 3327 static bool intel_pstate_hwp_is_enabled(void) 3328 { 3329 u64 value; 3330 3331 rdmsrl(MSR_PM_ENABLE, value); 3332 return !!(value & 0x1); 3333 } 3334 3335 static int __init intel_pstate_init(void) 3336 { 3337 static struct cpudata **_all_cpu_data; 3338 const struct x86_cpu_id *id; 3339 int rc; 3340 3341 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3342 return -ENODEV; 3343 3344 id = x86_match_cpu(hwp_support_ids); 3345 if (id) { 3346 bool hwp_forced = intel_pstate_hwp_is_enabled(); 3347 3348 if (hwp_forced) 3349 pr_info("HWP enabled by BIOS\n"); 3350 else if (no_load) 3351 return -ENODEV; 3352 3353 copy_cpu_funcs(&core_funcs); 3354 /* 3355 * Avoid enabling HWP for processors without EPP support, 3356 * because that means incomplete HWP implementation which is a 3357 * corner case and supporting it is generally problematic. 3358 * 3359 * If HWP is enabled already, though, there is no choice but to 3360 * deal with it. 3361 */ 3362 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3363 WRITE_ONCE(hwp_active, 1); 3364 hwp_mode_bdw = id->driver_data; 3365 intel_pstate.attr = hwp_cpufreq_attrs; 3366 intel_cpufreq.attr = hwp_cpufreq_attrs; 3367 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3368 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3369 if (!default_driver) 3370 default_driver = &intel_pstate; 3371 3372 if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) 3373 intel_pstate_cppc_set_cpu_scaling(); 3374 3375 goto hwp_cpu_matched; 3376 } 3377 pr_info("HWP not enabled\n"); 3378 } else { 3379 if (no_load) 3380 return -ENODEV; 3381 3382 id = x86_match_cpu(intel_pstate_cpu_ids); 3383 if (!id) { 3384 pr_info("CPU model not supported\n"); 3385 return -ENODEV; 3386 } 3387 3388 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3389 } 3390 3391 if (intel_pstate_msrs_not_valid()) { 3392 pr_info("Invalid MSRs\n"); 3393 return -ENODEV; 3394 } 3395 /* Without HWP start in the passive mode. */ 3396 if (!default_driver) 3397 default_driver = &intel_cpufreq; 3398 3399 hwp_cpu_matched: 3400 /* 3401 * The Intel pstate driver will be ignored if the platform 3402 * firmware has its own power management modes. 3403 */ 3404 if (intel_pstate_platform_pwr_mgmt_exists()) { 3405 pr_info("P-states controlled by the platform\n"); 3406 return -ENODEV; 3407 } 3408 3409 if (!hwp_active && hwp_only) 3410 return -ENOTSUPP; 3411 3412 pr_info("Intel P-state driver initializing\n"); 3413 3414 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3415 if (!_all_cpu_data) 3416 return -ENOMEM; 3417 3418 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3419 3420 intel_pstate_request_control_from_smm(); 3421 3422 intel_pstate_sysfs_expose_params(); 3423 3424 mutex_lock(&intel_pstate_driver_lock); 3425 rc = intel_pstate_register_driver(default_driver); 3426 mutex_unlock(&intel_pstate_driver_lock); 3427 if (rc) { 3428 intel_pstate_sysfs_remove(); 3429 return rc; 3430 } 3431 3432 if (hwp_active) { 3433 const struct x86_cpu_id *id; 3434 3435 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3436 if (id) { 3437 set_power_ctl_ee_state(false); 3438 pr_info("Disabling energy efficiency optimization\n"); 3439 } 3440 3441 pr_info("HWP enabled\n"); 3442 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3443 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3444 } 3445 3446 return 0; 3447 } 3448 device_initcall(intel_pstate_init); 3449 3450 static int __init intel_pstate_setup(char *str) 3451 { 3452 if (!str) 3453 return -EINVAL; 3454 3455 if (!strcmp(str, "disable")) 3456 no_load = 1; 3457 else if (!strcmp(str, "active")) 3458 default_driver = &intel_pstate; 3459 else if (!strcmp(str, "passive")) 3460 default_driver = &intel_cpufreq; 3461 3462 if (!strcmp(str, "no_hwp")) 3463 no_hwp = 1; 3464 3465 if (!strcmp(str, "force")) 3466 force_load = 1; 3467 if (!strcmp(str, "hwp_only")) 3468 hwp_only = 1; 3469 if (!strcmp(str, "per_cpu_perf_limits")) 3470 per_cpu_limits = true; 3471 3472 #ifdef CONFIG_ACPI 3473 if (!strcmp(str, "support_acpi_ppc")) 3474 acpi_ppc = true; 3475 #endif 3476 3477 return 0; 3478 } 3479 early_param("intel_pstate", intel_pstate_setup); 3480 3481 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3482 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3483 MODULE_LICENSE("GPL"); 3484