1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/cpu.h> 31 #include <asm/div64.h> 32 #include <asm/msr.h> 33 #include <asm/cpu_device_id.h> 34 #include <asm/cpufeature.h> 35 #include <asm/intel-family.h> 36 #include "../drivers/thermal/intel/thermal_interrupt.h" 37 38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 39 40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000 42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 43 44 #ifdef CONFIG_ACPI 45 #include <acpi/processor.h> 46 #include <acpi/cppc_acpi.h> 47 #endif 48 49 #define FRAC_BITS 8 50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 51 #define fp_toint(X) ((X) >> FRAC_BITS) 52 53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 54 55 #define EXT_BITS 6 56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 59 60 static inline int32_t mul_fp(int32_t x, int32_t y) 61 { 62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 63 } 64 65 static inline int32_t div_fp(s64 x, s64 y) 66 { 67 return div64_s64((int64_t)x << FRAC_BITS, y); 68 } 69 70 static inline int ceiling_fp(int32_t x) 71 { 72 int mask, ret; 73 74 ret = fp_toint(x); 75 mask = (1 << FRAC_BITS) - 1; 76 if (x & mask) 77 ret += 1; 78 return ret; 79 } 80 81 static inline u64 mul_ext_fp(u64 x, u64 y) 82 { 83 return (x * y) >> EXT_FRAC_BITS; 84 } 85 86 static inline u64 div_ext_fp(u64 x, u64 y) 87 { 88 return div64_u64(x << EXT_FRAC_BITS, y); 89 } 90 91 /** 92 * struct sample - Store performance sample 93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 94 * performance during last sample period 95 * @busy_scaled: Scaled busy value which is used to calculate next 96 * P state. This can be different than core_avg_perf 97 * to account for cpu idle period 98 * @aperf: Difference of actual performance frequency clock count 99 * read from APERF MSR between last and current sample 100 * @mperf: Difference of maximum performance frequency clock count 101 * read from MPERF MSR between last and current sample 102 * @tsc: Difference of time stamp counter between last and 103 * current sample 104 * @time: Current time from scheduler 105 * 106 * This structure is used in the cpudata structure to store performance sample 107 * data for choosing next P State. 108 */ 109 struct sample { 110 int32_t core_avg_perf; 111 int32_t busy_scaled; 112 u64 aperf; 113 u64 mperf; 114 u64 tsc; 115 u64 time; 116 }; 117 118 /** 119 * struct pstate_data - Store P state data 120 * @current_pstate: Current requested P state 121 * @min_pstate: Min P state possible for this platform 122 * @max_pstate: Max P state possible for this platform 123 * @max_pstate_physical:This is physical Max P state for a processor 124 * This can be higher than the max_pstate which can 125 * be limited by platform thermal design power limits 126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor 127 * @scaling: Scaling factor between performance and frequency 128 * @turbo_pstate: Max Turbo P state possible for this platform 129 * @min_freq: @min_pstate frequency in cpufreq units 130 * @max_freq: @max_pstate frequency in cpufreq units 131 * @turbo_freq: @turbo_pstate frequency in cpufreq units 132 * 133 * Stores the per cpu model P state limits and current P state. 134 */ 135 struct pstate_data { 136 int current_pstate; 137 int min_pstate; 138 int max_pstate; 139 int max_pstate_physical; 140 int perf_ctl_scaling; 141 int scaling; 142 int turbo_pstate; 143 unsigned int min_freq; 144 unsigned int max_freq; 145 unsigned int turbo_freq; 146 }; 147 148 /** 149 * struct vid_data - Stores voltage information data 150 * @min: VID data for this platform corresponding to 151 * the lowest P state 152 * @max: VID data corresponding to the highest P State. 153 * @turbo: VID data for turbo P state 154 * @ratio: Ratio of (vid max - vid min) / 155 * (max P state - Min P State) 156 * 157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 158 * This data is used in Atom platforms, where in addition to target P state, 159 * the voltage data needs to be specified to select next P State. 160 */ 161 struct vid_data { 162 int min; 163 int max; 164 int turbo; 165 int32_t ratio; 166 }; 167 168 /** 169 * struct global_params - Global parameters, mostly tunable via sysfs. 170 * @no_turbo: Whether or not to use turbo P-states. 171 * @turbo_disabled: Whether or not turbo P-states are available at all, 172 * based on the MSR_IA32_MISC_ENABLE value and whether or 173 * not the maximum reported turbo P-state is different from 174 * the maximum reported non-turbo one. 175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 177 * P-state capacity. 178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 179 * P-state capacity. 180 */ 181 struct global_params { 182 bool no_turbo; 183 bool turbo_disabled; 184 bool turbo_disabled_mf; 185 int max_perf_pct; 186 int min_perf_pct; 187 }; 188 189 /** 190 * struct cpudata - Per CPU instance data storage 191 * @cpu: CPU number for this instance data 192 * @policy: CPUFreq policy value 193 * @update_util: CPUFreq utility callback information 194 * @update_util_set: CPUFreq utility callback is set 195 * @iowait_boost: iowait-related boost fraction 196 * @last_update: Time of the last update. 197 * @pstate: Stores P state limits for this CPU 198 * @vid: Stores VID limits for this CPU 199 * @last_sample_time: Last Sample time 200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference 201 * @prev_aperf: Last APERF value read from APERF MSR 202 * @prev_mperf: Last MPERF value read from MPERF MSR 203 * @prev_tsc: Last timestamp counter (TSC) value 204 * @prev_cummulative_iowait: IO Wait time difference from last and 205 * current sample 206 * @sample: Storage for storing last Sample data 207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 209 * @acpi_perf_data: Stores ACPI perf information read from _PSS 210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 211 * @epp_powersave: Last saved HWP energy performance preference 212 * (EPP) or energy performance bias (EPB), 213 * when policy switched to performance 214 * @epp_policy: Last saved policy used to set EPP/EPB 215 * @epp_default: Power on default HWP energy performance 216 * preference/bias 217 * @epp_cached Cached HWP energy-performance preference value 218 * @hwp_req_cached: Cached value of the last HWP Request MSR 219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 220 * @last_io_update: Last time when IO wake flag was set 221 * @sched_flags: Store scheduler flags for possible cross CPU update 222 * @hwp_boost_min: Last HWP boosted min performance 223 * @suspended: Whether or not the driver has been suspended. 224 * @hwp_notify_work: workqueue for HWP notifications. 225 * 226 * This structure stores per CPU instance data for all CPUs. 227 */ 228 struct cpudata { 229 int cpu; 230 231 unsigned int policy; 232 struct update_util_data update_util; 233 bool update_util_set; 234 235 struct pstate_data pstate; 236 struct vid_data vid; 237 238 u64 last_update; 239 u64 last_sample_time; 240 u64 aperf_mperf_shift; 241 u64 prev_aperf; 242 u64 prev_mperf; 243 u64 prev_tsc; 244 u64 prev_cummulative_iowait; 245 struct sample sample; 246 int32_t min_perf_ratio; 247 int32_t max_perf_ratio; 248 #ifdef CONFIG_ACPI 249 struct acpi_processor_performance acpi_perf_data; 250 bool valid_pss_table; 251 #endif 252 unsigned int iowait_boost; 253 s16 epp_powersave; 254 s16 epp_policy; 255 s16 epp_default; 256 s16 epp_cached; 257 u64 hwp_req_cached; 258 u64 hwp_cap_cached; 259 u64 last_io_update; 260 unsigned int sched_flags; 261 u32 hwp_boost_min; 262 bool suspended; 263 struct delayed_work hwp_notify_work; 264 }; 265 266 static struct cpudata **all_cpu_data; 267 268 /** 269 * struct pstate_funcs - Per CPU model specific callbacks 270 * @get_max: Callback to get maximum non turbo effective P state 271 * @get_max_physical: Callback to get maximum non turbo physical P state 272 * @get_min: Callback to get minimum P state 273 * @get_turbo: Callback to get turbo P state 274 * @get_scaling: Callback to get frequency scaling factor 275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu 276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference 277 * @get_val: Callback to convert P state to actual MSR write value 278 * @get_vid: Callback to get VID data for Atom platforms 279 * 280 * Core and Atom CPU models have different way to get P State limits. This 281 * structure is used to store those callbacks. 282 */ 283 struct pstate_funcs { 284 int (*get_max)(int cpu); 285 int (*get_max_physical)(int cpu); 286 int (*get_min)(int cpu); 287 int (*get_turbo)(int cpu); 288 int (*get_scaling)(void); 289 int (*get_cpu_scaling)(int cpu); 290 int (*get_aperf_mperf_shift)(void); 291 u64 (*get_val)(struct cpudata*, int pstate); 292 void (*get_vid)(struct cpudata *); 293 }; 294 295 static struct pstate_funcs pstate_funcs __read_mostly; 296 297 static int hwp_active __read_mostly; 298 static int hwp_mode_bdw __read_mostly; 299 static bool per_cpu_limits __read_mostly; 300 static bool hwp_boost __read_mostly; 301 static bool hwp_forced __read_mostly; 302 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 304 305 #ifdef CONFIG_ACPI 306 static bool acpi_ppc; 307 #endif 308 309 static struct global_params global; 310 311 static DEFINE_MUTEX(intel_pstate_driver_lock); 312 static DEFINE_MUTEX(intel_pstate_limits_lock); 313 314 #ifdef CONFIG_ACPI 315 316 static bool intel_pstate_acpi_pm_profile_server(void) 317 { 318 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 319 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 320 return true; 321 322 return false; 323 } 324 325 static bool intel_pstate_get_ppc_enable_status(void) 326 { 327 if (intel_pstate_acpi_pm_profile_server()) 328 return true; 329 330 return acpi_ppc; 331 } 332 333 #ifdef CONFIG_ACPI_CPPC_LIB 334 335 /* The work item is needed to avoid CPU hotplug locking issues */ 336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 337 { 338 sched_set_itmt_support(); 339 } 340 341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 342 343 #define CPPC_MAX_PERF U8_MAX 344 345 static void intel_pstate_set_itmt_prio(int cpu) 346 { 347 struct cppc_perf_caps cppc_perf; 348 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 349 int ret; 350 351 ret = cppc_get_perf_caps(cpu, &cppc_perf); 352 if (ret) 353 return; 354 355 /* 356 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. 357 * In this case we can't use CPPC.highest_perf to enable ITMT. 358 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. 359 */ 360 if (cppc_perf.highest_perf == CPPC_MAX_PERF) 361 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); 362 363 /* 364 * The priorities can be set regardless of whether or not 365 * sched_set_itmt_support(true) has been called and it is valid to 366 * update them at any time after it has been called. 367 */ 368 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 369 370 if (max_highest_perf <= min_highest_perf) { 371 if (cppc_perf.highest_perf > max_highest_perf) 372 max_highest_perf = cppc_perf.highest_perf; 373 374 if (cppc_perf.highest_perf < min_highest_perf) 375 min_highest_perf = cppc_perf.highest_perf; 376 377 if (max_highest_perf > min_highest_perf) { 378 /* 379 * This code can be run during CPU online under the 380 * CPU hotplug locks, so sched_set_itmt_support() 381 * cannot be called from here. Queue up a work item 382 * to invoke it. 383 */ 384 schedule_work(&sched_itmt_work); 385 } 386 } 387 } 388 389 static int intel_pstate_get_cppc_guaranteed(int cpu) 390 { 391 struct cppc_perf_caps cppc_perf; 392 int ret; 393 394 ret = cppc_get_perf_caps(cpu, &cppc_perf); 395 if (ret) 396 return ret; 397 398 if (cppc_perf.guaranteed_perf) 399 return cppc_perf.guaranteed_perf; 400 401 return cppc_perf.nominal_perf; 402 } 403 #else /* CONFIG_ACPI_CPPC_LIB */ 404 static inline void intel_pstate_set_itmt_prio(int cpu) 405 { 406 } 407 #endif /* CONFIG_ACPI_CPPC_LIB */ 408 409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 410 { 411 struct cpudata *cpu; 412 int ret; 413 int i; 414 415 if (hwp_active) { 416 intel_pstate_set_itmt_prio(policy->cpu); 417 return; 418 } 419 420 if (!intel_pstate_get_ppc_enable_status()) 421 return; 422 423 cpu = all_cpu_data[policy->cpu]; 424 425 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 426 policy->cpu); 427 if (ret) 428 return; 429 430 /* 431 * Check if the control value in _PSS is for PERF_CTL MSR, which should 432 * guarantee that the states returned by it map to the states in our 433 * list directly. 434 */ 435 if (cpu->acpi_perf_data.control_register.space_id != 436 ACPI_ADR_SPACE_FIXED_HARDWARE) 437 goto err; 438 439 /* 440 * If there is only one entry _PSS, simply ignore _PSS and continue as 441 * usual without taking _PSS into account 442 */ 443 if (cpu->acpi_perf_data.state_count < 2) 444 goto err; 445 446 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 447 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 448 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 449 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 450 (u32) cpu->acpi_perf_data.states[i].core_frequency, 451 (u32) cpu->acpi_perf_data.states[i].power, 452 (u32) cpu->acpi_perf_data.states[i].control); 453 } 454 455 cpu->valid_pss_table = true; 456 pr_debug("_PPC limits will be enforced\n"); 457 458 return; 459 460 err: 461 cpu->valid_pss_table = false; 462 acpi_processor_unregister_performance(policy->cpu); 463 } 464 465 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 466 { 467 struct cpudata *cpu; 468 469 cpu = all_cpu_data[policy->cpu]; 470 if (!cpu->valid_pss_table) 471 return; 472 473 acpi_processor_unregister_performance(policy->cpu); 474 } 475 #else /* CONFIG_ACPI */ 476 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 477 { 478 } 479 480 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 481 { 482 } 483 484 static inline bool intel_pstate_acpi_pm_profile_server(void) 485 { 486 return false; 487 } 488 #endif /* CONFIG_ACPI */ 489 490 #ifndef CONFIG_ACPI_CPPC_LIB 491 static inline int intel_pstate_get_cppc_guaranteed(int cpu) 492 { 493 return -ENOTSUPP; 494 } 495 #endif /* CONFIG_ACPI_CPPC_LIB */ 496 497 /** 498 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels. 499 * @cpu: Target CPU. 500 * 501 * On hybrid processors, HWP may expose more performance levels than there are 502 * P-states accessible through the PERF_CTL interface. If that happens, the 503 * scaling factor between HWP performance levels and CPU frequency will be less 504 * than the scaling factor between P-state values and CPU frequency. 505 * 506 * In that case, adjust the CPU parameters used in computations accordingly. 507 */ 508 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu) 509 { 510 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical; 511 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 512 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu); 513 int scaling = cpu->pstate.scaling; 514 515 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 516 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 517 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 518 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 519 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 520 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 521 522 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 523 perf_ctl_scaling); 524 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling, 525 perf_ctl_scaling); 526 527 cpu->pstate.max_pstate_physical = 528 DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling, 529 scaling); 530 531 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 532 /* 533 * Cast the min P-state value retrieved via pstate_funcs.get_min() to 534 * the effective range of HWP performance levels. 535 */ 536 cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling); 537 } 538 539 static inline void update_turbo_state(void) 540 { 541 u64 misc_en; 542 struct cpudata *cpu; 543 544 cpu = all_cpu_data[0]; 545 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 546 global.turbo_disabled = 547 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 548 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 549 } 550 551 static int min_perf_pct_min(void) 552 { 553 struct cpudata *cpu = all_cpu_data[0]; 554 int turbo_pstate = cpu->pstate.turbo_pstate; 555 556 return turbo_pstate ? 557 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 558 } 559 560 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 561 { 562 u64 epb; 563 int ret; 564 565 if (!boot_cpu_has(X86_FEATURE_EPB)) 566 return -ENXIO; 567 568 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 569 if (ret) 570 return (s16)ret; 571 572 return (s16)(epb & 0x0f); 573 } 574 575 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 576 { 577 s16 epp; 578 579 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 580 /* 581 * When hwp_req_data is 0, means that caller didn't read 582 * MSR_HWP_REQUEST, so need to read and get EPP. 583 */ 584 if (!hwp_req_data) { 585 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 586 &hwp_req_data); 587 if (epp) 588 return epp; 589 } 590 epp = (hwp_req_data >> 24) & 0xff; 591 } else { 592 /* When there is no EPP present, HWP uses EPB settings */ 593 epp = intel_pstate_get_epb(cpu_data); 594 } 595 596 return epp; 597 } 598 599 static int intel_pstate_set_epb(int cpu, s16 pref) 600 { 601 u64 epb; 602 int ret; 603 604 if (!boot_cpu_has(X86_FEATURE_EPB)) 605 return -ENXIO; 606 607 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 608 if (ret) 609 return ret; 610 611 epb = (epb & ~0x0f) | pref; 612 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 613 614 return 0; 615 } 616 617 /* 618 * EPP/EPB display strings corresponding to EPP index in the 619 * energy_perf_strings[] 620 * index String 621 *------------------------------------- 622 * 0 default 623 * 1 performance 624 * 2 balance_performance 625 * 3 balance_power 626 * 4 power 627 */ 628 629 enum energy_perf_value_index { 630 EPP_INDEX_DEFAULT = 0, 631 EPP_INDEX_PERFORMANCE, 632 EPP_INDEX_BALANCE_PERFORMANCE, 633 EPP_INDEX_BALANCE_POWERSAVE, 634 EPP_INDEX_POWERSAVE, 635 }; 636 637 static const char * const energy_perf_strings[] = { 638 [EPP_INDEX_DEFAULT] = "default", 639 [EPP_INDEX_PERFORMANCE] = "performance", 640 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 641 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 642 [EPP_INDEX_POWERSAVE] = "power", 643 NULL 644 }; 645 static unsigned int epp_values[] = { 646 [EPP_INDEX_DEFAULT] = 0, /* Unused index */ 647 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE, 648 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE, 649 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE, 650 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE, 651 }; 652 653 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp) 654 { 655 s16 epp; 656 int index = -EINVAL; 657 658 *raw_epp = 0; 659 epp = intel_pstate_get_epp(cpu_data, 0); 660 if (epp < 0) 661 return epp; 662 663 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 664 if (epp == epp_values[EPP_INDEX_PERFORMANCE]) 665 return EPP_INDEX_PERFORMANCE; 666 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE]) 667 return EPP_INDEX_BALANCE_PERFORMANCE; 668 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE]) 669 return EPP_INDEX_BALANCE_POWERSAVE; 670 if (epp == epp_values[EPP_INDEX_POWERSAVE]) 671 return EPP_INDEX_POWERSAVE; 672 *raw_epp = epp; 673 return 0; 674 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 675 /* 676 * Range: 677 * 0x00-0x03 : Performance 678 * 0x04-0x07 : Balance performance 679 * 0x08-0x0B : Balance power 680 * 0x0C-0x0F : Power 681 * The EPB is a 4 bit value, but our ranges restrict the 682 * value which can be set. Here only using top two bits 683 * effectively. 684 */ 685 index = (epp >> 2) + 1; 686 } 687 688 return index; 689 } 690 691 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) 692 { 693 int ret; 694 695 /* 696 * Use the cached HWP Request MSR value, because in the active mode the 697 * register itself may be updated by intel_pstate_hwp_boost_up() or 698 * intel_pstate_hwp_boost_down() at any time. 699 */ 700 u64 value = READ_ONCE(cpu->hwp_req_cached); 701 702 value &= ~GENMASK_ULL(31, 24); 703 value |= (u64)epp << 24; 704 /* 705 * The only other updater of hwp_req_cached in the active mode, 706 * intel_pstate_hwp_set(), is called under the same lock as this 707 * function, so it cannot run in parallel with the update below. 708 */ 709 WRITE_ONCE(cpu->hwp_req_cached, value); 710 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 711 if (!ret) 712 cpu->epp_cached = epp; 713 714 return ret; 715 } 716 717 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 718 int pref_index, bool use_raw, 719 u32 raw_epp) 720 { 721 int epp = -EINVAL; 722 int ret; 723 724 if (!pref_index) 725 epp = cpu_data->epp_default; 726 727 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 728 if (use_raw) 729 epp = raw_epp; 730 else if (epp == -EINVAL) 731 epp = epp_values[pref_index]; 732 733 /* 734 * To avoid confusion, refuse to set EPP to any values different 735 * from 0 (performance) if the current policy is "performance", 736 * because those values would be overridden. 737 */ 738 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 739 return -EBUSY; 740 741 ret = intel_pstate_set_epp(cpu_data, epp); 742 } else { 743 if (epp == -EINVAL) 744 epp = (pref_index - 1) << 2; 745 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 746 } 747 748 return ret; 749 } 750 751 static ssize_t show_energy_performance_available_preferences( 752 struct cpufreq_policy *policy, char *buf) 753 { 754 int i = 0; 755 int ret = 0; 756 757 while (energy_perf_strings[i] != NULL) 758 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 759 760 ret += sprintf(&buf[ret], "\n"); 761 762 return ret; 763 } 764 765 cpufreq_freq_attr_ro(energy_performance_available_preferences); 766 767 static struct cpufreq_driver intel_pstate; 768 769 static ssize_t store_energy_performance_preference( 770 struct cpufreq_policy *policy, const char *buf, size_t count) 771 { 772 struct cpudata *cpu = all_cpu_data[policy->cpu]; 773 char str_preference[21]; 774 bool raw = false; 775 ssize_t ret; 776 u32 epp = 0; 777 778 ret = sscanf(buf, "%20s", str_preference); 779 if (ret != 1) 780 return -EINVAL; 781 782 ret = match_string(energy_perf_strings, -1, str_preference); 783 if (ret < 0) { 784 if (!boot_cpu_has(X86_FEATURE_HWP_EPP)) 785 return ret; 786 787 ret = kstrtouint(buf, 10, &epp); 788 if (ret) 789 return ret; 790 791 if (epp > 255) 792 return -EINVAL; 793 794 raw = true; 795 } 796 797 /* 798 * This function runs with the policy R/W semaphore held, which 799 * guarantees that the driver pointer will not change while it is 800 * running. 801 */ 802 if (!intel_pstate_driver) 803 return -EAGAIN; 804 805 mutex_lock(&intel_pstate_limits_lock); 806 807 if (intel_pstate_driver == &intel_pstate) { 808 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp); 809 } else { 810 /* 811 * In the passive mode the governor needs to be stopped on the 812 * target CPU before the EPP update and restarted after it, 813 * which is super-heavy-weight, so make sure it is worth doing 814 * upfront. 815 */ 816 if (!raw) 817 epp = ret ? epp_values[ret] : cpu->epp_default; 818 819 if (cpu->epp_cached != epp) { 820 int err; 821 822 cpufreq_stop_governor(policy); 823 ret = intel_pstate_set_epp(cpu, epp); 824 err = cpufreq_start_governor(policy); 825 if (!ret) 826 ret = err; 827 } else { 828 ret = 0; 829 } 830 } 831 832 mutex_unlock(&intel_pstate_limits_lock); 833 834 return ret ?: count; 835 } 836 837 static ssize_t show_energy_performance_preference( 838 struct cpufreq_policy *policy, char *buf) 839 { 840 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 841 int preference, raw_epp; 842 843 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp); 844 if (preference < 0) 845 return preference; 846 847 if (raw_epp) 848 return sprintf(buf, "%d\n", raw_epp); 849 else 850 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 851 } 852 853 cpufreq_freq_attr_rw(energy_performance_preference); 854 855 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 856 { 857 struct cpudata *cpu = all_cpu_data[policy->cpu]; 858 int ratio, freq; 859 860 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu); 861 if (ratio <= 0) { 862 u64 cap; 863 864 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 865 ratio = HWP_GUARANTEED_PERF(cap); 866 } 867 868 freq = ratio * cpu->pstate.scaling; 869 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling) 870 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling); 871 872 return sprintf(buf, "%d\n", freq); 873 } 874 875 cpufreq_freq_attr_ro(base_frequency); 876 877 static struct freq_attr *hwp_cpufreq_attrs[] = { 878 &energy_performance_preference, 879 &energy_performance_available_preferences, 880 &base_frequency, 881 NULL, 882 }; 883 884 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu) 885 { 886 u64 cap; 887 888 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 889 WRITE_ONCE(cpu->hwp_cap_cached, cap); 890 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 891 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); 892 } 893 894 static void intel_pstate_get_hwp_cap(struct cpudata *cpu) 895 { 896 int scaling = cpu->pstate.scaling; 897 898 __intel_pstate_get_hwp_cap(cpu); 899 900 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling; 901 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling; 902 if (scaling != cpu->pstate.perf_ctl_scaling) { 903 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 904 905 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq, 906 perf_ctl_scaling); 907 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq, 908 perf_ctl_scaling); 909 } 910 } 911 912 static void intel_pstate_hwp_set(unsigned int cpu) 913 { 914 struct cpudata *cpu_data = all_cpu_data[cpu]; 915 int max, min; 916 u64 value; 917 s16 epp; 918 919 max = cpu_data->max_perf_ratio; 920 min = cpu_data->min_perf_ratio; 921 922 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 923 min = max; 924 925 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 926 927 value &= ~HWP_MIN_PERF(~0L); 928 value |= HWP_MIN_PERF(min); 929 930 value &= ~HWP_MAX_PERF(~0L); 931 value |= HWP_MAX_PERF(max); 932 933 if (cpu_data->epp_policy == cpu_data->policy) 934 goto skip_epp; 935 936 cpu_data->epp_policy = cpu_data->policy; 937 938 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 939 epp = intel_pstate_get_epp(cpu_data, value); 940 cpu_data->epp_powersave = epp; 941 /* If EPP read was failed, then don't try to write */ 942 if (epp < 0) 943 goto skip_epp; 944 945 epp = 0; 946 } else { 947 /* skip setting EPP, when saved value is invalid */ 948 if (cpu_data->epp_powersave < 0) 949 goto skip_epp; 950 951 /* 952 * No need to restore EPP when it is not zero. This 953 * means: 954 * - Policy is not changed 955 * - user has manually changed 956 * - Error reading EPB 957 */ 958 epp = intel_pstate_get_epp(cpu_data, value); 959 if (epp) 960 goto skip_epp; 961 962 epp = cpu_data->epp_powersave; 963 } 964 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 965 value &= ~GENMASK_ULL(31, 24); 966 value |= (u64)epp << 24; 967 } else { 968 intel_pstate_set_epb(cpu, epp); 969 } 970 skip_epp: 971 WRITE_ONCE(cpu_data->hwp_req_cached, value); 972 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 973 } 974 975 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); 976 977 static void intel_pstate_hwp_offline(struct cpudata *cpu) 978 { 979 u64 value = READ_ONCE(cpu->hwp_req_cached); 980 int min_perf; 981 982 intel_pstate_disable_hwp_interrupt(cpu); 983 984 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 985 /* 986 * In case the EPP has been set to "performance" by the 987 * active mode "performance" scaling algorithm, replace that 988 * temporary value with the cached EPP one. 989 */ 990 value &= ~GENMASK_ULL(31, 24); 991 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached); 992 /* 993 * However, make sure that EPP will be set to "performance" when 994 * the CPU is brought back online again and the "performance" 995 * scaling algorithm is still in effect. 996 */ 997 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN; 998 } 999 1000 /* 1001 * Clear the desired perf field in the cached HWP request value to 1002 * prevent nonzero desired values from being leaked into the active 1003 * mode. 1004 */ 1005 value &= ~HWP_DESIRED_PERF(~0L); 1006 WRITE_ONCE(cpu->hwp_req_cached, value); 1007 1008 value &= ~GENMASK_ULL(31, 0); 1009 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached)); 1010 1011 /* Set hwp_max = hwp_min */ 1012 value |= HWP_MAX_PERF(min_perf); 1013 value |= HWP_MIN_PERF(min_perf); 1014 1015 /* Set EPP to min */ 1016 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1017 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1018 1019 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1020 } 1021 1022 #define POWER_CTL_EE_ENABLE 1 1023 #define POWER_CTL_EE_DISABLE 2 1024 1025 static int power_ctl_ee_state; 1026 1027 static void set_power_ctl_ee_state(bool input) 1028 { 1029 u64 power_ctl; 1030 1031 mutex_lock(&intel_pstate_driver_lock); 1032 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1033 if (input) { 1034 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1035 power_ctl_ee_state = POWER_CTL_EE_ENABLE; 1036 } else { 1037 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1038 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1039 } 1040 wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1041 mutex_unlock(&intel_pstate_driver_lock); 1042 } 1043 1044 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 1045 1046 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1047 { 1048 intel_pstate_hwp_enable(cpu); 1049 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1050 } 1051 1052 static int intel_pstate_suspend(struct cpufreq_policy *policy) 1053 { 1054 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1055 1056 pr_debug("CPU %d suspending\n", cpu->cpu); 1057 1058 cpu->suspended = true; 1059 1060 /* disable HWP interrupt and cancel any pending work */ 1061 intel_pstate_disable_hwp_interrupt(cpu); 1062 1063 return 0; 1064 } 1065 1066 static int intel_pstate_resume(struct cpufreq_policy *policy) 1067 { 1068 struct cpudata *cpu = all_cpu_data[policy->cpu]; 1069 1070 pr_debug("CPU %d resuming\n", cpu->cpu); 1071 1072 /* Only restore if the system default is changed */ 1073 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE) 1074 set_power_ctl_ee_state(true); 1075 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE) 1076 set_power_ctl_ee_state(false); 1077 1078 if (cpu->suspended && hwp_active) { 1079 mutex_lock(&intel_pstate_limits_lock); 1080 1081 /* Re-enable HWP, because "online" has not done that. */ 1082 intel_pstate_hwp_reenable(cpu); 1083 1084 mutex_unlock(&intel_pstate_limits_lock); 1085 } 1086 1087 cpu->suspended = false; 1088 1089 return 0; 1090 } 1091 1092 static void intel_pstate_update_policies(void) 1093 { 1094 int cpu; 1095 1096 for_each_possible_cpu(cpu) 1097 cpufreq_update_policy(cpu); 1098 } 1099 1100 static void __intel_pstate_update_max_freq(struct cpudata *cpudata, 1101 struct cpufreq_policy *policy) 1102 { 1103 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 1104 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 1105 refresh_frequency_limits(policy); 1106 } 1107 1108 static void intel_pstate_update_max_freq(unsigned int cpu) 1109 { 1110 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 1111 1112 if (!policy) 1113 return; 1114 1115 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy); 1116 1117 cpufreq_cpu_release(policy); 1118 } 1119 1120 static void intel_pstate_update_limits(unsigned int cpu) 1121 { 1122 mutex_lock(&intel_pstate_driver_lock); 1123 1124 update_turbo_state(); 1125 /* 1126 * If turbo has been turned on or off globally, policy limits for 1127 * all CPUs need to be updated to reflect that. 1128 */ 1129 if (global.turbo_disabled_mf != global.turbo_disabled) { 1130 global.turbo_disabled_mf = global.turbo_disabled; 1131 arch_set_max_freq_ratio(global.turbo_disabled); 1132 for_each_possible_cpu(cpu) 1133 intel_pstate_update_max_freq(cpu); 1134 } else { 1135 cpufreq_update_policy(cpu); 1136 } 1137 1138 mutex_unlock(&intel_pstate_driver_lock); 1139 } 1140 1141 /************************** sysfs begin ************************/ 1142 #define show_one(file_name, object) \ 1143 static ssize_t show_##file_name \ 1144 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 1145 { \ 1146 return sprintf(buf, "%u\n", global.object); \ 1147 } 1148 1149 static ssize_t intel_pstate_show_status(char *buf); 1150 static int intel_pstate_update_status(const char *buf, size_t size); 1151 1152 static ssize_t show_status(struct kobject *kobj, 1153 struct kobj_attribute *attr, char *buf) 1154 { 1155 ssize_t ret; 1156 1157 mutex_lock(&intel_pstate_driver_lock); 1158 ret = intel_pstate_show_status(buf); 1159 mutex_unlock(&intel_pstate_driver_lock); 1160 1161 return ret; 1162 } 1163 1164 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 1165 const char *buf, size_t count) 1166 { 1167 char *p = memchr(buf, '\n', count); 1168 int ret; 1169 1170 mutex_lock(&intel_pstate_driver_lock); 1171 ret = intel_pstate_update_status(buf, p ? p - buf : count); 1172 mutex_unlock(&intel_pstate_driver_lock); 1173 1174 return ret < 0 ? ret : count; 1175 } 1176 1177 static ssize_t show_turbo_pct(struct kobject *kobj, 1178 struct kobj_attribute *attr, char *buf) 1179 { 1180 struct cpudata *cpu; 1181 int total, no_turbo, turbo_pct; 1182 uint32_t turbo_fp; 1183 1184 mutex_lock(&intel_pstate_driver_lock); 1185 1186 if (!intel_pstate_driver) { 1187 mutex_unlock(&intel_pstate_driver_lock); 1188 return -EAGAIN; 1189 } 1190 1191 cpu = all_cpu_data[0]; 1192 1193 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1194 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1195 turbo_fp = div_fp(no_turbo, total); 1196 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1197 1198 mutex_unlock(&intel_pstate_driver_lock); 1199 1200 return sprintf(buf, "%u\n", turbo_pct); 1201 } 1202 1203 static ssize_t show_num_pstates(struct kobject *kobj, 1204 struct kobj_attribute *attr, char *buf) 1205 { 1206 struct cpudata *cpu; 1207 int total; 1208 1209 mutex_lock(&intel_pstate_driver_lock); 1210 1211 if (!intel_pstate_driver) { 1212 mutex_unlock(&intel_pstate_driver_lock); 1213 return -EAGAIN; 1214 } 1215 1216 cpu = all_cpu_data[0]; 1217 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1218 1219 mutex_unlock(&intel_pstate_driver_lock); 1220 1221 return sprintf(buf, "%u\n", total); 1222 } 1223 1224 static ssize_t show_no_turbo(struct kobject *kobj, 1225 struct kobj_attribute *attr, char *buf) 1226 { 1227 ssize_t ret; 1228 1229 mutex_lock(&intel_pstate_driver_lock); 1230 1231 if (!intel_pstate_driver) { 1232 mutex_unlock(&intel_pstate_driver_lock); 1233 return -EAGAIN; 1234 } 1235 1236 update_turbo_state(); 1237 if (global.turbo_disabled) 1238 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1239 else 1240 ret = sprintf(buf, "%u\n", global.no_turbo); 1241 1242 mutex_unlock(&intel_pstate_driver_lock); 1243 1244 return ret; 1245 } 1246 1247 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1248 const char *buf, size_t count) 1249 { 1250 unsigned int input; 1251 int ret; 1252 1253 ret = sscanf(buf, "%u", &input); 1254 if (ret != 1) 1255 return -EINVAL; 1256 1257 mutex_lock(&intel_pstate_driver_lock); 1258 1259 if (!intel_pstate_driver) { 1260 mutex_unlock(&intel_pstate_driver_lock); 1261 return -EAGAIN; 1262 } 1263 1264 mutex_lock(&intel_pstate_limits_lock); 1265 1266 update_turbo_state(); 1267 if (global.turbo_disabled) { 1268 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n"); 1269 mutex_unlock(&intel_pstate_limits_lock); 1270 mutex_unlock(&intel_pstate_driver_lock); 1271 return -EPERM; 1272 } 1273 1274 global.no_turbo = clamp_t(int, input, 0, 1); 1275 1276 if (global.no_turbo) { 1277 struct cpudata *cpu = all_cpu_data[0]; 1278 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1279 1280 /* Squash the global minimum into the permitted range. */ 1281 if (global.min_perf_pct > pct) 1282 global.min_perf_pct = pct; 1283 } 1284 1285 mutex_unlock(&intel_pstate_limits_lock); 1286 1287 intel_pstate_update_policies(); 1288 arch_set_max_freq_ratio(global.no_turbo); 1289 1290 mutex_unlock(&intel_pstate_driver_lock); 1291 1292 return count; 1293 } 1294 1295 static void update_qos_request(enum freq_qos_req_type type) 1296 { 1297 struct freq_qos_request *req; 1298 struct cpufreq_policy *policy; 1299 int i; 1300 1301 for_each_possible_cpu(i) { 1302 struct cpudata *cpu = all_cpu_data[i]; 1303 unsigned int freq, perf_pct; 1304 1305 policy = cpufreq_cpu_get(i); 1306 if (!policy) 1307 continue; 1308 1309 req = policy->driver_data; 1310 cpufreq_cpu_put(policy); 1311 1312 if (!req) 1313 continue; 1314 1315 if (hwp_active) 1316 intel_pstate_get_hwp_cap(cpu); 1317 1318 if (type == FREQ_QOS_MIN) { 1319 perf_pct = global.min_perf_pct; 1320 } else { 1321 req++; 1322 perf_pct = global.max_perf_pct; 1323 } 1324 1325 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100); 1326 1327 if (freq_qos_update_request(req, freq) < 0) 1328 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1329 } 1330 } 1331 1332 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1333 const char *buf, size_t count) 1334 { 1335 unsigned int input; 1336 int ret; 1337 1338 ret = sscanf(buf, "%u", &input); 1339 if (ret != 1) 1340 return -EINVAL; 1341 1342 mutex_lock(&intel_pstate_driver_lock); 1343 1344 if (!intel_pstate_driver) { 1345 mutex_unlock(&intel_pstate_driver_lock); 1346 return -EAGAIN; 1347 } 1348 1349 mutex_lock(&intel_pstate_limits_lock); 1350 1351 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1352 1353 mutex_unlock(&intel_pstate_limits_lock); 1354 1355 if (intel_pstate_driver == &intel_pstate) 1356 intel_pstate_update_policies(); 1357 else 1358 update_qos_request(FREQ_QOS_MAX); 1359 1360 mutex_unlock(&intel_pstate_driver_lock); 1361 1362 return count; 1363 } 1364 1365 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1366 const char *buf, size_t count) 1367 { 1368 unsigned int input; 1369 int ret; 1370 1371 ret = sscanf(buf, "%u", &input); 1372 if (ret != 1) 1373 return -EINVAL; 1374 1375 mutex_lock(&intel_pstate_driver_lock); 1376 1377 if (!intel_pstate_driver) { 1378 mutex_unlock(&intel_pstate_driver_lock); 1379 return -EAGAIN; 1380 } 1381 1382 mutex_lock(&intel_pstate_limits_lock); 1383 1384 global.min_perf_pct = clamp_t(int, input, 1385 min_perf_pct_min(), global.max_perf_pct); 1386 1387 mutex_unlock(&intel_pstate_limits_lock); 1388 1389 if (intel_pstate_driver == &intel_pstate) 1390 intel_pstate_update_policies(); 1391 else 1392 update_qos_request(FREQ_QOS_MIN); 1393 1394 mutex_unlock(&intel_pstate_driver_lock); 1395 1396 return count; 1397 } 1398 1399 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1400 struct kobj_attribute *attr, char *buf) 1401 { 1402 return sprintf(buf, "%u\n", hwp_boost); 1403 } 1404 1405 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1406 struct kobj_attribute *b, 1407 const char *buf, size_t count) 1408 { 1409 unsigned int input; 1410 int ret; 1411 1412 ret = kstrtouint(buf, 10, &input); 1413 if (ret) 1414 return ret; 1415 1416 mutex_lock(&intel_pstate_driver_lock); 1417 hwp_boost = !!input; 1418 intel_pstate_update_policies(); 1419 mutex_unlock(&intel_pstate_driver_lock); 1420 1421 return count; 1422 } 1423 1424 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr, 1425 char *buf) 1426 { 1427 u64 power_ctl; 1428 int enable; 1429 1430 rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1431 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1432 return sprintf(buf, "%d\n", !enable); 1433 } 1434 1435 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b, 1436 const char *buf, size_t count) 1437 { 1438 bool input; 1439 int ret; 1440 1441 ret = kstrtobool(buf, &input); 1442 if (ret) 1443 return ret; 1444 1445 set_power_ctl_ee_state(input); 1446 1447 return count; 1448 } 1449 1450 show_one(max_perf_pct, max_perf_pct); 1451 show_one(min_perf_pct, min_perf_pct); 1452 1453 define_one_global_rw(status); 1454 define_one_global_rw(no_turbo); 1455 define_one_global_rw(max_perf_pct); 1456 define_one_global_rw(min_perf_pct); 1457 define_one_global_ro(turbo_pct); 1458 define_one_global_ro(num_pstates); 1459 define_one_global_rw(hwp_dynamic_boost); 1460 define_one_global_rw(energy_efficiency); 1461 1462 static struct attribute *intel_pstate_attributes[] = { 1463 &status.attr, 1464 &no_turbo.attr, 1465 NULL 1466 }; 1467 1468 static const struct attribute_group intel_pstate_attr_group = { 1469 .attrs = intel_pstate_attributes, 1470 }; 1471 1472 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[]; 1473 1474 static struct kobject *intel_pstate_kobject; 1475 1476 static void __init intel_pstate_sysfs_expose_params(void) 1477 { 1478 struct device *dev_root = bus_get_dev_root(&cpu_subsys); 1479 int rc; 1480 1481 if (dev_root) { 1482 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj); 1483 put_device(dev_root); 1484 } 1485 if (WARN_ON(!intel_pstate_kobject)) 1486 return; 1487 1488 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1489 if (WARN_ON(rc)) 1490 return; 1491 1492 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1493 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr); 1494 WARN_ON(rc); 1495 1496 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr); 1497 WARN_ON(rc); 1498 } 1499 1500 /* 1501 * If per cpu limits are enforced there are no global limits, so 1502 * return without creating max/min_perf_pct attributes 1503 */ 1504 if (per_cpu_limits) 1505 return; 1506 1507 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1508 WARN_ON(rc); 1509 1510 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1511 WARN_ON(rc); 1512 1513 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) { 1514 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr); 1515 WARN_ON(rc); 1516 } 1517 } 1518 1519 static void __init intel_pstate_sysfs_remove(void) 1520 { 1521 if (!intel_pstate_kobject) 1522 return; 1523 1524 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group); 1525 1526 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 1527 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr); 1528 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr); 1529 } 1530 1531 if (!per_cpu_limits) { 1532 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr); 1533 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr); 1534 1535 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) 1536 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr); 1537 } 1538 1539 kobject_put(intel_pstate_kobject); 1540 } 1541 1542 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void) 1543 { 1544 int rc; 1545 1546 if (!hwp_active) 1547 return; 1548 1549 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1550 WARN_ON_ONCE(rc); 1551 } 1552 1553 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void) 1554 { 1555 if (!hwp_active) 1556 return; 1557 1558 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr); 1559 } 1560 1561 /************************** sysfs end ************************/ 1562 1563 static void intel_pstate_notify_work(struct work_struct *work) 1564 { 1565 struct cpudata *cpudata = 1566 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work); 1567 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); 1568 1569 if (policy) { 1570 intel_pstate_get_hwp_cap(cpudata); 1571 __intel_pstate_update_max_freq(cpudata, policy); 1572 1573 cpufreq_cpu_release(policy); 1574 } 1575 1576 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1577 } 1578 1579 static DEFINE_SPINLOCK(hwp_notify_lock); 1580 static cpumask_t hwp_intr_enable_mask; 1581 1582 void notify_hwp_interrupt(void) 1583 { 1584 unsigned int this_cpu = smp_processor_id(); 1585 struct cpudata *cpudata; 1586 unsigned long flags; 1587 u64 value; 1588 1589 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1590 return; 1591 1592 rdmsrl_safe(MSR_HWP_STATUS, &value); 1593 if (!(value & 0x01)) 1594 return; 1595 1596 spin_lock_irqsave(&hwp_notify_lock, flags); 1597 1598 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask)) 1599 goto ack_intr; 1600 1601 /* 1602 * Currently we never free all_cpu_data. And we can't reach here 1603 * without this allocated. But for safety for future changes, added 1604 * check. 1605 */ 1606 if (unlikely(!READ_ONCE(all_cpu_data))) 1607 goto ack_intr; 1608 1609 /* 1610 * The free is done during cleanup, when cpufreq registry is failed. 1611 * We wouldn't be here if it fails on init or switch status. But for 1612 * future changes, added check. 1613 */ 1614 cpudata = READ_ONCE(all_cpu_data[this_cpu]); 1615 if (unlikely(!cpudata)) 1616 goto ack_intr; 1617 1618 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10)); 1619 1620 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1621 1622 return; 1623 1624 ack_intr: 1625 wrmsrl_safe(MSR_HWP_STATUS, 0); 1626 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1627 } 1628 1629 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata) 1630 { 1631 unsigned long flags; 1632 1633 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1634 return; 1635 1636 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1637 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1638 1639 spin_lock_irqsave(&hwp_notify_lock, flags); 1640 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask)) 1641 cancel_delayed_work(&cpudata->hwp_notify_work); 1642 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1643 } 1644 1645 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata) 1646 { 1647 /* Enable HWP notification interrupt for guaranteed performance change */ 1648 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) { 1649 unsigned long flags; 1650 1651 spin_lock_irqsave(&hwp_notify_lock, flags); 1652 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work); 1653 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask); 1654 spin_unlock_irqrestore(&hwp_notify_lock, flags); 1655 1656 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1657 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01); 1658 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1659 } 1660 } 1661 1662 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata) 1663 { 1664 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1665 1666 /* 1667 * If this CPU gen doesn't call for change in balance_perf 1668 * EPP return. 1669 */ 1670 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE) 1671 return; 1672 1673 /* 1674 * If the EPP is set by firmware, which means that firmware enabled HWP 1675 * - Is equal or less than 0x80 (default balance_perf EPP) 1676 * - But less performance oriented than performance EPP 1677 * then use this as new balance_perf EPP. 1678 */ 1679 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE && 1680 cpudata->epp_default > HWP_EPP_PERFORMANCE) { 1681 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default; 1682 return; 1683 } 1684 1685 /* 1686 * Use hard coded value per gen to update the balance_perf 1687 * and default EPP. 1688 */ 1689 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE]; 1690 intel_pstate_set_epp(cpudata, cpudata->epp_default); 1691 } 1692 1693 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1694 { 1695 /* First disable HWP notification interrupt till we activate again */ 1696 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1697 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1698 1699 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1700 1701 intel_pstate_enable_hwp_interrupt(cpudata); 1702 1703 if (cpudata->epp_default >= 0) 1704 return; 1705 1706 intel_pstate_update_epp_defaults(cpudata); 1707 } 1708 1709 static int atom_get_min_pstate(int not_used) 1710 { 1711 u64 value; 1712 1713 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1714 return (value >> 8) & 0x7F; 1715 } 1716 1717 static int atom_get_max_pstate(int not_used) 1718 { 1719 u64 value; 1720 1721 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1722 return (value >> 16) & 0x7F; 1723 } 1724 1725 static int atom_get_turbo_pstate(int not_used) 1726 { 1727 u64 value; 1728 1729 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1730 return value & 0x7F; 1731 } 1732 1733 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1734 { 1735 u64 val; 1736 int32_t vid_fp; 1737 u32 vid; 1738 1739 val = (u64)pstate << 8; 1740 if (global.no_turbo && !global.turbo_disabled) 1741 val |= (u64)1 << 32; 1742 1743 vid_fp = cpudata->vid.min + mul_fp( 1744 int_tofp(pstate - cpudata->pstate.min_pstate), 1745 cpudata->vid.ratio); 1746 1747 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1748 vid = ceiling_fp(vid_fp); 1749 1750 if (pstate > cpudata->pstate.max_pstate) 1751 vid = cpudata->vid.turbo; 1752 1753 return val | vid; 1754 } 1755 1756 static int silvermont_get_scaling(void) 1757 { 1758 u64 value; 1759 int i; 1760 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1761 static int silvermont_freq_table[] = { 1762 83300, 100000, 133300, 116700, 80000}; 1763 1764 rdmsrl(MSR_FSB_FREQ, value); 1765 i = value & 0x7; 1766 WARN_ON(i > 4); 1767 1768 return silvermont_freq_table[i]; 1769 } 1770 1771 static int airmont_get_scaling(void) 1772 { 1773 u64 value; 1774 int i; 1775 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1776 static int airmont_freq_table[] = { 1777 83300, 100000, 133300, 116700, 80000, 1778 93300, 90000, 88900, 87500}; 1779 1780 rdmsrl(MSR_FSB_FREQ, value); 1781 i = value & 0xF; 1782 WARN_ON(i > 8); 1783 1784 return airmont_freq_table[i]; 1785 } 1786 1787 static void atom_get_vid(struct cpudata *cpudata) 1788 { 1789 u64 value; 1790 1791 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1792 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1793 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1794 cpudata->vid.ratio = div_fp( 1795 cpudata->vid.max - cpudata->vid.min, 1796 int_tofp(cpudata->pstate.max_pstate - 1797 cpudata->pstate.min_pstate)); 1798 1799 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1800 cpudata->vid.turbo = value & 0x7f; 1801 } 1802 1803 static int core_get_min_pstate(int cpu) 1804 { 1805 u64 value; 1806 1807 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1808 return (value >> 40) & 0xFF; 1809 } 1810 1811 static int core_get_max_pstate_physical(int cpu) 1812 { 1813 u64 value; 1814 1815 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 1816 return (value >> 8) & 0xFF; 1817 } 1818 1819 static int core_get_tdp_ratio(int cpu, u64 plat_info) 1820 { 1821 /* Check how many TDP levels present */ 1822 if (plat_info & 0x600000000) { 1823 u64 tdp_ctrl; 1824 u64 tdp_ratio; 1825 int tdp_msr; 1826 int err; 1827 1828 /* Get the TDP level (0, 1, 2) to get ratios */ 1829 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1830 if (err) 1831 return err; 1832 1833 /* TDP MSR are continuous starting at 0x648 */ 1834 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1835 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 1836 if (err) 1837 return err; 1838 1839 /* For level 1 and 2, bits[23:16] contain the ratio */ 1840 if (tdp_ctrl & 0x03) 1841 tdp_ratio >>= 16; 1842 1843 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1844 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1845 1846 return (int)tdp_ratio; 1847 } 1848 1849 return -ENXIO; 1850 } 1851 1852 static int core_get_max_pstate(int cpu) 1853 { 1854 u64 tar; 1855 u64 plat_info; 1856 int max_pstate; 1857 int tdp_ratio; 1858 int err; 1859 1860 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 1861 max_pstate = (plat_info >> 8) & 0xFF; 1862 1863 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); 1864 if (tdp_ratio <= 0) 1865 return max_pstate; 1866 1867 if (hwp_active) { 1868 /* Turbo activation ratio is not used on HWP platforms */ 1869 return tdp_ratio; 1870 } 1871 1872 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 1873 if (!err) { 1874 int tar_levels; 1875 1876 /* Do some sanity checking for safety */ 1877 tar_levels = tar & 0xff; 1878 if (tdp_ratio - 1 == tar_levels) { 1879 max_pstate = tar_levels; 1880 pr_debug("max_pstate=TAC %x\n", max_pstate); 1881 } 1882 } 1883 1884 return max_pstate; 1885 } 1886 1887 static int core_get_turbo_pstate(int cpu) 1888 { 1889 u64 value; 1890 int nont, ret; 1891 1892 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1893 nont = core_get_max_pstate(cpu); 1894 ret = (value) & 255; 1895 if (ret <= nont) 1896 ret = nont; 1897 return ret; 1898 } 1899 1900 static inline int core_get_scaling(void) 1901 { 1902 return 100000; 1903 } 1904 1905 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1906 { 1907 u64 val; 1908 1909 val = (u64)pstate << 8; 1910 if (global.no_turbo && !global.turbo_disabled) 1911 val |= (u64)1 << 32; 1912 1913 return val; 1914 } 1915 1916 static int knl_get_aperf_mperf_shift(void) 1917 { 1918 return 10; 1919 } 1920 1921 static int knl_get_turbo_pstate(int cpu) 1922 { 1923 u64 value; 1924 int nont, ret; 1925 1926 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 1927 nont = core_get_max_pstate(cpu); 1928 ret = (((value) >> 8) & 0xFF); 1929 if (ret <= nont) 1930 ret = nont; 1931 return ret; 1932 } 1933 1934 static void hybrid_get_type(void *data) 1935 { 1936 u8 *cpu_type = data; 1937 1938 *cpu_type = get_this_hybrid_cpu_type(); 1939 } 1940 1941 static int hybrid_get_cpu_scaling(int cpu) 1942 { 1943 u8 cpu_type = 0; 1944 1945 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); 1946 /* P-cores have a smaller perf level-to-freqency scaling factor. */ 1947 if (cpu_type == 0x40) 1948 return 78741; 1949 1950 return core_get_scaling(); 1951 } 1952 1953 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1954 { 1955 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1956 cpu->pstate.current_pstate = pstate; 1957 /* 1958 * Generally, there is no guarantee that this code will always run on 1959 * the CPU being updated, so force the register update to run on the 1960 * right CPU. 1961 */ 1962 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1963 pstate_funcs.get_val(cpu, pstate)); 1964 } 1965 1966 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1967 { 1968 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1969 } 1970 1971 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1972 { 1973 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1974 1975 update_turbo_state(); 1976 intel_pstate_set_pstate(cpu, pstate); 1977 } 1978 1979 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1980 { 1981 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 1982 int perf_ctl_scaling = pstate_funcs.get_scaling(); 1983 1984 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 1985 cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 1986 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 1987 1988 if (hwp_active && !hwp_mode_bdw) { 1989 __intel_pstate_get_hwp_cap(cpu); 1990 1991 if (pstate_funcs.get_cpu_scaling) { 1992 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 1993 if (cpu->pstate.scaling != perf_ctl_scaling) 1994 intel_pstate_hybrid_hwp_adjust(cpu); 1995 } else { 1996 cpu->pstate.scaling = perf_ctl_scaling; 1997 } 1998 } else { 1999 cpu->pstate.scaling = perf_ctl_scaling; 2000 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu); 2001 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu); 2002 } 2003 2004 if (cpu->pstate.scaling == perf_ctl_scaling) { 2005 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling; 2006 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling; 2007 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling; 2008 } 2009 2010 if (pstate_funcs.get_aperf_mperf_shift) 2011 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 2012 2013 if (pstate_funcs.get_vid) 2014 pstate_funcs.get_vid(cpu); 2015 2016 intel_pstate_set_min_pstate(cpu); 2017 } 2018 2019 /* 2020 * Long hold time will keep high perf limits for long time, 2021 * which negatively impacts perf/watt for some workloads, 2022 * like specpower. 3ms is based on experiements on some 2023 * workoads. 2024 */ 2025 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 2026 2027 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 2028 { 2029 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 2030 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2031 u32 max_limit = (hwp_req & 0xff00) >> 8; 2032 u32 min_limit = (hwp_req & 0xff); 2033 u32 boost_level1; 2034 2035 /* 2036 * Cases to consider (User changes via sysfs or boot time): 2037 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 2038 * No boost, return. 2039 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 2040 * Should result in one level boost only for P0. 2041 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 2042 * Should result in two level boost: 2043 * (min + p1)/2 and P1. 2044 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 2045 * Should result in three level boost: 2046 * (min + p1)/2, P1 and P0. 2047 */ 2048 2049 /* If max and min are equal or already at max, nothing to boost */ 2050 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 2051 return; 2052 2053 if (!cpu->hwp_boost_min) 2054 cpu->hwp_boost_min = min_limit; 2055 2056 /* level at half way mark between min and guranteed */ 2057 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1; 2058 2059 if (cpu->hwp_boost_min < boost_level1) 2060 cpu->hwp_boost_min = boost_level1; 2061 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap)) 2062 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap); 2063 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) && 2064 max_limit != HWP_GUARANTEED_PERF(hwp_cap)) 2065 cpu->hwp_boost_min = max_limit; 2066 else 2067 return; 2068 2069 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2070 wrmsrl(MSR_HWP_REQUEST, hwp_req); 2071 cpu->last_update = cpu->sample.time; 2072 } 2073 2074 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 2075 { 2076 if (cpu->hwp_boost_min) { 2077 bool expired; 2078 2079 /* Check if we are idle for hold time to boost down */ 2080 expired = time_after64(cpu->sample.time, cpu->last_update + 2081 hwp_boost_hold_time_ns); 2082 if (expired) { 2083 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2084 cpu->hwp_boost_min = 0; 2085 } 2086 } 2087 cpu->last_update = cpu->sample.time; 2088 } 2089 2090 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 2091 u64 time) 2092 { 2093 cpu->sample.time = time; 2094 2095 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 2096 bool do_io = false; 2097 2098 cpu->sched_flags = 0; 2099 /* 2100 * Set iowait_boost flag and update time. Since IO WAIT flag 2101 * is set all the time, we can't just conclude that there is 2102 * some IO bound activity is scheduled on this CPU with just 2103 * one occurrence. If we receive at least two in two 2104 * consecutive ticks, then we treat as boost candidate. 2105 */ 2106 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 2107 do_io = true; 2108 2109 cpu->last_io_update = time; 2110 2111 if (do_io) 2112 intel_pstate_hwp_boost_up(cpu); 2113 2114 } else { 2115 intel_pstate_hwp_boost_down(cpu); 2116 } 2117 } 2118 2119 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 2120 u64 time, unsigned int flags) 2121 { 2122 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2123 2124 cpu->sched_flags |= flags; 2125 2126 if (smp_processor_id() == cpu->cpu) 2127 intel_pstate_update_util_hwp_local(cpu, time); 2128 } 2129 2130 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 2131 { 2132 struct sample *sample = &cpu->sample; 2133 2134 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 2135 } 2136 2137 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 2138 { 2139 u64 aperf, mperf; 2140 unsigned long flags; 2141 u64 tsc; 2142 2143 local_irq_save(flags); 2144 rdmsrl(MSR_IA32_APERF, aperf); 2145 rdmsrl(MSR_IA32_MPERF, mperf); 2146 tsc = rdtsc(); 2147 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2148 local_irq_restore(flags); 2149 return false; 2150 } 2151 local_irq_restore(flags); 2152 2153 cpu->last_sample_time = cpu->sample.time; 2154 cpu->sample.time = time; 2155 cpu->sample.aperf = aperf; 2156 cpu->sample.mperf = mperf; 2157 cpu->sample.tsc = tsc; 2158 cpu->sample.aperf -= cpu->prev_aperf; 2159 cpu->sample.mperf -= cpu->prev_mperf; 2160 cpu->sample.tsc -= cpu->prev_tsc; 2161 2162 cpu->prev_aperf = aperf; 2163 cpu->prev_mperf = mperf; 2164 cpu->prev_tsc = tsc; 2165 /* 2166 * First time this function is invoked in a given cycle, all of the 2167 * previous sample data fields are equal to zero or stale and they must 2168 * be populated with meaningful numbers for things to work, so assume 2169 * that sample.time will always be reset before setting the utilization 2170 * update hook and make the caller skip the sample then. 2171 */ 2172 if (cpu->last_sample_time) { 2173 intel_pstate_calc_avg_perf(cpu); 2174 return true; 2175 } 2176 return false; 2177 } 2178 2179 static inline int32_t get_avg_frequency(struct cpudata *cpu) 2180 { 2181 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 2182 } 2183 2184 static inline int32_t get_avg_pstate(struct cpudata *cpu) 2185 { 2186 return mul_ext_fp(cpu->pstate.max_pstate_physical, 2187 cpu->sample.core_avg_perf); 2188 } 2189 2190 static inline int32_t get_target_pstate(struct cpudata *cpu) 2191 { 2192 struct sample *sample = &cpu->sample; 2193 int32_t busy_frac; 2194 int target, avg_pstate; 2195 2196 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 2197 sample->tsc); 2198 2199 if (busy_frac < cpu->iowait_boost) 2200 busy_frac = cpu->iowait_boost; 2201 2202 sample->busy_scaled = busy_frac * 100; 2203 2204 target = global.no_turbo || global.turbo_disabled ? 2205 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2206 target += target >> 2; 2207 target = mul_fp(target, busy_frac); 2208 if (target < cpu->pstate.min_pstate) 2209 target = cpu->pstate.min_pstate; 2210 2211 /* 2212 * If the average P-state during the previous cycle was higher than the 2213 * current target, add 50% of the difference to the target to reduce 2214 * possible performance oscillations and offset possible performance 2215 * loss related to moving the workload from one CPU to another within 2216 * a package/module. 2217 */ 2218 avg_pstate = get_avg_pstate(cpu); 2219 if (avg_pstate > target) 2220 target += (avg_pstate - target) >> 1; 2221 2222 return target; 2223 } 2224 2225 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 2226 { 2227 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 2228 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 2229 2230 return clamp_t(int, pstate, min_pstate, max_pstate); 2231 } 2232 2233 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 2234 { 2235 if (pstate == cpu->pstate.current_pstate) 2236 return; 2237 2238 cpu->pstate.current_pstate = pstate; 2239 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2240 } 2241 2242 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 2243 { 2244 int from = cpu->pstate.current_pstate; 2245 struct sample *sample; 2246 int target_pstate; 2247 2248 update_turbo_state(); 2249 2250 target_pstate = get_target_pstate(cpu); 2251 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2252 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 2253 intel_pstate_update_pstate(cpu, target_pstate); 2254 2255 sample = &cpu->sample; 2256 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 2257 fp_toint(sample->busy_scaled), 2258 from, 2259 cpu->pstate.current_pstate, 2260 sample->mperf, 2261 sample->aperf, 2262 sample->tsc, 2263 get_avg_frequency(cpu), 2264 fp_toint(cpu->iowait_boost * 100)); 2265 } 2266 2267 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 2268 unsigned int flags) 2269 { 2270 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 2271 u64 delta_ns; 2272 2273 /* Don't allow remote callbacks */ 2274 if (smp_processor_id() != cpu->cpu) 2275 return; 2276 2277 delta_ns = time - cpu->last_update; 2278 if (flags & SCHED_CPUFREQ_IOWAIT) { 2279 /* Start over if the CPU may have been idle. */ 2280 if (delta_ns > TICK_NSEC) { 2281 cpu->iowait_boost = ONE_EIGHTH_FP; 2282 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 2283 cpu->iowait_boost <<= 1; 2284 if (cpu->iowait_boost > int_tofp(1)) 2285 cpu->iowait_boost = int_tofp(1); 2286 } else { 2287 cpu->iowait_boost = ONE_EIGHTH_FP; 2288 } 2289 } else if (cpu->iowait_boost) { 2290 /* Clear iowait_boost if the CPU may have been idle. */ 2291 if (delta_ns > TICK_NSEC) 2292 cpu->iowait_boost = 0; 2293 else 2294 cpu->iowait_boost >>= 1; 2295 } 2296 cpu->last_update = time; 2297 delta_ns = time - cpu->sample.time; 2298 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 2299 return; 2300 2301 if (intel_pstate_sample(cpu, time)) 2302 intel_pstate_adjust_pstate(cpu); 2303 } 2304 2305 static struct pstate_funcs core_funcs = { 2306 .get_max = core_get_max_pstate, 2307 .get_max_physical = core_get_max_pstate_physical, 2308 .get_min = core_get_min_pstate, 2309 .get_turbo = core_get_turbo_pstate, 2310 .get_scaling = core_get_scaling, 2311 .get_val = core_get_val, 2312 }; 2313 2314 static const struct pstate_funcs silvermont_funcs = { 2315 .get_max = atom_get_max_pstate, 2316 .get_max_physical = atom_get_max_pstate, 2317 .get_min = atom_get_min_pstate, 2318 .get_turbo = atom_get_turbo_pstate, 2319 .get_val = atom_get_val, 2320 .get_scaling = silvermont_get_scaling, 2321 .get_vid = atom_get_vid, 2322 }; 2323 2324 static const struct pstate_funcs airmont_funcs = { 2325 .get_max = atom_get_max_pstate, 2326 .get_max_physical = atom_get_max_pstate, 2327 .get_min = atom_get_min_pstate, 2328 .get_turbo = atom_get_turbo_pstate, 2329 .get_val = atom_get_val, 2330 .get_scaling = airmont_get_scaling, 2331 .get_vid = atom_get_vid, 2332 }; 2333 2334 static const struct pstate_funcs knl_funcs = { 2335 .get_max = core_get_max_pstate, 2336 .get_max_physical = core_get_max_pstate_physical, 2337 .get_min = core_get_min_pstate, 2338 .get_turbo = knl_get_turbo_pstate, 2339 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 2340 .get_scaling = core_get_scaling, 2341 .get_val = core_get_val, 2342 }; 2343 2344 #define X86_MATCH(model, policy) \ 2345 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2346 X86_FEATURE_APERFMPERF, &policy) 2347 2348 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 2349 X86_MATCH(SANDYBRIDGE, core_funcs), 2350 X86_MATCH(SANDYBRIDGE_X, core_funcs), 2351 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 2352 X86_MATCH(IVYBRIDGE, core_funcs), 2353 X86_MATCH(HASWELL, core_funcs), 2354 X86_MATCH(BROADWELL, core_funcs), 2355 X86_MATCH(IVYBRIDGE_X, core_funcs), 2356 X86_MATCH(HASWELL_X, core_funcs), 2357 X86_MATCH(HASWELL_L, core_funcs), 2358 X86_MATCH(HASWELL_G, core_funcs), 2359 X86_MATCH(BROADWELL_G, core_funcs), 2360 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 2361 X86_MATCH(SKYLAKE_L, core_funcs), 2362 X86_MATCH(BROADWELL_X, core_funcs), 2363 X86_MATCH(SKYLAKE, core_funcs), 2364 X86_MATCH(BROADWELL_D, core_funcs), 2365 X86_MATCH(XEON_PHI_KNL, knl_funcs), 2366 X86_MATCH(XEON_PHI_KNM, knl_funcs), 2367 X86_MATCH(ATOM_GOLDMONT, core_funcs), 2368 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 2369 X86_MATCH(SKYLAKE_X, core_funcs), 2370 X86_MATCH(COMETLAKE, core_funcs), 2371 X86_MATCH(ICELAKE_X, core_funcs), 2372 X86_MATCH(TIGERLAKE, core_funcs), 2373 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2374 {} 2375 }; 2376 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 2377 2378 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 2379 X86_MATCH(BROADWELL_D, core_funcs), 2380 X86_MATCH(BROADWELL_X, core_funcs), 2381 X86_MATCH(SKYLAKE_X, core_funcs), 2382 X86_MATCH(ICELAKE_X, core_funcs), 2383 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs), 2384 {} 2385 }; 2386 2387 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 2388 X86_MATCH(KABYLAKE, core_funcs), 2389 {} 2390 }; 2391 2392 static int intel_pstate_init_cpu(unsigned int cpunum) 2393 { 2394 struct cpudata *cpu; 2395 2396 cpu = all_cpu_data[cpunum]; 2397 2398 if (!cpu) { 2399 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 2400 if (!cpu) 2401 return -ENOMEM; 2402 2403 WRITE_ONCE(all_cpu_data[cpunum], cpu); 2404 2405 cpu->cpu = cpunum; 2406 2407 cpu->epp_default = -EINVAL; 2408 2409 if (hwp_active) { 2410 intel_pstate_hwp_enable(cpu); 2411 2412 if (intel_pstate_acpi_pm_profile_server()) 2413 hwp_boost = true; 2414 } 2415 } else if (hwp_active) { 2416 /* 2417 * Re-enable HWP in case this happens after a resume from ACPI 2418 * S3 if the CPU was offline during the whole system/resume 2419 * cycle. 2420 */ 2421 intel_pstate_hwp_reenable(cpu); 2422 } 2423 2424 cpu->epp_powersave = -EINVAL; 2425 cpu->epp_policy = 0; 2426 2427 intel_pstate_get_cpu_pstates(cpu); 2428 2429 pr_debug("controlling: cpu %d\n", cpunum); 2430 2431 return 0; 2432 } 2433 2434 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2435 { 2436 struct cpudata *cpu = all_cpu_data[cpu_num]; 2437 2438 if (hwp_active && !hwp_boost) 2439 return; 2440 2441 if (cpu->update_util_set) 2442 return; 2443 2444 /* Prevent intel_pstate_update_util() from using stale data. */ 2445 cpu->sample.time = 0; 2446 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2447 (hwp_active ? 2448 intel_pstate_update_util_hwp : 2449 intel_pstate_update_util)); 2450 cpu->update_util_set = true; 2451 } 2452 2453 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2454 { 2455 struct cpudata *cpu_data = all_cpu_data[cpu]; 2456 2457 if (!cpu_data->update_util_set) 2458 return; 2459 2460 cpufreq_remove_update_util_hook(cpu); 2461 cpu_data->update_util_set = false; 2462 synchronize_rcu(); 2463 } 2464 2465 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2466 { 2467 return global.turbo_disabled || global.no_turbo ? 2468 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2469 } 2470 2471 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2472 unsigned int policy_min, 2473 unsigned int policy_max) 2474 { 2475 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling; 2476 int32_t max_policy_perf, min_policy_perf; 2477 2478 max_policy_perf = policy_max / perf_ctl_scaling; 2479 if (policy_max == policy_min) { 2480 min_policy_perf = max_policy_perf; 2481 } else { 2482 min_policy_perf = policy_min / perf_ctl_scaling; 2483 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2484 0, max_policy_perf); 2485 } 2486 2487 /* 2488 * HWP needs some special consideration, because HWP_REQUEST uses 2489 * abstract values to represent performance rather than pure ratios. 2490 */ 2491 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) { 2492 int scaling = cpu->pstate.scaling; 2493 int freq; 2494 2495 freq = max_policy_perf * perf_ctl_scaling; 2496 max_policy_perf = DIV_ROUND_UP(freq, scaling); 2497 freq = min_policy_perf * perf_ctl_scaling; 2498 min_policy_perf = DIV_ROUND_UP(freq, scaling); 2499 } 2500 2501 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n", 2502 cpu->cpu, min_policy_perf, max_policy_perf); 2503 2504 /* Normalize user input to [min_perf, max_perf] */ 2505 if (per_cpu_limits) { 2506 cpu->min_perf_ratio = min_policy_perf; 2507 cpu->max_perf_ratio = max_policy_perf; 2508 } else { 2509 int turbo_max = cpu->pstate.turbo_pstate; 2510 int32_t global_min, global_max; 2511 2512 /* Global limits are in percent of the maximum turbo P-state. */ 2513 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2514 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2515 global_min = clamp_t(int32_t, global_min, 0, global_max); 2516 2517 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2518 global_min, global_max); 2519 2520 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2521 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2522 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2523 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2524 2525 /* Make sure min_perf <= max_perf */ 2526 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2527 cpu->max_perf_ratio); 2528 2529 } 2530 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2531 cpu->max_perf_ratio, 2532 cpu->min_perf_ratio); 2533 } 2534 2535 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2536 { 2537 struct cpudata *cpu; 2538 2539 if (!policy->cpuinfo.max_freq) 2540 return -ENODEV; 2541 2542 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2543 policy->cpuinfo.max_freq, policy->max); 2544 2545 cpu = all_cpu_data[policy->cpu]; 2546 cpu->policy = policy->policy; 2547 2548 mutex_lock(&intel_pstate_limits_lock); 2549 2550 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2551 2552 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2553 /* 2554 * NOHZ_FULL CPUs need this as the governor callback may not 2555 * be invoked on them. 2556 */ 2557 intel_pstate_clear_update_util_hook(policy->cpu); 2558 intel_pstate_max_within_limits(cpu); 2559 } else { 2560 intel_pstate_set_update_util_hook(policy->cpu); 2561 } 2562 2563 if (hwp_active) { 2564 /* 2565 * When hwp_boost was active before and dynamically it 2566 * was turned off, in that case we need to clear the 2567 * update util hook. 2568 */ 2569 if (!hwp_boost) 2570 intel_pstate_clear_update_util_hook(policy->cpu); 2571 intel_pstate_hwp_set(policy->cpu); 2572 } 2573 2574 mutex_unlock(&intel_pstate_limits_lock); 2575 2576 return 0; 2577 } 2578 2579 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2580 struct cpufreq_policy_data *policy) 2581 { 2582 if (!hwp_active && 2583 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2584 policy->max < policy->cpuinfo.max_freq && 2585 policy->max > cpu->pstate.max_freq) { 2586 pr_debug("policy->max > max non turbo frequency\n"); 2587 policy->max = policy->cpuinfo.max_freq; 2588 } 2589 } 2590 2591 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2592 struct cpufreq_policy_data *policy) 2593 { 2594 int max_freq; 2595 2596 update_turbo_state(); 2597 if (hwp_active) { 2598 intel_pstate_get_hwp_cap(cpu); 2599 max_freq = global.no_turbo || global.turbo_disabled ? 2600 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2601 } else { 2602 max_freq = intel_pstate_get_max_freq(cpu); 2603 } 2604 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq); 2605 2606 intel_pstate_adjust_policy_max(cpu, policy); 2607 } 2608 2609 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2610 { 2611 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2612 2613 return 0; 2614 } 2615 2616 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy) 2617 { 2618 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2619 2620 pr_debug("CPU %d going offline\n", cpu->cpu); 2621 2622 if (cpu->suspended) 2623 return 0; 2624 2625 /* 2626 * If the CPU is an SMT thread and it goes offline with the performance 2627 * settings different from the minimum, it will prevent its sibling 2628 * from getting to lower performance levels, so force the minimum 2629 * performance on CPU offline to prevent that from happening. 2630 */ 2631 if (hwp_active) 2632 intel_pstate_hwp_offline(cpu); 2633 else 2634 intel_pstate_set_min_pstate(cpu); 2635 2636 intel_pstate_exit_perf_limits(policy); 2637 2638 return 0; 2639 } 2640 2641 static int intel_pstate_cpu_online(struct cpufreq_policy *policy) 2642 { 2643 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2644 2645 pr_debug("CPU %d going online\n", cpu->cpu); 2646 2647 intel_pstate_init_acpi_perf_limits(policy); 2648 2649 if (hwp_active) { 2650 /* 2651 * Re-enable HWP and clear the "suspended" flag to let "resume" 2652 * know that it need not do that. 2653 */ 2654 intel_pstate_hwp_reenable(cpu); 2655 cpu->suspended = false; 2656 } 2657 2658 return 0; 2659 } 2660 2661 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy) 2662 { 2663 intel_pstate_clear_update_util_hook(policy->cpu); 2664 2665 return intel_cpufreq_cpu_offline(policy); 2666 } 2667 2668 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2669 { 2670 pr_debug("CPU %d exiting\n", policy->cpu); 2671 2672 policy->fast_switch_possible = false; 2673 2674 return 0; 2675 } 2676 2677 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2678 { 2679 struct cpudata *cpu; 2680 int rc; 2681 2682 rc = intel_pstate_init_cpu(policy->cpu); 2683 if (rc) 2684 return rc; 2685 2686 cpu = all_cpu_data[policy->cpu]; 2687 2688 cpu->max_perf_ratio = 0xFF; 2689 cpu->min_perf_ratio = 0; 2690 2691 /* cpuinfo and default policy values */ 2692 policy->cpuinfo.min_freq = cpu->pstate.min_freq; 2693 update_turbo_state(); 2694 global.turbo_disabled_mf = global.turbo_disabled; 2695 policy->cpuinfo.max_freq = global.turbo_disabled ? 2696 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2697 2698 policy->min = policy->cpuinfo.min_freq; 2699 policy->max = policy->cpuinfo.max_freq; 2700 2701 intel_pstate_init_acpi_perf_limits(policy); 2702 2703 policy->fast_switch_possible = true; 2704 2705 return 0; 2706 } 2707 2708 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2709 { 2710 int ret = __intel_pstate_cpu_init(policy); 2711 2712 if (ret) 2713 return ret; 2714 2715 /* 2716 * Set the policy to powersave to provide a valid fallback value in case 2717 * the default cpufreq governor is neither powersave nor performance. 2718 */ 2719 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2720 2721 if (hwp_active) { 2722 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2723 2724 cpu->epp_cached = intel_pstate_get_epp(cpu, 0); 2725 } 2726 2727 return 0; 2728 } 2729 2730 static struct cpufreq_driver intel_pstate = { 2731 .flags = CPUFREQ_CONST_LOOPS, 2732 .verify = intel_pstate_verify_policy, 2733 .setpolicy = intel_pstate_set_policy, 2734 .suspend = intel_pstate_suspend, 2735 .resume = intel_pstate_resume, 2736 .init = intel_pstate_cpu_init, 2737 .exit = intel_pstate_cpu_exit, 2738 .offline = intel_pstate_cpu_offline, 2739 .online = intel_pstate_cpu_online, 2740 .update_limits = intel_pstate_update_limits, 2741 .name = "intel_pstate", 2742 }; 2743 2744 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2745 { 2746 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2747 2748 intel_pstate_verify_cpu_policy(cpu, policy); 2749 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2750 2751 return 0; 2752 } 2753 2754 /* Use of trace in passive mode: 2755 * 2756 * In passive mode the trace core_busy field (also known as the 2757 * performance field, and lablelled as such on the graphs; also known as 2758 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2759 * driver call was via the normal or fast switch path. Various graphs 2760 * output from the intel_pstate_tracer.py utility that include core_busy 2761 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2762 * so we use 10 to indicate the normal path through the driver, and 2763 * 90 to indicate the fast switch path through the driver. 2764 * The scaled_busy field is not used, and is set to 0. 2765 */ 2766 2767 #define INTEL_PSTATE_TRACE_TARGET 10 2768 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2769 2770 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2771 { 2772 struct sample *sample; 2773 2774 if (!trace_pstate_sample_enabled()) 2775 return; 2776 2777 if (!intel_pstate_sample(cpu, ktime_get())) 2778 return; 2779 2780 sample = &cpu->sample; 2781 trace_pstate_sample(trace_type, 2782 0, 2783 old_pstate, 2784 cpu->pstate.current_pstate, 2785 sample->mperf, 2786 sample->aperf, 2787 sample->tsc, 2788 get_avg_frequency(cpu), 2789 fp_toint(cpu->iowait_boost * 100)); 2790 } 2791 2792 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max, 2793 u32 desired, bool fast_switch) 2794 { 2795 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev; 2796 2797 value &= ~HWP_MIN_PERF(~0L); 2798 value |= HWP_MIN_PERF(min); 2799 2800 value &= ~HWP_MAX_PERF(~0L); 2801 value |= HWP_MAX_PERF(max); 2802 2803 value &= ~HWP_DESIRED_PERF(~0L); 2804 value |= HWP_DESIRED_PERF(desired); 2805 2806 if (value == prev) 2807 return; 2808 2809 WRITE_ONCE(cpu->hwp_req_cached, value); 2810 if (fast_switch) 2811 wrmsrl(MSR_HWP_REQUEST, value); 2812 else 2813 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 2814 } 2815 2816 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 2817 u32 target_pstate, bool fast_switch) 2818 { 2819 if (fast_switch) 2820 wrmsrl(MSR_IA32_PERF_CTL, 2821 pstate_funcs.get_val(cpu, target_pstate)); 2822 else 2823 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2824 pstate_funcs.get_val(cpu, target_pstate)); 2825 } 2826 2827 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy, 2828 int target_pstate, bool fast_switch) 2829 { 2830 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2831 int old_pstate = cpu->pstate.current_pstate; 2832 2833 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2834 if (hwp_active) { 2835 int max_pstate = policy->strict_target ? 2836 target_pstate : cpu->max_perf_ratio; 2837 2838 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0, 2839 fast_switch); 2840 } else if (target_pstate != old_pstate) { 2841 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch); 2842 } 2843 2844 cpu->pstate.current_pstate = target_pstate; 2845 2846 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH : 2847 INTEL_PSTATE_TRACE_TARGET, old_pstate); 2848 2849 return target_pstate; 2850 } 2851 2852 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2853 unsigned int target_freq, 2854 unsigned int relation) 2855 { 2856 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2857 struct cpufreq_freqs freqs; 2858 int target_pstate; 2859 2860 update_turbo_state(); 2861 2862 freqs.old = policy->cur; 2863 freqs.new = target_freq; 2864 2865 cpufreq_freq_transition_begin(policy, &freqs); 2866 2867 switch (relation) { 2868 case CPUFREQ_RELATION_L: 2869 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2870 break; 2871 case CPUFREQ_RELATION_H: 2872 target_pstate = freqs.new / cpu->pstate.scaling; 2873 break; 2874 default: 2875 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2876 break; 2877 } 2878 2879 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false); 2880 2881 freqs.new = target_pstate * cpu->pstate.scaling; 2882 2883 cpufreq_freq_transition_end(policy, &freqs, false); 2884 2885 return 0; 2886 } 2887 2888 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2889 unsigned int target_freq) 2890 { 2891 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2892 int target_pstate; 2893 2894 update_turbo_state(); 2895 2896 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2897 2898 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true); 2899 2900 return target_pstate * cpu->pstate.scaling; 2901 } 2902 2903 static void intel_cpufreq_adjust_perf(unsigned int cpunum, 2904 unsigned long min_perf, 2905 unsigned long target_perf, 2906 unsigned long capacity) 2907 { 2908 struct cpudata *cpu = all_cpu_data[cpunum]; 2909 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached); 2910 int old_pstate = cpu->pstate.current_pstate; 2911 int cap_pstate, min_pstate, max_pstate, target_pstate; 2912 2913 update_turbo_state(); 2914 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) : 2915 HWP_HIGHEST_PERF(hwp_cap); 2916 2917 /* Optimization: Avoid unnecessary divisions. */ 2918 2919 target_pstate = cap_pstate; 2920 if (target_perf < capacity) 2921 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity); 2922 2923 min_pstate = cap_pstate; 2924 if (min_perf < capacity) 2925 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity); 2926 2927 if (min_pstate < cpu->pstate.min_pstate) 2928 min_pstate = cpu->pstate.min_pstate; 2929 2930 if (min_pstate < cpu->min_perf_ratio) 2931 min_pstate = cpu->min_perf_ratio; 2932 2933 max_pstate = min(cap_pstate, cpu->max_perf_ratio); 2934 if (max_pstate < min_pstate) 2935 max_pstate = min_pstate; 2936 2937 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate); 2938 2939 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true); 2940 2941 cpu->pstate.current_pstate = target_pstate; 2942 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2943 } 2944 2945 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2946 { 2947 struct freq_qos_request *req; 2948 struct cpudata *cpu; 2949 struct device *dev; 2950 int ret, freq; 2951 2952 dev = get_cpu_device(policy->cpu); 2953 if (!dev) 2954 return -ENODEV; 2955 2956 ret = __intel_pstate_cpu_init(policy); 2957 if (ret) 2958 return ret; 2959 2960 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2961 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2962 policy->cur = policy->cpuinfo.min_freq; 2963 2964 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2965 if (!req) { 2966 ret = -ENOMEM; 2967 goto pstate_exit; 2968 } 2969 2970 cpu = all_cpu_data[policy->cpu]; 2971 2972 if (hwp_active) { 2973 u64 value; 2974 2975 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP; 2976 2977 intel_pstate_get_hwp_cap(cpu); 2978 2979 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 2980 WRITE_ONCE(cpu->hwp_req_cached, value); 2981 2982 cpu->epp_cached = intel_pstate_get_epp(cpu, value); 2983 } else { 2984 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2985 } 2986 2987 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100); 2988 2989 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 2990 freq); 2991 if (ret < 0) { 2992 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 2993 goto free_req; 2994 } 2995 2996 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100); 2997 2998 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 2999 freq); 3000 if (ret < 0) { 3001 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 3002 goto remove_min_req; 3003 } 3004 3005 policy->driver_data = req; 3006 3007 return 0; 3008 3009 remove_min_req: 3010 freq_qos_remove_request(req); 3011 free_req: 3012 kfree(req); 3013 pstate_exit: 3014 intel_pstate_exit_perf_limits(policy); 3015 3016 return ret; 3017 } 3018 3019 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 3020 { 3021 struct freq_qos_request *req; 3022 3023 req = policy->driver_data; 3024 3025 freq_qos_remove_request(req + 1); 3026 freq_qos_remove_request(req); 3027 kfree(req); 3028 3029 return intel_pstate_cpu_exit(policy); 3030 } 3031 3032 static int intel_cpufreq_suspend(struct cpufreq_policy *policy) 3033 { 3034 intel_pstate_suspend(policy); 3035 3036 if (hwp_active) { 3037 struct cpudata *cpu = all_cpu_data[policy->cpu]; 3038 u64 value = READ_ONCE(cpu->hwp_req_cached); 3039 3040 /* 3041 * Clear the desired perf field in MSR_HWP_REQUEST in case 3042 * intel_cpufreq_adjust_perf() is in use and the last value 3043 * written by it may not be suitable. 3044 */ 3045 value &= ~HWP_DESIRED_PERF(~0L); 3046 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3047 WRITE_ONCE(cpu->hwp_req_cached, value); 3048 } 3049 3050 return 0; 3051 } 3052 3053 static struct cpufreq_driver intel_cpufreq = { 3054 .flags = CPUFREQ_CONST_LOOPS, 3055 .verify = intel_cpufreq_verify_policy, 3056 .target = intel_cpufreq_target, 3057 .fast_switch = intel_cpufreq_fast_switch, 3058 .init = intel_cpufreq_cpu_init, 3059 .exit = intel_cpufreq_cpu_exit, 3060 .offline = intel_cpufreq_cpu_offline, 3061 .online = intel_pstate_cpu_online, 3062 .suspend = intel_cpufreq_suspend, 3063 .resume = intel_pstate_resume, 3064 .update_limits = intel_pstate_update_limits, 3065 .name = "intel_cpufreq", 3066 }; 3067 3068 static struct cpufreq_driver *default_driver; 3069 3070 static void intel_pstate_driver_cleanup(void) 3071 { 3072 unsigned int cpu; 3073 3074 cpus_read_lock(); 3075 for_each_online_cpu(cpu) { 3076 if (all_cpu_data[cpu]) { 3077 if (intel_pstate_driver == &intel_pstate) 3078 intel_pstate_clear_update_util_hook(cpu); 3079 3080 spin_lock(&hwp_notify_lock); 3081 kfree(all_cpu_data[cpu]); 3082 WRITE_ONCE(all_cpu_data[cpu], NULL); 3083 spin_unlock(&hwp_notify_lock); 3084 } 3085 } 3086 cpus_read_unlock(); 3087 3088 intel_pstate_driver = NULL; 3089 } 3090 3091 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 3092 { 3093 int ret; 3094 3095 if (driver == &intel_pstate) 3096 intel_pstate_sysfs_expose_hwp_dynamic_boost(); 3097 3098 memset(&global, 0, sizeof(global)); 3099 global.max_perf_pct = 100; 3100 3101 intel_pstate_driver = driver; 3102 ret = cpufreq_register_driver(intel_pstate_driver); 3103 if (ret) { 3104 intel_pstate_driver_cleanup(); 3105 return ret; 3106 } 3107 3108 global.min_perf_pct = min_perf_pct_min(); 3109 3110 return 0; 3111 } 3112 3113 static ssize_t intel_pstate_show_status(char *buf) 3114 { 3115 if (!intel_pstate_driver) 3116 return sprintf(buf, "off\n"); 3117 3118 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 3119 "active" : "passive"); 3120 } 3121 3122 static int intel_pstate_update_status(const char *buf, size_t size) 3123 { 3124 if (size == 3 && !strncmp(buf, "off", size)) { 3125 if (!intel_pstate_driver) 3126 return -EINVAL; 3127 3128 if (hwp_active) 3129 return -EBUSY; 3130 3131 cpufreq_unregister_driver(intel_pstate_driver); 3132 intel_pstate_driver_cleanup(); 3133 return 0; 3134 } 3135 3136 if (size == 6 && !strncmp(buf, "active", size)) { 3137 if (intel_pstate_driver) { 3138 if (intel_pstate_driver == &intel_pstate) 3139 return 0; 3140 3141 cpufreq_unregister_driver(intel_pstate_driver); 3142 } 3143 3144 return intel_pstate_register_driver(&intel_pstate); 3145 } 3146 3147 if (size == 7 && !strncmp(buf, "passive", size)) { 3148 if (intel_pstate_driver) { 3149 if (intel_pstate_driver == &intel_cpufreq) 3150 return 0; 3151 3152 cpufreq_unregister_driver(intel_pstate_driver); 3153 intel_pstate_sysfs_hide_hwp_dynamic_boost(); 3154 } 3155 3156 return intel_pstate_register_driver(&intel_cpufreq); 3157 } 3158 3159 return -EINVAL; 3160 } 3161 3162 static int no_load __initdata; 3163 static int no_hwp __initdata; 3164 static int hwp_only __initdata; 3165 static unsigned int force_load __initdata; 3166 3167 static int __init intel_pstate_msrs_not_valid(void) 3168 { 3169 if (!pstate_funcs.get_max(0) || 3170 !pstate_funcs.get_min(0) || 3171 !pstate_funcs.get_turbo(0)) 3172 return -ENODEV; 3173 3174 return 0; 3175 } 3176 3177 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 3178 { 3179 pstate_funcs.get_max = funcs->get_max; 3180 pstate_funcs.get_max_physical = funcs->get_max_physical; 3181 pstate_funcs.get_min = funcs->get_min; 3182 pstate_funcs.get_turbo = funcs->get_turbo; 3183 pstate_funcs.get_scaling = funcs->get_scaling; 3184 pstate_funcs.get_val = funcs->get_val; 3185 pstate_funcs.get_vid = funcs->get_vid; 3186 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 3187 } 3188 3189 #ifdef CONFIG_ACPI 3190 3191 static bool __init intel_pstate_no_acpi_pss(void) 3192 { 3193 int i; 3194 3195 for_each_possible_cpu(i) { 3196 acpi_status status; 3197 union acpi_object *pss; 3198 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 3199 struct acpi_processor *pr = per_cpu(processors, i); 3200 3201 if (!pr) 3202 continue; 3203 3204 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 3205 if (ACPI_FAILURE(status)) 3206 continue; 3207 3208 pss = buffer.pointer; 3209 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 3210 kfree(pss); 3211 return false; 3212 } 3213 3214 kfree(pss); 3215 } 3216 3217 pr_debug("ACPI _PSS not found\n"); 3218 return true; 3219 } 3220 3221 static bool __init intel_pstate_no_acpi_pcch(void) 3222 { 3223 acpi_status status; 3224 acpi_handle handle; 3225 3226 status = acpi_get_handle(NULL, "\\_SB", &handle); 3227 if (ACPI_FAILURE(status)) 3228 goto not_found; 3229 3230 if (acpi_has_method(handle, "PCCH")) 3231 return false; 3232 3233 not_found: 3234 pr_debug("ACPI PCCH not found\n"); 3235 return true; 3236 } 3237 3238 static bool __init intel_pstate_has_acpi_ppc(void) 3239 { 3240 int i; 3241 3242 for_each_possible_cpu(i) { 3243 struct acpi_processor *pr = per_cpu(processors, i); 3244 3245 if (!pr) 3246 continue; 3247 if (acpi_has_method(pr->handle, "_PPC")) 3248 return true; 3249 } 3250 pr_debug("ACPI _PPC not found\n"); 3251 return false; 3252 } 3253 3254 enum { 3255 PSS, 3256 PPC, 3257 }; 3258 3259 /* Hardware vendor-specific info that has its own power management modes */ 3260 static struct acpi_platform_list plat_info[] __initdata = { 3261 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 3262 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3263 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3264 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3265 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3266 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3267 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3268 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3269 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3270 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3271 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3272 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3273 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3274 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3275 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 3276 { } /* End */ 3277 }; 3278 3279 #define BITMASK_OOB (BIT(8) | BIT(18)) 3280 3281 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 3282 { 3283 const struct x86_cpu_id *id; 3284 u64 misc_pwr; 3285 int idx; 3286 3287 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3288 if (id) { 3289 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3290 if (misc_pwr & BITMASK_OOB) { 3291 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3292 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); 3293 return true; 3294 } 3295 } 3296 3297 idx = acpi_match_platform_list(plat_info); 3298 if (idx < 0) 3299 return false; 3300 3301 switch (plat_info[idx].data) { 3302 case PSS: 3303 if (!intel_pstate_no_acpi_pss()) 3304 return false; 3305 3306 return intel_pstate_no_acpi_pcch(); 3307 case PPC: 3308 return intel_pstate_has_acpi_ppc() && !force_load; 3309 } 3310 3311 return false; 3312 } 3313 3314 static void intel_pstate_request_control_from_smm(void) 3315 { 3316 /* 3317 * It may be unsafe to request P-states control from SMM if _PPC support 3318 * has not been enabled. 3319 */ 3320 if (acpi_ppc) 3321 acpi_processor_pstate_control(); 3322 } 3323 #else /* CONFIG_ACPI not enabled */ 3324 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 3325 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 3326 static inline void intel_pstate_request_control_from_smm(void) {} 3327 #endif /* CONFIG_ACPI */ 3328 3329 #define INTEL_PSTATE_HWP_BROADWELL 0x01 3330 3331 #define X86_MATCH_HWP(model, hwp_mode) \ 3332 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 3333 X86_FEATURE_HWP, hwp_mode) 3334 3335 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 3336 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 3337 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 3338 X86_MATCH_HWP(ANY, 0), 3339 {} 3340 }; 3341 3342 static bool intel_pstate_hwp_is_enabled(void) 3343 { 3344 u64 value; 3345 3346 rdmsrl(MSR_PM_ENABLE, value); 3347 return !!(value & 0x1); 3348 } 3349 3350 static const struct x86_cpu_id intel_epp_balance_perf[] = { 3351 /* 3352 * Set EPP value as 102, this is the max suggested EPP 3353 * which can result in one core turbo frequency for 3354 * AlderLake Mobile CPUs. 3355 */ 3356 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102), 3357 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32), 3358 {} 3359 }; 3360 3361 static int __init intel_pstate_init(void) 3362 { 3363 static struct cpudata **_all_cpu_data; 3364 const struct x86_cpu_id *id; 3365 int rc; 3366 3367 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 3368 return -ENODEV; 3369 3370 id = x86_match_cpu(hwp_support_ids); 3371 if (id) { 3372 hwp_forced = intel_pstate_hwp_is_enabled(); 3373 3374 if (hwp_forced) 3375 pr_info("HWP enabled by BIOS\n"); 3376 else if (no_load) 3377 return -ENODEV; 3378 3379 copy_cpu_funcs(&core_funcs); 3380 /* 3381 * Avoid enabling HWP for processors without EPP support, 3382 * because that means incomplete HWP implementation which is a 3383 * corner case and supporting it is generally problematic. 3384 * 3385 * If HWP is enabled already, though, there is no choice but to 3386 * deal with it. 3387 */ 3388 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) { 3389 WRITE_ONCE(hwp_active, 1); 3390 hwp_mode_bdw = id->driver_data; 3391 intel_pstate.attr = hwp_cpufreq_attrs; 3392 intel_cpufreq.attr = hwp_cpufreq_attrs; 3393 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS; 3394 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf; 3395 if (!default_driver) 3396 default_driver = &intel_pstate; 3397 3398 if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) 3399 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling; 3400 3401 goto hwp_cpu_matched; 3402 } 3403 pr_info("HWP not enabled\n"); 3404 } else { 3405 if (no_load) 3406 return -ENODEV; 3407 3408 id = x86_match_cpu(intel_pstate_cpu_ids); 3409 if (!id) { 3410 pr_info("CPU model not supported\n"); 3411 return -ENODEV; 3412 } 3413 3414 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 3415 } 3416 3417 if (intel_pstate_msrs_not_valid()) { 3418 pr_info("Invalid MSRs\n"); 3419 return -ENODEV; 3420 } 3421 /* Without HWP start in the passive mode. */ 3422 if (!default_driver) 3423 default_driver = &intel_cpufreq; 3424 3425 hwp_cpu_matched: 3426 /* 3427 * The Intel pstate driver will be ignored if the platform 3428 * firmware has its own power management modes. 3429 */ 3430 if (intel_pstate_platform_pwr_mgmt_exists()) { 3431 pr_info("P-states controlled by the platform\n"); 3432 return -ENODEV; 3433 } 3434 3435 if (!hwp_active && hwp_only) 3436 return -ENOTSUPP; 3437 3438 pr_info("Intel P-state driver initializing\n"); 3439 3440 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 3441 if (!_all_cpu_data) 3442 return -ENOMEM; 3443 3444 WRITE_ONCE(all_cpu_data, _all_cpu_data); 3445 3446 intel_pstate_request_control_from_smm(); 3447 3448 intel_pstate_sysfs_expose_params(); 3449 3450 if (hwp_active) { 3451 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf); 3452 3453 if (id) 3454 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data; 3455 } 3456 3457 mutex_lock(&intel_pstate_driver_lock); 3458 rc = intel_pstate_register_driver(default_driver); 3459 mutex_unlock(&intel_pstate_driver_lock); 3460 if (rc) { 3461 intel_pstate_sysfs_remove(); 3462 return rc; 3463 } 3464 3465 if (hwp_active) { 3466 const struct x86_cpu_id *id; 3467 3468 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 3469 if (id) { 3470 set_power_ctl_ee_state(false); 3471 pr_info("Disabling energy efficiency optimization\n"); 3472 } 3473 3474 pr_info("HWP enabled\n"); 3475 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) { 3476 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n"); 3477 } 3478 3479 return 0; 3480 } 3481 device_initcall(intel_pstate_init); 3482 3483 static int __init intel_pstate_setup(char *str) 3484 { 3485 if (!str) 3486 return -EINVAL; 3487 3488 if (!strcmp(str, "disable")) 3489 no_load = 1; 3490 else if (!strcmp(str, "active")) 3491 default_driver = &intel_pstate; 3492 else if (!strcmp(str, "passive")) 3493 default_driver = &intel_cpufreq; 3494 3495 if (!strcmp(str, "no_hwp")) 3496 no_hwp = 1; 3497 3498 if (!strcmp(str, "force")) 3499 force_load = 1; 3500 if (!strcmp(str, "hwp_only")) 3501 hwp_only = 1; 3502 if (!strcmp(str, "per_cpu_perf_limits")) 3503 per_cpu_limits = true; 3504 3505 #ifdef CONFIG_ACPI 3506 if (!strcmp(str, "support_acpi_ppc")) 3507 acpi_ppc = true; 3508 #endif 3509 3510 return 0; 3511 } 3512 early_param("intel_pstate", intel_pstate_setup); 3513 3514 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 3515 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 3516