1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * intel_pstate.c: Native P state management for Intel processors 4 * 5 * (C) Copyright 2012 Intel Corporation 6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/kernel.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/module.h> 14 #include <linux/ktime.h> 15 #include <linux/hrtimer.h> 16 #include <linux/tick.h> 17 #include <linux/slab.h> 18 #include <linux/sched/cpufreq.h> 19 #include <linux/list.h> 20 #include <linux/cpu.h> 21 #include <linux/cpufreq.h> 22 #include <linux/sysfs.h> 23 #include <linux/types.h> 24 #include <linux/fs.h> 25 #include <linux/acpi.h> 26 #include <linux/vmalloc.h> 27 #include <linux/pm_qos.h> 28 #include <trace/events/power.h> 29 30 #include <asm/div64.h> 31 #include <asm/msr.h> 32 #include <asm/cpu_device_id.h> 33 #include <asm/cpufeature.h> 34 #include <asm/intel-family.h> 35 36 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) 37 38 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 39 #define INTEL_CPUFREQ_TRANSITION_DELAY 500 40 41 #ifdef CONFIG_ACPI 42 #include <acpi/processor.h> 43 #include <acpi/cppc_acpi.h> 44 #endif 45 46 #define FRAC_BITS 8 47 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) 48 #define fp_toint(X) ((X) >> FRAC_BITS) 49 50 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3)) 51 52 #define EXT_BITS 6 53 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) 54 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) 55 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) 56 57 static inline int32_t mul_fp(int32_t x, int32_t y) 58 { 59 return ((int64_t)x * (int64_t)y) >> FRAC_BITS; 60 } 61 62 static inline int32_t div_fp(s64 x, s64 y) 63 { 64 return div64_s64((int64_t)x << FRAC_BITS, y); 65 } 66 67 static inline int ceiling_fp(int32_t x) 68 { 69 int mask, ret; 70 71 ret = fp_toint(x); 72 mask = (1 << FRAC_BITS) - 1; 73 if (x & mask) 74 ret += 1; 75 return ret; 76 } 77 78 static inline int32_t percent_fp(int percent) 79 { 80 return div_fp(percent, 100); 81 } 82 83 static inline u64 mul_ext_fp(u64 x, u64 y) 84 { 85 return (x * y) >> EXT_FRAC_BITS; 86 } 87 88 static inline u64 div_ext_fp(u64 x, u64 y) 89 { 90 return div64_u64(x << EXT_FRAC_BITS, y); 91 } 92 93 static inline int32_t percent_ext_fp(int percent) 94 { 95 return div_ext_fp(percent, 100); 96 } 97 98 /** 99 * struct sample - Store performance sample 100 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average 101 * performance during last sample period 102 * @busy_scaled: Scaled busy value which is used to calculate next 103 * P state. This can be different than core_avg_perf 104 * to account for cpu idle period 105 * @aperf: Difference of actual performance frequency clock count 106 * read from APERF MSR between last and current sample 107 * @mperf: Difference of maximum performance frequency clock count 108 * read from MPERF MSR between last and current sample 109 * @tsc: Difference of time stamp counter between last and 110 * current sample 111 * @time: Current time from scheduler 112 * 113 * This structure is used in the cpudata structure to store performance sample 114 * data for choosing next P State. 115 */ 116 struct sample { 117 int32_t core_avg_perf; 118 int32_t busy_scaled; 119 u64 aperf; 120 u64 mperf; 121 u64 tsc; 122 u64 time; 123 }; 124 125 /** 126 * struct pstate_data - Store P state data 127 * @current_pstate: Current requested P state 128 * @min_pstate: Min P state possible for this platform 129 * @max_pstate: Max P state possible for this platform 130 * @max_pstate_physical:This is physical Max P state for a processor 131 * This can be higher than the max_pstate which can 132 * be limited by platform thermal design power limits 133 * @scaling: Scaling factor to convert frequency to cpufreq 134 * frequency units 135 * @turbo_pstate: Max Turbo P state possible for this platform 136 * @max_freq: @max_pstate frequency in cpufreq units 137 * @turbo_freq: @turbo_pstate frequency in cpufreq units 138 * 139 * Stores the per cpu model P state limits and current P state. 140 */ 141 struct pstate_data { 142 int current_pstate; 143 int min_pstate; 144 int max_pstate; 145 int max_pstate_physical; 146 int scaling; 147 int turbo_pstate; 148 unsigned int max_freq; 149 unsigned int turbo_freq; 150 }; 151 152 /** 153 * struct vid_data - Stores voltage information data 154 * @min: VID data for this platform corresponding to 155 * the lowest P state 156 * @max: VID data corresponding to the highest P State. 157 * @turbo: VID data for turbo P state 158 * @ratio: Ratio of (vid max - vid min) / 159 * (max P state - Min P State) 160 * 161 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) 162 * This data is used in Atom platforms, where in addition to target P state, 163 * the voltage data needs to be specified to select next P State. 164 */ 165 struct vid_data { 166 int min; 167 int max; 168 int turbo; 169 int32_t ratio; 170 }; 171 172 /** 173 * struct global_params - Global parameters, mostly tunable via sysfs. 174 * @no_turbo: Whether or not to use turbo P-states. 175 * @turbo_disabled: Whether or not turbo P-states are available at all, 176 * based on the MSR_IA32_MISC_ENABLE value and whether or 177 * not the maximum reported turbo P-state is different from 178 * the maximum reported non-turbo one. 179 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq. 180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo 181 * P-state capacity. 182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo 183 * P-state capacity. 184 */ 185 struct global_params { 186 bool no_turbo; 187 bool turbo_disabled; 188 bool turbo_disabled_mf; 189 int max_perf_pct; 190 int min_perf_pct; 191 }; 192 193 /** 194 * struct cpudata - Per CPU instance data storage 195 * @cpu: CPU number for this instance data 196 * @policy: CPUFreq policy value 197 * @update_util: CPUFreq utility callback information 198 * @update_util_set: CPUFreq utility callback is set 199 * @iowait_boost: iowait-related boost fraction 200 * @last_update: Time of the last update. 201 * @pstate: Stores P state limits for this CPU 202 * @vid: Stores VID limits for this CPU 203 * @last_sample_time: Last Sample time 204 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented 205 * This shift is a multiplier to mperf delta to 206 * calculate CPU busy. 207 * @prev_aperf: Last APERF value read from APERF MSR 208 * @prev_mperf: Last MPERF value read from MPERF MSR 209 * @prev_tsc: Last timestamp counter (TSC) value 210 * @prev_cummulative_iowait: IO Wait time difference from last and 211 * current sample 212 * @sample: Storage for storing last Sample data 213 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios 214 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios 215 * @acpi_perf_data: Stores ACPI perf information read from _PSS 216 * @valid_pss_table: Set to true for valid ACPI _PSS entries found 217 * @epp_powersave: Last saved HWP energy performance preference 218 * (EPP) or energy performance bias (EPB), 219 * when policy switched to performance 220 * @epp_policy: Last saved policy used to set EPP/EPB 221 * @epp_default: Power on default HWP energy performance 222 * preference/bias 223 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline 224 * operation 225 * @hwp_req_cached: Cached value of the last HWP Request MSR 226 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR 227 * @last_io_update: Last time when IO wake flag was set 228 * @sched_flags: Store scheduler flags for possible cross CPU update 229 * @hwp_boost_min: Last HWP boosted min performance 230 * 231 * This structure stores per CPU instance data for all CPUs. 232 */ 233 struct cpudata { 234 int cpu; 235 236 unsigned int policy; 237 struct update_util_data update_util; 238 bool update_util_set; 239 240 struct pstate_data pstate; 241 struct vid_data vid; 242 243 u64 last_update; 244 u64 last_sample_time; 245 u64 aperf_mperf_shift; 246 u64 prev_aperf; 247 u64 prev_mperf; 248 u64 prev_tsc; 249 u64 prev_cummulative_iowait; 250 struct sample sample; 251 int32_t min_perf_ratio; 252 int32_t max_perf_ratio; 253 #ifdef CONFIG_ACPI 254 struct acpi_processor_performance acpi_perf_data; 255 bool valid_pss_table; 256 #endif 257 unsigned int iowait_boost; 258 s16 epp_powersave; 259 s16 epp_policy; 260 s16 epp_default; 261 s16 epp_saved; 262 u64 hwp_req_cached; 263 u64 hwp_cap_cached; 264 u64 last_io_update; 265 unsigned int sched_flags; 266 u32 hwp_boost_min; 267 }; 268 269 static struct cpudata **all_cpu_data; 270 271 /** 272 * struct pstate_funcs - Per CPU model specific callbacks 273 * @get_max: Callback to get maximum non turbo effective P state 274 * @get_max_physical: Callback to get maximum non turbo physical P state 275 * @get_min: Callback to get minimum P state 276 * @get_turbo: Callback to get turbo P state 277 * @get_scaling: Callback to get frequency scaling factor 278 * @get_val: Callback to convert P state to actual MSR write value 279 * @get_vid: Callback to get VID data for Atom platforms 280 * 281 * Core and Atom CPU models have different way to get P State limits. This 282 * structure is used to store those callbacks. 283 */ 284 struct pstate_funcs { 285 int (*get_max)(void); 286 int (*get_max_physical)(void); 287 int (*get_min)(void); 288 int (*get_turbo)(void); 289 int (*get_scaling)(void); 290 int (*get_aperf_mperf_shift)(void); 291 u64 (*get_val)(struct cpudata*, int pstate); 292 void (*get_vid)(struct cpudata *); 293 }; 294 295 static struct pstate_funcs pstate_funcs __read_mostly; 296 297 static int hwp_active __read_mostly; 298 static int hwp_mode_bdw __read_mostly; 299 static bool per_cpu_limits __read_mostly; 300 static bool hwp_boost __read_mostly; 301 302 static struct cpufreq_driver *intel_pstate_driver __read_mostly; 303 304 #ifdef CONFIG_ACPI 305 static bool acpi_ppc; 306 #endif 307 308 static struct global_params global; 309 310 static DEFINE_MUTEX(intel_pstate_driver_lock); 311 static DEFINE_MUTEX(intel_pstate_limits_lock); 312 313 #ifdef CONFIG_ACPI 314 315 static bool intel_pstate_acpi_pm_profile_server(void) 316 { 317 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || 318 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) 319 return true; 320 321 return false; 322 } 323 324 static bool intel_pstate_get_ppc_enable_status(void) 325 { 326 if (intel_pstate_acpi_pm_profile_server()) 327 return true; 328 329 return acpi_ppc; 330 } 331 332 #ifdef CONFIG_ACPI_CPPC_LIB 333 334 /* The work item is needed to avoid CPU hotplug locking issues */ 335 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) 336 { 337 sched_set_itmt_support(); 338 } 339 340 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); 341 342 static void intel_pstate_set_itmt_prio(int cpu) 343 { 344 struct cppc_perf_caps cppc_perf; 345 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; 346 int ret; 347 348 ret = cppc_get_perf_caps(cpu, &cppc_perf); 349 if (ret) 350 return; 351 352 /* 353 * The priorities can be set regardless of whether or not 354 * sched_set_itmt_support(true) has been called and it is valid to 355 * update them at any time after it has been called. 356 */ 357 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); 358 359 if (max_highest_perf <= min_highest_perf) { 360 if (cppc_perf.highest_perf > max_highest_perf) 361 max_highest_perf = cppc_perf.highest_perf; 362 363 if (cppc_perf.highest_perf < min_highest_perf) 364 min_highest_perf = cppc_perf.highest_perf; 365 366 if (max_highest_perf > min_highest_perf) { 367 /* 368 * This code can be run during CPU online under the 369 * CPU hotplug locks, so sched_set_itmt_support() 370 * cannot be called from here. Queue up a work item 371 * to invoke it. 372 */ 373 schedule_work(&sched_itmt_work); 374 } 375 } 376 } 377 378 static int intel_pstate_get_cppc_guranteed(int cpu) 379 { 380 struct cppc_perf_caps cppc_perf; 381 int ret; 382 383 ret = cppc_get_perf_caps(cpu, &cppc_perf); 384 if (ret) 385 return ret; 386 387 if (cppc_perf.guaranteed_perf) 388 return cppc_perf.guaranteed_perf; 389 390 return cppc_perf.nominal_perf; 391 } 392 393 #else /* CONFIG_ACPI_CPPC_LIB */ 394 static void intel_pstate_set_itmt_prio(int cpu) 395 { 396 } 397 #endif /* CONFIG_ACPI_CPPC_LIB */ 398 399 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 400 { 401 struct cpudata *cpu; 402 int ret; 403 int i; 404 405 if (hwp_active) { 406 intel_pstate_set_itmt_prio(policy->cpu); 407 return; 408 } 409 410 if (!intel_pstate_get_ppc_enable_status()) 411 return; 412 413 cpu = all_cpu_data[policy->cpu]; 414 415 ret = acpi_processor_register_performance(&cpu->acpi_perf_data, 416 policy->cpu); 417 if (ret) 418 return; 419 420 /* 421 * Check if the control value in _PSS is for PERF_CTL MSR, which should 422 * guarantee that the states returned by it map to the states in our 423 * list directly. 424 */ 425 if (cpu->acpi_perf_data.control_register.space_id != 426 ACPI_ADR_SPACE_FIXED_HARDWARE) 427 goto err; 428 429 /* 430 * If there is only one entry _PSS, simply ignore _PSS and continue as 431 * usual without taking _PSS into account 432 */ 433 if (cpu->acpi_perf_data.state_count < 2) 434 goto err; 435 436 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); 437 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { 438 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", 439 (i == cpu->acpi_perf_data.state ? '*' : ' '), i, 440 (u32) cpu->acpi_perf_data.states[i].core_frequency, 441 (u32) cpu->acpi_perf_data.states[i].power, 442 (u32) cpu->acpi_perf_data.states[i].control); 443 } 444 445 /* 446 * The _PSS table doesn't contain whole turbo frequency range. 447 * This just contains +1 MHZ above the max non turbo frequency, 448 * with control value corresponding to max turbo ratio. But 449 * when cpufreq set policy is called, it will call with this 450 * max frequency, which will cause a reduced performance as 451 * this driver uses real max turbo frequency as the max 452 * frequency. So correct this frequency in _PSS table to 453 * correct max turbo frequency based on the turbo state. 454 * Also need to convert to MHz as _PSS freq is in MHz. 455 */ 456 if (!global.turbo_disabled) 457 cpu->acpi_perf_data.states[0].core_frequency = 458 policy->cpuinfo.max_freq / 1000; 459 cpu->valid_pss_table = true; 460 pr_debug("_PPC limits will be enforced\n"); 461 462 return; 463 464 err: 465 cpu->valid_pss_table = false; 466 acpi_processor_unregister_performance(policy->cpu); 467 } 468 469 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 470 { 471 struct cpudata *cpu; 472 473 cpu = all_cpu_data[policy->cpu]; 474 if (!cpu->valid_pss_table) 475 return; 476 477 acpi_processor_unregister_performance(policy->cpu); 478 } 479 #else /* CONFIG_ACPI */ 480 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) 481 { 482 } 483 484 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) 485 { 486 } 487 488 static inline bool intel_pstate_acpi_pm_profile_server(void) 489 { 490 return false; 491 } 492 #endif /* CONFIG_ACPI */ 493 494 #ifndef CONFIG_ACPI_CPPC_LIB 495 static int intel_pstate_get_cppc_guranteed(int cpu) 496 { 497 return -ENOTSUPP; 498 } 499 #endif /* CONFIG_ACPI_CPPC_LIB */ 500 501 static inline void update_turbo_state(void) 502 { 503 u64 misc_en; 504 struct cpudata *cpu; 505 506 cpu = all_cpu_data[0]; 507 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 508 global.turbo_disabled = 509 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || 510 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); 511 } 512 513 static int min_perf_pct_min(void) 514 { 515 struct cpudata *cpu = all_cpu_data[0]; 516 int turbo_pstate = cpu->pstate.turbo_pstate; 517 518 return turbo_pstate ? 519 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; 520 } 521 522 static s16 intel_pstate_get_epb(struct cpudata *cpu_data) 523 { 524 u64 epb; 525 int ret; 526 527 if (!boot_cpu_has(X86_FEATURE_EPB)) 528 return -ENXIO; 529 530 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 531 if (ret) 532 return (s16)ret; 533 534 return (s16)(epb & 0x0f); 535 } 536 537 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) 538 { 539 s16 epp; 540 541 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 542 /* 543 * When hwp_req_data is 0, means that caller didn't read 544 * MSR_HWP_REQUEST, so need to read and get EPP. 545 */ 546 if (!hwp_req_data) { 547 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 548 &hwp_req_data); 549 if (epp) 550 return epp; 551 } 552 epp = (hwp_req_data >> 24) & 0xff; 553 } else { 554 /* When there is no EPP present, HWP uses EPB settings */ 555 epp = intel_pstate_get_epb(cpu_data); 556 } 557 558 return epp; 559 } 560 561 static int intel_pstate_set_epb(int cpu, s16 pref) 562 { 563 u64 epb; 564 int ret; 565 566 if (!boot_cpu_has(X86_FEATURE_EPB)) 567 return -ENXIO; 568 569 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 570 if (ret) 571 return ret; 572 573 epb = (epb & ~0x0f) | pref; 574 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 575 576 return 0; 577 } 578 579 /* 580 * EPP/EPB display strings corresponding to EPP index in the 581 * energy_perf_strings[] 582 * index String 583 *------------------------------------- 584 * 0 default 585 * 1 performance 586 * 2 balance_performance 587 * 3 balance_power 588 * 4 power 589 */ 590 static const char * const energy_perf_strings[] = { 591 "default", 592 "performance", 593 "balance_performance", 594 "balance_power", 595 "power", 596 NULL 597 }; 598 static const unsigned int epp_values[] = { 599 HWP_EPP_PERFORMANCE, 600 HWP_EPP_BALANCE_PERFORMANCE, 601 HWP_EPP_BALANCE_POWERSAVE, 602 HWP_EPP_POWERSAVE 603 }; 604 605 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) 606 { 607 s16 epp; 608 int index = -EINVAL; 609 610 epp = intel_pstate_get_epp(cpu_data, 0); 611 if (epp < 0) 612 return epp; 613 614 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 615 if (epp == HWP_EPP_PERFORMANCE) 616 return 1; 617 if (epp <= HWP_EPP_BALANCE_PERFORMANCE) 618 return 2; 619 if (epp <= HWP_EPP_BALANCE_POWERSAVE) 620 return 3; 621 else 622 return 4; 623 } else if (boot_cpu_has(X86_FEATURE_EPB)) { 624 /* 625 * Range: 626 * 0x00-0x03 : Performance 627 * 0x04-0x07 : Balance performance 628 * 0x08-0x0B : Balance power 629 * 0x0C-0x0F : Power 630 * The EPB is a 4 bit value, but our ranges restrict the 631 * value which can be set. Here only using top two bits 632 * effectively. 633 */ 634 index = (epp >> 2) + 1; 635 } 636 637 return index; 638 } 639 640 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, 641 int pref_index) 642 { 643 int epp = -EINVAL; 644 int ret; 645 646 if (!pref_index) 647 epp = cpu_data->epp_default; 648 649 mutex_lock(&intel_pstate_limits_lock); 650 651 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 652 u64 value; 653 654 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); 655 if (ret) 656 goto return_pref; 657 658 value &= ~GENMASK_ULL(31, 24); 659 660 if (epp == -EINVAL) 661 epp = epp_values[pref_index - 1]; 662 663 value |= (u64)epp << 24; 664 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); 665 } else { 666 if (epp == -EINVAL) 667 epp = (pref_index - 1) << 2; 668 ret = intel_pstate_set_epb(cpu_data->cpu, epp); 669 } 670 return_pref: 671 mutex_unlock(&intel_pstate_limits_lock); 672 673 return ret; 674 } 675 676 static ssize_t show_energy_performance_available_preferences( 677 struct cpufreq_policy *policy, char *buf) 678 { 679 int i = 0; 680 int ret = 0; 681 682 while (energy_perf_strings[i] != NULL) 683 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); 684 685 ret += sprintf(&buf[ret], "\n"); 686 687 return ret; 688 } 689 690 cpufreq_freq_attr_ro(energy_performance_available_preferences); 691 692 static ssize_t store_energy_performance_preference( 693 struct cpufreq_policy *policy, const char *buf, size_t count) 694 { 695 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 696 char str_preference[21]; 697 int ret; 698 699 ret = sscanf(buf, "%20s", str_preference); 700 if (ret != 1) 701 return -EINVAL; 702 703 ret = match_string(energy_perf_strings, -1, str_preference); 704 if (ret < 0) 705 return ret; 706 707 intel_pstate_set_energy_pref_index(cpu_data, ret); 708 return count; 709 } 710 711 static ssize_t show_energy_performance_preference( 712 struct cpufreq_policy *policy, char *buf) 713 { 714 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 715 int preference; 716 717 preference = intel_pstate_get_energy_pref_index(cpu_data); 718 if (preference < 0) 719 return preference; 720 721 return sprintf(buf, "%s\n", energy_perf_strings[preference]); 722 } 723 724 cpufreq_freq_attr_rw(energy_performance_preference); 725 726 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf) 727 { 728 struct cpudata *cpu; 729 u64 cap; 730 int ratio; 731 732 ratio = intel_pstate_get_cppc_guranteed(policy->cpu); 733 if (ratio <= 0) { 734 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 735 ratio = HWP_GUARANTEED_PERF(cap); 736 } 737 738 cpu = all_cpu_data[policy->cpu]; 739 740 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling); 741 } 742 743 cpufreq_freq_attr_ro(base_frequency); 744 745 static struct freq_attr *hwp_cpufreq_attrs[] = { 746 &energy_performance_preference, 747 &energy_performance_available_preferences, 748 &base_frequency, 749 NULL, 750 }; 751 752 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, 753 int *current_max) 754 { 755 u64 cap; 756 757 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); 758 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap); 759 if (global.no_turbo) 760 *current_max = HWP_GUARANTEED_PERF(cap); 761 else 762 *current_max = HWP_HIGHEST_PERF(cap); 763 764 *phy_max = HWP_HIGHEST_PERF(cap); 765 } 766 767 static void intel_pstate_hwp_set(unsigned int cpu) 768 { 769 struct cpudata *cpu_data = all_cpu_data[cpu]; 770 int max, min; 771 u64 value; 772 s16 epp; 773 774 max = cpu_data->max_perf_ratio; 775 min = cpu_data->min_perf_ratio; 776 777 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 778 min = max; 779 780 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 781 782 value &= ~HWP_MIN_PERF(~0L); 783 value |= HWP_MIN_PERF(min); 784 785 value &= ~HWP_MAX_PERF(~0L); 786 value |= HWP_MAX_PERF(max); 787 788 if (cpu_data->epp_policy == cpu_data->policy) 789 goto skip_epp; 790 791 cpu_data->epp_policy = cpu_data->policy; 792 793 if (cpu_data->epp_saved >= 0) { 794 epp = cpu_data->epp_saved; 795 cpu_data->epp_saved = -EINVAL; 796 goto update_epp; 797 } 798 799 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { 800 epp = intel_pstate_get_epp(cpu_data, value); 801 cpu_data->epp_powersave = epp; 802 /* If EPP read was failed, then don't try to write */ 803 if (epp < 0) 804 goto skip_epp; 805 806 epp = 0; 807 } else { 808 /* skip setting EPP, when saved value is invalid */ 809 if (cpu_data->epp_powersave < 0) 810 goto skip_epp; 811 812 /* 813 * No need to restore EPP when it is not zero. This 814 * means: 815 * - Policy is not changed 816 * - user has manually changed 817 * - Error reading EPB 818 */ 819 epp = intel_pstate_get_epp(cpu_data, value); 820 if (epp) 821 goto skip_epp; 822 823 epp = cpu_data->epp_powersave; 824 } 825 update_epp: 826 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { 827 value &= ~GENMASK_ULL(31, 24); 828 value |= (u64)epp << 24; 829 } else { 830 intel_pstate_set_epb(cpu, epp); 831 } 832 skip_epp: 833 WRITE_ONCE(cpu_data->hwp_req_cached, value); 834 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 835 } 836 837 static void intel_pstate_hwp_force_min_perf(int cpu) 838 { 839 u64 value; 840 int min_perf; 841 842 value = all_cpu_data[cpu]->hwp_req_cached; 843 value &= ~GENMASK_ULL(31, 0); 844 min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached); 845 846 /* Set hwp_max = hwp_min */ 847 value |= HWP_MAX_PERF(min_perf); 848 value |= HWP_MIN_PERF(min_perf); 849 850 /* Set EPP to min */ 851 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 852 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 853 854 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 855 } 856 857 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) 858 { 859 struct cpudata *cpu_data = all_cpu_data[policy->cpu]; 860 861 if (!hwp_active) 862 return 0; 863 864 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); 865 866 return 0; 867 } 868 869 static void intel_pstate_hwp_enable(struct cpudata *cpudata); 870 871 static int intel_pstate_resume(struct cpufreq_policy *policy) 872 { 873 if (!hwp_active) 874 return 0; 875 876 mutex_lock(&intel_pstate_limits_lock); 877 878 if (policy->cpu == 0) 879 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]); 880 881 all_cpu_data[policy->cpu]->epp_policy = 0; 882 intel_pstate_hwp_set(policy->cpu); 883 884 mutex_unlock(&intel_pstate_limits_lock); 885 886 return 0; 887 } 888 889 static void intel_pstate_update_policies(void) 890 { 891 int cpu; 892 893 for_each_possible_cpu(cpu) 894 cpufreq_update_policy(cpu); 895 } 896 897 static void intel_pstate_update_max_freq(unsigned int cpu) 898 { 899 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu); 900 struct cpudata *cpudata; 901 902 if (!policy) 903 return; 904 905 cpudata = all_cpu_data[cpu]; 906 policy->cpuinfo.max_freq = global.turbo_disabled_mf ? 907 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq; 908 909 refresh_frequency_limits(policy); 910 911 cpufreq_cpu_release(policy); 912 } 913 914 static void intel_pstate_update_limits(unsigned int cpu) 915 { 916 mutex_lock(&intel_pstate_driver_lock); 917 918 update_turbo_state(); 919 /* 920 * If turbo has been turned on or off globally, policy limits for 921 * all CPUs need to be updated to reflect that. 922 */ 923 if (global.turbo_disabled_mf != global.turbo_disabled) { 924 global.turbo_disabled_mf = global.turbo_disabled; 925 arch_set_max_freq_ratio(global.turbo_disabled); 926 for_each_possible_cpu(cpu) 927 intel_pstate_update_max_freq(cpu); 928 } else { 929 cpufreq_update_policy(cpu); 930 } 931 932 mutex_unlock(&intel_pstate_driver_lock); 933 } 934 935 /************************** sysfs begin ************************/ 936 #define show_one(file_name, object) \ 937 static ssize_t show_##file_name \ 938 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 939 { \ 940 return sprintf(buf, "%u\n", global.object); \ 941 } 942 943 static ssize_t intel_pstate_show_status(char *buf); 944 static int intel_pstate_update_status(const char *buf, size_t size); 945 946 static ssize_t show_status(struct kobject *kobj, 947 struct kobj_attribute *attr, char *buf) 948 { 949 ssize_t ret; 950 951 mutex_lock(&intel_pstate_driver_lock); 952 ret = intel_pstate_show_status(buf); 953 mutex_unlock(&intel_pstate_driver_lock); 954 955 return ret; 956 } 957 958 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, 959 const char *buf, size_t count) 960 { 961 char *p = memchr(buf, '\n', count); 962 int ret; 963 964 mutex_lock(&intel_pstate_driver_lock); 965 ret = intel_pstate_update_status(buf, p ? p - buf : count); 966 mutex_unlock(&intel_pstate_driver_lock); 967 968 return ret < 0 ? ret : count; 969 } 970 971 static ssize_t show_turbo_pct(struct kobject *kobj, 972 struct kobj_attribute *attr, char *buf) 973 { 974 struct cpudata *cpu; 975 int total, no_turbo, turbo_pct; 976 uint32_t turbo_fp; 977 978 mutex_lock(&intel_pstate_driver_lock); 979 980 if (!intel_pstate_driver) { 981 mutex_unlock(&intel_pstate_driver_lock); 982 return -EAGAIN; 983 } 984 985 cpu = all_cpu_data[0]; 986 987 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 988 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 989 turbo_fp = div_fp(no_turbo, total); 990 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 991 992 mutex_unlock(&intel_pstate_driver_lock); 993 994 return sprintf(buf, "%u\n", turbo_pct); 995 } 996 997 static ssize_t show_num_pstates(struct kobject *kobj, 998 struct kobj_attribute *attr, char *buf) 999 { 1000 struct cpudata *cpu; 1001 int total; 1002 1003 mutex_lock(&intel_pstate_driver_lock); 1004 1005 if (!intel_pstate_driver) { 1006 mutex_unlock(&intel_pstate_driver_lock); 1007 return -EAGAIN; 1008 } 1009 1010 cpu = all_cpu_data[0]; 1011 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1012 1013 mutex_unlock(&intel_pstate_driver_lock); 1014 1015 return sprintf(buf, "%u\n", total); 1016 } 1017 1018 static ssize_t show_no_turbo(struct kobject *kobj, 1019 struct kobj_attribute *attr, char *buf) 1020 { 1021 ssize_t ret; 1022 1023 mutex_lock(&intel_pstate_driver_lock); 1024 1025 if (!intel_pstate_driver) { 1026 mutex_unlock(&intel_pstate_driver_lock); 1027 return -EAGAIN; 1028 } 1029 1030 update_turbo_state(); 1031 if (global.turbo_disabled) 1032 ret = sprintf(buf, "%u\n", global.turbo_disabled); 1033 else 1034 ret = sprintf(buf, "%u\n", global.no_turbo); 1035 1036 mutex_unlock(&intel_pstate_driver_lock); 1037 1038 return ret; 1039 } 1040 1041 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, 1042 const char *buf, size_t count) 1043 { 1044 unsigned int input; 1045 int ret; 1046 1047 ret = sscanf(buf, "%u", &input); 1048 if (ret != 1) 1049 return -EINVAL; 1050 1051 mutex_lock(&intel_pstate_driver_lock); 1052 1053 if (!intel_pstate_driver) { 1054 mutex_unlock(&intel_pstate_driver_lock); 1055 return -EAGAIN; 1056 } 1057 1058 mutex_lock(&intel_pstate_limits_lock); 1059 1060 update_turbo_state(); 1061 if (global.turbo_disabled) { 1062 pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); 1063 mutex_unlock(&intel_pstate_limits_lock); 1064 mutex_unlock(&intel_pstate_driver_lock); 1065 return -EPERM; 1066 } 1067 1068 global.no_turbo = clamp_t(int, input, 0, 1); 1069 1070 if (global.no_turbo) { 1071 struct cpudata *cpu = all_cpu_data[0]; 1072 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; 1073 1074 /* Squash the global minimum into the permitted range. */ 1075 if (global.min_perf_pct > pct) 1076 global.min_perf_pct = pct; 1077 } 1078 1079 mutex_unlock(&intel_pstate_limits_lock); 1080 1081 intel_pstate_update_policies(); 1082 1083 mutex_unlock(&intel_pstate_driver_lock); 1084 1085 return count; 1086 } 1087 1088 static struct cpufreq_driver intel_pstate; 1089 1090 static void update_qos_request(enum freq_qos_req_type type) 1091 { 1092 int max_state, turbo_max, freq, i, perf_pct; 1093 struct freq_qos_request *req; 1094 struct cpufreq_policy *policy; 1095 1096 for_each_possible_cpu(i) { 1097 struct cpudata *cpu = all_cpu_data[i]; 1098 1099 policy = cpufreq_cpu_get(i); 1100 if (!policy) 1101 continue; 1102 1103 req = policy->driver_data; 1104 cpufreq_cpu_put(policy); 1105 1106 if (!req) 1107 continue; 1108 1109 if (hwp_active) 1110 intel_pstate_get_hwp_max(i, &turbo_max, &max_state); 1111 else 1112 turbo_max = cpu->pstate.turbo_pstate; 1113 1114 if (type == FREQ_QOS_MIN) { 1115 perf_pct = global.min_perf_pct; 1116 } else { 1117 req++; 1118 perf_pct = global.max_perf_pct; 1119 } 1120 1121 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100); 1122 freq *= cpu->pstate.scaling; 1123 1124 if (freq_qos_update_request(req, freq) < 0) 1125 pr_warn("Failed to update freq constraint: CPU%d\n", i); 1126 } 1127 } 1128 1129 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b, 1130 const char *buf, size_t count) 1131 { 1132 unsigned int input; 1133 int ret; 1134 1135 ret = sscanf(buf, "%u", &input); 1136 if (ret != 1) 1137 return -EINVAL; 1138 1139 mutex_lock(&intel_pstate_driver_lock); 1140 1141 if (!intel_pstate_driver) { 1142 mutex_unlock(&intel_pstate_driver_lock); 1143 return -EAGAIN; 1144 } 1145 1146 mutex_lock(&intel_pstate_limits_lock); 1147 1148 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); 1149 1150 mutex_unlock(&intel_pstate_limits_lock); 1151 1152 if (intel_pstate_driver == &intel_pstate) 1153 intel_pstate_update_policies(); 1154 else 1155 update_qos_request(FREQ_QOS_MAX); 1156 1157 mutex_unlock(&intel_pstate_driver_lock); 1158 1159 return count; 1160 } 1161 1162 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b, 1163 const char *buf, size_t count) 1164 { 1165 unsigned int input; 1166 int ret; 1167 1168 ret = sscanf(buf, "%u", &input); 1169 if (ret != 1) 1170 return -EINVAL; 1171 1172 mutex_lock(&intel_pstate_driver_lock); 1173 1174 if (!intel_pstate_driver) { 1175 mutex_unlock(&intel_pstate_driver_lock); 1176 return -EAGAIN; 1177 } 1178 1179 mutex_lock(&intel_pstate_limits_lock); 1180 1181 global.min_perf_pct = clamp_t(int, input, 1182 min_perf_pct_min(), global.max_perf_pct); 1183 1184 mutex_unlock(&intel_pstate_limits_lock); 1185 1186 if (intel_pstate_driver == &intel_pstate) 1187 intel_pstate_update_policies(); 1188 else 1189 update_qos_request(FREQ_QOS_MIN); 1190 1191 mutex_unlock(&intel_pstate_driver_lock); 1192 1193 return count; 1194 } 1195 1196 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj, 1197 struct kobj_attribute *attr, char *buf) 1198 { 1199 return sprintf(buf, "%u\n", hwp_boost); 1200 } 1201 1202 static ssize_t store_hwp_dynamic_boost(struct kobject *a, 1203 struct kobj_attribute *b, 1204 const char *buf, size_t count) 1205 { 1206 unsigned int input; 1207 int ret; 1208 1209 ret = kstrtouint(buf, 10, &input); 1210 if (ret) 1211 return ret; 1212 1213 mutex_lock(&intel_pstate_driver_lock); 1214 hwp_boost = !!input; 1215 intel_pstate_update_policies(); 1216 mutex_unlock(&intel_pstate_driver_lock); 1217 1218 return count; 1219 } 1220 1221 show_one(max_perf_pct, max_perf_pct); 1222 show_one(min_perf_pct, min_perf_pct); 1223 1224 define_one_global_rw(status); 1225 define_one_global_rw(no_turbo); 1226 define_one_global_rw(max_perf_pct); 1227 define_one_global_rw(min_perf_pct); 1228 define_one_global_ro(turbo_pct); 1229 define_one_global_ro(num_pstates); 1230 define_one_global_rw(hwp_dynamic_boost); 1231 1232 static struct attribute *intel_pstate_attributes[] = { 1233 &status.attr, 1234 &no_turbo.attr, 1235 &turbo_pct.attr, 1236 &num_pstates.attr, 1237 NULL 1238 }; 1239 1240 static const struct attribute_group intel_pstate_attr_group = { 1241 .attrs = intel_pstate_attributes, 1242 }; 1243 1244 static void __init intel_pstate_sysfs_expose_params(void) 1245 { 1246 struct kobject *intel_pstate_kobject; 1247 int rc; 1248 1249 intel_pstate_kobject = kobject_create_and_add("intel_pstate", 1250 &cpu_subsys.dev_root->kobj); 1251 if (WARN_ON(!intel_pstate_kobject)) 1252 return; 1253 1254 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); 1255 if (WARN_ON(rc)) 1256 return; 1257 1258 /* 1259 * If per cpu limits are enforced there are no global limits, so 1260 * return without creating max/min_perf_pct attributes 1261 */ 1262 if (per_cpu_limits) 1263 return; 1264 1265 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); 1266 WARN_ON(rc); 1267 1268 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); 1269 WARN_ON(rc); 1270 1271 if (hwp_active) { 1272 rc = sysfs_create_file(intel_pstate_kobject, 1273 &hwp_dynamic_boost.attr); 1274 WARN_ON(rc); 1275 } 1276 } 1277 /************************** sysfs end ************************/ 1278 1279 static void intel_pstate_hwp_enable(struct cpudata *cpudata) 1280 { 1281 /* First disable HWP notification interrupt as we don't process them */ 1282 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1283 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1284 1285 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1286 cpudata->epp_policy = 0; 1287 if (cpudata->epp_default == -EINVAL) 1288 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); 1289 } 1290 1291 #define MSR_IA32_POWER_CTL_BIT_EE 19 1292 1293 /* Disable energy efficiency optimization */ 1294 static void intel_pstate_disable_ee(int cpu) 1295 { 1296 u64 power_ctl; 1297 int ret; 1298 1299 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); 1300 if (ret) 1301 return; 1302 1303 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { 1304 pr_info("Disabling energy efficiency optimization\n"); 1305 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1306 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); 1307 } 1308 } 1309 1310 static int atom_get_min_pstate(void) 1311 { 1312 u64 value; 1313 1314 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1315 return (value >> 8) & 0x7F; 1316 } 1317 1318 static int atom_get_max_pstate(void) 1319 { 1320 u64 value; 1321 1322 rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1323 return (value >> 16) & 0x7F; 1324 } 1325 1326 static int atom_get_turbo_pstate(void) 1327 { 1328 u64 value; 1329 1330 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 1331 return value & 0x7F; 1332 } 1333 1334 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 1335 { 1336 u64 val; 1337 int32_t vid_fp; 1338 u32 vid; 1339 1340 val = (u64)pstate << 8; 1341 if (global.no_turbo && !global.turbo_disabled) 1342 val |= (u64)1 << 32; 1343 1344 vid_fp = cpudata->vid.min + mul_fp( 1345 int_tofp(pstate - cpudata->pstate.min_pstate), 1346 cpudata->vid.ratio); 1347 1348 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); 1349 vid = ceiling_fp(vid_fp); 1350 1351 if (pstate > cpudata->pstate.max_pstate) 1352 vid = cpudata->vid.turbo; 1353 1354 return val | vid; 1355 } 1356 1357 static int silvermont_get_scaling(void) 1358 { 1359 u64 value; 1360 int i; 1361 /* Defined in Table 35-6 from SDM (Sept 2015) */ 1362 static int silvermont_freq_table[] = { 1363 83300, 100000, 133300, 116700, 80000}; 1364 1365 rdmsrl(MSR_FSB_FREQ, value); 1366 i = value & 0x7; 1367 WARN_ON(i > 4); 1368 1369 return silvermont_freq_table[i]; 1370 } 1371 1372 static int airmont_get_scaling(void) 1373 { 1374 u64 value; 1375 int i; 1376 /* Defined in Table 35-10 from SDM (Sept 2015) */ 1377 static int airmont_freq_table[] = { 1378 83300, 100000, 133300, 116700, 80000, 1379 93300, 90000, 88900, 87500}; 1380 1381 rdmsrl(MSR_FSB_FREQ, value); 1382 i = value & 0xF; 1383 WARN_ON(i > 8); 1384 1385 return airmont_freq_table[i]; 1386 } 1387 1388 static void atom_get_vid(struct cpudata *cpudata) 1389 { 1390 u64 value; 1391 1392 rdmsrl(MSR_ATOM_CORE_VIDS, value); 1393 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 1394 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 1395 cpudata->vid.ratio = div_fp( 1396 cpudata->vid.max - cpudata->vid.min, 1397 int_tofp(cpudata->pstate.max_pstate - 1398 cpudata->pstate.min_pstate)); 1399 1400 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 1401 cpudata->vid.turbo = value & 0x7f; 1402 } 1403 1404 static int core_get_min_pstate(void) 1405 { 1406 u64 value; 1407 1408 rdmsrl(MSR_PLATFORM_INFO, value); 1409 return (value >> 40) & 0xFF; 1410 } 1411 1412 static int core_get_max_pstate_physical(void) 1413 { 1414 u64 value; 1415 1416 rdmsrl(MSR_PLATFORM_INFO, value); 1417 return (value >> 8) & 0xFF; 1418 } 1419 1420 static int core_get_tdp_ratio(u64 plat_info) 1421 { 1422 /* Check how many TDP levels present */ 1423 if (plat_info & 0x600000000) { 1424 u64 tdp_ctrl; 1425 u64 tdp_ratio; 1426 int tdp_msr; 1427 int err; 1428 1429 /* Get the TDP level (0, 1, 2) to get ratios */ 1430 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 1431 if (err) 1432 return err; 1433 1434 /* TDP MSR are continuous starting at 0x648 */ 1435 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 1436 err = rdmsrl_safe(tdp_msr, &tdp_ratio); 1437 if (err) 1438 return err; 1439 1440 /* For level 1 and 2, bits[23:16] contain the ratio */ 1441 if (tdp_ctrl & 0x03) 1442 tdp_ratio >>= 16; 1443 1444 tdp_ratio &= 0xff; /* ratios are only 8 bits long */ 1445 pr_debug("tdp_ratio %x\n", (int)tdp_ratio); 1446 1447 return (int)tdp_ratio; 1448 } 1449 1450 return -ENXIO; 1451 } 1452 1453 static int core_get_max_pstate(void) 1454 { 1455 u64 tar; 1456 u64 plat_info; 1457 int max_pstate; 1458 int tdp_ratio; 1459 int err; 1460 1461 rdmsrl(MSR_PLATFORM_INFO, plat_info); 1462 max_pstate = (plat_info >> 8) & 0xFF; 1463 1464 tdp_ratio = core_get_tdp_ratio(plat_info); 1465 if (tdp_ratio <= 0) 1466 return max_pstate; 1467 1468 if (hwp_active) { 1469 /* Turbo activation ratio is not used on HWP platforms */ 1470 return tdp_ratio; 1471 } 1472 1473 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); 1474 if (!err) { 1475 int tar_levels; 1476 1477 /* Do some sanity checking for safety */ 1478 tar_levels = tar & 0xff; 1479 if (tdp_ratio - 1 == tar_levels) { 1480 max_pstate = tar_levels; 1481 pr_debug("max_pstate=TAC %x\n", max_pstate); 1482 } 1483 } 1484 1485 return max_pstate; 1486 } 1487 1488 static int core_get_turbo_pstate(void) 1489 { 1490 u64 value; 1491 int nont, ret; 1492 1493 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1494 nont = core_get_max_pstate(); 1495 ret = (value) & 255; 1496 if (ret <= nont) 1497 ret = nont; 1498 return ret; 1499 } 1500 1501 static inline int core_get_scaling(void) 1502 { 1503 return 100000; 1504 } 1505 1506 static u64 core_get_val(struct cpudata *cpudata, int pstate) 1507 { 1508 u64 val; 1509 1510 val = (u64)pstate << 8; 1511 if (global.no_turbo && !global.turbo_disabled) 1512 val |= (u64)1 << 32; 1513 1514 return val; 1515 } 1516 1517 static int knl_get_aperf_mperf_shift(void) 1518 { 1519 return 10; 1520 } 1521 1522 static int knl_get_turbo_pstate(void) 1523 { 1524 u64 value; 1525 int nont, ret; 1526 1527 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); 1528 nont = core_get_max_pstate(); 1529 ret = (((value) >> 8) & 0xFF); 1530 if (ret <= nont) 1531 ret = nont; 1532 return ret; 1533 } 1534 1535 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) 1536 { 1537 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); 1538 cpu->pstate.current_pstate = pstate; 1539 /* 1540 * Generally, there is no guarantee that this code will always run on 1541 * the CPU being updated, so force the register update to run on the 1542 * right CPU. 1543 */ 1544 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 1545 pstate_funcs.get_val(cpu, pstate)); 1546 } 1547 1548 static void intel_pstate_set_min_pstate(struct cpudata *cpu) 1549 { 1550 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); 1551 } 1552 1553 static void intel_pstate_max_within_limits(struct cpudata *cpu) 1554 { 1555 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); 1556 1557 update_turbo_state(); 1558 intel_pstate_set_pstate(cpu, pstate); 1559 } 1560 1561 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 1562 { 1563 cpu->pstate.min_pstate = pstate_funcs.get_min(); 1564 cpu->pstate.max_pstate = pstate_funcs.get_max(); 1565 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); 1566 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); 1567 cpu->pstate.scaling = pstate_funcs.get_scaling(); 1568 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; 1569 1570 if (hwp_active && !hwp_mode_bdw) { 1571 unsigned int phy_max, current_max; 1572 1573 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max); 1574 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling; 1575 } else { 1576 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 1577 } 1578 1579 if (pstate_funcs.get_aperf_mperf_shift) 1580 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); 1581 1582 if (pstate_funcs.get_vid) 1583 pstate_funcs.get_vid(cpu); 1584 1585 intel_pstate_set_min_pstate(cpu); 1586 } 1587 1588 /* 1589 * Long hold time will keep high perf limits for long time, 1590 * which negatively impacts perf/watt for some workloads, 1591 * like specpower. 3ms is based on experiements on some 1592 * workoads. 1593 */ 1594 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC; 1595 1596 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu) 1597 { 1598 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached); 1599 u32 max_limit = (hwp_req & 0xff00) >> 8; 1600 u32 min_limit = (hwp_req & 0xff); 1601 u32 boost_level1; 1602 1603 /* 1604 * Cases to consider (User changes via sysfs or boot time): 1605 * If, P0 (Turbo max) = P1 (Guaranteed max) = min: 1606 * No boost, return. 1607 * If, P0 (Turbo max) > P1 (Guaranteed max) = min: 1608 * Should result in one level boost only for P0. 1609 * If, P0 (Turbo max) = P1 (Guaranteed max) > min: 1610 * Should result in two level boost: 1611 * (min + p1)/2 and P1. 1612 * If, P0 (Turbo max) > P1 (Guaranteed max) > min: 1613 * Should result in three level boost: 1614 * (min + p1)/2, P1 and P0. 1615 */ 1616 1617 /* If max and min are equal or already at max, nothing to boost */ 1618 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit) 1619 return; 1620 1621 if (!cpu->hwp_boost_min) 1622 cpu->hwp_boost_min = min_limit; 1623 1624 /* level at half way mark between min and guranteed */ 1625 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1; 1626 1627 if (cpu->hwp_boost_min < boost_level1) 1628 cpu->hwp_boost_min = boost_level1; 1629 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1630 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached); 1631 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) && 1632 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached)) 1633 cpu->hwp_boost_min = max_limit; 1634 else 1635 return; 1636 1637 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 1638 wrmsrl(MSR_HWP_REQUEST, hwp_req); 1639 cpu->last_update = cpu->sample.time; 1640 } 1641 1642 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu) 1643 { 1644 if (cpu->hwp_boost_min) { 1645 bool expired; 1646 1647 /* Check if we are idle for hold time to boost down */ 1648 expired = time_after64(cpu->sample.time, cpu->last_update + 1649 hwp_boost_hold_time_ns); 1650 if (expired) { 1651 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 1652 cpu->hwp_boost_min = 0; 1653 } 1654 } 1655 cpu->last_update = cpu->sample.time; 1656 } 1657 1658 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu, 1659 u64 time) 1660 { 1661 cpu->sample.time = time; 1662 1663 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) { 1664 bool do_io = false; 1665 1666 cpu->sched_flags = 0; 1667 /* 1668 * Set iowait_boost flag and update time. Since IO WAIT flag 1669 * is set all the time, we can't just conclude that there is 1670 * some IO bound activity is scheduled on this CPU with just 1671 * one occurrence. If we receive at least two in two 1672 * consecutive ticks, then we treat as boost candidate. 1673 */ 1674 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC)) 1675 do_io = true; 1676 1677 cpu->last_io_update = time; 1678 1679 if (do_io) 1680 intel_pstate_hwp_boost_up(cpu); 1681 1682 } else { 1683 intel_pstate_hwp_boost_down(cpu); 1684 } 1685 } 1686 1687 static inline void intel_pstate_update_util_hwp(struct update_util_data *data, 1688 u64 time, unsigned int flags) 1689 { 1690 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1691 1692 cpu->sched_flags |= flags; 1693 1694 if (smp_processor_id() == cpu->cpu) 1695 intel_pstate_update_util_hwp_local(cpu, time); 1696 } 1697 1698 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) 1699 { 1700 struct sample *sample = &cpu->sample; 1701 1702 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); 1703 } 1704 1705 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) 1706 { 1707 u64 aperf, mperf; 1708 unsigned long flags; 1709 u64 tsc; 1710 1711 local_irq_save(flags); 1712 rdmsrl(MSR_IA32_APERF, aperf); 1713 rdmsrl(MSR_IA32_MPERF, mperf); 1714 tsc = rdtsc(); 1715 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 1716 local_irq_restore(flags); 1717 return false; 1718 } 1719 local_irq_restore(flags); 1720 1721 cpu->last_sample_time = cpu->sample.time; 1722 cpu->sample.time = time; 1723 cpu->sample.aperf = aperf; 1724 cpu->sample.mperf = mperf; 1725 cpu->sample.tsc = tsc; 1726 cpu->sample.aperf -= cpu->prev_aperf; 1727 cpu->sample.mperf -= cpu->prev_mperf; 1728 cpu->sample.tsc -= cpu->prev_tsc; 1729 1730 cpu->prev_aperf = aperf; 1731 cpu->prev_mperf = mperf; 1732 cpu->prev_tsc = tsc; 1733 /* 1734 * First time this function is invoked in a given cycle, all of the 1735 * previous sample data fields are equal to zero or stale and they must 1736 * be populated with meaningful numbers for things to work, so assume 1737 * that sample.time will always be reset before setting the utilization 1738 * update hook and make the caller skip the sample then. 1739 */ 1740 if (cpu->last_sample_time) { 1741 intel_pstate_calc_avg_perf(cpu); 1742 return true; 1743 } 1744 return false; 1745 } 1746 1747 static inline int32_t get_avg_frequency(struct cpudata *cpu) 1748 { 1749 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); 1750 } 1751 1752 static inline int32_t get_avg_pstate(struct cpudata *cpu) 1753 { 1754 return mul_ext_fp(cpu->pstate.max_pstate_physical, 1755 cpu->sample.core_avg_perf); 1756 } 1757 1758 static inline int32_t get_target_pstate(struct cpudata *cpu) 1759 { 1760 struct sample *sample = &cpu->sample; 1761 int32_t busy_frac; 1762 int target, avg_pstate; 1763 1764 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, 1765 sample->tsc); 1766 1767 if (busy_frac < cpu->iowait_boost) 1768 busy_frac = cpu->iowait_boost; 1769 1770 sample->busy_scaled = busy_frac * 100; 1771 1772 target = global.no_turbo || global.turbo_disabled ? 1773 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 1774 target += target >> 2; 1775 target = mul_fp(target, busy_frac); 1776 if (target < cpu->pstate.min_pstate) 1777 target = cpu->pstate.min_pstate; 1778 1779 /* 1780 * If the average P-state during the previous cycle was higher than the 1781 * current target, add 50% of the difference to the target to reduce 1782 * possible performance oscillations and offset possible performance 1783 * loss related to moving the workload from one CPU to another within 1784 * a package/module. 1785 */ 1786 avg_pstate = get_avg_pstate(cpu); 1787 if (avg_pstate > target) 1788 target += (avg_pstate - target) >> 1; 1789 1790 return target; 1791 } 1792 1793 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) 1794 { 1795 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); 1796 int max_pstate = max(min_pstate, cpu->max_perf_ratio); 1797 1798 return clamp_t(int, pstate, min_pstate, max_pstate); 1799 } 1800 1801 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) 1802 { 1803 if (pstate == cpu->pstate.current_pstate) 1804 return; 1805 1806 cpu->pstate.current_pstate = pstate; 1807 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 1808 } 1809 1810 static void intel_pstate_adjust_pstate(struct cpudata *cpu) 1811 { 1812 int from = cpu->pstate.current_pstate; 1813 struct sample *sample; 1814 int target_pstate; 1815 1816 update_turbo_state(); 1817 1818 target_pstate = get_target_pstate(cpu); 1819 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 1820 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); 1821 intel_pstate_update_pstate(cpu, target_pstate); 1822 1823 sample = &cpu->sample; 1824 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), 1825 fp_toint(sample->busy_scaled), 1826 from, 1827 cpu->pstate.current_pstate, 1828 sample->mperf, 1829 sample->aperf, 1830 sample->tsc, 1831 get_avg_frequency(cpu), 1832 fp_toint(cpu->iowait_boost * 100)); 1833 } 1834 1835 static void intel_pstate_update_util(struct update_util_data *data, u64 time, 1836 unsigned int flags) 1837 { 1838 struct cpudata *cpu = container_of(data, struct cpudata, update_util); 1839 u64 delta_ns; 1840 1841 /* Don't allow remote callbacks */ 1842 if (smp_processor_id() != cpu->cpu) 1843 return; 1844 1845 delta_ns = time - cpu->last_update; 1846 if (flags & SCHED_CPUFREQ_IOWAIT) { 1847 /* Start over if the CPU may have been idle. */ 1848 if (delta_ns > TICK_NSEC) { 1849 cpu->iowait_boost = ONE_EIGHTH_FP; 1850 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) { 1851 cpu->iowait_boost <<= 1; 1852 if (cpu->iowait_boost > int_tofp(1)) 1853 cpu->iowait_boost = int_tofp(1); 1854 } else { 1855 cpu->iowait_boost = ONE_EIGHTH_FP; 1856 } 1857 } else if (cpu->iowait_boost) { 1858 /* Clear iowait_boost if the CPU may have been idle. */ 1859 if (delta_ns > TICK_NSEC) 1860 cpu->iowait_boost = 0; 1861 else 1862 cpu->iowait_boost >>= 1; 1863 } 1864 cpu->last_update = time; 1865 delta_ns = time - cpu->sample.time; 1866 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) 1867 return; 1868 1869 if (intel_pstate_sample(cpu, time)) 1870 intel_pstate_adjust_pstate(cpu); 1871 } 1872 1873 static struct pstate_funcs core_funcs = { 1874 .get_max = core_get_max_pstate, 1875 .get_max_physical = core_get_max_pstate_physical, 1876 .get_min = core_get_min_pstate, 1877 .get_turbo = core_get_turbo_pstate, 1878 .get_scaling = core_get_scaling, 1879 .get_val = core_get_val, 1880 }; 1881 1882 static const struct pstate_funcs silvermont_funcs = { 1883 .get_max = atom_get_max_pstate, 1884 .get_max_physical = atom_get_max_pstate, 1885 .get_min = atom_get_min_pstate, 1886 .get_turbo = atom_get_turbo_pstate, 1887 .get_val = atom_get_val, 1888 .get_scaling = silvermont_get_scaling, 1889 .get_vid = atom_get_vid, 1890 }; 1891 1892 static const struct pstate_funcs airmont_funcs = { 1893 .get_max = atom_get_max_pstate, 1894 .get_max_physical = atom_get_max_pstate, 1895 .get_min = atom_get_min_pstate, 1896 .get_turbo = atom_get_turbo_pstate, 1897 .get_val = atom_get_val, 1898 .get_scaling = airmont_get_scaling, 1899 .get_vid = atom_get_vid, 1900 }; 1901 1902 static const struct pstate_funcs knl_funcs = { 1903 .get_max = core_get_max_pstate, 1904 .get_max_physical = core_get_max_pstate_physical, 1905 .get_min = core_get_min_pstate, 1906 .get_turbo = knl_get_turbo_pstate, 1907 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, 1908 .get_scaling = core_get_scaling, 1909 .get_val = core_get_val, 1910 }; 1911 1912 #define X86_MATCH(model, policy) \ 1913 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 1914 X86_FEATURE_APERFMPERF, &policy) 1915 1916 static const struct x86_cpu_id intel_pstate_cpu_ids[] = { 1917 X86_MATCH(SANDYBRIDGE, core_funcs), 1918 X86_MATCH(SANDYBRIDGE_X, core_funcs), 1919 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs), 1920 X86_MATCH(IVYBRIDGE, core_funcs), 1921 X86_MATCH(HASWELL, core_funcs), 1922 X86_MATCH(BROADWELL, core_funcs), 1923 X86_MATCH(IVYBRIDGE_X, core_funcs), 1924 X86_MATCH(HASWELL_X, core_funcs), 1925 X86_MATCH(HASWELL_L, core_funcs), 1926 X86_MATCH(HASWELL_G, core_funcs), 1927 X86_MATCH(BROADWELL_G, core_funcs), 1928 X86_MATCH(ATOM_AIRMONT, airmont_funcs), 1929 X86_MATCH(SKYLAKE_L, core_funcs), 1930 X86_MATCH(BROADWELL_X, core_funcs), 1931 X86_MATCH(SKYLAKE, core_funcs), 1932 X86_MATCH(BROADWELL_D, core_funcs), 1933 X86_MATCH(XEON_PHI_KNL, knl_funcs), 1934 X86_MATCH(XEON_PHI_KNM, knl_funcs), 1935 X86_MATCH(ATOM_GOLDMONT, core_funcs), 1936 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs), 1937 X86_MATCH(SKYLAKE_X, core_funcs), 1938 {} 1939 }; 1940 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); 1941 1942 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { 1943 X86_MATCH(BROADWELL_D, core_funcs), 1944 X86_MATCH(BROADWELL_X, core_funcs), 1945 X86_MATCH(SKYLAKE_X, core_funcs), 1946 {} 1947 }; 1948 1949 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { 1950 X86_MATCH(KABYLAKE, core_funcs), 1951 {} 1952 }; 1953 1954 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = { 1955 X86_MATCH(SKYLAKE_X, core_funcs), 1956 X86_MATCH(SKYLAKE, core_funcs), 1957 {} 1958 }; 1959 1960 static int intel_pstate_init_cpu(unsigned int cpunum) 1961 { 1962 struct cpudata *cpu; 1963 1964 cpu = all_cpu_data[cpunum]; 1965 1966 if (!cpu) { 1967 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); 1968 if (!cpu) 1969 return -ENOMEM; 1970 1971 all_cpu_data[cpunum] = cpu; 1972 1973 cpu->epp_default = -EINVAL; 1974 cpu->epp_powersave = -EINVAL; 1975 cpu->epp_saved = -EINVAL; 1976 } 1977 1978 cpu = all_cpu_data[cpunum]; 1979 1980 cpu->cpu = cpunum; 1981 1982 if (hwp_active) { 1983 const struct x86_cpu_id *id; 1984 1985 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); 1986 if (id) 1987 intel_pstate_disable_ee(cpunum); 1988 1989 intel_pstate_hwp_enable(cpu); 1990 1991 id = x86_match_cpu(intel_pstate_hwp_boost_ids); 1992 if (id && intel_pstate_acpi_pm_profile_server()) 1993 hwp_boost = true; 1994 } 1995 1996 intel_pstate_get_cpu_pstates(cpu); 1997 1998 pr_debug("controlling: cpu %d\n", cpunum); 1999 2000 return 0; 2001 } 2002 2003 static void intel_pstate_set_update_util_hook(unsigned int cpu_num) 2004 { 2005 struct cpudata *cpu = all_cpu_data[cpu_num]; 2006 2007 if (hwp_active && !hwp_boost) 2008 return; 2009 2010 if (cpu->update_util_set) 2011 return; 2012 2013 /* Prevent intel_pstate_update_util() from using stale data. */ 2014 cpu->sample.time = 0; 2015 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, 2016 (hwp_active ? 2017 intel_pstate_update_util_hwp : 2018 intel_pstate_update_util)); 2019 cpu->update_util_set = true; 2020 } 2021 2022 static void intel_pstate_clear_update_util_hook(unsigned int cpu) 2023 { 2024 struct cpudata *cpu_data = all_cpu_data[cpu]; 2025 2026 if (!cpu_data->update_util_set) 2027 return; 2028 2029 cpufreq_remove_update_util_hook(cpu); 2030 cpu_data->update_util_set = false; 2031 synchronize_rcu(); 2032 } 2033 2034 static int intel_pstate_get_max_freq(struct cpudata *cpu) 2035 { 2036 return global.turbo_disabled || global.no_turbo ? 2037 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2038 } 2039 2040 static void intel_pstate_update_perf_limits(struct cpudata *cpu, 2041 unsigned int policy_min, 2042 unsigned int policy_max) 2043 { 2044 int max_freq = intel_pstate_get_max_freq(cpu); 2045 int32_t max_policy_perf, min_policy_perf; 2046 int max_state, turbo_max; 2047 2048 /* 2049 * HWP needs some special consideration, because on BDX the 2050 * HWP_REQUEST uses abstract value to represent performance 2051 * rather than pure ratios. 2052 */ 2053 if (hwp_active) { 2054 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state); 2055 } else { 2056 max_state = global.no_turbo || global.turbo_disabled ? 2057 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2058 turbo_max = cpu->pstate.turbo_pstate; 2059 } 2060 2061 max_policy_perf = max_state * policy_max / max_freq; 2062 if (policy_max == policy_min) { 2063 min_policy_perf = max_policy_perf; 2064 } else { 2065 min_policy_perf = max_state * policy_min / max_freq; 2066 min_policy_perf = clamp_t(int32_t, min_policy_perf, 2067 0, max_policy_perf); 2068 } 2069 2070 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n", 2071 cpu->cpu, max_state, min_policy_perf, max_policy_perf); 2072 2073 /* Normalize user input to [min_perf, max_perf] */ 2074 if (per_cpu_limits) { 2075 cpu->min_perf_ratio = min_policy_perf; 2076 cpu->max_perf_ratio = max_policy_perf; 2077 } else { 2078 int32_t global_min, global_max; 2079 2080 /* Global limits are in percent of the maximum turbo P-state. */ 2081 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2082 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2083 global_min = clamp_t(int32_t, global_min, 0, global_max); 2084 2085 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu, 2086 global_min, global_max); 2087 2088 cpu->min_perf_ratio = max(min_policy_perf, global_min); 2089 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); 2090 cpu->max_perf_ratio = min(max_policy_perf, global_max); 2091 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); 2092 2093 /* Make sure min_perf <= max_perf */ 2094 cpu->min_perf_ratio = min(cpu->min_perf_ratio, 2095 cpu->max_perf_ratio); 2096 2097 } 2098 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu, 2099 cpu->max_perf_ratio, 2100 cpu->min_perf_ratio); 2101 } 2102 2103 static int intel_pstate_set_policy(struct cpufreq_policy *policy) 2104 { 2105 struct cpudata *cpu; 2106 2107 if (!policy->cpuinfo.max_freq) 2108 return -ENODEV; 2109 2110 pr_debug("set_policy cpuinfo.max %u policy->max %u\n", 2111 policy->cpuinfo.max_freq, policy->max); 2112 2113 cpu = all_cpu_data[policy->cpu]; 2114 cpu->policy = policy->policy; 2115 2116 mutex_lock(&intel_pstate_limits_lock); 2117 2118 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2119 2120 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { 2121 /* 2122 * NOHZ_FULL CPUs need this as the governor callback may not 2123 * be invoked on them. 2124 */ 2125 intel_pstate_clear_update_util_hook(policy->cpu); 2126 intel_pstate_max_within_limits(cpu); 2127 } else { 2128 intel_pstate_set_update_util_hook(policy->cpu); 2129 } 2130 2131 if (hwp_active) { 2132 /* 2133 * When hwp_boost was active before and dynamically it 2134 * was turned off, in that case we need to clear the 2135 * update util hook. 2136 */ 2137 if (!hwp_boost) 2138 intel_pstate_clear_update_util_hook(policy->cpu); 2139 intel_pstate_hwp_set(policy->cpu); 2140 } 2141 2142 mutex_unlock(&intel_pstate_limits_lock); 2143 2144 return 0; 2145 } 2146 2147 static void intel_pstate_adjust_policy_max(struct cpudata *cpu, 2148 struct cpufreq_policy_data *policy) 2149 { 2150 if (!hwp_active && 2151 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && 2152 policy->max < policy->cpuinfo.max_freq && 2153 policy->max > cpu->pstate.max_freq) { 2154 pr_debug("policy->max > max non turbo frequency\n"); 2155 policy->max = policy->cpuinfo.max_freq; 2156 } 2157 } 2158 2159 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu, 2160 struct cpufreq_policy_data *policy) 2161 { 2162 update_turbo_state(); 2163 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, 2164 intel_pstate_get_max_freq(cpu)); 2165 2166 intel_pstate_adjust_policy_max(cpu, policy); 2167 } 2168 2169 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) 2170 { 2171 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); 2172 2173 return 0; 2174 } 2175 2176 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) 2177 { 2178 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); 2179 } 2180 2181 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) 2182 { 2183 pr_debug("CPU %d exiting\n", policy->cpu); 2184 2185 intel_pstate_clear_update_util_hook(policy->cpu); 2186 if (hwp_active) { 2187 intel_pstate_hwp_save_state(policy); 2188 intel_pstate_hwp_force_min_perf(policy->cpu); 2189 } else { 2190 intel_cpufreq_stop_cpu(policy); 2191 } 2192 } 2193 2194 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) 2195 { 2196 intel_pstate_exit_perf_limits(policy); 2197 2198 policy->fast_switch_possible = false; 2199 2200 return 0; 2201 } 2202 2203 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) 2204 { 2205 struct cpudata *cpu; 2206 int rc; 2207 2208 rc = intel_pstate_init_cpu(policy->cpu); 2209 if (rc) 2210 return rc; 2211 2212 cpu = all_cpu_data[policy->cpu]; 2213 2214 cpu->max_perf_ratio = 0xFF; 2215 cpu->min_perf_ratio = 0; 2216 2217 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; 2218 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; 2219 2220 /* cpuinfo and default policy values */ 2221 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; 2222 update_turbo_state(); 2223 global.turbo_disabled_mf = global.turbo_disabled; 2224 policy->cpuinfo.max_freq = global.turbo_disabled ? 2225 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; 2226 policy->cpuinfo.max_freq *= cpu->pstate.scaling; 2227 2228 if (hwp_active) { 2229 unsigned int max_freq; 2230 2231 max_freq = global.turbo_disabled ? 2232 cpu->pstate.max_freq : cpu->pstate.turbo_freq; 2233 if (max_freq < policy->cpuinfo.max_freq) 2234 policy->cpuinfo.max_freq = max_freq; 2235 } 2236 2237 intel_pstate_init_acpi_perf_limits(policy); 2238 2239 policy->fast_switch_possible = true; 2240 2241 return 0; 2242 } 2243 2244 static int intel_pstate_cpu_init(struct cpufreq_policy *policy) 2245 { 2246 int ret = __intel_pstate_cpu_init(policy); 2247 2248 if (ret) 2249 return ret; 2250 2251 /* 2252 * Set the policy to powersave to provide a valid fallback value in case 2253 * the default cpufreq governor is neither powersave nor performance. 2254 */ 2255 policy->policy = CPUFREQ_POLICY_POWERSAVE; 2256 2257 return 0; 2258 } 2259 2260 static struct cpufreq_driver intel_pstate = { 2261 .flags = CPUFREQ_CONST_LOOPS, 2262 .verify = intel_pstate_verify_policy, 2263 .setpolicy = intel_pstate_set_policy, 2264 .suspend = intel_pstate_hwp_save_state, 2265 .resume = intel_pstate_resume, 2266 .init = intel_pstate_cpu_init, 2267 .exit = intel_pstate_cpu_exit, 2268 .stop_cpu = intel_pstate_stop_cpu, 2269 .update_limits = intel_pstate_update_limits, 2270 .name = "intel_pstate", 2271 }; 2272 2273 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy) 2274 { 2275 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2276 2277 intel_pstate_verify_cpu_policy(cpu, policy); 2278 intel_pstate_update_perf_limits(cpu, policy->min, policy->max); 2279 2280 return 0; 2281 } 2282 2283 /* Use of trace in passive mode: 2284 * 2285 * In passive mode the trace core_busy field (also known as the 2286 * performance field, and lablelled as such on the graphs; also known as 2287 * core_avg_perf) is not needed and so is re-assigned to indicate if the 2288 * driver call was via the normal or fast switch path. Various graphs 2289 * output from the intel_pstate_tracer.py utility that include core_busy 2290 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%, 2291 * so we use 10 to indicate the the normal path through the driver, and 2292 * 90 to indicate the fast switch path through the driver. 2293 * The scaled_busy field is not used, and is set to 0. 2294 */ 2295 2296 #define INTEL_PSTATE_TRACE_TARGET 10 2297 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90 2298 2299 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate) 2300 { 2301 struct sample *sample; 2302 2303 if (!trace_pstate_sample_enabled()) 2304 return; 2305 2306 if (!intel_pstate_sample(cpu, ktime_get())) 2307 return; 2308 2309 sample = &cpu->sample; 2310 trace_pstate_sample(trace_type, 2311 0, 2312 old_pstate, 2313 cpu->pstate.current_pstate, 2314 sample->mperf, 2315 sample->aperf, 2316 sample->tsc, 2317 get_avg_frequency(cpu), 2318 fp_toint(cpu->iowait_boost * 100)); 2319 } 2320 2321 static int intel_cpufreq_target(struct cpufreq_policy *policy, 2322 unsigned int target_freq, 2323 unsigned int relation) 2324 { 2325 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2326 struct cpufreq_freqs freqs; 2327 int target_pstate, old_pstate; 2328 2329 update_turbo_state(); 2330 2331 freqs.old = policy->cur; 2332 freqs.new = target_freq; 2333 2334 cpufreq_freq_transition_begin(policy, &freqs); 2335 switch (relation) { 2336 case CPUFREQ_RELATION_L: 2337 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); 2338 break; 2339 case CPUFREQ_RELATION_H: 2340 target_pstate = freqs.new / cpu->pstate.scaling; 2341 break; 2342 default: 2343 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); 2344 break; 2345 } 2346 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2347 old_pstate = cpu->pstate.current_pstate; 2348 if (target_pstate != cpu->pstate.current_pstate) { 2349 cpu->pstate.current_pstate = target_pstate; 2350 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, 2351 pstate_funcs.get_val(cpu, target_pstate)); 2352 } 2353 freqs.new = target_pstate * cpu->pstate.scaling; 2354 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate); 2355 cpufreq_freq_transition_end(policy, &freqs, false); 2356 2357 return 0; 2358 } 2359 2360 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, 2361 unsigned int target_freq) 2362 { 2363 struct cpudata *cpu = all_cpu_data[policy->cpu]; 2364 int target_pstate, old_pstate; 2365 2366 update_turbo_state(); 2367 2368 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); 2369 target_pstate = intel_pstate_prepare_request(cpu, target_pstate); 2370 old_pstate = cpu->pstate.current_pstate; 2371 intel_pstate_update_pstate(cpu, target_pstate); 2372 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate); 2373 return target_pstate * cpu->pstate.scaling; 2374 } 2375 2376 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) 2377 { 2378 int max_state, turbo_max, min_freq, max_freq, ret; 2379 struct freq_qos_request *req; 2380 struct cpudata *cpu; 2381 struct device *dev; 2382 2383 dev = get_cpu_device(policy->cpu); 2384 if (!dev) 2385 return -ENODEV; 2386 2387 ret = __intel_pstate_cpu_init(policy); 2388 if (ret) 2389 return ret; 2390 2391 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; 2392 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; 2393 /* This reflects the intel_pstate_get_cpu_pstates() setting. */ 2394 policy->cur = policy->cpuinfo.min_freq; 2395 2396 req = kcalloc(2, sizeof(*req), GFP_KERNEL); 2397 if (!req) { 2398 ret = -ENOMEM; 2399 goto pstate_exit; 2400 } 2401 2402 cpu = all_cpu_data[policy->cpu]; 2403 2404 if (hwp_active) 2405 intel_pstate_get_hwp_max(policy->cpu, &turbo_max, &max_state); 2406 else 2407 turbo_max = cpu->pstate.turbo_pstate; 2408 2409 min_freq = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); 2410 min_freq *= cpu->pstate.scaling; 2411 max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); 2412 max_freq *= cpu->pstate.scaling; 2413 2414 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN, 2415 min_freq); 2416 if (ret < 0) { 2417 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 2418 goto free_req; 2419 } 2420 2421 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX, 2422 max_freq); 2423 if (ret < 0) { 2424 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 2425 goto remove_min_req; 2426 } 2427 2428 policy->driver_data = req; 2429 2430 return 0; 2431 2432 remove_min_req: 2433 freq_qos_remove_request(req); 2434 free_req: 2435 kfree(req); 2436 pstate_exit: 2437 intel_pstate_exit_perf_limits(policy); 2438 2439 return ret; 2440 } 2441 2442 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy) 2443 { 2444 struct freq_qos_request *req; 2445 2446 req = policy->driver_data; 2447 2448 freq_qos_remove_request(req + 1); 2449 freq_qos_remove_request(req); 2450 kfree(req); 2451 2452 return intel_pstate_cpu_exit(policy); 2453 } 2454 2455 static struct cpufreq_driver intel_cpufreq = { 2456 .flags = CPUFREQ_CONST_LOOPS, 2457 .verify = intel_cpufreq_verify_policy, 2458 .target = intel_cpufreq_target, 2459 .fast_switch = intel_cpufreq_fast_switch, 2460 .init = intel_cpufreq_cpu_init, 2461 .exit = intel_cpufreq_cpu_exit, 2462 .stop_cpu = intel_cpufreq_stop_cpu, 2463 .update_limits = intel_pstate_update_limits, 2464 .name = "intel_cpufreq", 2465 }; 2466 2467 static struct cpufreq_driver *default_driver = &intel_pstate; 2468 2469 static void intel_pstate_driver_cleanup(void) 2470 { 2471 unsigned int cpu; 2472 2473 get_online_cpus(); 2474 for_each_online_cpu(cpu) { 2475 if (all_cpu_data[cpu]) { 2476 if (intel_pstate_driver == &intel_pstate) 2477 intel_pstate_clear_update_util_hook(cpu); 2478 2479 kfree(all_cpu_data[cpu]); 2480 all_cpu_data[cpu] = NULL; 2481 } 2482 } 2483 put_online_cpus(); 2484 intel_pstate_driver = NULL; 2485 } 2486 2487 static int intel_pstate_register_driver(struct cpufreq_driver *driver) 2488 { 2489 int ret; 2490 2491 memset(&global, 0, sizeof(global)); 2492 global.max_perf_pct = 100; 2493 2494 intel_pstate_driver = driver; 2495 ret = cpufreq_register_driver(intel_pstate_driver); 2496 if (ret) { 2497 intel_pstate_driver_cleanup(); 2498 return ret; 2499 } 2500 2501 global.min_perf_pct = min_perf_pct_min(); 2502 2503 return 0; 2504 } 2505 2506 static int intel_pstate_unregister_driver(void) 2507 { 2508 if (hwp_active) 2509 return -EBUSY; 2510 2511 cpufreq_unregister_driver(intel_pstate_driver); 2512 intel_pstate_driver_cleanup(); 2513 2514 return 0; 2515 } 2516 2517 static ssize_t intel_pstate_show_status(char *buf) 2518 { 2519 if (!intel_pstate_driver) 2520 return sprintf(buf, "off\n"); 2521 2522 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? 2523 "active" : "passive"); 2524 } 2525 2526 static int intel_pstate_update_status(const char *buf, size_t size) 2527 { 2528 int ret; 2529 2530 if (size == 3 && !strncmp(buf, "off", size)) 2531 return intel_pstate_driver ? 2532 intel_pstate_unregister_driver() : -EINVAL; 2533 2534 if (size == 6 && !strncmp(buf, "active", size)) { 2535 if (intel_pstate_driver) { 2536 if (intel_pstate_driver == &intel_pstate) 2537 return 0; 2538 2539 ret = intel_pstate_unregister_driver(); 2540 if (ret) 2541 return ret; 2542 } 2543 2544 return intel_pstate_register_driver(&intel_pstate); 2545 } 2546 2547 if (size == 7 && !strncmp(buf, "passive", size)) { 2548 if (intel_pstate_driver) { 2549 if (intel_pstate_driver == &intel_cpufreq) 2550 return 0; 2551 2552 ret = intel_pstate_unregister_driver(); 2553 if (ret) 2554 return ret; 2555 } 2556 2557 return intel_pstate_register_driver(&intel_cpufreq); 2558 } 2559 2560 return -EINVAL; 2561 } 2562 2563 static int no_load __initdata; 2564 static int no_hwp __initdata; 2565 static int hwp_only __initdata; 2566 static unsigned int force_load __initdata; 2567 2568 static int __init intel_pstate_msrs_not_valid(void) 2569 { 2570 if (!pstate_funcs.get_max() || 2571 !pstate_funcs.get_min() || 2572 !pstate_funcs.get_turbo()) 2573 return -ENODEV; 2574 2575 return 0; 2576 } 2577 2578 static void __init copy_cpu_funcs(struct pstate_funcs *funcs) 2579 { 2580 pstate_funcs.get_max = funcs->get_max; 2581 pstate_funcs.get_max_physical = funcs->get_max_physical; 2582 pstate_funcs.get_min = funcs->get_min; 2583 pstate_funcs.get_turbo = funcs->get_turbo; 2584 pstate_funcs.get_scaling = funcs->get_scaling; 2585 pstate_funcs.get_val = funcs->get_val; 2586 pstate_funcs.get_vid = funcs->get_vid; 2587 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; 2588 } 2589 2590 #ifdef CONFIG_ACPI 2591 2592 static bool __init intel_pstate_no_acpi_pss(void) 2593 { 2594 int i; 2595 2596 for_each_possible_cpu(i) { 2597 acpi_status status; 2598 union acpi_object *pss; 2599 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2600 struct acpi_processor *pr = per_cpu(processors, i); 2601 2602 if (!pr) 2603 continue; 2604 2605 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); 2606 if (ACPI_FAILURE(status)) 2607 continue; 2608 2609 pss = buffer.pointer; 2610 if (pss && pss->type == ACPI_TYPE_PACKAGE) { 2611 kfree(pss); 2612 return false; 2613 } 2614 2615 kfree(pss); 2616 } 2617 2618 pr_debug("ACPI _PSS not found\n"); 2619 return true; 2620 } 2621 2622 static bool __init intel_pstate_no_acpi_pcch(void) 2623 { 2624 acpi_status status; 2625 acpi_handle handle; 2626 2627 status = acpi_get_handle(NULL, "\\_SB", &handle); 2628 if (ACPI_FAILURE(status)) 2629 goto not_found; 2630 2631 if (acpi_has_method(handle, "PCCH")) 2632 return false; 2633 2634 not_found: 2635 pr_debug("ACPI PCCH not found\n"); 2636 return true; 2637 } 2638 2639 static bool __init intel_pstate_has_acpi_ppc(void) 2640 { 2641 int i; 2642 2643 for_each_possible_cpu(i) { 2644 struct acpi_processor *pr = per_cpu(processors, i); 2645 2646 if (!pr) 2647 continue; 2648 if (acpi_has_method(pr->handle, "_PPC")) 2649 return true; 2650 } 2651 pr_debug("ACPI _PPC not found\n"); 2652 return false; 2653 } 2654 2655 enum { 2656 PSS, 2657 PPC, 2658 }; 2659 2660 /* Hardware vendor-specific info that has its own power management modes */ 2661 static struct acpi_platform_list plat_info[] __initdata = { 2662 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS}, 2663 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2664 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2665 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2666 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2667 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2668 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2669 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2670 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2671 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2672 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2673 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2674 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2675 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2676 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC}, 2677 { } /* End */ 2678 }; 2679 2680 static bool __init intel_pstate_platform_pwr_mgmt_exists(void) 2681 { 2682 const struct x86_cpu_id *id; 2683 u64 misc_pwr; 2684 int idx; 2685 2686 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 2687 if (id) { 2688 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 2689 if (misc_pwr & (1 << 8)) { 2690 pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n"); 2691 return true; 2692 } 2693 } 2694 2695 idx = acpi_match_platform_list(plat_info); 2696 if (idx < 0) 2697 return false; 2698 2699 switch (plat_info[idx].data) { 2700 case PSS: 2701 if (!intel_pstate_no_acpi_pss()) 2702 return false; 2703 2704 return intel_pstate_no_acpi_pcch(); 2705 case PPC: 2706 return intel_pstate_has_acpi_ppc() && !force_load; 2707 } 2708 2709 return false; 2710 } 2711 2712 static void intel_pstate_request_control_from_smm(void) 2713 { 2714 /* 2715 * It may be unsafe to request P-states control from SMM if _PPC support 2716 * has not been enabled. 2717 */ 2718 if (acpi_ppc) 2719 acpi_processor_pstate_control(); 2720 } 2721 #else /* CONFIG_ACPI not enabled */ 2722 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } 2723 static inline bool intel_pstate_has_acpi_ppc(void) { return false; } 2724 static inline void intel_pstate_request_control_from_smm(void) {} 2725 #endif /* CONFIG_ACPI */ 2726 2727 #define INTEL_PSTATE_HWP_BROADWELL 0x01 2728 2729 #define X86_MATCH_HWP(model, hwp_mode) \ 2730 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ 2731 X86_FEATURE_HWP, hwp_mode) 2732 2733 static const struct x86_cpu_id hwp_support_ids[] __initconst = { 2734 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), 2735 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL), 2736 X86_MATCH_HWP(ANY, 0), 2737 {} 2738 }; 2739 2740 static int __init intel_pstate_init(void) 2741 { 2742 const struct x86_cpu_id *id; 2743 int rc; 2744 2745 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2746 return -ENODEV; 2747 2748 if (no_load) 2749 return -ENODEV; 2750 2751 id = x86_match_cpu(hwp_support_ids); 2752 if (id) { 2753 copy_cpu_funcs(&core_funcs); 2754 if (!no_hwp) { 2755 hwp_active++; 2756 hwp_mode_bdw = id->driver_data; 2757 intel_pstate.attr = hwp_cpufreq_attrs; 2758 goto hwp_cpu_matched; 2759 } 2760 } else { 2761 id = x86_match_cpu(intel_pstate_cpu_ids); 2762 if (!id) { 2763 pr_info("CPU model not supported\n"); 2764 return -ENODEV; 2765 } 2766 2767 copy_cpu_funcs((struct pstate_funcs *)id->driver_data); 2768 } 2769 2770 if (intel_pstate_msrs_not_valid()) { 2771 pr_info("Invalid MSRs\n"); 2772 return -ENODEV; 2773 } 2774 2775 hwp_cpu_matched: 2776 /* 2777 * The Intel pstate driver will be ignored if the platform 2778 * firmware has its own power management modes. 2779 */ 2780 if (intel_pstate_platform_pwr_mgmt_exists()) { 2781 pr_info("P-states controlled by the platform\n"); 2782 return -ENODEV; 2783 } 2784 2785 if (!hwp_active && hwp_only) 2786 return -ENOTSUPP; 2787 2788 pr_info("Intel P-state driver initializing\n"); 2789 2790 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus())); 2791 if (!all_cpu_data) 2792 return -ENOMEM; 2793 2794 intel_pstate_request_control_from_smm(); 2795 2796 intel_pstate_sysfs_expose_params(); 2797 2798 mutex_lock(&intel_pstate_driver_lock); 2799 rc = intel_pstate_register_driver(default_driver); 2800 mutex_unlock(&intel_pstate_driver_lock); 2801 if (rc) 2802 return rc; 2803 2804 if (hwp_active) 2805 pr_info("HWP enabled\n"); 2806 2807 return 0; 2808 } 2809 device_initcall(intel_pstate_init); 2810 2811 static int __init intel_pstate_setup(char *str) 2812 { 2813 if (!str) 2814 return -EINVAL; 2815 2816 if (!strcmp(str, "disable")) { 2817 no_load = 1; 2818 } else if (!strcmp(str, "passive")) { 2819 pr_info("Passive mode enabled\n"); 2820 default_driver = &intel_cpufreq; 2821 no_hwp = 1; 2822 } 2823 if (!strcmp(str, "no_hwp")) { 2824 pr_info("HWP disabled\n"); 2825 no_hwp = 1; 2826 } 2827 if (!strcmp(str, "force")) 2828 force_load = 1; 2829 if (!strcmp(str, "hwp_only")) 2830 hwp_only = 1; 2831 if (!strcmp(str, "per_cpu_perf_limits")) 2832 per_cpu_limits = true; 2833 2834 #ifdef CONFIG_ACPI 2835 if (!strcmp(str, "support_acpi_ppc")) 2836 acpi_ppc = true; 2837 #endif 2838 2839 return 0; 2840 } 2841 early_param("intel_pstate", intel_pstate_setup); 2842 2843 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); 2844 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); 2845 MODULE_LICENSE("GPL"); 2846