1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 19 #define PU_SOC_VOLTAGE_NORMAL 1250000 20 #define PU_SOC_VOLTAGE_HIGH 1275000 21 #define FREQ_1P2_GHZ 1200000000 22 23 static struct regulator *arm_reg; 24 static struct regulator *pu_reg; 25 static struct regulator *soc_reg; 26 27 static struct clk *arm_clk; 28 static struct clk *pll1_sys_clk; 29 static struct clk *pll1_sw_clk; 30 static struct clk *step_clk; 31 static struct clk *pll2_pfd2_396m_clk; 32 33 /* clk used by i.MX6UL */ 34 static struct clk *pll2_bus_clk; 35 static struct clk *secondary_sel_clk; 36 37 static struct device *cpu_dev; 38 static bool free_opp; 39 static struct cpufreq_frequency_table *freq_table; 40 static unsigned int transition_latency; 41 42 static u32 *imx6_soc_volt; 43 static u32 soc_opp_count; 44 45 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 46 { 47 struct dev_pm_opp *opp; 48 unsigned long freq_hz, volt, volt_old; 49 unsigned int old_freq, new_freq; 50 int ret; 51 52 new_freq = freq_table[index].frequency; 53 freq_hz = new_freq * 1000; 54 old_freq = clk_get_rate(arm_clk) / 1000; 55 56 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 57 if (IS_ERR(opp)) { 58 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 59 return PTR_ERR(opp); 60 } 61 62 volt = dev_pm_opp_get_voltage(opp); 63 dev_pm_opp_put(opp); 64 65 volt_old = regulator_get_voltage(arm_reg); 66 67 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 68 old_freq / 1000, volt_old / 1000, 69 new_freq / 1000, volt / 1000); 70 71 /* scaling up? scale voltage before frequency */ 72 if (new_freq > old_freq) { 73 if (!IS_ERR(pu_reg)) { 74 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 75 if (ret) { 76 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 77 return ret; 78 } 79 } 80 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 81 if (ret) { 82 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 83 return ret; 84 } 85 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 86 if (ret) { 87 dev_err(cpu_dev, 88 "failed to scale vddarm up: %d\n", ret); 89 return ret; 90 } 91 } 92 93 /* 94 * The setpoints are selected per PLL/PDF frequencies, so we need to 95 * reprogram PLL for frequency scaling. The procedure of reprogramming 96 * PLL1 is as below. 97 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 98 * flow is slightly different from other i.MX6 OSC. 99 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 100 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 101 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 102 * - Disable pll2_pfd2_396m_clk 103 */ 104 if (of_machine_is_compatible("fsl,imx6ul")) { 105 /* 106 * When changing pll1_sw_clk's parent to pll1_sys_clk, 107 * CPU may run at higher than 528MHz, this will lead to 108 * the system unstable if the voltage is lower than the 109 * voltage of 528MHz, so lower the CPU frequency to one 110 * half before changing CPU frequency. 111 */ 112 clk_set_rate(arm_clk, (old_freq >> 1) * 1000); 113 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 114 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) 115 clk_set_parent(secondary_sel_clk, pll2_bus_clk); 116 else 117 clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); 118 clk_set_parent(step_clk, secondary_sel_clk); 119 clk_set_parent(pll1_sw_clk, step_clk); 120 } else { 121 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 122 clk_set_parent(pll1_sw_clk, step_clk); 123 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 124 clk_set_rate(pll1_sys_clk, new_freq * 1000); 125 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 126 } 127 } 128 129 /* Ensure the arm clock divider is what we expect */ 130 ret = clk_set_rate(arm_clk, new_freq * 1000); 131 if (ret) { 132 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 133 regulator_set_voltage_tol(arm_reg, volt_old, 0); 134 return ret; 135 } 136 137 /* scaling down? scale voltage after frequency */ 138 if (new_freq < old_freq) { 139 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 140 if (ret) { 141 dev_warn(cpu_dev, 142 "failed to scale vddarm down: %d\n", ret); 143 ret = 0; 144 } 145 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 146 if (ret) { 147 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 148 ret = 0; 149 } 150 if (!IS_ERR(pu_reg)) { 151 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 152 if (ret) { 153 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 154 ret = 0; 155 } 156 } 157 } 158 159 return 0; 160 } 161 162 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 163 { 164 int ret; 165 166 policy->clk = arm_clk; 167 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 168 policy->suspend_freq = policy->max; 169 170 return ret; 171 } 172 173 static struct cpufreq_driver imx6q_cpufreq_driver = { 174 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 175 .verify = cpufreq_generic_frequency_table_verify, 176 .target_index = imx6q_set_target, 177 .get = cpufreq_generic_get, 178 .init = imx6q_cpufreq_init, 179 .name = "imx6q-cpufreq", 180 .attr = cpufreq_generic_attr, 181 .suspend = cpufreq_generic_suspend, 182 }; 183 184 static int imx6q_cpufreq_probe(struct platform_device *pdev) 185 { 186 struct device_node *np; 187 struct dev_pm_opp *opp; 188 unsigned long min_volt, max_volt; 189 int num, ret; 190 const struct property *prop; 191 const __be32 *val; 192 u32 nr, i, j; 193 194 cpu_dev = get_cpu_device(0); 195 if (!cpu_dev) { 196 pr_err("failed to get cpu0 device\n"); 197 return -ENODEV; 198 } 199 200 np = of_node_get(cpu_dev->of_node); 201 if (!np) { 202 dev_err(cpu_dev, "failed to find cpu0 node\n"); 203 return -ENOENT; 204 } 205 206 arm_clk = clk_get(cpu_dev, "arm"); 207 pll1_sys_clk = clk_get(cpu_dev, "pll1_sys"); 208 pll1_sw_clk = clk_get(cpu_dev, "pll1_sw"); 209 step_clk = clk_get(cpu_dev, "step"); 210 pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m"); 211 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 212 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 213 dev_err(cpu_dev, "failed to get clocks\n"); 214 ret = -ENOENT; 215 goto put_clk; 216 } 217 218 if (of_machine_is_compatible("fsl,imx6ul")) { 219 pll2_bus_clk = clk_get(cpu_dev, "pll2_bus"); 220 secondary_sel_clk = clk_get(cpu_dev, "secondary_sel"); 221 if (IS_ERR(pll2_bus_clk) || IS_ERR(secondary_sel_clk)) { 222 dev_err(cpu_dev, "failed to get clocks specific to imx6ul\n"); 223 ret = -ENOENT; 224 goto put_clk; 225 } 226 } 227 228 arm_reg = regulator_get(cpu_dev, "arm"); 229 pu_reg = regulator_get_optional(cpu_dev, "pu"); 230 soc_reg = regulator_get(cpu_dev, "soc"); 231 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 232 PTR_ERR(soc_reg) == -EPROBE_DEFER || 233 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 234 ret = -EPROBE_DEFER; 235 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 236 goto put_reg; 237 } 238 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 239 dev_err(cpu_dev, "failed to get regulators\n"); 240 ret = -ENOENT; 241 goto put_reg; 242 } 243 244 /* 245 * We expect an OPP table supplied by platform. 246 * Just, incase the platform did not supply the OPP 247 * table, it will try to get it. 248 */ 249 num = dev_pm_opp_get_opp_count(cpu_dev); 250 if (num < 0) { 251 ret = dev_pm_opp_of_add_table(cpu_dev); 252 if (ret < 0) { 253 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 254 goto put_reg; 255 } 256 257 /* Because we have added the OPPs here, we must free them */ 258 free_opp = true; 259 260 num = dev_pm_opp_get_opp_count(cpu_dev); 261 if (num < 0) { 262 ret = num; 263 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 264 goto out_free_opp; 265 } 266 } 267 268 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 269 if (ret) { 270 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 271 goto out_free_opp; 272 } 273 274 /* Make imx6_soc_volt array's size same as arm opp number */ 275 imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); 276 if (imx6_soc_volt == NULL) { 277 ret = -ENOMEM; 278 goto free_freq_table; 279 } 280 281 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 282 if (!prop || !prop->value) 283 goto soc_opp_out; 284 285 /* 286 * Each OPP is a set of tuples consisting of frequency and 287 * voltage like <freq-kHz vol-uV>. 288 */ 289 nr = prop->length / sizeof(u32); 290 if (nr % 2 || (nr / 2) < num) 291 goto soc_opp_out; 292 293 for (j = 0; j < num; j++) { 294 val = prop->value; 295 for (i = 0; i < nr / 2; i++) { 296 unsigned long freq = be32_to_cpup(val++); 297 unsigned long volt = be32_to_cpup(val++); 298 if (freq_table[j].frequency == freq) { 299 imx6_soc_volt[soc_opp_count++] = volt; 300 break; 301 } 302 } 303 } 304 305 soc_opp_out: 306 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 307 if (soc_opp_count != num) { 308 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 309 for (j = 0; j < num; j++) 310 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 311 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 312 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 313 } 314 315 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 316 transition_latency = CPUFREQ_ETERNAL; 317 318 /* 319 * Calculate the ramp time for max voltage change in the 320 * VDDSOC and VDDPU regulators. 321 */ 322 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 323 if (ret > 0) 324 transition_latency += ret * 1000; 325 if (!IS_ERR(pu_reg)) { 326 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 327 if (ret > 0) 328 transition_latency += ret * 1000; 329 } 330 331 /* 332 * OPP is maintained in order of increasing frequency, and 333 * freq_table initialised from OPP is therefore sorted in the 334 * same order. 335 */ 336 opp = dev_pm_opp_find_freq_exact(cpu_dev, 337 freq_table[0].frequency * 1000, true); 338 min_volt = dev_pm_opp_get_voltage(opp); 339 dev_pm_opp_put(opp); 340 opp = dev_pm_opp_find_freq_exact(cpu_dev, 341 freq_table[--num].frequency * 1000, true); 342 max_volt = dev_pm_opp_get_voltage(opp); 343 dev_pm_opp_put(opp); 344 345 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 346 if (ret > 0) 347 transition_latency += ret * 1000; 348 349 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 350 if (ret) { 351 dev_err(cpu_dev, "failed register driver: %d\n", ret); 352 goto free_freq_table; 353 } 354 355 of_node_put(np); 356 return 0; 357 358 free_freq_table: 359 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 360 out_free_opp: 361 if (free_opp) 362 dev_pm_opp_of_remove_table(cpu_dev); 363 put_reg: 364 if (!IS_ERR(arm_reg)) 365 regulator_put(arm_reg); 366 if (!IS_ERR(pu_reg)) 367 regulator_put(pu_reg); 368 if (!IS_ERR(soc_reg)) 369 regulator_put(soc_reg); 370 put_clk: 371 if (!IS_ERR(arm_clk)) 372 clk_put(arm_clk); 373 if (!IS_ERR(pll1_sys_clk)) 374 clk_put(pll1_sys_clk); 375 if (!IS_ERR(pll1_sw_clk)) 376 clk_put(pll1_sw_clk); 377 if (!IS_ERR(step_clk)) 378 clk_put(step_clk); 379 if (!IS_ERR(pll2_pfd2_396m_clk)) 380 clk_put(pll2_pfd2_396m_clk); 381 if (!IS_ERR(pll2_bus_clk)) 382 clk_put(pll2_bus_clk); 383 if (!IS_ERR(secondary_sel_clk)) 384 clk_put(secondary_sel_clk); 385 of_node_put(np); 386 return ret; 387 } 388 389 static int imx6q_cpufreq_remove(struct platform_device *pdev) 390 { 391 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 392 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 393 if (free_opp) 394 dev_pm_opp_of_remove_table(cpu_dev); 395 regulator_put(arm_reg); 396 if (!IS_ERR(pu_reg)) 397 regulator_put(pu_reg); 398 regulator_put(soc_reg); 399 clk_put(arm_clk); 400 clk_put(pll1_sys_clk); 401 clk_put(pll1_sw_clk); 402 clk_put(step_clk); 403 clk_put(pll2_pfd2_396m_clk); 404 clk_put(pll2_bus_clk); 405 clk_put(secondary_sel_clk); 406 407 return 0; 408 } 409 410 static struct platform_driver imx6q_cpufreq_platdrv = { 411 .driver = { 412 .name = "imx6q-cpufreq", 413 }, 414 .probe = imx6q_cpufreq_probe, 415 .remove = imx6q_cpufreq_remove, 416 }; 417 module_platform_driver(imx6q_cpufreq_platdrv); 418 419 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 420 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 421 MODULE_LICENSE("GPL"); 422