1 /* 2 * acpi-cpufreq.c - ACPI Processor P-States Driver 3 * 4 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> 5 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> 7 * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> 8 * 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, write to the Free Software Foundation, Inc., 23 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 24 * 25 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/init.h> 31 #include <linux/smp.h> 32 #include <linux/sched.h> 33 #include <linux/cpufreq.h> 34 #include <linux/compiler.h> 35 #include <linux/dmi.h> 36 #include <linux/slab.h> 37 38 #include <linux/acpi.h> 39 #include <linux/io.h> 40 #include <linux/delay.h> 41 #include <linux/uaccess.h> 42 43 #include <acpi/processor.h> 44 45 #include <asm/msr.h> 46 #include <asm/processor.h> 47 #include <asm/cpufeature.h> 48 #include "mperf.h" 49 50 MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); 51 MODULE_DESCRIPTION("ACPI Processor P-States Driver"); 52 MODULE_LICENSE("GPL"); 53 54 #define PFX "acpi-cpufreq: " 55 56 enum { 57 UNDEFINED_CAPABLE = 0, 58 SYSTEM_INTEL_MSR_CAPABLE, 59 SYSTEM_AMD_MSR_CAPABLE, 60 SYSTEM_IO_CAPABLE, 61 }; 62 63 #define INTEL_MSR_RANGE (0xffff) 64 #define AMD_MSR_RANGE (0x7) 65 66 #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) 67 68 struct acpi_cpufreq_data { 69 struct acpi_processor_performance *acpi_data; 70 struct cpufreq_frequency_table *freq_table; 71 unsigned int resume; 72 unsigned int cpu_feature; 73 }; 74 75 static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data); 76 77 /* acpi_perf_data is a pointer to percpu data. */ 78 static struct acpi_processor_performance __percpu *acpi_perf_data; 79 80 static struct cpufreq_driver acpi_cpufreq_driver; 81 82 static unsigned int acpi_pstate_strict; 83 static bool boost_enabled, boost_supported; 84 static struct msr __percpu *msrs; 85 86 static bool boost_state(unsigned int cpu) 87 { 88 u32 lo, hi; 89 u64 msr; 90 91 switch (boot_cpu_data.x86_vendor) { 92 case X86_VENDOR_INTEL: 93 rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); 94 msr = lo | ((u64)hi << 32); 95 return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 96 case X86_VENDOR_AMD: 97 rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); 98 msr = lo | ((u64)hi << 32); 99 return !(msr & MSR_K7_HWCR_CPB_DIS); 100 } 101 return false; 102 } 103 104 static void boost_set_msrs(bool enable, const struct cpumask *cpumask) 105 { 106 u32 cpu; 107 u32 msr_addr; 108 u64 msr_mask; 109 110 switch (boot_cpu_data.x86_vendor) { 111 case X86_VENDOR_INTEL: 112 msr_addr = MSR_IA32_MISC_ENABLE; 113 msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; 114 break; 115 case X86_VENDOR_AMD: 116 msr_addr = MSR_K7_HWCR; 117 msr_mask = MSR_K7_HWCR_CPB_DIS; 118 break; 119 default: 120 return; 121 } 122 123 rdmsr_on_cpus(cpumask, msr_addr, msrs); 124 125 for_each_cpu(cpu, cpumask) { 126 struct msr *reg = per_cpu_ptr(msrs, cpu); 127 if (enable) 128 reg->q &= ~msr_mask; 129 else 130 reg->q |= msr_mask; 131 } 132 133 wrmsr_on_cpus(cpumask, msr_addr, msrs); 134 } 135 136 static ssize_t _store_boost(const char *buf, size_t count) 137 { 138 int ret; 139 unsigned long val = 0; 140 141 if (!boost_supported) 142 return -EINVAL; 143 144 ret = kstrtoul(buf, 10, &val); 145 if (ret || (val > 1)) 146 return -EINVAL; 147 148 if ((val && boost_enabled) || (!val && !boost_enabled)) 149 return count; 150 151 get_online_cpus(); 152 153 boost_set_msrs(val, cpu_online_mask); 154 155 put_online_cpus(); 156 157 boost_enabled = val; 158 pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); 159 160 return count; 161 } 162 163 static ssize_t store_global_boost(struct kobject *kobj, struct attribute *attr, 164 const char *buf, size_t count) 165 { 166 return _store_boost(buf, count); 167 } 168 169 static ssize_t show_global_boost(struct kobject *kobj, 170 struct attribute *attr, char *buf) 171 { 172 return sprintf(buf, "%u\n", boost_enabled); 173 } 174 175 static struct global_attr global_boost = __ATTR(boost, 0644, 176 show_global_boost, 177 store_global_boost); 178 179 #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB 180 static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, 181 size_t count) 182 { 183 return _store_boost(buf, count); 184 } 185 186 static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) 187 { 188 return sprintf(buf, "%u\n", boost_enabled); 189 } 190 191 static struct freq_attr cpb = __ATTR(cpb, 0644, show_cpb, store_cpb); 192 #endif 193 194 static int check_est_cpu(unsigned int cpuid) 195 { 196 struct cpuinfo_x86 *cpu = &cpu_data(cpuid); 197 198 return cpu_has(cpu, X86_FEATURE_EST); 199 } 200 201 static int check_amd_hwpstate_cpu(unsigned int cpuid) 202 { 203 struct cpuinfo_x86 *cpu = &cpu_data(cpuid); 204 205 return cpu_has(cpu, X86_FEATURE_HW_PSTATE); 206 } 207 208 static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) 209 { 210 struct acpi_processor_performance *perf; 211 int i; 212 213 perf = data->acpi_data; 214 215 for (i = 0; i < perf->state_count; i++) { 216 if (value == perf->states[i].status) 217 return data->freq_table[i].frequency; 218 } 219 return 0; 220 } 221 222 static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) 223 { 224 int i; 225 struct acpi_processor_performance *perf; 226 227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 228 msr &= AMD_MSR_RANGE; 229 else 230 msr &= INTEL_MSR_RANGE; 231 232 perf = data->acpi_data; 233 234 for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { 235 if (msr == perf->states[data->freq_table[i].index].status) 236 return data->freq_table[i].frequency; 237 } 238 return data->freq_table[0].frequency; 239 } 240 241 static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) 242 { 243 switch (data->cpu_feature) { 244 case SYSTEM_INTEL_MSR_CAPABLE: 245 case SYSTEM_AMD_MSR_CAPABLE: 246 return extract_msr(val, data); 247 case SYSTEM_IO_CAPABLE: 248 return extract_io(val, data); 249 default: 250 return 0; 251 } 252 } 253 254 struct msr_addr { 255 u32 reg; 256 }; 257 258 struct io_addr { 259 u16 port; 260 u8 bit_width; 261 }; 262 263 struct drv_cmd { 264 unsigned int type; 265 const struct cpumask *mask; 266 union { 267 struct msr_addr msr; 268 struct io_addr io; 269 } addr; 270 u32 val; 271 }; 272 273 /* Called via smp_call_function_single(), on the target CPU */ 274 static void do_drv_read(void *_cmd) 275 { 276 struct drv_cmd *cmd = _cmd; 277 u32 h; 278 279 switch (cmd->type) { 280 case SYSTEM_INTEL_MSR_CAPABLE: 281 case SYSTEM_AMD_MSR_CAPABLE: 282 rdmsr(cmd->addr.msr.reg, cmd->val, h); 283 break; 284 case SYSTEM_IO_CAPABLE: 285 acpi_os_read_port((acpi_io_address)cmd->addr.io.port, 286 &cmd->val, 287 (u32)cmd->addr.io.bit_width); 288 break; 289 default: 290 break; 291 } 292 } 293 294 /* Called via smp_call_function_many(), on the target CPUs */ 295 static void do_drv_write(void *_cmd) 296 { 297 struct drv_cmd *cmd = _cmd; 298 u32 lo, hi; 299 300 switch (cmd->type) { 301 case SYSTEM_INTEL_MSR_CAPABLE: 302 rdmsr(cmd->addr.msr.reg, lo, hi); 303 lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); 304 wrmsr(cmd->addr.msr.reg, lo, hi); 305 break; 306 case SYSTEM_AMD_MSR_CAPABLE: 307 wrmsr(cmd->addr.msr.reg, cmd->val, 0); 308 break; 309 case SYSTEM_IO_CAPABLE: 310 acpi_os_write_port((acpi_io_address)cmd->addr.io.port, 311 cmd->val, 312 (u32)cmd->addr.io.bit_width); 313 break; 314 default: 315 break; 316 } 317 } 318 319 static void drv_read(struct drv_cmd *cmd) 320 { 321 int err; 322 cmd->val = 0; 323 324 err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); 325 WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ 326 } 327 328 static void drv_write(struct drv_cmd *cmd) 329 { 330 int this_cpu; 331 332 this_cpu = get_cpu(); 333 if (cpumask_test_cpu(this_cpu, cmd->mask)) 334 do_drv_write(cmd); 335 smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); 336 put_cpu(); 337 } 338 339 static u32 get_cur_val(const struct cpumask *mask) 340 { 341 struct acpi_processor_performance *perf; 342 struct drv_cmd cmd; 343 344 if (unlikely(cpumask_empty(mask))) 345 return 0; 346 347 switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { 348 case SYSTEM_INTEL_MSR_CAPABLE: 349 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; 350 cmd.addr.msr.reg = MSR_IA32_PERF_STATUS; 351 break; 352 case SYSTEM_AMD_MSR_CAPABLE: 353 cmd.type = SYSTEM_AMD_MSR_CAPABLE; 354 cmd.addr.msr.reg = MSR_AMD_PERF_STATUS; 355 break; 356 case SYSTEM_IO_CAPABLE: 357 cmd.type = SYSTEM_IO_CAPABLE; 358 perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; 359 cmd.addr.io.port = perf->control_register.address; 360 cmd.addr.io.bit_width = perf->control_register.bit_width; 361 break; 362 default: 363 return 0; 364 } 365 366 cmd.mask = mask; 367 drv_read(&cmd); 368 369 pr_debug("get_cur_val = %u\n", cmd.val); 370 371 return cmd.val; 372 } 373 374 static unsigned int get_cur_freq_on_cpu(unsigned int cpu) 375 { 376 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, cpu); 377 unsigned int freq; 378 unsigned int cached_freq; 379 380 pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); 381 382 if (unlikely(data == NULL || 383 data->acpi_data == NULL || data->freq_table == NULL)) { 384 return 0; 385 } 386 387 cached_freq = data->freq_table[data->acpi_data->state].frequency; 388 freq = extract_freq(get_cur_val(cpumask_of(cpu)), data); 389 if (freq != cached_freq) { 390 /* 391 * The dreaded BIOS frequency change behind our back. 392 * Force set the frequency on next target call. 393 */ 394 data->resume = 1; 395 } 396 397 pr_debug("cur freq = %u\n", freq); 398 399 return freq; 400 } 401 402 static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, 403 struct acpi_cpufreq_data *data) 404 { 405 unsigned int cur_freq; 406 unsigned int i; 407 408 for (i = 0; i < 100; i++) { 409 cur_freq = extract_freq(get_cur_val(mask), data); 410 if (cur_freq == freq) 411 return 1; 412 udelay(10); 413 } 414 return 0; 415 } 416 417 static int acpi_cpufreq_target(struct cpufreq_policy *policy, 418 unsigned int target_freq, unsigned int relation) 419 { 420 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); 421 struct acpi_processor_performance *perf; 422 struct cpufreq_freqs freqs; 423 struct drv_cmd cmd; 424 unsigned int next_state = 0; /* Index into freq_table */ 425 unsigned int next_perf_state = 0; /* Index into perf table */ 426 unsigned int i; 427 int result = 0; 428 429 pr_debug("acpi_cpufreq_target %d (%d)\n", target_freq, policy->cpu); 430 431 if (unlikely(data == NULL || 432 data->acpi_data == NULL || data->freq_table == NULL)) { 433 return -ENODEV; 434 } 435 436 perf = data->acpi_data; 437 result = cpufreq_frequency_table_target(policy, 438 data->freq_table, 439 target_freq, 440 relation, &next_state); 441 if (unlikely(result)) { 442 result = -ENODEV; 443 goto out; 444 } 445 446 next_perf_state = data->freq_table[next_state].index; 447 if (perf->state == next_perf_state) { 448 if (unlikely(data->resume)) { 449 pr_debug("Called after resume, resetting to P%d\n", 450 next_perf_state); 451 data->resume = 0; 452 } else { 453 pr_debug("Already at target state (P%d)\n", 454 next_perf_state); 455 goto out; 456 } 457 } 458 459 switch (data->cpu_feature) { 460 case SYSTEM_INTEL_MSR_CAPABLE: 461 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; 462 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; 463 cmd.val = (u32) perf->states[next_perf_state].control; 464 break; 465 case SYSTEM_AMD_MSR_CAPABLE: 466 cmd.type = SYSTEM_AMD_MSR_CAPABLE; 467 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; 468 cmd.val = (u32) perf->states[next_perf_state].control; 469 break; 470 case SYSTEM_IO_CAPABLE: 471 cmd.type = SYSTEM_IO_CAPABLE; 472 cmd.addr.io.port = perf->control_register.address; 473 cmd.addr.io.bit_width = perf->control_register.bit_width; 474 cmd.val = (u32) perf->states[next_perf_state].control; 475 break; 476 default: 477 result = -ENODEV; 478 goto out; 479 } 480 481 /* cpufreq holds the hotplug lock, so we are safe from here on */ 482 if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) 483 cmd.mask = policy->cpus; 484 else 485 cmd.mask = cpumask_of(policy->cpu); 486 487 freqs.old = perf->states[perf->state].core_frequency * 1000; 488 freqs.new = data->freq_table[next_state].frequency; 489 for_each_cpu(i, policy->cpus) { 490 freqs.cpu = i; 491 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 492 } 493 494 drv_write(&cmd); 495 496 if (acpi_pstate_strict) { 497 if (!check_freqs(cmd.mask, freqs.new, data)) { 498 pr_debug("acpi_cpufreq_target failed (%d)\n", 499 policy->cpu); 500 result = -EAGAIN; 501 goto out; 502 } 503 } 504 505 for_each_cpu(i, policy->cpus) { 506 freqs.cpu = i; 507 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 508 } 509 perf->state = next_perf_state; 510 511 out: 512 return result; 513 } 514 515 static int acpi_cpufreq_verify(struct cpufreq_policy *policy) 516 { 517 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); 518 519 pr_debug("acpi_cpufreq_verify\n"); 520 521 return cpufreq_frequency_table_verify(policy, data->freq_table); 522 } 523 524 static unsigned long 525 acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) 526 { 527 struct acpi_processor_performance *perf = data->acpi_data; 528 529 if (cpu_khz) { 530 /* search the closest match to cpu_khz */ 531 unsigned int i; 532 unsigned long freq; 533 unsigned long freqn = perf->states[0].core_frequency * 1000; 534 535 for (i = 0; i < (perf->state_count-1); i++) { 536 freq = freqn; 537 freqn = perf->states[i+1].core_frequency * 1000; 538 if ((2 * cpu_khz) > (freqn + freq)) { 539 perf->state = i; 540 return freq; 541 } 542 } 543 perf->state = perf->state_count-1; 544 return freqn; 545 } else { 546 /* assume CPU is at P0... */ 547 perf->state = 0; 548 return perf->states[0].core_frequency * 1000; 549 } 550 } 551 552 static void free_acpi_perf_data(void) 553 { 554 unsigned int i; 555 556 /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ 557 for_each_possible_cpu(i) 558 free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) 559 ->shared_cpu_map); 560 free_percpu(acpi_perf_data); 561 } 562 563 static int boost_notify(struct notifier_block *nb, unsigned long action, 564 void *hcpu) 565 { 566 unsigned cpu = (long)hcpu; 567 const struct cpumask *cpumask; 568 569 cpumask = get_cpu_mask(cpu); 570 571 /* 572 * Clear the boost-disable bit on the CPU_DOWN path so that 573 * this cpu cannot block the remaining ones from boosting. On 574 * the CPU_UP path we simply keep the boost-disable flag in 575 * sync with the current global state. 576 */ 577 578 switch (action) { 579 case CPU_UP_PREPARE: 580 case CPU_UP_PREPARE_FROZEN: 581 boost_set_msrs(boost_enabled, cpumask); 582 break; 583 584 case CPU_DOWN_PREPARE: 585 case CPU_DOWN_PREPARE_FROZEN: 586 boost_set_msrs(1, cpumask); 587 break; 588 589 default: 590 break; 591 } 592 593 return NOTIFY_OK; 594 } 595 596 597 static struct notifier_block boost_nb = { 598 .notifier_call = boost_notify, 599 }; 600 601 /* 602 * acpi_cpufreq_early_init - initialize ACPI P-States library 603 * 604 * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) 605 * in order to determine correct frequency and voltage pairings. We can 606 * do _PDC and _PSD and find out the processor dependency for the 607 * actual init that will happen later... 608 */ 609 static int __init acpi_cpufreq_early_init(void) 610 { 611 unsigned int i; 612 pr_debug("acpi_cpufreq_early_init\n"); 613 614 acpi_perf_data = alloc_percpu(struct acpi_processor_performance); 615 if (!acpi_perf_data) { 616 pr_debug("Memory allocation error for acpi_perf_data.\n"); 617 return -ENOMEM; 618 } 619 for_each_possible_cpu(i) { 620 if (!zalloc_cpumask_var_node( 621 &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, 622 GFP_KERNEL, cpu_to_node(i))) { 623 624 /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ 625 free_acpi_perf_data(); 626 return -ENOMEM; 627 } 628 } 629 630 /* Do initialization in ACPI core */ 631 acpi_processor_preregister_performance(acpi_perf_data); 632 return 0; 633 } 634 635 #ifdef CONFIG_SMP 636 /* 637 * Some BIOSes do SW_ANY coordination internally, either set it up in hw 638 * or do it in BIOS firmware and won't inform about it to OS. If not 639 * detected, this has a side effect of making CPU run at a different speed 640 * than OS intended it to run at. Detect it and handle it cleanly. 641 */ 642 static int bios_with_sw_any_bug; 643 644 static int sw_any_bug_found(const struct dmi_system_id *d) 645 { 646 bios_with_sw_any_bug = 1; 647 return 0; 648 } 649 650 static const struct dmi_system_id sw_any_bug_dmi_table[] = { 651 { 652 .callback = sw_any_bug_found, 653 .ident = "Supermicro Server X6DLP", 654 .matches = { 655 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 656 DMI_MATCH(DMI_BIOS_VERSION, "080010"), 657 DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), 658 }, 659 }, 660 { } 661 }; 662 663 static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) 664 { 665 /* Intel Xeon Processor 7100 Series Specification Update 666 * http://www.intel.com/Assets/PDF/specupdate/314554.pdf 667 * AL30: A Machine Check Exception (MCE) Occurring during an 668 * Enhanced Intel SpeedStep Technology Ratio Change May Cause 669 * Both Processor Cores to Lock Up. */ 670 if (c->x86_vendor == X86_VENDOR_INTEL) { 671 if ((c->x86 == 15) && 672 (c->x86_model == 6) && 673 (c->x86_mask == 8)) { 674 printk(KERN_INFO "acpi-cpufreq: Intel(R) " 675 "Xeon(R) 7100 Errata AL30, processors may " 676 "lock up on frequency changes: disabling " 677 "acpi-cpufreq.\n"); 678 return -ENODEV; 679 } 680 } 681 return 0; 682 } 683 #endif 684 685 static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) 686 { 687 unsigned int i; 688 unsigned int valid_states = 0; 689 unsigned int cpu = policy->cpu; 690 struct acpi_cpufreq_data *data; 691 unsigned int result = 0; 692 struct cpuinfo_x86 *c = &cpu_data(policy->cpu); 693 struct acpi_processor_performance *perf; 694 #ifdef CONFIG_SMP 695 static int blacklisted; 696 #endif 697 698 pr_debug("acpi_cpufreq_cpu_init\n"); 699 700 #ifdef CONFIG_SMP 701 if (blacklisted) 702 return blacklisted; 703 blacklisted = acpi_cpufreq_blacklist(c); 704 if (blacklisted) 705 return blacklisted; 706 #endif 707 708 data = kzalloc(sizeof(struct acpi_cpufreq_data), GFP_KERNEL); 709 if (!data) 710 return -ENOMEM; 711 712 data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); 713 per_cpu(acfreq_data, cpu) = data; 714 715 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) 716 acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; 717 718 result = acpi_processor_register_performance(data->acpi_data, cpu); 719 if (result) 720 goto err_free; 721 722 perf = data->acpi_data; 723 policy->shared_type = perf->shared_type; 724 725 /* 726 * Will let policy->cpus know about dependency only when software 727 * coordination is required. 728 */ 729 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || 730 policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { 731 cpumask_copy(policy->cpus, perf->shared_cpu_map); 732 } 733 cpumask_copy(policy->related_cpus, perf->shared_cpu_map); 734 735 #ifdef CONFIG_SMP 736 dmi_check_system(sw_any_bug_dmi_table); 737 if (bios_with_sw_any_bug && cpumask_weight(policy->cpus) == 1) { 738 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; 739 cpumask_copy(policy->cpus, cpu_core_mask(cpu)); 740 } 741 742 if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { 743 cpumask_clear(policy->cpus); 744 cpumask_set_cpu(cpu, policy->cpus); 745 cpumask_copy(policy->related_cpus, cpu_sibling_mask(cpu)); 746 policy->shared_type = CPUFREQ_SHARED_TYPE_HW; 747 pr_info_once(PFX "overriding BIOS provided _PSD data\n"); 748 } 749 #endif 750 751 /* capability check */ 752 if (perf->state_count <= 1) { 753 pr_debug("No P-States\n"); 754 result = -ENODEV; 755 goto err_unreg; 756 } 757 758 if (perf->control_register.space_id != perf->status_register.space_id) { 759 result = -ENODEV; 760 goto err_unreg; 761 } 762 763 switch (perf->control_register.space_id) { 764 case ACPI_ADR_SPACE_SYSTEM_IO: 765 pr_debug("SYSTEM IO addr space\n"); 766 data->cpu_feature = SYSTEM_IO_CAPABLE; 767 break; 768 case ACPI_ADR_SPACE_FIXED_HARDWARE: 769 pr_debug("HARDWARE addr space\n"); 770 if (check_est_cpu(cpu)) { 771 data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; 772 break; 773 } 774 if (check_amd_hwpstate_cpu(cpu)) { 775 data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; 776 break; 777 } 778 result = -ENODEV; 779 goto err_unreg; 780 default: 781 pr_debug("Unknown addr space %d\n", 782 (u32) (perf->control_register.space_id)); 783 result = -ENODEV; 784 goto err_unreg; 785 } 786 787 data->freq_table = kmalloc(sizeof(struct cpufreq_frequency_table) * 788 (perf->state_count+1), GFP_KERNEL); 789 if (!data->freq_table) { 790 result = -ENOMEM; 791 goto err_unreg; 792 } 793 794 /* detect transition latency */ 795 policy->cpuinfo.transition_latency = 0; 796 for (i = 0; i < perf->state_count; i++) { 797 if ((perf->states[i].transition_latency * 1000) > 798 policy->cpuinfo.transition_latency) 799 policy->cpuinfo.transition_latency = 800 perf->states[i].transition_latency * 1000; 801 } 802 803 /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ 804 if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && 805 policy->cpuinfo.transition_latency > 20 * 1000) { 806 policy->cpuinfo.transition_latency = 20 * 1000; 807 printk_once(KERN_INFO 808 "P-state transition latency capped at 20 uS\n"); 809 } 810 811 /* table init */ 812 for (i = 0; i < perf->state_count; i++) { 813 if (i > 0 && perf->states[i].core_frequency >= 814 data->freq_table[valid_states-1].frequency / 1000) 815 continue; 816 817 data->freq_table[valid_states].index = i; 818 data->freq_table[valid_states].frequency = 819 perf->states[i].core_frequency * 1000; 820 valid_states++; 821 } 822 data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END; 823 perf->state = 0; 824 825 result = cpufreq_frequency_table_cpuinfo(policy, data->freq_table); 826 if (result) 827 goto err_freqfree; 828 829 if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) 830 printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n"); 831 832 switch (perf->control_register.space_id) { 833 case ACPI_ADR_SPACE_SYSTEM_IO: 834 /* Current speed is unknown and not detectable by IO port */ 835 policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); 836 break; 837 case ACPI_ADR_SPACE_FIXED_HARDWARE: 838 acpi_cpufreq_driver.get = get_cur_freq_on_cpu; 839 policy->cur = get_cur_freq_on_cpu(cpu); 840 break; 841 default: 842 break; 843 } 844 845 /* notify BIOS that we exist */ 846 acpi_processor_notify_smm(THIS_MODULE); 847 848 /* Check for APERF/MPERF support in hardware */ 849 if (boot_cpu_has(X86_FEATURE_APERFMPERF)) 850 acpi_cpufreq_driver.getavg = cpufreq_get_measured_perf; 851 852 pr_debug("CPU%u - ACPI performance management activated.\n", cpu); 853 for (i = 0; i < perf->state_count; i++) 854 pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", 855 (i == perf->state ? '*' : ' '), i, 856 (u32) perf->states[i].core_frequency, 857 (u32) perf->states[i].power, 858 (u32) perf->states[i].transition_latency); 859 860 cpufreq_frequency_table_get_attr(data->freq_table, policy->cpu); 861 862 /* 863 * the first call to ->target() should result in us actually 864 * writing something to the appropriate registers. 865 */ 866 data->resume = 1; 867 868 return result; 869 870 err_freqfree: 871 kfree(data->freq_table); 872 err_unreg: 873 acpi_processor_unregister_performance(perf, cpu); 874 err_free: 875 kfree(data); 876 per_cpu(acfreq_data, cpu) = NULL; 877 878 return result; 879 } 880 881 static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) 882 { 883 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); 884 885 pr_debug("acpi_cpufreq_cpu_exit\n"); 886 887 if (data) { 888 cpufreq_frequency_table_put_attr(policy->cpu); 889 per_cpu(acfreq_data, policy->cpu) = NULL; 890 acpi_processor_unregister_performance(data->acpi_data, 891 policy->cpu); 892 kfree(data->freq_table); 893 kfree(data); 894 } 895 896 return 0; 897 } 898 899 static int acpi_cpufreq_resume(struct cpufreq_policy *policy) 900 { 901 struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); 902 903 pr_debug("acpi_cpufreq_resume\n"); 904 905 data->resume = 1; 906 907 return 0; 908 } 909 910 static struct freq_attr *acpi_cpufreq_attr[] = { 911 &cpufreq_freq_attr_scaling_available_freqs, 912 NULL, /* this is a placeholder for cpb, do not remove */ 913 NULL, 914 }; 915 916 static struct cpufreq_driver acpi_cpufreq_driver = { 917 .verify = acpi_cpufreq_verify, 918 .target = acpi_cpufreq_target, 919 .bios_limit = acpi_processor_get_bios_limit, 920 .init = acpi_cpufreq_cpu_init, 921 .exit = acpi_cpufreq_cpu_exit, 922 .resume = acpi_cpufreq_resume, 923 .name = "acpi-cpufreq", 924 .owner = THIS_MODULE, 925 .attr = acpi_cpufreq_attr, 926 }; 927 928 static void __init acpi_cpufreq_boost_init(void) 929 { 930 if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { 931 msrs = msrs_alloc(); 932 933 if (!msrs) 934 return; 935 936 boost_supported = true; 937 boost_enabled = boost_state(0); 938 939 get_online_cpus(); 940 941 /* Force all MSRs to the same value */ 942 boost_set_msrs(boost_enabled, cpu_online_mask); 943 944 register_cpu_notifier(&boost_nb); 945 946 put_online_cpus(); 947 } else 948 global_boost.attr.mode = 0444; 949 950 /* We create the boost file in any case, though for systems without 951 * hardware support it will be read-only and hardwired to return 0. 952 */ 953 if (sysfs_create_file(cpufreq_global_kobject, &(global_boost.attr))) 954 pr_warn(PFX "could not register global boost sysfs file\n"); 955 else 956 pr_debug("registered global boost sysfs file\n"); 957 } 958 959 static void __exit acpi_cpufreq_boost_exit(void) 960 { 961 sysfs_remove_file(cpufreq_global_kobject, &(global_boost.attr)); 962 963 if (msrs) { 964 unregister_cpu_notifier(&boost_nb); 965 966 msrs_free(msrs); 967 msrs = NULL; 968 } 969 } 970 971 static int __init acpi_cpufreq_init(void) 972 { 973 int ret; 974 975 if (acpi_disabled) 976 return 0; 977 978 pr_debug("acpi_cpufreq_init\n"); 979 980 ret = acpi_cpufreq_early_init(); 981 if (ret) 982 return ret; 983 984 #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB 985 /* this is a sysfs file with a strange name and an even stranger 986 * semantic - per CPU instantiation, but system global effect. 987 * Lets enable it only on AMD CPUs for compatibility reasons and 988 * only if configured. This is considered legacy code, which 989 * will probably be removed at some point in the future. 990 */ 991 if (check_amd_hwpstate_cpu(0)) { 992 struct freq_attr **iter; 993 994 pr_debug("adding sysfs entry for cpb\n"); 995 996 for (iter = acpi_cpufreq_attr; *iter != NULL; iter++) 997 ; 998 999 /* make sure there is a terminator behind it */ 1000 if (iter[1] == NULL) 1001 *iter = &cpb; 1002 } 1003 #endif 1004 1005 ret = cpufreq_register_driver(&acpi_cpufreq_driver); 1006 if (ret) 1007 free_acpi_perf_data(); 1008 else 1009 acpi_cpufreq_boost_init(); 1010 1011 return ret; 1012 } 1013 1014 static void __exit acpi_cpufreq_exit(void) 1015 { 1016 pr_debug("acpi_cpufreq_exit\n"); 1017 1018 acpi_cpufreq_boost_exit(); 1019 1020 cpufreq_unregister_driver(&acpi_cpufreq_driver); 1021 1022 free_acpi_perf_data(); 1023 } 1024 1025 module_param(acpi_pstate_strict, uint, 0644); 1026 MODULE_PARM_DESC(acpi_pstate_strict, 1027 "value 0 or non-zero. non-zero -> strict ACPI checks are " 1028 "performed during frequency changes."); 1029 1030 late_initcall(acpi_cpufreq_init); 1031 module_exit(acpi_cpufreq_exit); 1032 1033 static const struct x86_cpu_id acpi_cpufreq_ids[] = { 1034 X86_FEATURE_MATCH(X86_FEATURE_ACPI), 1035 X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), 1036 {} 1037 }; 1038 MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); 1039 1040 MODULE_ALIAS("acpi"); 1041