1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ECAP Capture driver 4 * 5 * Copyright (C) 2022 Julien Panis <jpanis@baylibre.com> 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/clk.h> 10 #include <linux/counter.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/mutex.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 21 #define ECAP_DRV_NAME "ecap" 22 23 /* ECAP event IDs */ 24 #define ECAP_CEVT1 0 25 #define ECAP_CEVT2 1 26 #define ECAP_CEVT3 2 27 #define ECAP_CEVT4 3 28 #define ECAP_CNTOVF 4 29 30 #define ECAP_CEVT_LAST ECAP_CEVT4 31 #define ECAP_NB_CEVT (ECAP_CEVT_LAST + 1) 32 33 #define ECAP_EVT_LAST ECAP_CNTOVF 34 #define ECAP_NB_EVT (ECAP_EVT_LAST + 1) 35 36 /* Registers */ 37 #define ECAP_TSCNT_REG 0x00 38 39 #define ECAP_CAP_REG(i) (((i) << 2) + 0x08) 40 41 #define ECAP_ECCTL_REG 0x28 42 #define ECAP_CAPPOL_BIT(i) BIT((i) << 1) 43 #define ECAP_EV_MODE_MASK GENMASK(7, 0) 44 #define ECAP_CAPLDEN_BIT BIT(8) 45 #define ECAP_CONT_ONESHT_BIT BIT(16) 46 #define ECAP_STOPVALUE_MASK GENMASK(18, 17) 47 #define ECAP_TSCNTSTP_BIT BIT(20) 48 #define ECAP_SYNCO_DIS_MASK GENMASK(23, 22) 49 #define ECAP_CAP_APWM_BIT BIT(25) 50 #define ECAP_ECCTL_EN_MASK (ECAP_CAPLDEN_BIT | ECAP_TSCNTSTP_BIT) 51 #define ECAP_ECCTL_CFG_MASK (ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK \ 52 | ECAP_ECCTL_EN_MASK | ECAP_CAP_APWM_BIT \ 53 | ECAP_CONT_ONESHT_BIT) 54 55 #define ECAP_ECINT_EN_FLG_REG 0x2c 56 #define ECAP_EVT_EN_MASK GENMASK(ECAP_NB_EVT, ECAP_NB_CEVT) 57 #define ECAP_EVT_FLG_BIT(i) BIT((i) + 17) 58 59 #define ECAP_ECINT_CLR_FRC_REG 0x30 60 #define ECAP_INT_CLR_BIT BIT(0) 61 #define ECAP_EVT_CLR_BIT(i) BIT((i) + 1) 62 #define ECAP_EVT_CLR_MASK GENMASK(ECAP_NB_EVT, 0) 63 64 #define ECAP_PID_REG 0x5c 65 66 /* ECAP signals */ 67 #define ECAP_CLOCK_SIG 0 68 #define ECAP_INPUT_SIG 1 69 70 static const struct regmap_config ecap_cnt_regmap_config = { 71 .reg_bits = 32, 72 .reg_stride = 4, 73 .val_bits = 32, 74 .max_register = ECAP_PID_REG, 75 }; 76 77 /** 78 * struct ecap_cnt_dev - device private data structure 79 * @enabled: device state 80 * @lock: synchronization lock to prevent I/O race conditions 81 * @clk: device clock 82 * @regmap: device register map 83 * @nb_ovf: number of overflows since capture start 84 * @pm_ctx: device context for PM operations 85 * @pm_ctx.ev_mode: event mode bits 86 * @pm_ctx.time_cntr: timestamp counter value 87 */ 88 struct ecap_cnt_dev { 89 bool enabled; 90 struct mutex lock; 91 struct clk *clk; 92 struct regmap *regmap; 93 atomic_t nb_ovf; 94 struct { 95 u8 ev_mode; 96 u32 time_cntr; 97 } pm_ctx; 98 }; 99 100 static u8 ecap_cnt_capture_get_evmode(struct counter_device *counter) 101 { 102 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 103 unsigned int regval; 104 105 pm_runtime_get_sync(counter->parent); 106 regmap_read(ecap_dev->regmap, ECAP_ECCTL_REG, ®val); 107 pm_runtime_put_sync(counter->parent); 108 109 return regval; 110 } 111 112 static void ecap_cnt_capture_set_evmode(struct counter_device *counter, u8 ev_mode) 113 { 114 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 115 116 pm_runtime_get_sync(counter->parent); 117 regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_EV_MODE_MASK, ev_mode); 118 pm_runtime_put_sync(counter->parent); 119 } 120 121 static void ecap_cnt_capture_enable(struct counter_device *counter) 122 { 123 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 124 125 pm_runtime_get_sync(counter->parent); 126 127 /* Enable interrupts on events */ 128 regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, 129 ECAP_EVT_EN_MASK, ECAP_EVT_EN_MASK); 130 131 /* Run counter */ 132 regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_CFG_MASK, 133 ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK | ECAP_ECCTL_EN_MASK); 134 } 135 136 static void ecap_cnt_capture_disable(struct counter_device *counter) 137 { 138 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 139 140 /* Stop counter */ 141 regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_EN_MASK, 0); 142 143 /* Disable interrupts on events */ 144 regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, ECAP_EVT_EN_MASK, 0); 145 146 pm_runtime_put_sync(counter->parent); 147 } 148 149 static u32 ecap_cnt_count_get_val(struct counter_device *counter, unsigned int reg) 150 { 151 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 152 unsigned int regval; 153 154 pm_runtime_get_sync(counter->parent); 155 regmap_read(ecap_dev->regmap, reg, ®val); 156 pm_runtime_put_sync(counter->parent); 157 158 return regval; 159 } 160 161 static void ecap_cnt_count_set_val(struct counter_device *counter, unsigned int reg, u32 val) 162 { 163 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 164 165 pm_runtime_get_sync(counter->parent); 166 regmap_write(ecap_dev->regmap, reg, val); 167 pm_runtime_put_sync(counter->parent); 168 } 169 170 static int ecap_cnt_count_read(struct counter_device *counter, 171 struct counter_count *count, u64 *val) 172 { 173 *val = ecap_cnt_count_get_val(counter, ECAP_TSCNT_REG); 174 175 return 0; 176 } 177 178 static int ecap_cnt_count_write(struct counter_device *counter, 179 struct counter_count *count, u64 val) 180 { 181 if (val > U32_MAX) 182 return -ERANGE; 183 184 ecap_cnt_count_set_val(counter, ECAP_TSCNT_REG, val); 185 186 return 0; 187 } 188 189 static int ecap_cnt_function_read(struct counter_device *counter, 190 struct counter_count *count, 191 enum counter_function *function) 192 { 193 *function = COUNTER_FUNCTION_INCREASE; 194 195 return 0; 196 } 197 198 static int ecap_cnt_action_read(struct counter_device *counter, 199 struct counter_count *count, 200 struct counter_synapse *synapse, 201 enum counter_synapse_action *action) 202 { 203 *action = (synapse->signal->id == ECAP_CLOCK_SIG) ? 204 COUNTER_SYNAPSE_ACTION_RISING_EDGE : 205 COUNTER_SYNAPSE_ACTION_NONE; 206 207 return 0; 208 } 209 210 static int ecap_cnt_watch_validate(struct counter_device *counter, 211 const struct counter_watch *watch) 212 { 213 if (watch->channel > ECAP_CEVT_LAST) 214 return -EINVAL; 215 216 switch (watch->event) { 217 case COUNTER_EVENT_CAPTURE: 218 case COUNTER_EVENT_OVERFLOW: 219 return 0; 220 default: 221 return -EINVAL; 222 } 223 } 224 225 static int ecap_cnt_clk_get_freq(struct counter_device *counter, 226 struct counter_signal *signal, u64 *freq) 227 { 228 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 229 230 *freq = clk_get_rate(ecap_dev->clk); 231 232 return 0; 233 } 234 235 static int ecap_cnt_pol_read(struct counter_device *counter, 236 struct counter_signal *signal, 237 size_t idx, enum counter_signal_polarity *pol) 238 { 239 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 240 int bitval; 241 242 pm_runtime_get_sync(counter->parent); 243 bitval = regmap_test_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); 244 pm_runtime_put_sync(counter->parent); 245 246 *pol = bitval ? COUNTER_SIGNAL_POLARITY_NEGATIVE : COUNTER_SIGNAL_POLARITY_POSITIVE; 247 248 return 0; 249 } 250 251 static int ecap_cnt_pol_write(struct counter_device *counter, 252 struct counter_signal *signal, 253 size_t idx, enum counter_signal_polarity pol) 254 { 255 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 256 257 pm_runtime_get_sync(counter->parent); 258 if (pol == COUNTER_SIGNAL_POLARITY_NEGATIVE) 259 regmap_set_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); 260 else 261 regmap_clear_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); 262 pm_runtime_put_sync(counter->parent); 263 264 return 0; 265 } 266 267 static int ecap_cnt_cap_read(struct counter_device *counter, 268 struct counter_count *count, 269 size_t idx, u64 *cap) 270 { 271 *cap = ecap_cnt_count_get_val(counter, ECAP_CAP_REG(idx)); 272 273 return 0; 274 } 275 276 static int ecap_cnt_cap_write(struct counter_device *counter, 277 struct counter_count *count, 278 size_t idx, u64 cap) 279 { 280 if (cap > U32_MAX) 281 return -ERANGE; 282 283 ecap_cnt_count_set_val(counter, ECAP_CAP_REG(idx), cap); 284 285 return 0; 286 } 287 288 static int ecap_cnt_nb_ovf_read(struct counter_device *counter, 289 struct counter_count *count, u64 *val) 290 { 291 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 292 293 *val = atomic_read(&ecap_dev->nb_ovf); 294 295 return 0; 296 } 297 298 static int ecap_cnt_nb_ovf_write(struct counter_device *counter, 299 struct counter_count *count, u64 val) 300 { 301 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 302 303 if (val > U32_MAX) 304 return -ERANGE; 305 306 atomic_set(&ecap_dev->nb_ovf, val); 307 308 return 0; 309 } 310 311 static int ecap_cnt_ceiling_read(struct counter_device *counter, 312 struct counter_count *count, u64 *val) 313 { 314 *val = U32_MAX; 315 316 return 0; 317 } 318 319 static int ecap_cnt_enable_read(struct counter_device *counter, 320 struct counter_count *count, u8 *enable) 321 { 322 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 323 324 *enable = ecap_dev->enabled; 325 326 return 0; 327 } 328 329 static int ecap_cnt_enable_write(struct counter_device *counter, 330 struct counter_count *count, u8 enable) 331 { 332 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 333 334 mutex_lock(&ecap_dev->lock); 335 336 if (enable == ecap_dev->enabled) 337 goto out; 338 339 if (enable) 340 ecap_cnt_capture_enable(counter); 341 else 342 ecap_cnt_capture_disable(counter); 343 ecap_dev->enabled = enable; 344 345 out: 346 mutex_unlock(&ecap_dev->lock); 347 348 return 0; 349 } 350 351 static const struct counter_ops ecap_cnt_ops = { 352 .count_read = ecap_cnt_count_read, 353 .count_write = ecap_cnt_count_write, 354 .function_read = ecap_cnt_function_read, 355 .action_read = ecap_cnt_action_read, 356 .watch_validate = ecap_cnt_watch_validate, 357 }; 358 359 static const enum counter_function ecap_cnt_functions[] = { 360 COUNTER_FUNCTION_INCREASE, 361 }; 362 363 static const enum counter_synapse_action ecap_cnt_clock_actions[] = { 364 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 365 }; 366 367 static const enum counter_synapse_action ecap_cnt_input_actions[] = { 368 COUNTER_SYNAPSE_ACTION_NONE, 369 }; 370 371 static struct counter_comp ecap_cnt_clock_ext[] = { 372 COUNTER_COMP_SIGNAL_U64("frequency", ecap_cnt_clk_get_freq, NULL), 373 }; 374 375 static const enum counter_signal_polarity ecap_cnt_pol_avail[] = { 376 COUNTER_SIGNAL_POLARITY_POSITIVE, 377 COUNTER_SIGNAL_POLARITY_NEGATIVE, 378 }; 379 380 static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_avail, ECAP_NB_CEVT); 381 382 static struct counter_comp ecap_cnt_signal_ext[] = { 383 COUNTER_COMP_ARRAY_POLARITY(ecap_cnt_pol_read, ecap_cnt_pol_write, ecap_cnt_pol_array), 384 }; 385 386 static struct counter_signal ecap_cnt_signals[] = { 387 { 388 .id = ECAP_CLOCK_SIG, 389 .name = "Clock Signal", 390 .ext = ecap_cnt_clock_ext, 391 .num_ext = ARRAY_SIZE(ecap_cnt_clock_ext), 392 }, 393 { 394 .id = ECAP_INPUT_SIG, 395 .name = "Input Signal", 396 .ext = ecap_cnt_signal_ext, 397 .num_ext = ARRAY_SIZE(ecap_cnt_signal_ext), 398 }, 399 }; 400 401 static struct counter_synapse ecap_cnt_synapses[] = { 402 { 403 .actions_list = ecap_cnt_clock_actions, 404 .num_actions = ARRAY_SIZE(ecap_cnt_clock_actions), 405 .signal = &ecap_cnt_signals[ECAP_CLOCK_SIG], 406 }, 407 { 408 .actions_list = ecap_cnt_input_actions, 409 .num_actions = ARRAY_SIZE(ecap_cnt_input_actions), 410 .signal = &ecap_cnt_signals[ECAP_INPUT_SIG], 411 }, 412 }; 413 414 static DEFINE_COUNTER_ARRAY_CAPTURE(ecap_cnt_cap_array, ECAP_NB_CEVT); 415 416 static struct counter_comp ecap_cnt_count_ext[] = { 417 COUNTER_COMP_ARRAY_CAPTURE(ecap_cnt_cap_read, ecap_cnt_cap_write, ecap_cnt_cap_array), 418 COUNTER_COMP_COUNT_U64("num_overflows", ecap_cnt_nb_ovf_read, ecap_cnt_nb_ovf_write), 419 COUNTER_COMP_CEILING(ecap_cnt_ceiling_read, NULL), 420 COUNTER_COMP_ENABLE(ecap_cnt_enable_read, ecap_cnt_enable_write), 421 }; 422 423 static struct counter_count ecap_cnt_counts[] = { 424 { 425 .name = "Timestamp Counter", 426 .functions_list = ecap_cnt_functions, 427 .num_functions = ARRAY_SIZE(ecap_cnt_functions), 428 .synapses = ecap_cnt_synapses, 429 .num_synapses = ARRAY_SIZE(ecap_cnt_synapses), 430 .ext = ecap_cnt_count_ext, 431 .num_ext = ARRAY_SIZE(ecap_cnt_count_ext), 432 }, 433 }; 434 435 static irqreturn_t ecap_cnt_isr(int irq, void *dev_id) 436 { 437 struct counter_device *counter_dev = dev_id; 438 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 439 unsigned int clr = 0; 440 unsigned int flg; 441 int i; 442 443 regmap_read(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, &flg); 444 445 /* Check capture events */ 446 for (i = 0 ; i < ECAP_NB_CEVT ; i++) { 447 if (flg & ECAP_EVT_FLG_BIT(i)) { 448 counter_push_event(counter_dev, COUNTER_EVENT_CAPTURE, i); 449 clr |= ECAP_EVT_CLR_BIT(i); 450 } 451 } 452 453 /* Check counter overflow */ 454 if (flg & ECAP_EVT_FLG_BIT(ECAP_CNTOVF)) { 455 atomic_inc(&ecap_dev->nb_ovf); 456 for (i = 0 ; i < ECAP_NB_CEVT ; i++) 457 counter_push_event(counter_dev, COUNTER_EVENT_OVERFLOW, i); 458 clr |= ECAP_EVT_CLR_BIT(ECAP_CNTOVF); 459 } 460 461 clr |= ECAP_INT_CLR_BIT; 462 regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_CLR_FRC_REG, ECAP_EVT_CLR_MASK, clr); 463 464 return IRQ_HANDLED; 465 } 466 467 static void ecap_cnt_pm_disable(void *dev) 468 { 469 pm_runtime_disable(dev); 470 } 471 472 static int ecap_cnt_probe(struct platform_device *pdev) 473 { 474 struct device *dev = &pdev->dev; 475 struct ecap_cnt_dev *ecap_dev; 476 struct counter_device *counter_dev; 477 void __iomem *mmio_base; 478 unsigned long clk_rate; 479 int ret; 480 481 counter_dev = devm_counter_alloc(dev, sizeof(*ecap_dev)); 482 if (IS_ERR(counter_dev)) 483 return PTR_ERR(counter_dev); 484 485 counter_dev->name = ECAP_DRV_NAME; 486 counter_dev->parent = dev; 487 counter_dev->ops = &ecap_cnt_ops; 488 counter_dev->signals = ecap_cnt_signals; 489 counter_dev->num_signals = ARRAY_SIZE(ecap_cnt_signals); 490 counter_dev->counts = ecap_cnt_counts; 491 counter_dev->num_counts = ARRAY_SIZE(ecap_cnt_counts); 492 493 ecap_dev = counter_priv(counter_dev); 494 495 mutex_init(&ecap_dev->lock); 496 497 ecap_dev->clk = devm_clk_get_enabled(dev, "fck"); 498 if (IS_ERR(ecap_dev->clk)) 499 return dev_err_probe(dev, PTR_ERR(ecap_dev->clk), "failed to get clock\n"); 500 501 clk_rate = clk_get_rate(ecap_dev->clk); 502 if (!clk_rate) { 503 dev_err(dev, "failed to get clock rate\n"); 504 return -EINVAL; 505 } 506 507 mmio_base = devm_platform_ioremap_resource(pdev, 0); 508 if (IS_ERR(mmio_base)) 509 return PTR_ERR(mmio_base); 510 511 ecap_dev->regmap = devm_regmap_init_mmio(dev, mmio_base, &ecap_cnt_regmap_config); 512 if (IS_ERR(ecap_dev->regmap)) 513 return dev_err_probe(dev, PTR_ERR(ecap_dev->regmap), "failed to init regmap\n"); 514 515 ret = platform_get_irq(pdev, 0); 516 if (ret < 0) 517 return dev_err_probe(dev, ret, "failed to get irq\n"); 518 519 ret = devm_request_irq(dev, ret, ecap_cnt_isr, 0, pdev->name, counter_dev); 520 if (ret) 521 return dev_err_probe(dev, ret, "failed to request irq\n"); 522 523 platform_set_drvdata(pdev, counter_dev); 524 525 pm_runtime_enable(dev); 526 527 /* Register a cleanup callback to care for disabling PM */ 528 ret = devm_add_action_or_reset(dev, ecap_cnt_pm_disable, dev); 529 if (ret) 530 return dev_err_probe(dev, ret, "failed to add pm disable action\n"); 531 532 ret = devm_counter_add(dev, counter_dev); 533 if (ret) 534 return dev_err_probe(dev, ret, "failed to add counter\n"); 535 536 return 0; 537 } 538 539 static int ecap_cnt_remove(struct platform_device *pdev) 540 { 541 struct counter_device *counter_dev = platform_get_drvdata(pdev); 542 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 543 544 if (ecap_dev->enabled) 545 ecap_cnt_capture_disable(counter_dev); 546 547 return 0; 548 } 549 550 static int ecap_cnt_suspend(struct device *dev) 551 { 552 struct counter_device *counter_dev = dev_get_drvdata(dev); 553 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 554 555 /* If eCAP is running, stop capture then save timestamp counter */ 556 if (ecap_dev->enabled) { 557 /* 558 * Disabling capture has the following effects: 559 * - interrupts are disabled 560 * - loading of capture registers is disabled 561 * - timebase counter is stopped 562 */ 563 ecap_cnt_capture_disable(counter_dev); 564 ecap_dev->pm_ctx.time_cntr = ecap_cnt_count_get_val(counter_dev, ECAP_TSCNT_REG); 565 } 566 567 ecap_dev->pm_ctx.ev_mode = ecap_cnt_capture_get_evmode(counter_dev); 568 569 clk_disable(ecap_dev->clk); 570 571 return 0; 572 } 573 574 static int ecap_cnt_resume(struct device *dev) 575 { 576 struct counter_device *counter_dev = dev_get_drvdata(dev); 577 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 578 579 clk_enable(ecap_dev->clk); 580 581 ecap_cnt_capture_set_evmode(counter_dev, ecap_dev->pm_ctx.ev_mode); 582 583 /* If eCAP was running, restore timestamp counter then run capture */ 584 if (ecap_dev->enabled) { 585 ecap_cnt_count_set_val(counter_dev, ECAP_TSCNT_REG, ecap_dev->pm_ctx.time_cntr); 586 ecap_cnt_capture_enable(counter_dev); 587 } 588 589 return 0; 590 } 591 592 static DEFINE_SIMPLE_DEV_PM_OPS(ecap_cnt_pm_ops, ecap_cnt_suspend, ecap_cnt_resume); 593 594 static const struct of_device_id ecap_cnt_of_match[] = { 595 { .compatible = "ti,am62-ecap-capture" }, 596 {}, 597 }; 598 MODULE_DEVICE_TABLE(of, ecap_cnt_of_match); 599 600 static struct platform_driver ecap_cnt_driver = { 601 .probe = ecap_cnt_probe, 602 .remove = ecap_cnt_remove, 603 .driver = { 604 .name = "ecap-capture", 605 .of_match_table = ecap_cnt_of_match, 606 .pm = pm_sleep_ptr(&ecap_cnt_pm_ops), 607 }, 608 }; 609 module_platform_driver(ecap_cnt_driver); 610 611 MODULE_DESCRIPTION("ECAP Capture driver"); 612 MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>"); 613 MODULE_LICENSE("GPL"); 614 MODULE_IMPORT_NS(COUNTER); 615