1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 Microchip 4 * 5 * Author: Kamel Bouhara <kamel.bouhara@bootlin.com> 6 */ 7 #include <linux/clk.h> 8 #include <linux/counter.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/module.h> 11 #include <linux/mutex.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <soc/at91/atmel_tcb.h> 17 18 #define ATMEL_TC_CMR_MASK (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \ 19 ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \ 20 ATMEL_TC_LDBSTOP) 21 22 #define ATMEL_TC_QDEN BIT(8) 23 #define ATMEL_TC_POSEN BIT(9) 24 25 struct mchp_tc_data { 26 const struct atmel_tcb_config *tc_cfg; 27 struct counter_device counter; 28 struct regmap *regmap; 29 int qdec_mode; 30 int num_channels; 31 int channel[2]; 32 bool trig_inverted; 33 }; 34 35 static const enum counter_function mchp_tc_count_functions[] = { 36 COUNTER_FUNCTION_INCREASE, 37 COUNTER_FUNCTION_QUADRATURE_X4, 38 }; 39 40 static const enum counter_synapse_action mchp_tc_synapse_actions[] = { 41 COUNTER_SYNAPSE_ACTION_NONE, 42 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 43 COUNTER_SYNAPSE_ACTION_FALLING_EDGE, 44 COUNTER_SYNAPSE_ACTION_BOTH_EDGES, 45 }; 46 47 static struct counter_signal mchp_tc_count_signals[] = { 48 { 49 .id = 0, 50 .name = "Channel A", 51 }, 52 { 53 .id = 1, 54 .name = "Channel B", 55 } 56 }; 57 58 static struct counter_synapse mchp_tc_count_synapses[] = { 59 { 60 .actions_list = mchp_tc_synapse_actions, 61 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions), 62 .signal = &mchp_tc_count_signals[0] 63 }, 64 { 65 .actions_list = mchp_tc_synapse_actions, 66 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions), 67 .signal = &mchp_tc_count_signals[1] 68 } 69 }; 70 71 static int mchp_tc_count_function_read(struct counter_device *counter, 72 struct counter_count *count, 73 enum counter_function *function) 74 { 75 struct mchp_tc_data *const priv = counter->priv; 76 77 if (priv->qdec_mode) 78 *function = COUNTER_FUNCTION_QUADRATURE_X4; 79 else 80 *function = COUNTER_FUNCTION_INCREASE; 81 82 return 0; 83 } 84 85 static int mchp_tc_count_function_write(struct counter_device *counter, 86 struct counter_count *count, 87 enum counter_function function) 88 { 89 struct mchp_tc_data *const priv = counter->priv; 90 u32 bmr, cmr; 91 92 regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr); 93 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr); 94 95 /* Set capture mode */ 96 cmr &= ~ATMEL_TC_WAVE; 97 98 switch (function) { 99 case COUNTER_FUNCTION_INCREASE: 100 priv->qdec_mode = 0; 101 /* Set highest rate based on whether soc has gclk or not */ 102 bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN); 103 if (priv->tc_cfg->has_gclk) 104 cmr |= ATMEL_TC_TIMER_CLOCK2; 105 else 106 cmr |= ATMEL_TC_TIMER_CLOCK1; 107 /* Setup the period capture mode */ 108 cmr |= ATMEL_TC_CMR_MASK; 109 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0); 110 break; 111 case COUNTER_FUNCTION_QUADRATURE_X4: 112 if (!priv->tc_cfg->has_qdec) 113 return -EINVAL; 114 /* In QDEC mode settings both channels 0 and 1 are required */ 115 if (priv->num_channels < 2 || priv->channel[0] != 0 || 116 priv->channel[1] != 1) { 117 pr_err("Invalid channels number or id for quadrature mode\n"); 118 return -EINVAL; 119 } 120 priv->qdec_mode = 1; 121 bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN; 122 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0; 123 break; 124 default: 125 /* should never reach this path */ 126 return -EINVAL; 127 } 128 129 regmap_write(priv->regmap, ATMEL_TC_BMR, bmr); 130 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr); 131 132 /* Enable clock and trigger counter */ 133 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), 134 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG); 135 136 if (priv->qdec_mode) { 137 regmap_write(priv->regmap, 138 ATMEL_TC_REG(priv->channel[1], CMR), cmr); 139 regmap_write(priv->regmap, 140 ATMEL_TC_REG(priv->channel[1], CCR), 141 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG); 142 } 143 144 return 0; 145 } 146 147 static int mchp_tc_count_signal_read(struct counter_device *counter, 148 struct counter_signal *signal, 149 enum counter_signal_level *lvl) 150 { 151 struct mchp_tc_data *const priv = counter->priv; 152 bool sigstatus; 153 u32 sr; 154 155 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr); 156 157 if (priv->trig_inverted) 158 sigstatus = (sr & ATMEL_TC_MTIOB); 159 else 160 sigstatus = (sr & ATMEL_TC_MTIOA); 161 162 *lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; 163 164 return 0; 165 } 166 167 static int mchp_tc_count_action_read(struct counter_device *counter, 168 struct counter_count *count, 169 struct counter_synapse *synapse, 170 enum counter_synapse_action *action) 171 { 172 struct mchp_tc_data *const priv = counter->priv; 173 u32 cmr; 174 175 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr); 176 177 switch (cmr & ATMEL_TC_ETRGEDG) { 178 default: 179 *action = COUNTER_SYNAPSE_ACTION_NONE; 180 break; 181 case ATMEL_TC_ETRGEDG_RISING: 182 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 183 break; 184 case ATMEL_TC_ETRGEDG_FALLING: 185 *action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE; 186 break; 187 case ATMEL_TC_ETRGEDG_BOTH: 188 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 189 break; 190 } 191 192 return 0; 193 } 194 195 static int mchp_tc_count_action_write(struct counter_device *counter, 196 struct counter_count *count, 197 struct counter_synapse *synapse, 198 enum counter_synapse_action action) 199 { 200 struct mchp_tc_data *const priv = counter->priv; 201 u32 edge = ATMEL_TC_ETRGEDG_NONE; 202 203 /* QDEC mode is rising edge only */ 204 if (priv->qdec_mode) 205 return -EINVAL; 206 207 switch (action) { 208 case COUNTER_SYNAPSE_ACTION_NONE: 209 edge = ATMEL_TC_ETRGEDG_NONE; 210 break; 211 case COUNTER_SYNAPSE_ACTION_RISING_EDGE: 212 edge = ATMEL_TC_ETRGEDG_RISING; 213 break; 214 case COUNTER_SYNAPSE_ACTION_FALLING_EDGE: 215 edge = ATMEL_TC_ETRGEDG_FALLING; 216 break; 217 case COUNTER_SYNAPSE_ACTION_BOTH_EDGES: 218 edge = ATMEL_TC_ETRGEDG_BOTH; 219 break; 220 default: 221 /* should never reach this path */ 222 return -EINVAL; 223 } 224 225 return regmap_write_bits(priv->regmap, 226 ATMEL_TC_REG(priv->channel[0], CMR), 227 ATMEL_TC_ETRGEDG, edge); 228 } 229 230 static int mchp_tc_count_read(struct counter_device *counter, 231 struct counter_count *count, u64 *val) 232 { 233 struct mchp_tc_data *const priv = counter->priv; 234 u32 cnt; 235 236 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt); 237 *val = cnt; 238 239 return 0; 240 } 241 242 static struct counter_count mchp_tc_counts[] = { 243 { 244 .id = 0, 245 .name = "Timer Counter", 246 .functions_list = mchp_tc_count_functions, 247 .num_functions = ARRAY_SIZE(mchp_tc_count_functions), 248 .synapses = mchp_tc_count_synapses, 249 .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses), 250 }, 251 }; 252 253 static const struct counter_ops mchp_tc_ops = { 254 .signal_read = mchp_tc_count_signal_read, 255 .count_read = mchp_tc_count_read, 256 .function_read = mchp_tc_count_function_read, 257 .function_write = mchp_tc_count_function_write, 258 .action_read = mchp_tc_count_action_read, 259 .action_write = mchp_tc_count_action_write 260 }; 261 262 static const struct atmel_tcb_config tcb_rm9200_config = { 263 .counter_width = 16, 264 }; 265 266 static const struct atmel_tcb_config tcb_sam9x5_config = { 267 .counter_width = 32, 268 }; 269 270 static const struct atmel_tcb_config tcb_sama5d2_config = { 271 .counter_width = 32, 272 .has_gclk = true, 273 .has_qdec = true, 274 }; 275 276 static const struct atmel_tcb_config tcb_sama5d3_config = { 277 .counter_width = 32, 278 .has_qdec = true, 279 }; 280 281 static const struct of_device_id atmel_tc_of_match[] = { 282 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, }, 283 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, }, 284 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, }, 285 { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, }, 286 { /* sentinel */ } 287 }; 288 289 static void mchp_tc_clk_remove(void *ptr) 290 { 291 clk_disable_unprepare((struct clk *)ptr); 292 } 293 294 static int mchp_tc_probe(struct platform_device *pdev) 295 { 296 struct device_node *np = pdev->dev.of_node; 297 const struct atmel_tcb_config *tcb_config; 298 const struct of_device_id *match; 299 struct mchp_tc_data *priv; 300 char clk_name[7]; 301 struct regmap *regmap; 302 struct clk *clk[3]; 303 int channel; 304 int ret, i; 305 306 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 307 if (!priv) 308 return -ENOMEM; 309 310 platform_set_drvdata(pdev, priv); 311 312 match = of_match_node(atmel_tc_of_match, np->parent); 313 tcb_config = match->data; 314 if (!tcb_config) { 315 dev_err(&pdev->dev, "No matching parent node found\n"); 316 return -ENODEV; 317 } 318 319 regmap = syscon_node_to_regmap(np->parent); 320 if (IS_ERR(regmap)) 321 return PTR_ERR(regmap); 322 323 /* max. channels number is 2 when in QDEC mode */ 324 priv->num_channels = of_property_count_u32_elems(np, "reg"); 325 if (priv->num_channels < 0) { 326 dev_err(&pdev->dev, "Invalid or missing channel\n"); 327 return -EINVAL; 328 } 329 330 /* Register channels and initialize clocks */ 331 for (i = 0; i < priv->num_channels; i++) { 332 ret = of_property_read_u32_index(np, "reg", i, &channel); 333 if (ret < 0 || channel > 2) 334 return -ENODEV; 335 336 priv->channel[i] = channel; 337 338 snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel); 339 340 clk[i] = of_clk_get_by_name(np->parent, clk_name); 341 if (IS_ERR(clk[i])) { 342 /* Fallback to t0_clk */ 343 clk[i] = of_clk_get_by_name(np->parent, "t0_clk"); 344 if (IS_ERR(clk[i])) 345 return PTR_ERR(clk[i]); 346 } 347 348 ret = clk_prepare_enable(clk[i]); 349 if (ret) 350 return ret; 351 352 ret = devm_add_action_or_reset(&pdev->dev, 353 mchp_tc_clk_remove, 354 clk[i]); 355 if (ret) 356 return ret; 357 358 dev_dbg(&pdev->dev, 359 "Initialized capture mode on channel %d\n", 360 channel); 361 } 362 363 priv->tc_cfg = tcb_config; 364 priv->regmap = regmap; 365 priv->counter.name = dev_name(&pdev->dev); 366 priv->counter.parent = &pdev->dev; 367 priv->counter.ops = &mchp_tc_ops; 368 priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts); 369 priv->counter.counts = mchp_tc_counts; 370 priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals); 371 priv->counter.signals = mchp_tc_count_signals; 372 priv->counter.priv = priv; 373 374 return devm_counter_register(&pdev->dev, &priv->counter); 375 } 376 377 static const struct of_device_id mchp_tc_dt_ids[] = { 378 { .compatible = "microchip,tcb-capture", }, 379 { /* sentinel */ }, 380 }; 381 MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids); 382 383 static struct platform_driver mchp_tc_driver = { 384 .probe = mchp_tc_probe, 385 .driver = { 386 .name = "microchip-tcb-capture", 387 .of_match_table = mchp_tc_dt_ids, 388 }, 389 }; 390 module_platform_driver(mchp_tc_driver); 391 392 MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>"); 393 MODULE_DESCRIPTION("Microchip TCB Capture driver"); 394 MODULE_LICENSE("GPL v2"); 395