xref: /openbmc/linux/drivers/counter/ftm-quaddec.c (revision ac5f3136)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Flex Timer Module Quadrature decoder
4  *
5  * This module implements a driver for decoding the FTM quadrature
6  * of ex. a LS1021A
7  */
8 
9 #include <linux/fsl/ftm.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13 #include <linux/io.h>
14 #include <linux/mutex.h>
15 #include <linux/counter.h>
16 #include <linux/bitfield.h>
17 
18 #define FTM_FIELD_UPDATE(ftm, offset, mask, val)			\
19 	({								\
20 		uint32_t flags;						\
21 		ftm_read(ftm, offset, &flags);				\
22 		flags &= ~mask;						\
23 		flags |= FIELD_PREP(mask, val);				\
24 		ftm_write(ftm, offset, flags);				\
25 	})
26 
27 struct ftm_quaddec {
28 	struct counter_device counter;
29 	struct platform_device *pdev;
30 	void __iomem *ftm_base;
31 	bool big_endian;
32 	struct mutex ftm_quaddec_mutex;
33 };
34 
35 static void ftm_read(struct ftm_quaddec *ftm, uint32_t offset, uint32_t *data)
36 {
37 	if (ftm->big_endian)
38 		*data = ioread32be(ftm->ftm_base + offset);
39 	else
40 		*data = ioread32(ftm->ftm_base + offset);
41 }
42 
43 static void ftm_write(struct ftm_quaddec *ftm, uint32_t offset, uint32_t data)
44 {
45 	if (ftm->big_endian)
46 		iowrite32be(data, ftm->ftm_base + offset);
47 	else
48 		iowrite32(data, ftm->ftm_base + offset);
49 }
50 
51 /* Hold mutex before modifying write protection state */
52 static void ftm_clear_write_protection(struct ftm_quaddec *ftm)
53 {
54 	uint32_t flag;
55 
56 	/* First see if it is enabled */
57 	ftm_read(ftm, FTM_FMS, &flag);
58 
59 	if (flag & FTM_FMS_WPEN)
60 		FTM_FIELD_UPDATE(ftm, FTM_MODE, FTM_MODE_WPDIS, 1);
61 }
62 
63 static void ftm_set_write_protection(struct ftm_quaddec *ftm)
64 {
65 	FTM_FIELD_UPDATE(ftm, FTM_FMS, FTM_FMS_WPEN, 1);
66 }
67 
68 static void ftm_reset_counter(struct ftm_quaddec *ftm)
69 {
70 	/* Reset hardware counter to CNTIN */
71 	ftm_write(ftm, FTM_CNT, 0x0);
72 }
73 
74 static void ftm_quaddec_init(struct ftm_quaddec *ftm)
75 {
76 	ftm_clear_write_protection(ftm);
77 
78 	/*
79 	 * Do not write in the region from the CNTIN register through the
80 	 * PWMLOAD register when FTMEN = 0.
81 	 * Also reset other fields to zero
82 	 */
83 	ftm_write(ftm, FTM_MODE, FTM_MODE_FTMEN);
84 	ftm_write(ftm, FTM_CNTIN, 0x0000);
85 	ftm_write(ftm, FTM_MOD, 0xffff);
86 	ftm_write(ftm, FTM_CNT, 0x0);
87 	/* Set prescaler, reset other fields to zero */
88 	ftm_write(ftm, FTM_SC, FTM_SC_PS_1);
89 
90 	/* Select quad mode, reset other fields to zero */
91 	ftm_write(ftm, FTM_QDCTRL, FTM_QDCTRL_QUADEN);
92 
93 	/* Unused features and reset to default section */
94 	ftm_write(ftm, FTM_POL, 0x0);
95 	ftm_write(ftm, FTM_FLTCTRL, 0x0);
96 	ftm_write(ftm, FTM_SYNCONF, 0x0);
97 	ftm_write(ftm, FTM_SYNC, 0xffff);
98 
99 	/* Lock the FTM */
100 	ftm_set_write_protection(ftm);
101 }
102 
103 static void ftm_quaddec_disable(void *ftm)
104 {
105 	struct ftm_quaddec *ftm_qua = ftm;
106 
107 	ftm_clear_write_protection(ftm_qua);
108 	ftm_write(ftm_qua, FTM_MODE, 0);
109 	ftm_write(ftm_qua, FTM_QDCTRL, 0);
110 	/*
111 	 * This is enough to disable the counter. No clock has been
112 	 * selected by writing to FTM_SC in init()
113 	 */
114 	ftm_set_write_protection(ftm_qua);
115 }
116 
117 static int ftm_quaddec_get_prescaler(struct counter_device *counter,
118 				     struct counter_count *count,
119 				     size_t *cnt_mode)
120 {
121 	struct ftm_quaddec *ftm = counter->priv;
122 	uint32_t scflags;
123 
124 	ftm_read(ftm, FTM_SC, &scflags);
125 
126 	*cnt_mode = FIELD_GET(FTM_SC_PS_MASK, scflags);
127 
128 	return 0;
129 }
130 
131 static int ftm_quaddec_set_prescaler(struct counter_device *counter,
132 				     struct counter_count *count,
133 				     size_t cnt_mode)
134 {
135 	struct ftm_quaddec *ftm = counter->priv;
136 
137 	mutex_lock(&ftm->ftm_quaddec_mutex);
138 
139 	ftm_clear_write_protection(ftm);
140 	FTM_FIELD_UPDATE(ftm, FTM_SC, FTM_SC_PS_MASK, cnt_mode);
141 	ftm_set_write_protection(ftm);
142 
143 	/* Also resets the counter as it is undefined anyway now */
144 	ftm_reset_counter(ftm);
145 
146 	mutex_unlock(&ftm->ftm_quaddec_mutex);
147 	return 0;
148 }
149 
150 static const char * const ftm_quaddec_prescaler[] = {
151 	"1", "2", "4", "8", "16", "32", "64", "128"
152 };
153 
154 static struct counter_count_enum_ext ftm_quaddec_prescaler_enum = {
155 	.items = ftm_quaddec_prescaler,
156 	.num_items = ARRAY_SIZE(ftm_quaddec_prescaler),
157 	.get = ftm_quaddec_get_prescaler,
158 	.set = ftm_quaddec_set_prescaler
159 };
160 
161 enum ftm_quaddec_synapse_action {
162 	FTM_QUADDEC_SYNAPSE_ACTION_BOTH_EDGES,
163 };
164 
165 static const enum counter_synapse_action ftm_quaddec_synapse_actions[] = {
166 	[FTM_QUADDEC_SYNAPSE_ACTION_BOTH_EDGES] =
167 	COUNTER_SYNAPSE_ACTION_BOTH_EDGES
168 };
169 
170 enum ftm_quaddec_count_function {
171 	FTM_QUADDEC_COUNT_ENCODER_MODE_1,
172 };
173 
174 static const enum counter_function ftm_quaddec_count_functions[] = {
175 	[FTM_QUADDEC_COUNT_ENCODER_MODE_1] = COUNTER_FUNCTION_QUADRATURE_X4
176 };
177 
178 static int ftm_quaddec_count_read(struct counter_device *counter,
179 				  struct counter_count *count,
180 				  unsigned long *val)
181 {
182 	struct ftm_quaddec *const ftm = counter->priv;
183 	uint32_t cntval;
184 
185 	ftm_read(ftm, FTM_CNT, &cntval);
186 
187 	*val = cntval;
188 
189 	return 0;
190 }
191 
192 static int ftm_quaddec_count_write(struct counter_device *counter,
193 				   struct counter_count *count,
194 				   const unsigned long val)
195 {
196 	struct ftm_quaddec *const ftm = counter->priv;
197 
198 	if (val != 0) {
199 		dev_warn(&ftm->pdev->dev, "Can only accept '0' as new counter value\n");
200 		return -EINVAL;
201 	}
202 
203 	ftm_reset_counter(ftm);
204 
205 	return 0;
206 }
207 
208 static int ftm_quaddec_count_function_get(struct counter_device *counter,
209 					  struct counter_count *count,
210 					  size_t *function)
211 {
212 	*function = FTM_QUADDEC_COUNT_ENCODER_MODE_1;
213 
214 	return 0;
215 }
216 
217 static int ftm_quaddec_action_get(struct counter_device *counter,
218 				  struct counter_count *count,
219 				  struct counter_synapse *synapse,
220 				  size_t *action)
221 {
222 	*action = FTM_QUADDEC_SYNAPSE_ACTION_BOTH_EDGES;
223 
224 	return 0;
225 }
226 
227 static const struct counter_ops ftm_quaddec_cnt_ops = {
228 	.count_read = ftm_quaddec_count_read,
229 	.count_write = ftm_quaddec_count_write,
230 	.function_get = ftm_quaddec_count_function_get,
231 	.action_get = ftm_quaddec_action_get,
232 };
233 
234 static struct counter_signal ftm_quaddec_signals[] = {
235 	{
236 		.id = 0,
237 		.name = "Channel 1 Phase A"
238 	},
239 	{
240 		.id = 1,
241 		.name = "Channel 1 Phase B"
242 	}
243 };
244 
245 static struct counter_synapse ftm_quaddec_count_synapses[] = {
246 	{
247 		.actions_list = ftm_quaddec_synapse_actions,
248 		.num_actions = ARRAY_SIZE(ftm_quaddec_synapse_actions),
249 		.signal = &ftm_quaddec_signals[0]
250 	},
251 	{
252 		.actions_list = ftm_quaddec_synapse_actions,
253 		.num_actions = ARRAY_SIZE(ftm_quaddec_synapse_actions),
254 		.signal = &ftm_quaddec_signals[1]
255 	}
256 };
257 
258 static const struct counter_count_ext ftm_quaddec_count_ext[] = {
259 	COUNTER_COUNT_ENUM("prescaler", &ftm_quaddec_prescaler_enum),
260 	COUNTER_COUNT_ENUM_AVAILABLE("prescaler", &ftm_quaddec_prescaler_enum),
261 };
262 
263 static struct counter_count ftm_quaddec_counts = {
264 	.id = 0,
265 	.name = "Channel 1 Count",
266 	.functions_list = ftm_quaddec_count_functions,
267 	.num_functions = ARRAY_SIZE(ftm_quaddec_count_functions),
268 	.synapses = ftm_quaddec_count_synapses,
269 	.num_synapses = ARRAY_SIZE(ftm_quaddec_count_synapses),
270 	.ext = ftm_quaddec_count_ext,
271 	.num_ext = ARRAY_SIZE(ftm_quaddec_count_ext)
272 };
273 
274 static int ftm_quaddec_probe(struct platform_device *pdev)
275 {
276 	struct ftm_quaddec *ftm;
277 
278 	struct device_node *node = pdev->dev.of_node;
279 	struct resource *io;
280 	int ret;
281 
282 	ftm = devm_kzalloc(&pdev->dev, sizeof(*ftm), GFP_KERNEL);
283 	if (!ftm)
284 		return -ENOMEM;
285 
286 	platform_set_drvdata(pdev, ftm);
287 
288 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289 	if (!io) {
290 		dev_err(&pdev->dev, "Failed to get memory region\n");
291 		return -ENODEV;
292 	}
293 
294 	ftm->pdev = pdev;
295 	ftm->big_endian = of_property_read_bool(node, "big-endian");
296 	ftm->ftm_base = devm_ioremap(&pdev->dev, io->start, resource_size(io));
297 
298 	if (!ftm->ftm_base) {
299 		dev_err(&pdev->dev, "Failed to map memory region\n");
300 		return -EINVAL;
301 	}
302 	ftm->counter.name = dev_name(&pdev->dev);
303 	ftm->counter.parent = &pdev->dev;
304 	ftm->counter.ops = &ftm_quaddec_cnt_ops;
305 	ftm->counter.counts = &ftm_quaddec_counts;
306 	ftm->counter.num_counts = 1;
307 	ftm->counter.signals = ftm_quaddec_signals;
308 	ftm->counter.num_signals = ARRAY_SIZE(ftm_quaddec_signals);
309 	ftm->counter.priv = ftm;
310 
311 	mutex_init(&ftm->ftm_quaddec_mutex);
312 
313 	ftm_quaddec_init(ftm);
314 
315 	ret = devm_add_action_or_reset(&pdev->dev, ftm_quaddec_disable, ftm);
316 	if (ret)
317 		return ret;
318 
319 	ret = devm_counter_register(&pdev->dev, &ftm->counter);
320 	if (ret)
321 		return ret;
322 
323 	return 0;
324 }
325 
326 static const struct of_device_id ftm_quaddec_match[] = {
327 	{ .compatible = "fsl,ftm-quaddec" },
328 	{},
329 };
330 
331 static struct platform_driver ftm_quaddec_driver = {
332 	.driver = {
333 		.name = "ftm-quaddec",
334 		.of_match_table = ftm_quaddec_match,
335 	},
336 	.probe = ftm_quaddec_probe,
337 };
338 
339 module_platform_driver(ftm_quaddec_driver);
340 
341 MODULE_LICENSE("GPL");
342 MODULE_AUTHOR("Kjeld Flarup <kfa@deif.com>");
343 MODULE_AUTHOR("Patrick Havelange <patrick.havelange@essensium.com>");
344