1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Counter driver for the ACCES 104-QUAD-8 4 * Copyright (C) 2016 William Breathitt Gray 5 * 6 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4. 7 */ 8 #include <linux/bitops.h> 9 #include <linux/counter.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/io.h> 13 #include <linux/ioport.h> 14 #include <linux/interrupt.h> 15 #include <linux/isa.h> 16 #include <linux/kernel.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/types.h> 21 #include <linux/spinlock.h> 22 23 #define QUAD8_EXTENT 32 24 25 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)]; 26 static unsigned int num_quad8; 27 module_param_hw_array(base, uint, ioport, &num_quad8, 0); 28 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); 29 30 static unsigned int irq[max_num_isa_dev(QUAD8_EXTENT)]; 31 module_param_hw_array(irq, uint, irq, NULL, 0); 32 MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers"); 33 34 #define QUAD8_NUM_COUNTERS 8 35 36 /** 37 * struct channel_reg - channel register structure 38 * @data: Count data 39 * @control: Channel flags and control 40 */ 41 struct channel_reg { 42 u8 data; 43 u8 control; 44 }; 45 46 /** 47 * struct quad8_reg - device register structure 48 * @channel: quadrature counter data and control 49 * @interrupt_status: channel interrupt status 50 * @channel_oper: enable/reset counters and interrupt functions 51 * @index_interrupt: enable channel interrupts 52 * @reserved: reserved for Factory Use 53 * @index_input_levels: index signal logical input level 54 * @cable_status: differential encoder cable status 55 */ 56 struct quad8_reg { 57 struct channel_reg channel[QUAD8_NUM_COUNTERS]; 58 u8 interrupt_status; 59 u8 channel_oper; 60 u8 index_interrupt; 61 u8 reserved[3]; 62 u8 index_input_levels; 63 u8 cable_status; 64 }; 65 66 /** 67 * struct quad8 - device private data structure 68 * @lock: lock to prevent clobbering device states during R/W ops 69 * @counter: instance of the counter_device 70 * @fck_prescaler: array of filter clock prescaler configurations 71 * @preset: array of preset values 72 * @count_mode: array of count mode configurations 73 * @quadrature_mode: array of quadrature mode configurations 74 * @quadrature_scale: array of quadrature mode scale configurations 75 * @ab_enable: array of A and B inputs enable configurations 76 * @preset_enable: array of set_to_preset_on_index attribute configurations 77 * @irq_trigger: array of current IRQ trigger function configurations 78 * @synchronous_mode: array of index function synchronous mode configurations 79 * @index_polarity: array of index function polarity configurations 80 * @cable_fault_enable: differential encoder cable status enable configurations 81 * @reg: I/O address offset for the device registers 82 */ 83 struct quad8 { 84 spinlock_t lock; 85 unsigned int fck_prescaler[QUAD8_NUM_COUNTERS]; 86 unsigned int preset[QUAD8_NUM_COUNTERS]; 87 unsigned int count_mode[QUAD8_NUM_COUNTERS]; 88 unsigned int quadrature_mode[QUAD8_NUM_COUNTERS]; 89 unsigned int quadrature_scale[QUAD8_NUM_COUNTERS]; 90 unsigned int ab_enable[QUAD8_NUM_COUNTERS]; 91 unsigned int preset_enable[QUAD8_NUM_COUNTERS]; 92 unsigned int irq_trigger[QUAD8_NUM_COUNTERS]; 93 unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; 94 unsigned int index_polarity[QUAD8_NUM_COUNTERS]; 95 unsigned int cable_fault_enable; 96 struct quad8_reg __iomem *reg; 97 }; 98 99 /* Borrow Toggle flip-flop */ 100 #define QUAD8_FLAG_BT BIT(0) 101 /* Carry Toggle flip-flop */ 102 #define QUAD8_FLAG_CT BIT(1) 103 /* Error flag */ 104 #define QUAD8_FLAG_E BIT(4) 105 /* Up/Down flag */ 106 #define QUAD8_FLAG_UD BIT(5) 107 /* Reset and Load Signal Decoders */ 108 #define QUAD8_CTR_RLD 0x00 109 /* Counter Mode Register */ 110 #define QUAD8_CTR_CMR 0x20 111 /* Input / Output Control Register */ 112 #define QUAD8_CTR_IOR 0x40 113 /* Index Control Register */ 114 #define QUAD8_CTR_IDR 0x60 115 /* Reset Byte Pointer (three byte data pointer) */ 116 #define QUAD8_RLD_RESET_BP 0x01 117 /* Reset Counter */ 118 #define QUAD8_RLD_RESET_CNTR 0x02 119 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */ 120 #define QUAD8_RLD_RESET_FLAGS 0x04 121 /* Reset Error flag */ 122 #define QUAD8_RLD_RESET_E 0x06 123 /* Preset Register to Counter */ 124 #define QUAD8_RLD_PRESET_CNTR 0x08 125 /* Transfer Counter to Output Latch */ 126 #define QUAD8_RLD_CNTR_OUT 0x10 127 /* Transfer Preset Register LSB to FCK Prescaler */ 128 #define QUAD8_RLD_PRESET_PSC 0x18 129 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01 130 #define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04 131 #define QUAD8_CMR_QUADRATURE_X1 0x08 132 #define QUAD8_CMR_QUADRATURE_X2 0x10 133 #define QUAD8_CMR_QUADRATURE_X4 0x18 134 135 static int quad8_signal_read(struct counter_device *counter, 136 struct counter_signal *signal, 137 enum counter_signal_level *level) 138 { 139 const struct quad8 *const priv = counter_priv(counter); 140 unsigned int state; 141 142 /* Only Index signal levels can be read */ 143 if (signal->id < 16) 144 return -EINVAL; 145 146 state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16); 147 148 *level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; 149 150 return 0; 151 } 152 153 static int quad8_count_read(struct counter_device *counter, 154 struct counter_count *count, u64 *val) 155 { 156 struct quad8 *const priv = counter_priv(counter); 157 struct channel_reg __iomem *const chan = priv->reg->channel + count->id; 158 unsigned int flags; 159 unsigned int borrow; 160 unsigned int carry; 161 unsigned long irqflags; 162 int i; 163 164 flags = ioread8(&chan->control); 165 borrow = flags & QUAD8_FLAG_BT; 166 carry = !!(flags & QUAD8_FLAG_CT); 167 168 /* Borrow XOR Carry effectively doubles count range */ 169 *val = (unsigned long)(borrow ^ carry) << 24; 170 171 spin_lock_irqsave(&priv->lock, irqflags); 172 173 /* Reset Byte Pointer; transfer Counter to Output Latch */ 174 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, 175 &chan->control); 176 177 for (i = 0; i < 3; i++) 178 *val |= (unsigned long)ioread8(&chan->data) << (8 * i); 179 180 spin_unlock_irqrestore(&priv->lock, irqflags); 181 182 return 0; 183 } 184 185 static int quad8_count_write(struct counter_device *counter, 186 struct counter_count *count, u64 val) 187 { 188 struct quad8 *const priv = counter_priv(counter); 189 struct channel_reg __iomem *const chan = priv->reg->channel + count->id; 190 unsigned long irqflags; 191 int i; 192 193 /* Only 24-bit values are supported */ 194 if (val > 0xFFFFFF) 195 return -ERANGE; 196 197 spin_lock_irqsave(&priv->lock, irqflags); 198 199 /* Reset Byte Pointer */ 200 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 201 202 /* Counter can only be set via Preset Register */ 203 for (i = 0; i < 3; i++) 204 iowrite8(val >> (8 * i), &chan->data); 205 206 /* Transfer Preset Register to Counter */ 207 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control); 208 209 /* Reset Byte Pointer */ 210 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 211 212 /* Set Preset Register back to original value */ 213 val = priv->preset[count->id]; 214 for (i = 0; i < 3; i++) 215 iowrite8(val >> (8 * i), &chan->data); 216 217 /* Reset Borrow, Carry, Compare, and Sign flags */ 218 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); 219 /* Reset Error flag */ 220 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); 221 222 spin_unlock_irqrestore(&priv->lock, irqflags); 223 224 return 0; 225 } 226 227 static const enum counter_function quad8_count_functions_list[] = { 228 COUNTER_FUNCTION_PULSE_DIRECTION, 229 COUNTER_FUNCTION_QUADRATURE_X1_A, 230 COUNTER_FUNCTION_QUADRATURE_X2_A, 231 COUNTER_FUNCTION_QUADRATURE_X4, 232 }; 233 234 static int quad8_function_read(struct counter_device *counter, 235 struct counter_count *count, 236 enum counter_function *function) 237 { 238 struct quad8 *const priv = counter_priv(counter); 239 const int id = count->id; 240 unsigned long irqflags; 241 242 spin_lock_irqsave(&priv->lock, irqflags); 243 244 if (priv->quadrature_mode[id]) 245 switch (priv->quadrature_scale[id]) { 246 case 0: 247 *function = COUNTER_FUNCTION_QUADRATURE_X1_A; 248 break; 249 case 1: 250 *function = COUNTER_FUNCTION_QUADRATURE_X2_A; 251 break; 252 case 2: 253 *function = COUNTER_FUNCTION_QUADRATURE_X4; 254 break; 255 } 256 else 257 *function = COUNTER_FUNCTION_PULSE_DIRECTION; 258 259 spin_unlock_irqrestore(&priv->lock, irqflags); 260 261 return 0; 262 } 263 264 static int quad8_function_write(struct counter_device *counter, 265 struct counter_count *count, 266 enum counter_function function) 267 { 268 struct quad8 *const priv = counter_priv(counter); 269 const int id = count->id; 270 unsigned int *const quadrature_mode = priv->quadrature_mode + id; 271 unsigned int *const scale = priv->quadrature_scale + id; 272 unsigned int *const synchronous_mode = priv->synchronous_mode + id; 273 u8 __iomem *const control = &priv->reg->channel[id].control; 274 unsigned long irqflags; 275 unsigned int mode_cfg; 276 unsigned int idr_cfg; 277 278 spin_lock_irqsave(&priv->lock, irqflags); 279 280 mode_cfg = priv->count_mode[id] << 1; 281 idr_cfg = priv->index_polarity[id] << 1; 282 283 if (function == COUNTER_FUNCTION_PULSE_DIRECTION) { 284 *quadrature_mode = 0; 285 286 /* Quadrature scaling only available in quadrature mode */ 287 *scale = 0; 288 289 /* Synchronous function not supported in non-quadrature mode */ 290 if (*synchronous_mode) { 291 *synchronous_mode = 0; 292 /* Disable synchronous function mode */ 293 iowrite8(QUAD8_CTR_IDR | idr_cfg, control); 294 } 295 } else { 296 *quadrature_mode = 1; 297 298 switch (function) { 299 case COUNTER_FUNCTION_QUADRATURE_X1_A: 300 *scale = 0; 301 mode_cfg |= QUAD8_CMR_QUADRATURE_X1; 302 break; 303 case COUNTER_FUNCTION_QUADRATURE_X2_A: 304 *scale = 1; 305 mode_cfg |= QUAD8_CMR_QUADRATURE_X2; 306 break; 307 case COUNTER_FUNCTION_QUADRATURE_X4: 308 *scale = 2; 309 mode_cfg |= QUAD8_CMR_QUADRATURE_X4; 310 break; 311 default: 312 /* should never reach this path */ 313 spin_unlock_irqrestore(&priv->lock, irqflags); 314 return -EINVAL; 315 } 316 } 317 318 /* Load mode configuration to Counter Mode Register */ 319 iowrite8(QUAD8_CTR_CMR | mode_cfg, control); 320 321 spin_unlock_irqrestore(&priv->lock, irqflags); 322 323 return 0; 324 } 325 326 static int quad8_direction_read(struct counter_device *counter, 327 struct counter_count *count, 328 enum counter_count_direction *direction) 329 { 330 const struct quad8 *const priv = counter_priv(counter); 331 unsigned int ud_flag; 332 u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; 333 334 /* U/D flag: nonzero = up, zero = down */ 335 ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD; 336 337 *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : 338 COUNTER_COUNT_DIRECTION_BACKWARD; 339 340 return 0; 341 } 342 343 static const enum counter_synapse_action quad8_index_actions_list[] = { 344 COUNTER_SYNAPSE_ACTION_NONE, 345 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 346 }; 347 348 static const enum counter_synapse_action quad8_synapse_actions_list[] = { 349 COUNTER_SYNAPSE_ACTION_NONE, 350 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 351 COUNTER_SYNAPSE_ACTION_FALLING_EDGE, 352 COUNTER_SYNAPSE_ACTION_BOTH_EDGES, 353 }; 354 355 static int quad8_action_read(struct counter_device *counter, 356 struct counter_count *count, 357 struct counter_synapse *synapse, 358 enum counter_synapse_action *action) 359 { 360 struct quad8 *const priv = counter_priv(counter); 361 int err; 362 enum counter_function function; 363 const size_t signal_a_id = count->synapses[0].signal->id; 364 enum counter_count_direction direction; 365 366 /* Handle Index signals */ 367 if (synapse->signal->id >= 16) { 368 if (priv->preset_enable[count->id]) 369 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 370 else 371 *action = COUNTER_SYNAPSE_ACTION_NONE; 372 373 return 0; 374 } 375 376 err = quad8_function_read(counter, count, &function); 377 if (err) 378 return err; 379 380 /* Default action mode */ 381 *action = COUNTER_SYNAPSE_ACTION_NONE; 382 383 /* Determine action mode based on current count function mode */ 384 switch (function) { 385 case COUNTER_FUNCTION_PULSE_DIRECTION: 386 if (synapse->signal->id == signal_a_id) 387 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 388 return 0; 389 case COUNTER_FUNCTION_QUADRATURE_X1_A: 390 if (synapse->signal->id == signal_a_id) { 391 err = quad8_direction_read(counter, count, &direction); 392 if (err) 393 return err; 394 395 if (direction == COUNTER_COUNT_DIRECTION_FORWARD) 396 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 397 else 398 *action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE; 399 } 400 return 0; 401 case COUNTER_FUNCTION_QUADRATURE_X2_A: 402 if (synapse->signal->id == signal_a_id) 403 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 404 return 0; 405 case COUNTER_FUNCTION_QUADRATURE_X4: 406 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 407 return 0; 408 default: 409 /* should never reach this path */ 410 return -EINVAL; 411 } 412 } 413 414 enum { 415 QUAD8_EVENT_CARRY = 0, 416 QUAD8_EVENT_COMPARE = 1, 417 QUAD8_EVENT_CARRY_BORROW = 2, 418 QUAD8_EVENT_INDEX = 3, 419 }; 420 421 static int quad8_events_configure(struct counter_device *counter) 422 { 423 struct quad8 *const priv = counter_priv(counter); 424 unsigned long irq_enabled = 0; 425 unsigned long irqflags; 426 struct counter_event_node *event_node; 427 unsigned int next_irq_trigger; 428 unsigned long ior_cfg; 429 430 spin_lock_irqsave(&priv->lock, irqflags); 431 432 list_for_each_entry(event_node, &counter->events_list, l) { 433 switch (event_node->event) { 434 case COUNTER_EVENT_OVERFLOW: 435 next_irq_trigger = QUAD8_EVENT_CARRY; 436 break; 437 case COUNTER_EVENT_THRESHOLD: 438 next_irq_trigger = QUAD8_EVENT_COMPARE; 439 break; 440 case COUNTER_EVENT_OVERFLOW_UNDERFLOW: 441 next_irq_trigger = QUAD8_EVENT_CARRY_BORROW; 442 break; 443 case COUNTER_EVENT_INDEX: 444 next_irq_trigger = QUAD8_EVENT_INDEX; 445 break; 446 default: 447 /* should never reach this path */ 448 spin_unlock_irqrestore(&priv->lock, irqflags); 449 return -EINVAL; 450 } 451 452 /* Skip configuration if it is the same as previously set */ 453 if (priv->irq_trigger[event_node->channel] == next_irq_trigger) 454 continue; 455 456 /* Save new IRQ function configuration */ 457 priv->irq_trigger[event_node->channel] = next_irq_trigger; 458 459 /* Load configuration to I/O Control Register */ 460 ior_cfg = priv->ab_enable[event_node->channel] | 461 priv->preset_enable[event_node->channel] << 1 | 462 priv->irq_trigger[event_node->channel] << 3; 463 iowrite8(QUAD8_CTR_IOR | ior_cfg, 464 &priv->reg->channel[event_node->channel].control); 465 466 /* Enable IRQ line */ 467 irq_enabled |= BIT(event_node->channel); 468 } 469 470 iowrite8(irq_enabled, &priv->reg->index_interrupt); 471 472 spin_unlock_irqrestore(&priv->lock, irqflags); 473 474 return 0; 475 } 476 477 static int quad8_watch_validate(struct counter_device *counter, 478 const struct counter_watch *watch) 479 { 480 struct counter_event_node *event_node; 481 482 if (watch->channel > QUAD8_NUM_COUNTERS - 1) 483 return -EINVAL; 484 485 switch (watch->event) { 486 case COUNTER_EVENT_OVERFLOW: 487 case COUNTER_EVENT_THRESHOLD: 488 case COUNTER_EVENT_OVERFLOW_UNDERFLOW: 489 case COUNTER_EVENT_INDEX: 490 list_for_each_entry(event_node, &counter->next_events_list, l) 491 if (watch->channel == event_node->channel && 492 watch->event != event_node->event) 493 return -EINVAL; 494 return 0; 495 default: 496 return -EINVAL; 497 } 498 } 499 500 static const struct counter_ops quad8_ops = { 501 .signal_read = quad8_signal_read, 502 .count_read = quad8_count_read, 503 .count_write = quad8_count_write, 504 .function_read = quad8_function_read, 505 .function_write = quad8_function_write, 506 .action_read = quad8_action_read, 507 .events_configure = quad8_events_configure, 508 .watch_validate = quad8_watch_validate, 509 }; 510 511 static const char *const quad8_index_polarity_modes[] = { 512 "negative", 513 "positive" 514 }; 515 516 static int quad8_index_polarity_get(struct counter_device *counter, 517 struct counter_signal *signal, 518 u32 *index_polarity) 519 { 520 const struct quad8 *const priv = counter_priv(counter); 521 const size_t channel_id = signal->id - 16; 522 523 *index_polarity = priv->index_polarity[channel_id]; 524 525 return 0; 526 } 527 528 static int quad8_index_polarity_set(struct counter_device *counter, 529 struct counter_signal *signal, 530 u32 index_polarity) 531 { 532 struct quad8 *const priv = counter_priv(counter); 533 const size_t channel_id = signal->id - 16; 534 u8 __iomem *const control = &priv->reg->channel[channel_id].control; 535 unsigned long irqflags; 536 unsigned int idr_cfg = index_polarity << 1; 537 538 spin_lock_irqsave(&priv->lock, irqflags); 539 540 idr_cfg |= priv->synchronous_mode[channel_id]; 541 542 priv->index_polarity[channel_id] = index_polarity; 543 544 /* Load Index Control configuration to Index Control Register */ 545 iowrite8(QUAD8_CTR_IDR | idr_cfg, control); 546 547 spin_unlock_irqrestore(&priv->lock, irqflags); 548 549 return 0; 550 } 551 552 static const char *const quad8_synchronous_modes[] = { 553 "non-synchronous", 554 "synchronous" 555 }; 556 557 static int quad8_synchronous_mode_get(struct counter_device *counter, 558 struct counter_signal *signal, 559 u32 *synchronous_mode) 560 { 561 const struct quad8 *const priv = counter_priv(counter); 562 const size_t channel_id = signal->id - 16; 563 564 *synchronous_mode = priv->synchronous_mode[channel_id]; 565 566 return 0; 567 } 568 569 static int quad8_synchronous_mode_set(struct counter_device *counter, 570 struct counter_signal *signal, 571 u32 synchronous_mode) 572 { 573 struct quad8 *const priv = counter_priv(counter); 574 const size_t channel_id = signal->id - 16; 575 u8 __iomem *const control = &priv->reg->channel[channel_id].control; 576 unsigned long irqflags; 577 unsigned int idr_cfg = synchronous_mode; 578 579 spin_lock_irqsave(&priv->lock, irqflags); 580 581 idr_cfg |= priv->index_polarity[channel_id] << 1; 582 583 /* Index function must be non-synchronous in non-quadrature mode */ 584 if (synchronous_mode && !priv->quadrature_mode[channel_id]) { 585 spin_unlock_irqrestore(&priv->lock, irqflags); 586 return -EINVAL; 587 } 588 589 priv->synchronous_mode[channel_id] = synchronous_mode; 590 591 /* Load Index Control configuration to Index Control Register */ 592 iowrite8(QUAD8_CTR_IDR | idr_cfg, control); 593 594 spin_unlock_irqrestore(&priv->lock, irqflags); 595 596 return 0; 597 } 598 599 static int quad8_count_floor_read(struct counter_device *counter, 600 struct counter_count *count, u64 *floor) 601 { 602 /* Only a floor of 0 is supported */ 603 *floor = 0; 604 605 return 0; 606 } 607 608 static int quad8_count_mode_read(struct counter_device *counter, 609 struct counter_count *count, 610 enum counter_count_mode *cnt_mode) 611 { 612 const struct quad8 *const priv = counter_priv(counter); 613 614 /* Map 104-QUAD-8 count mode to Generic Counter count mode */ 615 switch (priv->count_mode[count->id]) { 616 case 0: 617 *cnt_mode = COUNTER_COUNT_MODE_NORMAL; 618 break; 619 case 1: 620 *cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT; 621 break; 622 case 2: 623 *cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE; 624 break; 625 case 3: 626 *cnt_mode = COUNTER_COUNT_MODE_MODULO_N; 627 break; 628 } 629 630 return 0; 631 } 632 633 static int quad8_count_mode_write(struct counter_device *counter, 634 struct counter_count *count, 635 enum counter_count_mode cnt_mode) 636 { 637 struct quad8 *const priv = counter_priv(counter); 638 unsigned int count_mode; 639 unsigned int mode_cfg; 640 u8 __iomem *const control = &priv->reg->channel[count->id].control; 641 unsigned long irqflags; 642 643 /* Map Generic Counter count mode to 104-QUAD-8 count mode */ 644 switch (cnt_mode) { 645 case COUNTER_COUNT_MODE_NORMAL: 646 count_mode = 0; 647 break; 648 case COUNTER_COUNT_MODE_RANGE_LIMIT: 649 count_mode = 1; 650 break; 651 case COUNTER_COUNT_MODE_NON_RECYCLE: 652 count_mode = 2; 653 break; 654 case COUNTER_COUNT_MODE_MODULO_N: 655 count_mode = 3; 656 break; 657 default: 658 /* should never reach this path */ 659 return -EINVAL; 660 } 661 662 spin_lock_irqsave(&priv->lock, irqflags); 663 664 priv->count_mode[count->id] = count_mode; 665 666 /* Set count mode configuration value */ 667 mode_cfg = count_mode << 1; 668 669 /* Add quadrature mode configuration */ 670 if (priv->quadrature_mode[count->id]) 671 mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3; 672 673 /* Load mode configuration to Counter Mode Register */ 674 iowrite8(QUAD8_CTR_CMR | mode_cfg, control); 675 676 spin_unlock_irqrestore(&priv->lock, irqflags); 677 678 return 0; 679 } 680 681 static int quad8_count_enable_read(struct counter_device *counter, 682 struct counter_count *count, u8 *enable) 683 { 684 const struct quad8 *const priv = counter_priv(counter); 685 686 *enable = priv->ab_enable[count->id]; 687 688 return 0; 689 } 690 691 static int quad8_count_enable_write(struct counter_device *counter, 692 struct counter_count *count, u8 enable) 693 { 694 struct quad8 *const priv = counter_priv(counter); 695 u8 __iomem *const control = &priv->reg->channel[count->id].control; 696 unsigned long irqflags; 697 unsigned int ior_cfg; 698 699 spin_lock_irqsave(&priv->lock, irqflags); 700 701 priv->ab_enable[count->id] = enable; 702 703 ior_cfg = enable | priv->preset_enable[count->id] << 1 | 704 priv->irq_trigger[count->id] << 3; 705 706 /* Load I/O control configuration */ 707 iowrite8(QUAD8_CTR_IOR | ior_cfg, control); 708 709 spin_unlock_irqrestore(&priv->lock, irqflags); 710 711 return 0; 712 } 713 714 static const char *const quad8_noise_error_states[] = { 715 "No excessive noise is present at the count inputs", 716 "Excessive noise is present at the count inputs" 717 }; 718 719 static int quad8_error_noise_get(struct counter_device *counter, 720 struct counter_count *count, u32 *noise_error) 721 { 722 const struct quad8 *const priv = counter_priv(counter); 723 u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; 724 725 *noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E); 726 727 return 0; 728 } 729 730 static int quad8_count_preset_read(struct counter_device *counter, 731 struct counter_count *count, u64 *preset) 732 { 733 const struct quad8 *const priv = counter_priv(counter); 734 735 *preset = priv->preset[count->id]; 736 737 return 0; 738 } 739 740 static void quad8_preset_register_set(struct quad8 *const priv, const int id, 741 const unsigned int preset) 742 { 743 struct channel_reg __iomem *const chan = priv->reg->channel + id; 744 int i; 745 746 priv->preset[id] = preset; 747 748 /* Reset Byte Pointer */ 749 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 750 751 /* Set Preset Register */ 752 for (i = 0; i < 3; i++) 753 iowrite8(preset >> (8 * i), &chan->data); 754 } 755 756 static int quad8_count_preset_write(struct counter_device *counter, 757 struct counter_count *count, u64 preset) 758 { 759 struct quad8 *const priv = counter_priv(counter); 760 unsigned long irqflags; 761 762 /* Only 24-bit values are supported */ 763 if (preset > 0xFFFFFF) 764 return -ERANGE; 765 766 spin_lock_irqsave(&priv->lock, irqflags); 767 768 quad8_preset_register_set(priv, count->id, preset); 769 770 spin_unlock_irqrestore(&priv->lock, irqflags); 771 772 return 0; 773 } 774 775 static int quad8_count_ceiling_read(struct counter_device *counter, 776 struct counter_count *count, u64 *ceiling) 777 { 778 struct quad8 *const priv = counter_priv(counter); 779 unsigned long irqflags; 780 781 spin_lock_irqsave(&priv->lock, irqflags); 782 783 /* Range Limit and Modulo-N count modes use preset value as ceiling */ 784 switch (priv->count_mode[count->id]) { 785 case 1: 786 case 3: 787 *ceiling = priv->preset[count->id]; 788 break; 789 default: 790 /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */ 791 *ceiling = 0x1FFFFFF; 792 break; 793 } 794 795 spin_unlock_irqrestore(&priv->lock, irqflags); 796 797 return 0; 798 } 799 800 static int quad8_count_ceiling_write(struct counter_device *counter, 801 struct counter_count *count, u64 ceiling) 802 { 803 struct quad8 *const priv = counter_priv(counter); 804 unsigned long irqflags; 805 806 /* Only 24-bit values are supported */ 807 if (ceiling > 0xFFFFFF) 808 return -ERANGE; 809 810 spin_lock_irqsave(&priv->lock, irqflags); 811 812 /* Range Limit and Modulo-N count modes use preset value as ceiling */ 813 switch (priv->count_mode[count->id]) { 814 case 1: 815 case 3: 816 quad8_preset_register_set(priv, count->id, ceiling); 817 spin_unlock_irqrestore(&priv->lock, irqflags); 818 return 0; 819 } 820 821 spin_unlock_irqrestore(&priv->lock, irqflags); 822 823 return -EINVAL; 824 } 825 826 static int quad8_count_preset_enable_read(struct counter_device *counter, 827 struct counter_count *count, 828 u8 *preset_enable) 829 { 830 const struct quad8 *const priv = counter_priv(counter); 831 832 *preset_enable = !priv->preset_enable[count->id]; 833 834 return 0; 835 } 836 837 static int quad8_count_preset_enable_write(struct counter_device *counter, 838 struct counter_count *count, 839 u8 preset_enable) 840 { 841 struct quad8 *const priv = counter_priv(counter); 842 u8 __iomem *const control = &priv->reg->channel[count->id].control; 843 unsigned long irqflags; 844 unsigned int ior_cfg; 845 846 /* Preset enable is active low in Input/Output Control register */ 847 preset_enable = !preset_enable; 848 849 spin_lock_irqsave(&priv->lock, irqflags); 850 851 priv->preset_enable[count->id] = preset_enable; 852 853 ior_cfg = priv->ab_enable[count->id] | preset_enable << 1 | 854 priv->irq_trigger[count->id] << 3; 855 856 /* Load I/O control configuration to Input / Output Control Register */ 857 iowrite8(QUAD8_CTR_IOR | ior_cfg, control); 858 859 spin_unlock_irqrestore(&priv->lock, irqflags); 860 861 return 0; 862 } 863 864 static int quad8_signal_cable_fault_read(struct counter_device *counter, 865 struct counter_signal *signal, 866 u8 *cable_fault) 867 { 868 struct quad8 *const priv = counter_priv(counter); 869 const size_t channel_id = signal->id / 2; 870 unsigned long irqflags; 871 bool disabled; 872 unsigned int status; 873 874 spin_lock_irqsave(&priv->lock, irqflags); 875 876 disabled = !(priv->cable_fault_enable & BIT(channel_id)); 877 878 if (disabled) { 879 spin_unlock_irqrestore(&priv->lock, irqflags); 880 return -EINVAL; 881 } 882 883 /* Logic 0 = cable fault */ 884 status = ioread8(&priv->reg->cable_status); 885 886 spin_unlock_irqrestore(&priv->lock, irqflags); 887 888 /* Mask respective channel and invert logic */ 889 *cable_fault = !(status & BIT(channel_id)); 890 891 return 0; 892 } 893 894 static int quad8_signal_cable_fault_enable_read(struct counter_device *counter, 895 struct counter_signal *signal, 896 u8 *enable) 897 { 898 const struct quad8 *const priv = counter_priv(counter); 899 const size_t channel_id = signal->id / 2; 900 901 *enable = !!(priv->cable_fault_enable & BIT(channel_id)); 902 903 return 0; 904 } 905 906 static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, 907 struct counter_signal *signal, 908 u8 enable) 909 { 910 struct quad8 *const priv = counter_priv(counter); 911 const size_t channel_id = signal->id / 2; 912 unsigned long irqflags; 913 unsigned int cable_fault_enable; 914 915 spin_lock_irqsave(&priv->lock, irqflags); 916 917 if (enable) 918 priv->cable_fault_enable |= BIT(channel_id); 919 else 920 priv->cable_fault_enable &= ~BIT(channel_id); 921 922 /* Enable is active low in Differential Encoder Cable Status register */ 923 cable_fault_enable = ~priv->cable_fault_enable; 924 925 iowrite8(cable_fault_enable, &priv->reg->cable_status); 926 927 spin_unlock_irqrestore(&priv->lock, irqflags); 928 929 return 0; 930 } 931 932 static int quad8_signal_fck_prescaler_read(struct counter_device *counter, 933 struct counter_signal *signal, 934 u8 *prescaler) 935 { 936 const struct quad8 *const priv = counter_priv(counter); 937 938 *prescaler = priv->fck_prescaler[signal->id / 2]; 939 940 return 0; 941 } 942 943 static int quad8_signal_fck_prescaler_write(struct counter_device *counter, 944 struct counter_signal *signal, 945 u8 prescaler) 946 { 947 struct quad8 *const priv = counter_priv(counter); 948 const size_t channel_id = signal->id / 2; 949 struct channel_reg __iomem *const chan = priv->reg->channel + channel_id; 950 unsigned long irqflags; 951 952 spin_lock_irqsave(&priv->lock, irqflags); 953 954 priv->fck_prescaler[channel_id] = prescaler; 955 956 /* Reset Byte Pointer */ 957 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 958 959 /* Set filter clock factor */ 960 iowrite8(prescaler, &chan->data); 961 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, 962 &chan->control); 963 964 spin_unlock_irqrestore(&priv->lock, irqflags); 965 966 return 0; 967 } 968 969 static struct counter_comp quad8_signal_ext[] = { 970 COUNTER_COMP_SIGNAL_BOOL("cable_fault", quad8_signal_cable_fault_read, 971 NULL), 972 COUNTER_COMP_SIGNAL_BOOL("cable_fault_enable", 973 quad8_signal_cable_fault_enable_read, 974 quad8_signal_cable_fault_enable_write), 975 COUNTER_COMP_SIGNAL_U8("filter_clock_prescaler", 976 quad8_signal_fck_prescaler_read, 977 quad8_signal_fck_prescaler_write) 978 }; 979 980 static DEFINE_COUNTER_ENUM(quad8_index_pol_enum, quad8_index_polarity_modes); 981 static DEFINE_COUNTER_ENUM(quad8_synch_mode_enum, quad8_synchronous_modes); 982 983 static struct counter_comp quad8_index_ext[] = { 984 COUNTER_COMP_SIGNAL_ENUM("index_polarity", quad8_index_polarity_get, 985 quad8_index_polarity_set, 986 quad8_index_pol_enum), 987 COUNTER_COMP_SIGNAL_ENUM("synchronous_mode", quad8_synchronous_mode_get, 988 quad8_synchronous_mode_set, 989 quad8_synch_mode_enum), 990 }; 991 992 #define QUAD8_QUAD_SIGNAL(_id, _name) { \ 993 .id = (_id), \ 994 .name = (_name), \ 995 .ext = quad8_signal_ext, \ 996 .num_ext = ARRAY_SIZE(quad8_signal_ext) \ 997 } 998 999 #define QUAD8_INDEX_SIGNAL(_id, _name) { \ 1000 .id = (_id), \ 1001 .name = (_name), \ 1002 .ext = quad8_index_ext, \ 1003 .num_ext = ARRAY_SIZE(quad8_index_ext) \ 1004 } 1005 1006 static struct counter_signal quad8_signals[] = { 1007 QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"), 1008 QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"), 1009 QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"), 1010 QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"), 1011 QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"), 1012 QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"), 1013 QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"), 1014 QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"), 1015 QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"), 1016 QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"), 1017 QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"), 1018 QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"), 1019 QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"), 1020 QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"), 1021 QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"), 1022 QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"), 1023 QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"), 1024 QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"), 1025 QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"), 1026 QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"), 1027 QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"), 1028 QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"), 1029 QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"), 1030 QUAD8_INDEX_SIGNAL(23, "Channel 8 Index") 1031 }; 1032 1033 #define QUAD8_COUNT_SYNAPSES(_id) { \ 1034 { \ 1035 .actions_list = quad8_synapse_actions_list, \ 1036 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \ 1037 .signal = quad8_signals + 2 * (_id) \ 1038 }, \ 1039 { \ 1040 .actions_list = quad8_synapse_actions_list, \ 1041 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \ 1042 .signal = quad8_signals + 2 * (_id) + 1 \ 1043 }, \ 1044 { \ 1045 .actions_list = quad8_index_actions_list, \ 1046 .num_actions = ARRAY_SIZE(quad8_index_actions_list), \ 1047 .signal = quad8_signals + 2 * (_id) + 16 \ 1048 } \ 1049 } 1050 1051 static struct counter_synapse quad8_count_synapses[][3] = { 1052 QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1), 1053 QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3), 1054 QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5), 1055 QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7) 1056 }; 1057 1058 static const enum counter_count_mode quad8_cnt_modes[] = { 1059 COUNTER_COUNT_MODE_NORMAL, 1060 COUNTER_COUNT_MODE_RANGE_LIMIT, 1061 COUNTER_COUNT_MODE_NON_RECYCLE, 1062 COUNTER_COUNT_MODE_MODULO_N, 1063 }; 1064 1065 static DEFINE_COUNTER_AVAILABLE(quad8_count_mode_available, quad8_cnt_modes); 1066 1067 static DEFINE_COUNTER_ENUM(quad8_error_noise_enum, quad8_noise_error_states); 1068 1069 static struct counter_comp quad8_count_ext[] = { 1070 COUNTER_COMP_CEILING(quad8_count_ceiling_read, 1071 quad8_count_ceiling_write), 1072 COUNTER_COMP_FLOOR(quad8_count_floor_read, NULL), 1073 COUNTER_COMP_COUNT_MODE(quad8_count_mode_read, quad8_count_mode_write, 1074 quad8_count_mode_available), 1075 COUNTER_COMP_DIRECTION(quad8_direction_read), 1076 COUNTER_COMP_ENABLE(quad8_count_enable_read, quad8_count_enable_write), 1077 COUNTER_COMP_COUNT_ENUM("error_noise", quad8_error_noise_get, NULL, 1078 quad8_error_noise_enum), 1079 COUNTER_COMP_PRESET(quad8_count_preset_read, quad8_count_preset_write), 1080 COUNTER_COMP_PRESET_ENABLE(quad8_count_preset_enable_read, 1081 quad8_count_preset_enable_write), 1082 }; 1083 1084 #define QUAD8_COUNT(_id, _cntname) { \ 1085 .id = (_id), \ 1086 .name = (_cntname), \ 1087 .functions_list = quad8_count_functions_list, \ 1088 .num_functions = ARRAY_SIZE(quad8_count_functions_list), \ 1089 .synapses = quad8_count_synapses[(_id)], \ 1090 .num_synapses = 2, \ 1091 .ext = quad8_count_ext, \ 1092 .num_ext = ARRAY_SIZE(quad8_count_ext) \ 1093 } 1094 1095 static struct counter_count quad8_counts[] = { 1096 QUAD8_COUNT(0, "Channel 1 Count"), 1097 QUAD8_COUNT(1, "Channel 2 Count"), 1098 QUAD8_COUNT(2, "Channel 3 Count"), 1099 QUAD8_COUNT(3, "Channel 4 Count"), 1100 QUAD8_COUNT(4, "Channel 5 Count"), 1101 QUAD8_COUNT(5, "Channel 6 Count"), 1102 QUAD8_COUNT(6, "Channel 7 Count"), 1103 QUAD8_COUNT(7, "Channel 8 Count") 1104 }; 1105 1106 static irqreturn_t quad8_irq_handler(int irq, void *private) 1107 { 1108 struct counter_device *counter = private; 1109 struct quad8 *const priv = counter_priv(counter); 1110 unsigned long irq_status; 1111 unsigned long channel; 1112 u8 event; 1113 1114 irq_status = ioread8(&priv->reg->interrupt_status); 1115 if (!irq_status) 1116 return IRQ_NONE; 1117 1118 for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) { 1119 switch (priv->irq_trigger[channel]) { 1120 case QUAD8_EVENT_CARRY: 1121 event = COUNTER_EVENT_OVERFLOW; 1122 break; 1123 case QUAD8_EVENT_COMPARE: 1124 event = COUNTER_EVENT_THRESHOLD; 1125 break; 1126 case QUAD8_EVENT_CARRY_BORROW: 1127 event = COUNTER_EVENT_OVERFLOW_UNDERFLOW; 1128 break; 1129 case QUAD8_EVENT_INDEX: 1130 event = COUNTER_EVENT_INDEX; 1131 break; 1132 default: 1133 /* should never reach this path */ 1134 WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n", 1135 priv->irq_trigger[channel], channel); 1136 continue; 1137 } 1138 1139 counter_push_event(counter, event, channel); 1140 } 1141 1142 /* Clear pending interrupts on device */ 1143 iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); 1144 1145 return IRQ_HANDLED; 1146 } 1147 1148 static void quad8_init_counter(struct channel_reg __iomem *const chan) 1149 { 1150 unsigned long i; 1151 1152 /* Reset Byte Pointer */ 1153 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 1154 /* Reset filter clock factor */ 1155 iowrite8(0, &chan->data); 1156 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, 1157 &chan->control); 1158 /* Reset Byte Pointer */ 1159 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 1160 /* Reset Preset Register */ 1161 for (i = 0; i < 3; i++) 1162 iowrite8(0x00, &chan->data); 1163 /* Reset Borrow, Carry, Compare, and Sign flags */ 1164 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); 1165 /* Reset Error flag */ 1166 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); 1167 /* Binary encoding; Normal count; non-quadrature mode */ 1168 iowrite8(QUAD8_CTR_CMR, &chan->control); 1169 /* Disable A and B inputs; preset on index; FLG1 as Carry */ 1170 iowrite8(QUAD8_CTR_IOR, &chan->control); 1171 /* Disable index function; negative index polarity */ 1172 iowrite8(QUAD8_CTR_IDR, &chan->control); 1173 } 1174 1175 static int quad8_probe(struct device *dev, unsigned int id) 1176 { 1177 struct counter_device *counter; 1178 struct quad8 *priv; 1179 unsigned long i; 1180 int err; 1181 1182 if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { 1183 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 1184 base[id], base[id] + QUAD8_EXTENT); 1185 return -EBUSY; 1186 } 1187 1188 counter = devm_counter_alloc(dev, sizeof(*priv)); 1189 if (!counter) 1190 return -ENOMEM; 1191 priv = counter_priv(counter); 1192 1193 priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT); 1194 if (!priv->reg) 1195 return -ENOMEM; 1196 1197 /* Initialize Counter device and driver data */ 1198 counter->name = dev_name(dev); 1199 counter->parent = dev; 1200 counter->ops = &quad8_ops; 1201 counter->counts = quad8_counts; 1202 counter->num_counts = ARRAY_SIZE(quad8_counts); 1203 counter->signals = quad8_signals; 1204 counter->num_signals = ARRAY_SIZE(quad8_signals); 1205 1206 spin_lock_init(&priv->lock); 1207 1208 /* Reset Index/Interrupt Register */ 1209 iowrite8(0x00, &priv->reg->index_interrupt); 1210 /* Reset all counters and disable interrupt function */ 1211 iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper); 1212 /* Set initial configuration for all counters */ 1213 for (i = 0; i < QUAD8_NUM_COUNTERS; i++) 1214 quad8_init_counter(priv->reg->channel + i); 1215 /* Disable Differential Encoder Cable Status for all channels */ 1216 iowrite8(0xFF, &priv->reg->cable_status); 1217 /* Enable all counters and enable interrupt function */ 1218 iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); 1219 1220 err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, 1221 IRQF_SHARED, counter->name, counter); 1222 if (err) 1223 return err; 1224 1225 err = devm_counter_add(dev, counter); 1226 if (err < 0) 1227 return dev_err_probe(dev, err, "Failed to add counter\n"); 1228 1229 return 0; 1230 } 1231 1232 static struct isa_driver quad8_driver = { 1233 .probe = quad8_probe, 1234 .driver = { 1235 .name = "104-quad-8" 1236 } 1237 }; 1238 1239 module_isa_driver(quad8_driver, num_quad8); 1240 1241 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 1242 MODULE_DESCRIPTION("ACCES 104-QUAD-8 driver"); 1243 MODULE_LICENSE("GPL v2"); 1244